1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox.
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_malloc.h>
26 #include <rte_ethdev_driver.h>
27 #include <rte_common.h>
29 #include "mlx5_utils.h"
30 #include "mlx5_defs.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_glue.h"
37 * Allocate TX queue elements.
40 * Pointer to TX queue structure.
43 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
45 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
48 for (i = 0; (i != elts_n); ++i)
49 (*txq_ctrl->txq.elts)[i] = NULL;
50 DEBUG("port %u Tx queue %u allocated and configured %u WRs",
51 txq_ctrl->priv->dev->data->port_id, txq_ctrl->idx, elts_n);
52 txq_ctrl->txq.elts_head = 0;
53 txq_ctrl->txq.elts_tail = 0;
54 txq_ctrl->txq.elts_comp = 0;
58 * Free TX queue elements.
61 * Pointer to TX queue structure.
64 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
66 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
67 const uint16_t elts_m = elts_n - 1;
68 uint16_t elts_head = txq_ctrl->txq.elts_head;
69 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
70 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
72 DEBUG("port %u Tx queue %u freeing WRs",
73 txq_ctrl->priv->dev->data->port_id, txq_ctrl->idx);
74 txq_ctrl->txq.elts_head = 0;
75 txq_ctrl->txq.elts_tail = 0;
76 txq_ctrl->txq.elts_comp = 0;
78 while (elts_tail != elts_head) {
79 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
82 rte_pktmbuf_free_seg(elt);
85 memset(&(*elts)[elts_tail & elts_m],
87 sizeof((*elts)[elts_tail & elts_m]));
94 * Returns the per-port supported offloads.
97 * Pointer to Ethernet device.
100 * Supported Tx offloads.
103 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
105 struct priv *priv = dev->data->dev_private;
106 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
107 DEV_TX_OFFLOAD_VLAN_INSERT);
108 struct mlx5_dev_config *config = &priv->config;
111 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
112 DEV_TX_OFFLOAD_UDP_CKSUM |
113 DEV_TX_OFFLOAD_TCP_CKSUM);
115 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
116 if (config->tunnel_en) {
118 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
120 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
121 DEV_TX_OFFLOAD_GRE_TNL_TSO);
127 * Checks if the per-queue offload configuration is valid.
130 * Pointer to Ethernet device.
132 * Per-queue offloads configuration.
135 * 1 if the configuration is valid, 0 otherwise.
138 mlx5_is_tx_queue_offloads_allowed(struct rte_eth_dev *dev, uint64_t offloads)
140 uint64_t port_offloads = dev->data->dev_conf.txmode.offloads;
141 uint64_t port_supp_offloads = mlx5_get_tx_port_offloads(dev);
143 /* There are no Tx offloads which are per queue. */
144 if ((offloads & port_supp_offloads) != offloads)
146 if ((port_offloads ^ offloads) & port_supp_offloads)
152 * DPDK callback to configure a TX queue.
155 * Pointer to Ethernet device structure.
159 * Number of descriptors to configure in queue.
161 * NUMA socket on which memory must be allocated.
163 * Thresholds parameters.
166 * 0 on success, a negative errno value otherwise and rte_errno is set.
169 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
170 unsigned int socket, const struct rte_eth_txconf *conf)
172 struct priv *priv = dev->data->dev_private;
173 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
174 struct mlx5_txq_ctrl *txq_ctrl =
175 container_of(txq, struct mlx5_txq_ctrl, txq);
178 * Don't verify port offloads for application which
181 if (!!(conf->txq_flags & ETH_TXQ_FLAGS_IGNORE) &&
182 !mlx5_is_tx_queue_offloads_allowed(dev, conf->offloads)) {
184 ERROR("port %u Tx queue offloads 0x%" PRIx64 " don't match"
185 " port offloads 0x%" PRIx64 " or supported offloads 0x%"
187 dev->data->port_id, conf->offloads,
188 dev->data->dev_conf.txmode.offloads,
189 mlx5_get_tx_port_offloads(dev));
192 if (desc <= MLX5_TX_COMP_THRESH) {
193 WARN("port %u number of descriptors requested for Tx queue %u"
194 " must be higher than MLX5_TX_COMP_THRESH, using"
196 dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc);
197 desc = MLX5_TX_COMP_THRESH + 1;
199 if (!rte_is_power_of_2(desc)) {
200 desc = 1 << log2above(desc);
201 WARN("port %u increased number of descriptors in Tx queue %u"
202 " to the next power of two (%d)",
203 dev->data->port_id, idx, desc);
205 DEBUG("port %u configuring queue %u for %u descriptors",
206 dev->data->port_id, idx, desc);
207 if (idx >= priv->txqs_n) {
208 ERROR("port %u Tx queue index out of range (%u >= %u)",
209 dev->data->port_id, idx, priv->txqs_n);
210 rte_errno = EOVERFLOW;
213 if (!mlx5_txq_releasable(dev, idx)) {
215 ERROR("port %u unable to release queue index %u",
216 dev->data->port_id, idx);
219 mlx5_txq_release(dev, idx);
220 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
222 ERROR("port %u unable to allocate queue index %u",
223 dev->data->port_id, idx);
226 DEBUG("port %u adding Tx queue %u to list", dev->data->port_id, idx);
227 (*priv->txqs)[idx] = &txq_ctrl->txq;
232 * DPDK callback to release a TX queue.
235 * Generic TX queue pointer.
238 mlx5_tx_queue_release(void *dpdk_txq)
240 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
241 struct mlx5_txq_ctrl *txq_ctrl;
247 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
248 priv = txq_ctrl->priv;
249 for (i = 0; (i != priv->txqs_n); ++i)
250 if ((*priv->txqs)[i] == txq) {
251 mlx5_txq_release(priv->dev, i);
252 DEBUG("port %u removing Tx queue %u from list",
253 priv->dev->data->port_id, txq_ctrl->idx);
260 * Mmap TX UAR(HW doorbell) pages into reserved UAR address space.
261 * Both primary and secondary process do mmap to make UAR address
265 * Pointer to Ethernet device.
267 * Verbs file descriptor to map UAR pages.
270 * 0 on success, a negative errno value otherwise and rte_errno is set.
273 mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd)
275 struct priv *priv = dev->data->dev_private;
277 uintptr_t pages[priv->txqs_n];
278 unsigned int pages_n = 0;
283 struct mlx5_txq_data *txq;
284 struct mlx5_txq_ctrl *txq_ctrl;
286 size_t page_size = sysconf(_SC_PAGESIZE);
288 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t));
290 * As rdma-core, UARs are mapped in size of OS page size.
291 * Use aligned address to avoid duplicate mmap.
292 * Ref to libmlx5 function: mlx5_init_context()
294 for (i = 0; i != priv->txqs_n; ++i) {
295 if (!(*priv->txqs)[i])
297 txq = (*priv->txqs)[i];
298 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
299 assert(txq_ctrl->idx == (uint16_t)i);
300 /* UAR addr form verbs used to find dup and offset in page. */
301 uar_va = (uintptr_t)txq_ctrl->bf_reg_orig;
302 off = uar_va & (page_size - 1); /* offset in page. */
303 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size); /* page addr. */
305 for (j = 0; j != pages_n; ++j) {
306 if (pages[j] == uar_va) {
311 /* new address in reserved UAR address space. */
312 addr = RTE_PTR_ADD(priv->uar_base,
313 uar_va & (MLX5_UAR_SIZE - 1));
314 if (!already_mapped) {
315 pages[pages_n++] = uar_va;
316 /* fixed mmap to specified address in reserved
319 ret = mmap(addr, page_size,
320 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd,
321 txq_ctrl->uar_mmap_offset);
323 /* fixed mmap have to return same address */
324 ERROR("port %u call to mmap failed on UAR for"
325 " txq %u", dev->data->port_id,
331 if (rte_eal_process_type() == RTE_PROC_PRIMARY) /* save once */
332 txq_ctrl->txq.bf_reg = RTE_PTR_ADD((void *)addr, off);
334 assert(txq_ctrl->txq.bf_reg ==
335 RTE_PTR_ADD((void *)addr, off));
341 * Check if the burst function is using eMPW.
343 * @param tx_pkt_burst
344 * Tx burst function pointer.
347 * 1 if the burst function is using eMPW, 0 otherwise.
350 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst)
352 if (tx_pkt_burst == mlx5_tx_burst_raw_vec ||
353 tx_pkt_burst == mlx5_tx_burst_vec ||
354 tx_pkt_burst == mlx5_tx_burst_empw)
360 * Create the Tx queue Verbs object.
363 * Pointer to Ethernet device.
365 * Queue index in DPDK Rx queue array
368 * The Verbs object initialised, NULL otherwise and rte_errno is set.
370 struct mlx5_txq_ibv *
371 mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
373 struct priv *priv = dev->data->dev_private;
374 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
375 struct mlx5_txq_ctrl *txq_ctrl =
376 container_of(txq_data, struct mlx5_txq_ctrl, txq);
377 struct mlx5_txq_ibv tmpl;
378 struct mlx5_txq_ibv *txq_ibv;
380 struct ibv_qp_init_attr_ex init;
381 struct ibv_cq_init_attr_ex cq;
382 struct ibv_qp_attr mod;
383 struct ibv_cq_ex cq_attr;
386 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
387 struct mlx5dv_cq cq_info;
388 struct mlx5dv_obj obj;
389 const int desc = 1 << txq_data->elts_n;
390 eth_tx_burst_t tx_pkt_burst = mlx5_select_tx_function(dev);
394 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
395 priv->verbs_alloc_ctx.obj = txq_ctrl;
396 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
397 ERROR("port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
402 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
403 /* MRs will be registered in mp2mr[] later. */
404 attr.cq = (struct ibv_cq_init_attr_ex){
407 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
408 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
409 if (is_empw_burst_func(tx_pkt_burst))
410 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
411 tmpl.cq = mlx5_glue->create_cq(priv->ctx, cqe_n, NULL, NULL, 0);
412 if (tmpl.cq == NULL) {
413 ERROR("port %u Tx queue %u CQ creation failure",
414 dev->data->port_id, idx);
418 attr.init = (struct ibv_qp_init_attr_ex){
419 /* CQ to be associated with the send queue. */
421 /* CQ to be associated with the receive queue. */
424 /* Max number of outstanding WRs. */
426 ((priv->device_attr.orig_attr.max_qp_wr <
428 priv->device_attr.orig_attr.max_qp_wr :
431 * Max number of scatter/gather elements in a WR,
432 * must be 1 to prevent libmlx5 from trying to affect
433 * too much memory. TX gather is not impacted by the
434 * priv->device_attr.max_sge limit and will still work
439 .qp_type = IBV_QPT_RAW_PACKET,
441 * Do *NOT* enable this, completions events are managed per
446 .comp_mask = IBV_QP_INIT_ATTR_PD,
448 if (txq_data->max_inline)
449 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
450 if (txq_data->tso_en) {
451 attr.init.max_tso_header = txq_ctrl->max_tso_header;
452 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
454 tmpl.qp = mlx5_glue->create_qp_ex(priv->ctx, &attr.init);
455 if (tmpl.qp == NULL) {
456 ERROR("port %u Tx queue %u QP creation failure",
457 dev->data->port_id, idx);
461 attr.mod = (struct ibv_qp_attr){
462 /* Move the QP to this state. */
463 .qp_state = IBV_QPS_INIT,
464 /* Primary port number. */
465 .port_num = priv->port
467 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
468 (IBV_QP_STATE | IBV_QP_PORT));
470 ERROR("port %u Tx queue %u QP state to IBV_QPS_INIT failed",
471 dev->data->port_id, idx);
475 attr.mod = (struct ibv_qp_attr){
476 .qp_state = IBV_QPS_RTR
478 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
480 ERROR("port %u Tx queue %u QP state to IBV_QPS_RTR failed",
481 dev->data->port_id, idx);
485 attr.mod.qp_state = IBV_QPS_RTS;
486 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
488 ERROR("port %u Tx queue %u QP state to IBV_QPS_RTS failed",
489 dev->data->port_id, idx);
493 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
496 ERROR("port %u Tx queue %u cannot allocate memory",
497 dev->data->port_id, idx);
502 obj.cq.out = &cq_info;
505 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
510 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
511 ERROR("port %u wrong MLX5_CQE_SIZE environment variable value: "
512 "it should be set to %u", dev->data->port_id,
513 RTE_CACHE_LINE_SIZE);
517 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
518 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
519 txq_data->wqes = qp.sq.buf;
520 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
521 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
522 txq_ctrl->bf_reg_orig = qp.bf.reg;
523 txq_data->cq_db = cq_info.dbrec;
525 (volatile struct mlx5_cqe (*)[])
526 (uintptr_t)cq_info.buf;
531 txq_data->wqe_ci = 0;
532 txq_data->wqe_pi = 0;
533 txq_ibv->qp = tmpl.qp;
534 txq_ibv->cq = tmpl.cq;
535 rte_atomic32_inc(&txq_ibv->refcnt);
536 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
537 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
539 ERROR("port %u failed to retrieve UAR info, invalid libmlx5.so",
544 DEBUG("port %u Verbs Tx queue %u: refcnt %d", dev->data->port_id, idx,
545 rte_atomic32_read(&txq_ibv->refcnt));
546 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
547 txq_ibv->txq_ctrl = txq_ctrl;
548 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
551 ret = rte_errno; /* Save rte_errno before cleanup. */
553 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
555 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
556 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
557 rte_errno = ret; /* Restore rte_errno. */
562 * Get an Tx queue Verbs object.
565 * Pointer to Ethernet device.
567 * Queue index in DPDK Rx queue array
570 * The Verbs object if it exists.
572 struct mlx5_txq_ibv *
573 mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
575 struct priv *priv = dev->data->dev_private;
576 struct mlx5_txq_ctrl *txq_ctrl;
578 if (idx >= priv->txqs_n)
580 if (!(*priv->txqs)[idx])
582 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
584 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
585 DEBUG("port %u Verbs Tx queue %u: refcnt %d",
586 dev->data->port_id, txq_ctrl->idx,
587 rte_atomic32_read(&txq_ctrl->ibv->refcnt));
589 return txq_ctrl->ibv;
593 * Release an Tx verbs queue object.
596 * Verbs Tx queue object.
599 * 1 while a reference on it exists, 0 when freed.
602 mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv)
605 DEBUG("port %u Verbs Tx queue %u: refcnt %d",
606 txq_ibv->txq_ctrl->priv->dev->data->port_id,
607 txq_ibv->txq_ctrl->idx, rte_atomic32_read(&txq_ibv->refcnt));
608 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
609 claim_zero(mlx5_glue->destroy_qp(txq_ibv->qp));
610 claim_zero(mlx5_glue->destroy_cq(txq_ibv->cq));
611 LIST_REMOVE(txq_ibv, next);
619 * Return true if a single reference exists on the object.
622 * Verbs Tx queue object.
625 mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv)
628 return (rte_atomic32_read(&txq_ibv->refcnt) == 1);
632 * Verify the Verbs Tx queue list is empty
635 * Pointer to Ethernet device.
638 * The number of object not released.
641 mlx5_txq_ibv_verify(struct rte_eth_dev *dev)
643 struct priv *priv = dev->data->dev_private;
645 struct mlx5_txq_ibv *txq_ibv;
647 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
648 DEBUG("port %u Verbs Tx queue %u still referenced",
650 txq_ibv->txq_ctrl->idx);
657 * Set Tx queue parameters from device configuration.
660 * Pointer to Tx queue control structure.
663 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
665 struct priv *priv = txq_ctrl->priv;
666 struct mlx5_dev_config *config = &priv->config;
667 const unsigned int max_tso_inline =
668 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) /
669 RTE_CACHE_LINE_SIZE);
670 unsigned int txq_inline;
671 unsigned int txqs_inline;
672 unsigned int inline_max_packet_sz;
673 eth_tx_burst_t tx_pkt_burst =
674 mlx5_select_tx_function(txq_ctrl->priv->dev);
675 int is_empw_func = is_empw_burst_func(tx_pkt_burst);
676 int tso = !!(txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_TCP_TSO);
678 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ?
679 0 : config->txq_inline;
680 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ?
681 0 : config->txqs_inline;
682 inline_max_packet_sz =
683 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ?
684 0 : config->inline_max_packet_sz;
686 if (config->txq_inline == MLX5_ARG_UNSET)
687 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
688 if (config->txqs_inline == MLX5_ARG_UNSET)
689 txqs_inline = MLX5_EMPW_MIN_TXQS;
690 if (config->inline_max_packet_sz == MLX5_ARG_UNSET)
691 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
692 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg;
693 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz;
695 if (txq_inline && priv->txqs_n >= txqs_inline) {
698 txq_ctrl->txq.max_inline =
699 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
700 RTE_CACHE_LINE_SIZE);
702 /* To minimize the size of data set, avoid requesting
705 txq_ctrl->max_inline_data =
706 ((RTE_MIN(txq_inline,
707 inline_max_packet_sz) +
708 (RTE_CACHE_LINE_SIZE - 1)) /
709 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
711 int inline_diff = txq_ctrl->txq.max_inline -
715 * Adjust inline value as Verbs aggregates
716 * tso_inline and txq_inline fields.
718 txq_ctrl->max_inline_data = inline_diff > 0 ?
720 RTE_CACHE_LINE_SIZE :
723 txq_ctrl->max_inline_data =
724 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE;
727 * Check if the inline size is too large in a way which
728 * can make the WQE DS to overflow.
729 * Considering in calculation:
734 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE);
735 if (ds_cnt > MLX5_DSEG_MAX) {
736 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
739 max_inline = max_inline - (max_inline %
740 RTE_CACHE_LINE_SIZE);
741 WARN("port %u txq inline is too large (%d) setting it"
742 " to the maximum possible: %d\n",
743 priv->dev->data->port_id, txq_inline, max_inline);
744 txq_ctrl->txq.max_inline = max_inline /
749 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE;
750 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline,
752 txq_ctrl->txq.tso_en = 1;
754 txq_ctrl->txq.tunnel_en = config->tunnel_en;
758 * Create a DPDK Tx queue.
761 * Pointer to Ethernet device.
765 * Number of descriptors to configure in queue.
767 * NUMA socket on which memory must be allocated.
769 * Thresholds parameters.
772 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
774 struct mlx5_txq_ctrl *
775 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
776 unsigned int socket, const struct rte_eth_txconf *conf)
778 struct priv *priv = dev->data->dev_private;
779 struct mlx5_txq_ctrl *tmpl;
781 tmpl = rte_calloc_socket("TXQ", 1,
783 desc * sizeof(struct rte_mbuf *),
789 assert(desc > MLX5_TX_COMP_THRESH);
790 tmpl->txq.offloads = conf->offloads;
792 tmpl->socket = socket;
793 tmpl->txq.elts_n = log2above(desc);
795 txq_set_params(tmpl);
796 /* MRs will be registered in mp2mr[] later. */
797 DEBUG("port %u priv->device_attr.max_qp_wr is %d", dev->data->port_id,
798 priv->device_attr.orig_attr.max_qp_wr);
799 DEBUG("port %u priv->device_attr.max_sge is %d", dev->data->port_id,
800 priv->device_attr.orig_attr.max_sge);
802 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
803 tmpl->txq.stats.idx = idx;
804 rte_atomic32_inc(&tmpl->refcnt);
805 DEBUG("port %u Tx queue %u: refcnt %d", dev->data->port_id,
806 idx, rte_atomic32_read(&tmpl->refcnt));
807 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
815 * Pointer to Ethernet device.
820 * A pointer to the queue if it exists.
822 struct mlx5_txq_ctrl *
823 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
825 struct priv *priv = dev->data->dev_private;
826 struct mlx5_txq_ctrl *ctrl = NULL;
828 if ((*priv->txqs)[idx]) {
829 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
833 mlx5_txq_ibv_get(dev, idx);
834 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
835 if (ctrl->txq.mp2mr[i])
838 ctrl->txq.mp2mr[i]->mp));
840 rte_atomic32_inc(&ctrl->refcnt);
841 DEBUG("port %u Tx queue %u refcnt %d", dev->data->port_id,
842 ctrl->idx, rte_atomic32_read(&ctrl->refcnt));
848 * Release a Tx queue.
851 * Pointer to Ethernet device.
856 * 1 while a reference on it exists, 0 when freed.
859 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
861 struct priv *priv = dev->data->dev_private;
863 struct mlx5_txq_ctrl *txq;
864 size_t page_size = sysconf(_SC_PAGESIZE);
866 if (!(*priv->txqs)[idx])
868 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
869 DEBUG("port %u Tx queue %u: refcnt %d", dev->data->port_id,
870 txq->idx, rte_atomic32_read(&txq->refcnt));
871 if (txq->ibv && !mlx5_txq_ibv_release(txq->ibv))
873 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
874 if (txq->txq.mp2mr[i]) {
875 mlx5_mr_release(txq->txq.mp2mr[i]);
876 txq->txq.mp2mr[i] = NULL;
880 munmap((void *)RTE_ALIGN_FLOOR((uintptr_t)txq->txq.bf_reg,
881 page_size), page_size);
882 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
884 LIST_REMOVE(txq, next);
886 (*priv->txqs)[idx] = NULL;
893 * Verify if the queue can be released.
896 * Pointer to Ethernet device.
901 * 1 if the queue can be released.
904 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
906 struct priv *priv = dev->data->dev_private;
907 struct mlx5_txq_ctrl *txq;
909 if (!(*priv->txqs)[idx])
911 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
912 return (rte_atomic32_read(&txq->refcnt) == 1);
916 * Verify the Tx Queue list is empty
919 * Pointer to Ethernet device.
922 * The number of object not released.
925 mlx5_txq_verify(struct rte_eth_dev *dev)
927 struct priv *priv = dev->data->dev_private;
928 struct mlx5_txq_ctrl *txq;
931 LIST_FOREACH(txq, &priv->txqsctrl, next) {
932 DEBUG("port %u Tx queue %u still referenced",
933 dev->data->port_id, txq->idx);