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5 * Copyright 2015 Mellanox.
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41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
47 #pragma GCC diagnostic error "-Wpedantic"
51 #include <rte_malloc.h>
52 #include <rte_ethdev.h>
53 #include <rte_common.h>
55 #include "mlx5_utils.h"
56 #include "mlx5_defs.h"
58 #include "mlx5_rxtx.h"
59 #include "mlx5_autoconf.h"
62 * Allocate TX queue elements.
65 * Pointer to TX queue structure.
67 * Number of elements to allocate.
70 txq_alloc_elts(struct txq_ctrl *txq_ctrl, unsigned int elts_n)
74 for (i = 0; (i != elts_n); ++i)
75 (*txq_ctrl->txq.elts)[i] = NULL;
76 for (i = 0; (i != (1u << txq_ctrl->txq.wqe_n)); ++i) {
77 volatile struct mlx5_wqe64 *wqe =
78 (volatile struct mlx5_wqe64 *)
79 txq_ctrl->txq.wqes + i;
81 memset((void *)(uintptr_t)wqe, 0x0, sizeof(*wqe));
83 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
84 txq_ctrl->txq.elts_head = 0;
85 txq_ctrl->txq.elts_tail = 0;
86 txq_ctrl->txq.elts_comp = 0;
90 * Free TX queue elements.
93 * Pointer to TX queue structure.
96 txq_free_elts(struct txq_ctrl *txq_ctrl)
98 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
99 const uint16_t elts_m = elts_n - 1;
100 uint16_t elts_head = txq_ctrl->txq.elts_head;
101 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
102 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
104 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
105 txq_ctrl->txq.elts_head = 0;
106 txq_ctrl->txq.elts_tail = 0;
107 txq_ctrl->txq.elts_comp = 0;
109 while (elts_tail != elts_head) {
110 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
113 rte_pktmbuf_free_seg(elt);
116 memset(&(*elts)[elts_tail & elts_m],
118 sizeof((*elts)[elts_tail & elts_m]));
125 * Clean up a TX queue.
127 * Destroy objects, free allocated memory and reset the structure for reuse.
130 * Pointer to TX queue structure.
133 txq_cleanup(struct txq_ctrl *txq_ctrl)
137 DEBUG("cleaning up %p", (void *)txq_ctrl);
138 txq_free_elts(txq_ctrl);
139 if (txq_ctrl->qp != NULL)
140 claim_zero(ibv_destroy_qp(txq_ctrl->qp));
141 if (txq_ctrl->cq != NULL)
142 claim_zero(ibv_destroy_cq(txq_ctrl->cq));
143 for (i = 0; (i != RTE_DIM(txq_ctrl->txq.mp2mr)); ++i) {
144 if (txq_ctrl->txq.mp2mr[i].mr == NULL)
146 claim_zero(ibv_dereg_mr(txq_ctrl->txq.mp2mr[i].mr));
148 memset(txq_ctrl, 0, sizeof(*txq_ctrl));
152 * Initialize TX queue.
155 * Pointer to TX queue control template.
157 * Pointer to TX queue control.
160 * 0 on success, errno value on failure.
163 txq_setup(struct txq_ctrl *tmpl, struct txq_ctrl *txq_ctrl)
166 struct ibv_cq *ibcq = tmpl->cq;
167 struct mlx5dv_cq cq_info;
168 struct mlx5dv_obj obj;
172 obj.cq.out = &cq_info;
173 obj.qp.in = tmpl->qp;
175 ret = mlx5dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
179 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
180 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
181 "it should be set to %u", RTE_CACHE_LINE_SIZE);
184 tmpl->txq.cqe_n = log2above(cq_info.cqe_cnt);
185 tmpl->txq.qp_num_8s = tmpl->qp->qp_num << 8;
186 tmpl->txq.wqes = qp.sq.buf;
187 tmpl->txq.wqe_n = log2above(qp.sq.wqe_cnt);
188 tmpl->txq.qp_db = &qp.dbrec[MLX5_SND_DBR];
189 tmpl->txq.bf_reg = qp.bf.reg;
190 tmpl->txq.cq_db = cq_info.dbrec;
192 (volatile struct mlx5_cqe (*)[])
193 (uintptr_t)cq_info.buf;
195 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])
196 ((uintptr_t)txq_ctrl + sizeof(*txq_ctrl));
201 * Configure a TX queue.
204 * Pointer to Ethernet device structure.
206 * Pointer to TX queue structure.
208 * Number of descriptors to configure in queue.
210 * NUMA socket on which memory must be allocated.
212 * Thresholds parameters.
215 * 0 on success, errno value on failure.
218 txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
219 uint16_t desc, unsigned int socket,
220 const struct rte_eth_txconf *conf)
222 struct priv *priv = mlx5_get_priv(dev);
223 struct txq_ctrl tmpl = {
228 struct ibv_qp_init_attr_ex init;
229 struct ibv_cq_init_attr_ex cq;
230 struct ibv_qp_attr mod;
231 struct ibv_cq_ex cq_attr;
234 const unsigned int max_tso_inline = ((MLX5_MAX_TSO_HEADER +
235 (RTE_CACHE_LINE_SIZE - 1)) /
236 RTE_CACHE_LINE_SIZE);
239 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
241 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
244 tmpl.txq.flags = conf->txq_flags;
245 assert(desc > MLX5_TX_COMP_THRESH);
246 tmpl.txq.elts_n = log2above(desc);
247 if (priv->mps == MLX5_MPW_ENHANCED)
248 tmpl.txq.mpw_hdr_dseg = priv->mpw_hdr_dseg;
249 /* MRs will be registered in mp2mr[] later. */
250 attr.cq = (struct ibv_cq_init_attr_ex){
253 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
254 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
255 if (priv->mps == MLX5_MPW_ENHANCED)
256 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
257 tmpl.cq = ibv_create_cq(priv->ctx,
260 if (tmpl.cq == NULL) {
262 ERROR("%p: CQ creation failure: %s",
263 (void *)dev, strerror(ret));
266 DEBUG("priv->device_attr.max_qp_wr is %d",
267 priv->device_attr.orig_attr.max_qp_wr);
268 DEBUG("priv->device_attr.max_sge is %d",
269 priv->device_attr.orig_attr.max_sge);
270 attr.init = (struct ibv_qp_init_attr_ex){
271 /* CQ to be associated with the send queue. */
273 /* CQ to be associated with the receive queue. */
276 /* Max number of outstanding WRs. */
278 ((priv->device_attr.orig_attr.max_qp_wr < desc) ?
279 priv->device_attr.orig_attr.max_qp_wr :
282 * Max number of scatter/gather elements in a WR,
283 * must be 1 to prevent libmlx5 from trying to affect
284 * too much memory. TX gather is not impacted by the
285 * priv->device_attr.max_sge limit and will still work
290 .qp_type = IBV_QPT_RAW_PACKET,
291 /* Do *NOT* enable this, completions events are managed per
295 .comp_mask = IBV_QP_INIT_ATTR_PD,
297 if (priv->txq_inline && (priv->txqs_n >= priv->txqs_inline)) {
300 tmpl.txq.max_inline =
301 ((priv->txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
302 RTE_CACHE_LINE_SIZE);
303 tmpl.txq.inline_en = 1;
304 /* TSO and MPS can't be enabled concurrently. */
305 assert(!priv->tso || !priv->mps);
306 if (priv->mps == MLX5_MPW_ENHANCED) {
307 tmpl.txq.inline_max_packet_sz =
308 priv->inline_max_packet_sz;
309 /* To minimize the size of data set, avoid requesting
312 attr.init.cap.max_inline_data =
313 ((RTE_MIN(priv->txq_inline,
314 priv->inline_max_packet_sz) +
315 (RTE_CACHE_LINE_SIZE - 1)) /
316 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
317 } else if (priv->tso) {
318 int inline_diff = tmpl.txq.max_inline - max_tso_inline;
321 * Adjust inline value as Verbs aggregates
322 * tso_inline and txq_inline fields.
324 attr.init.cap.max_inline_data = inline_diff > 0 ?
326 RTE_CACHE_LINE_SIZE :
329 attr.init.cap.max_inline_data =
330 tmpl.txq.max_inline * RTE_CACHE_LINE_SIZE;
333 * Check if the inline size is too large in a way which
334 * can make the WQE DS to overflow.
335 * Considering in calculation:
341 (attr.init.cap.max_inline_data / MLX5_WQE_DWORD_SIZE);
342 if (ds_cnt > MLX5_DSEG_MAX) {
343 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
346 max_inline = max_inline - (max_inline %
347 RTE_CACHE_LINE_SIZE);
348 WARN("txq inline is too large (%d) setting it to "
349 "the maximum possible: %d\n",
350 priv->txq_inline, max_inline);
351 tmpl.txq.max_inline = max_inline / RTE_CACHE_LINE_SIZE;
352 attr.init.cap.max_inline_data = max_inline;
356 attr.init.max_tso_header =
357 max_tso_inline * RTE_CACHE_LINE_SIZE;
358 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
359 tmpl.txq.max_inline = RTE_MAX(tmpl.txq.max_inline,
364 tmpl.txq.tunnel_en = 1;
365 tmpl.qp = ibv_create_qp_ex(priv->ctx, &attr.init);
366 if (tmpl.qp == NULL) {
367 ret = (errno ? errno : EINVAL);
368 ERROR("%p: QP creation failure: %s",
369 (void *)dev, strerror(ret));
372 DEBUG("TX queue capabilities: max_send_wr=%u, max_send_sge=%u,"
373 " max_inline_data=%u",
374 attr.init.cap.max_send_wr,
375 attr.init.cap.max_send_sge,
376 attr.init.cap.max_inline_data);
377 attr.mod = (struct ibv_qp_attr){
378 /* Move the QP to this state. */
379 .qp_state = IBV_QPS_INIT,
380 /* Primary port number. */
381 .port_num = priv->port
383 ret = ibv_modify_qp(tmpl.qp, &attr.mod,
384 (IBV_QP_STATE | IBV_QP_PORT));
386 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
387 (void *)dev, strerror(ret));
390 ret = txq_setup(&tmpl, txq_ctrl);
392 ERROR("%p: cannot initialize TX queue structure: %s",
393 (void *)dev, strerror(ret));
396 txq_alloc_elts(&tmpl, desc);
397 attr.mod = (struct ibv_qp_attr){
398 .qp_state = IBV_QPS_RTR
400 ret = ibv_modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
402 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
403 (void *)dev, strerror(ret));
406 attr.mod.qp_state = IBV_QPS_RTS;
407 ret = ibv_modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
409 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
410 (void *)dev, strerror(ret));
413 /* Clean up txq in case we're reinitializing it. */
414 DEBUG("%p: cleaning-up old txq just in case", (void *)txq_ctrl);
415 txq_cleanup(txq_ctrl);
417 DEBUG("%p: txq updated with %p", (void *)txq_ctrl, (void *)&tmpl);
418 /* Pre-register known mempools. */
419 rte_mempool_walk(txq_mp2mr_iter, txq_ctrl);
429 * DPDK callback to configure a TX queue.
432 * Pointer to Ethernet device structure.
436 * Number of descriptors to configure in queue.
438 * NUMA socket on which memory must be allocated.
440 * Thresholds parameters.
443 * 0 on success, negative errno value on failure.
446 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
447 unsigned int socket, const struct rte_eth_txconf *conf)
449 struct priv *priv = dev->data->dev_private;
450 struct txq *txq = (*priv->txqs)[idx];
451 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
454 if (mlx5_is_secondary())
455 return -E_RTE_SECONDARY;
458 if (desc <= MLX5_TX_COMP_THRESH) {
459 WARN("%p: number of descriptors requested for TX queue %u"
460 " must be higher than MLX5_TX_COMP_THRESH, using"
462 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
463 desc = MLX5_TX_COMP_THRESH + 1;
465 if (!rte_is_power_of_2(desc)) {
466 desc = 1 << log2above(desc);
467 WARN("%p: increased number of descriptors in TX queue %u"
468 " to the next power of two (%d)",
469 (void *)dev, idx, desc);
471 DEBUG("%p: configuring queue %u for %u descriptors",
472 (void *)dev, idx, desc);
473 if (idx >= priv->txqs_n) {
474 ERROR("%p: queue index out of range (%u >= %u)",
475 (void *)dev, idx, priv->txqs_n);
480 DEBUG("%p: reusing already allocated queue index %u (%p)",
481 (void *)dev, idx, (void *)txq);
486 (*priv->txqs)[idx] = NULL;
487 txq_cleanup(txq_ctrl);
488 /* Resize if txq size is changed. */
489 if (txq_ctrl->txq.elts_n != log2above(desc)) {
490 txq_ctrl = rte_realloc(txq_ctrl,
492 desc * sizeof(struct rte_mbuf *),
493 RTE_CACHE_LINE_SIZE);
495 ERROR("%p: unable to reallocate queue index %u",
503 rte_calloc_socket("TXQ", 1,
505 desc * sizeof(struct rte_mbuf *),
507 if (txq_ctrl == NULL) {
508 ERROR("%p: unable to allocate queue index %u",
514 ret = txq_ctrl_setup(dev, txq_ctrl, desc, socket, conf);
518 txq_ctrl->txq.stats.idx = idx;
519 DEBUG("%p: adding TX queue %p to list",
520 (void *)dev, (void *)txq_ctrl);
521 (*priv->txqs)[idx] = &txq_ctrl->txq;
528 * DPDK callback to release a TX queue.
531 * Generic TX queue pointer.
534 mlx5_tx_queue_release(void *dpdk_txq)
536 struct txq *txq = (struct txq *)dpdk_txq;
537 struct txq_ctrl *txq_ctrl;
541 if (mlx5_is_secondary())
546 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
547 priv = txq_ctrl->priv;
549 for (i = 0; (i != priv->txqs_n); ++i)
550 if ((*priv->txqs)[i] == txq) {
551 DEBUG("%p: removing TX queue %p from list",
552 (void *)priv->dev, (void *)txq_ctrl);
553 (*priv->txqs)[i] = NULL;
556 txq_cleanup(txq_ctrl);