drivers/net/mlx5/windows/mlx5_os.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <errno.h>
   6 #include <stdalign.h>
   7 #include <stddef.h>
   8 #include <stdint.h>
   9 #include <stdlib.h>
  10
  11 #include <rte_windows.h>
  12 #include <ethdev_pci.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_devx_cmds.h>
  16 #include <mlx5_common.h>
  17 #include <mlx5_common_mp.h>
  18 #include <mlx5_common_mr.h>
  19 #include <mlx5_malloc.h>
  20
  21 #include "mlx5_defs.h"
  22 #include "mlx5.h"
  23 #include "mlx5_common_os.h"
  24 #include "mlx5_utils.h"
  25 #include "mlx5_rxtx.h"
  26 #include "mlx5_rx.h"
  27 #include "mlx5_tx.h"
  28 #include "mlx5_autoconf.h"
  29 #include "mlx5_flow.h"
  30 #include "mlx5_devx.h"
  31
  32 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
  33
  34 /* Spinlock for mlx5_shared_data allocation. */
  35 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
  36
  37 /* rte flow indexed pool configuration. */
  38 static struct mlx5_indexed_pool_config icfg[] = {
  39         {
  40                 .size = sizeof(struct rte_flow),
  41                 .trunk_size = 64,
  42                 .need_lock = 1,
  43                 .release_mem_en = 0,
  44                 .malloc = mlx5_malloc,
  45                 .free = mlx5_free,
  46                 .per_core_cache = 0,
  47                 .type = "ctl_flow_ipool",
  48         },
  49         {
  50                 .size = sizeof(struct rte_flow),
  51                 .trunk_size = 64,
  52                 .grow_trunk = 3,
  53                 .grow_shift = 2,
  54                 .need_lock = 1,
  55                 .release_mem_en = 0,
  56                 .malloc = mlx5_malloc,
  57                 .free = mlx5_free,
  58                 .per_core_cache = 1 << 14,
  59                 .type = "rte_flow_ipool",
  60         },
  61         {
  62                 .size = sizeof(struct rte_flow),
  63                 .trunk_size = 64,
  64                 .grow_trunk = 3,
  65                 .grow_shift = 2,
  66                 .need_lock = 1,
  67                 .release_mem_en = 0,
  68                 .malloc = mlx5_malloc,
  69                 .free = mlx5_free,
  70                 .per_core_cache = 0,
  71                 .type = "mcp_flow_ipool",
  72         },
  73 };
  74
  75 static void
  76 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev)
  77 {
  78         struct mlx5_priv *priv = dev->data->dev_private;
  79         void *ctx = priv->sh->cdev->ctx;
  80
  81         priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx);
  82         if (!priv->q_counters) {
  83                 DRV_LOG(ERR, "Port %d queue counter object cannot be created "
  84                         "by DevX - imissed counter will be unavailable",
  85                         dev->data->port_id);
  86                 return;
  87         }
  88         priv->counter_set_id = priv->q_counters->id;
  89 }
  90
  91 /**
  92  * Initialize shared data between primary and secondary process.
  93  *
  94  * A memzone is reserved by primary process and secondary processes attach to
  95  * the memzone.
  96  *
  97  * @return
  98  *   0 on success, a negative errno value otherwise and rte_errno is set.
  99  */
 100 static int
 101 mlx5_init_shared_data(void)
 102 {
 103         const struct rte_memzone *mz;
 104         int ret = 0;
 105
 106         rte_spinlock_lock(&mlx5_shared_data_lock);
 107         if (mlx5_shared_data == NULL) {
 108                 /* Allocate shared memory. */
 109                 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 110                                          sizeof(*mlx5_shared_data),
 111                                          SOCKET_ID_ANY, 0);
 112                 if (mz == NULL) {
 113                         DRV_LOG(ERR,
 114                                 "Cannot allocate mlx5 shared data");
 115                         ret = -rte_errno;
 116                         goto error;
 117                 }
 118                 mlx5_shared_data = mz->addr;
 119                 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 120                 rte_spinlock_init(&mlx5_shared_data->lock);
 121         }
 122 error:
 123         rte_spinlock_unlock(&mlx5_shared_data_lock);
 124         return ret;
 125 }
 126
 127 /**
 128  * PMD global initialization.
 129  *
 130  * Independent from individual device, this function initializes global
 131  * per-PMD data structures distinguishing primary and secondary processes.
 132  * Hence, each initialization is called once per a process.
 133  *
 134  * @return
 135  *   0 on success, a negative errno value otherwise and rte_errno is set.
 136  */
 137 static int
 138 mlx5_init_once(void)
 139 {
 140         if (mlx5_init_shared_data())
 141                 return -rte_errno;
 142         return 0;
 143 }
 144
 145 /**
 146  * Get mlx5 device attributes.
 147  *
 148  * @param cdev
 149  *   Pointer to mlx5 device.
 150  *
 151  * @param device_attr
 152  *   Pointer to mlx5 device attributes.
 153  *
 154  * @return
 155  *   0 on success, a negative errno value otherwise and rte_errno is set.
 156  */
 157 int
 158 mlx5_os_get_dev_attr(struct mlx5_common_device *cdev,
 159                      struct mlx5_dev_attr *device_attr)
 160 {
 161         struct mlx5_context *mlx5_ctx;
 162         void *pv_iseg = NULL;
 163         u32 cb_iseg = 0;
 164
 165         if (!cdev || !cdev->ctx) {
 166                 rte_errno = EINVAL;
 167                 return -rte_errno;
 168         }
 169         mlx5_ctx = (struct mlx5_context *)cdev->ctx;
 170         memset(device_attr, 0, sizeof(*device_attr));
 171         device_attr->max_cq = 1 << cdev->config.hca_attr.log_max_cq;
 172         device_attr->max_qp = 1 << cdev->config.hca_attr.log_max_qp;
 173         device_attr->max_qp_wr = 1 << cdev->config.hca_attr.log_max_qp_sz;
 174         device_attr->max_cqe = 1 << cdev->config.hca_attr.log_max_cq_sz;
 175         device_attr->max_mr = 1 << cdev->config.hca_attr.log_max_mrw_sz;
 176         device_attr->max_pd = 1 << cdev->config.hca_attr.log_max_pd;
 177         device_attr->max_srq = 1 << cdev->config.hca_attr.log_max_srq;
 178         device_attr->max_srq_wr = 1 << cdev->config.hca_attr.log_max_srq_sz;
 179         device_attr->max_tso = 1 << cdev->config.hca_attr.max_lso_cap;
 180         if (cdev->config.hca_attr.rss_ind_tbl_cap) {
 181                 device_attr->max_rwq_indirection_table_size =
 182                         1 << cdev->config.hca_attr.rss_ind_tbl_cap;
 183         }
 184         device_attr->sw_parsing_offloads =
 185                 mlx5_get_supported_sw_parsing_offloads(&cdev->config.hca_attr);
 186         device_attr->tunnel_offloads_caps =
 187                 mlx5_get_supported_tunneling_offloads(&cdev->config.hca_attr);
 188         pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
 189         if (pv_iseg == NULL) {
 190                 DRV_LOG(ERR, "Failed to get device hca_iseg");
 191                 rte_errno = errno;
 192                 return -rte_errno;
 193         }
 194         snprintf(device_attr->fw_ver, 64, "%x.%x.%04x",
 195                  MLX5_GET(initial_seg, pv_iseg, fw_rev_major),
 196                  MLX5_GET(initial_seg, pv_iseg, fw_rev_minor),
 197                  MLX5_GET(initial_seg, pv_iseg, fw_rev_subminor));
 198         return 0;
 199 }
 200
 201 /**
 202  * Initialize DR related data within private structure.
 203  * Routine checks the reference counter and does actual
 204  * resources creation/initialization only if counter is zero.
 205  *
 206  * @param[in] priv
 207  *   Pointer to the private device data structure.
 208  *
 209  * @return
 210  *   Zero on success, positive error code otherwise.
 211  */
 212 static int
 213 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
 214 {
 215         struct mlx5_dev_ctx_shared *sh = priv->sh;
 216         int err = 0;
 217
 218         if (!sh->flow_tbls)
 219                 err = mlx5_alloc_table_hash_list(priv);
 220         else
 221                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse",
 222                         (void *)sh->flow_tbls);
 223         return err;
 224 }
 225 /**
 226  * Destroy DR related data within private structure.
 227  *
 228  * @param[in] priv
 229  *   Pointer to the private device data structure.
 230  */
 231 void
 232 mlx5_os_free_shared_dr(struct mlx5_priv *priv)
 233 {
 234         mlx5_free_table_hash_list(priv);
 235 }
 236
 237 /**
 238  * Set the completion channel file descriptor interrupt as non-blocking.
 239  * Currently it has no support under Windows.
 240  *
 241  * @param[in] rxq_obj
 242  *   Pointer to RQ channel object, which includes the channel fd
 243  *
 244  * @param[out] fd
 245  *   The file descriptor (representing the interrupt) used in this channel.
 246  *
 247  * @return
 248  *   0 on successfully setting the fd to non-blocking, non-zero otherwise.
 249  */
 250 int
 251 mlx5_os_set_nonblock_channel_fd(int fd)
 252 {
 253         (void)fd;
 254         DRV_LOG(WARNING, "%s: is not supported", __func__);
 255         return -ENOTSUP;
 256 }
 257
 258 /**
 259  * DV flow counter mode detect and config.
 260  *
 261  * @param dev
 262  *   Pointer to rte_eth_dev structure.
 263  *
 264  */
 265 static void
 266 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
 267 {
 268 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 269         struct mlx5_priv *priv = dev->data->dev_private;
 270         struct mlx5_dev_ctx_shared *sh = priv->sh;
 271         struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;
 272         bool fallback;
 273
 274 #ifndef HAVE_IBV_DEVX_ASYNC
 275         fallback = true;
 276 #else
 277         fallback = false;
 278         if (!sh->devx || !priv->config.dv_flow_en ||
 279             !hca_attr->flow_counters_dump ||
 280             !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||
 281             (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
 282                 fallback = true;
 283 #endif
 284         if (fallback)
 285                 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
 286                         "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
 287                         hca_attr->flow_counters_dump,
 288                         hca_attr->flow_counter_bulk_alloc_bitmap);
 289         /* Initialize fallback mode only on the port initializes sh. */
 290         if (sh->refcnt == 1)
 291                 sh->cmng.counter_fallback = fallback;
 292         else if (fallback != sh->cmng.counter_fallback)
 293                 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
 294                         "with others:%d.", PORT_ID(priv), fallback);
 295 #endif
 296 }
 297
 298 /**
 299  * Spawn an Ethernet device from DevX information.
 300  *
 301  * @param dpdk_dev
 302  *   Backing DPDK device.
 303  * @param spawn
 304  *   Verbs device parameters (name, port, switch_info) to spawn.
 305  * @param config
 306  *   Device configuration parameters.
 307  *
 308  * @return
 309  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
 310  *   is set. The following errors are defined:
 311  *
 312  *   EEXIST: device is already spawned
 313  */
 314 static struct rte_eth_dev *
 315 mlx5_dev_spawn(struct rte_device *dpdk_dev,
 316                struct mlx5_dev_spawn_data *spawn,
 317                struct mlx5_dev_config *config)
 318 {
 319         const struct mlx5_switch_info *switch_info = &spawn->info;
 320         struct mlx5_dev_ctx_shared *sh = NULL;
 321         struct mlx5_dev_attr device_attr;
 322         struct mlx5_hca_attr *hca_attr;
 323         struct rte_eth_dev *eth_dev = NULL;
 324         struct mlx5_priv *priv = NULL;
 325         int err = 0;
 326         struct rte_ether_addr mac;
 327         char name[RTE_ETH_NAME_MAX_LEN];
 328         int own_domain_id = 0;
 329         uint16_t port_id;
 330         int i;
 331
 332         /* Build device name. */
 333         strlcpy(name, dpdk_dev->name, sizeof(name));
 334         /* check if the device is already spawned */
 335         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
 336                 rte_errno = EEXIST;
 337                 return NULL;
 338         }
 339         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
 340         /* Process parameters. */
 341         err = mlx5_args(config, dpdk_dev->devargs);
 342         if (err) {
 343                 err = rte_errno;
 344                 DRV_LOG(ERR, "failed to process device arguments: %s",
 345                         strerror(rte_errno));
 346                 goto error;
 347         }
 348         sh = mlx5_alloc_shared_dev_ctx(spawn, config);
 349         if (!sh)
 350                 return NULL;
 351         /* Update final values for devargs before check sibling config. */
 352         config->dv_esw_en = 0;
 353         if (!config->dv_flow_en) {
 354                 DRV_LOG(ERR, "Windows flow mode must be DV flow enable.");
 355                 err = ENOTSUP;
 356                 goto error;
 357         }
 358         if (!config->dv_esw_en &&
 359             config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
 360                 DRV_LOG(WARNING,
 361                         "Metadata mode %u is not supported (no E-Switch).",
 362                         config->dv_xmeta_en);
 363                 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
 364         }
 365         /* Check sibling device configurations. */
 366         err = mlx5_dev_check_sibling_config(sh, config, dpdk_dev);
 367         if (err)
 368                 goto error;
 369         /* Initialize the shutdown event in mlx5_dev_spawn to
 370          * support mlx5_is_removed for Windows.
 371          */
 372         err = mlx5_glue->devx_init_showdown_event(sh->cdev->ctx);
 373         if (err) {
 374                 DRV_LOG(ERR, "failed to init showdown event: %s",
 375                         strerror(errno));
 376                 goto error;
 377         }
 378         DRV_LOG(DEBUG, "MPW isn't supported");
 379         mlx5_os_get_dev_attr(sh->cdev, &device_attr);
 380         config->swp = device_attr.sw_parsing_offloads &
 381                 (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
 382                  MLX5_SW_PARSING_TSO_CAP);
 383         config->ind_table_max_size =
 384                 sh->device_attr.max_rwq_indirection_table_size;
 385         config->tunnel_en = device_attr.tunnel_offloads_caps &
 386                 (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |
 387                  MLX5_TUNNELED_OFFLOADS_GRE_CAP |
 388                  MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);
 389         if (config->tunnel_en) {
 390                 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
 391                 config->tunnel_en &
 392                 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "",
 393                 config->tunnel_en &
 394                 MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "",
 395                 config->tunnel_en &
 396                 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""
 397                 );
 398         } else {
 399                 DRV_LOG(DEBUG, "tunnel offloading is not supported");
 400         }
 401         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported");
 402         config->mpls_en = 0;
 403         /* Allocate private eth device data. */
 404         priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 405                            sizeof(*priv),
 406                            RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 407         if (priv == NULL) {
 408                 DRV_LOG(ERR, "priv allocation failure");
 409                 err = ENOMEM;
 410                 goto error;
 411         }
 412         priv->sh = sh;
 413         priv->dev_port = spawn->phys_port;
 414         priv->pci_dev = spawn->pci_dev;
 415         priv->mtu = RTE_ETHER_MTU;
 416         priv->mp_id.port_id = port_id;
 417         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
 418         priv->representor = !!switch_info->representor;
 419         priv->master = !!switch_info->master;
 420         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
 421         priv->vport_meta_tag = 0;
 422         priv->vport_meta_mask = 0;
 423         priv->pf_bond = spawn->pf_bond;
 424         priv->vport_id = -1;
 425         /* representor_id field keeps the unmodified VF index. */
 426         priv->representor_id = -1;
 427         /*
 428          * Look for sibling devices in order to reuse their switch domain
 429          * if any, otherwise allocate one.
 430          */
 431         MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
 432                 const struct mlx5_priv *opriv =
 433                         rte_eth_devices[port_id].data->dev_private;
 434
 435                 if (!opriv ||
 436                     opriv->sh != priv->sh ||
 437                         opriv->domain_id ==
 438                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
 439                         continue;
 440                 priv->domain_id = opriv->domain_id;
 441                 break;
 442         }
 443         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
 444                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
 445                 if (err) {
 446                         err = rte_errno;
 447                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
 448                                 strerror(rte_errno));
 449                         goto error;
 450                 }
 451                 own_domain_id = 1;
 452         }
 453         DRV_LOG(DEBUG, "counters are not supported");
 454         config->ind_table_max_size =
 455                 sh->device_attr.max_rwq_indirection_table_size;
 456         /*
 457          * Remove this check once DPDK supports larger/variable
 458          * indirection tables.
 459          */
 460         if (config->ind_table_max_size > (unsigned int)RTE_ETH_RSS_RETA_SIZE_512)
 461                 config->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512;
 462         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 463                 config->ind_table_max_size);
 464         if (config->hw_padding) {
 465                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
 466                 config->hw_padding = 0;
 467         }
 468         config->tso = (sh->device_attr.max_tso > 0);
 469         if (config->tso)
 470                 config->tso_max_payload_sz = sh->device_attr.max_tso;
 471         DRV_LOG(DEBUG, "%sMPS is %s.",
 472                 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
 473                 config->mps == MLX5_MPW ? "legacy " : "",
 474                 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
 475         if (config->cqe_comp) {
 476                 DRV_LOG(WARNING, "Rx CQE compression isn't supported.");
 477                 config->cqe_comp = 0;
 478         }
 479         if (sh->devx) {
 480                 hca_attr = &sh->cdev->config.hca_attr;
 481                 config->hw_csum = hca_attr->csum_cap;
 482                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 483                         (config->hw_csum ? "" : "not "));
 484                 config->hw_vlan_strip = hca_attr->vlan_cap;
 485                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 486                         (config->hw_vlan_strip ? "" : "not "));
 487                 config->hw_fcs_strip = hca_attr->scatter_fcs;
 488         }
 489         if (sh->devx) {
 490                 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
 491
 492                 err = hca_attr->access_register_user ?
 493                         mlx5_devx_cmd_register_read
 494                                 (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,
 495                                 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
 496                 if (!err) {
 497                         uint32_t ts_mode;
 498
 499                         /* MTUTC register is read successfully. */
 500                         ts_mode = MLX5_GET(register_mtutc, reg,
 501                                            time_stamp_mode);
 502                         if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
 503                                 config->rt_timestamp = 1;
 504                 } else {
 505                         /* Kernel does not support register reading. */
 506                         if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))
 507                                 config->rt_timestamp = 1;
 508                 }
 509         }
 510         if (config->mprq.enabled) {
 511                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
 512                 config->mprq.enabled = 0;
 513         }
 514         if (config->max_dump_files_num == 0)
 515                 config->max_dump_files_num = 128;
 516         eth_dev = rte_eth_dev_allocate(name);
 517         if (eth_dev == NULL) {
 518                 DRV_LOG(ERR, "can not allocate rte ethdev");
 519                 err = ENOMEM;
 520                 goto error;
 521         }
 522         if (priv->representor) {
 523                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
 524                 eth_dev->data->representor_id = priv->representor_id;
 525                 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
 526                         struct mlx5_priv *opriv =
 527                                 rte_eth_devices[port_id].data->dev_private;
 528                         if (opriv &&
 529                             opriv->master &&
 530                             opriv->domain_id == priv->domain_id &&
 531                             opriv->sh == priv->sh) {
 532                                 eth_dev->data->backer_port_id = port_id;
 533                                 break;
 534                         }
 535                 }
 536                 if (port_id >= RTE_MAX_ETHPORTS)
 537                         eth_dev->data->backer_port_id = eth_dev->data->port_id;
 538         }
 539         /*
 540          * Store associated network device interface index. This index
 541          * is permanent throughout the lifetime of device. So, we may store
 542          * the ifindex here and use the cached value further.
 543          */
 544         MLX5_ASSERT(spawn->ifindex);
 545         priv->if_index = spawn->ifindex;
 546         eth_dev->data->dev_private = priv;
 547         priv->dev_data = eth_dev->data;
 548         eth_dev->data->mac_addrs = priv->mac;
 549         eth_dev->device = dpdk_dev;
 550         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 551         /* Configure the first MAC address by default. */
 552         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
 553                 DRV_LOG(ERR,
 554                         "port %u cannot get MAC address, is mlx5_en"
 555                         " loaded? (errno: %s).",
 556                         eth_dev->data->port_id, strerror(rte_errno));
 557                 err = ENODEV;
 558                 goto error;
 559         }
 560         DRV_LOG(INFO,
 561                 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT,
 562                 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac));
 563 #ifdef RTE_LIBRTE_MLX5_DEBUG
 564         {
 565                 char ifname[MLX5_NAMESIZE];
 566
 567                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
 568                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
 569                                 eth_dev->data->port_id, ifname);
 570                 else
 571                         DRV_LOG(DEBUG, "port %u ifname is unknown.",
 572                                 eth_dev->data->port_id);
 573         }
 574 #endif
 575         /* Get actual MTU if possible. */
 576         err = mlx5_get_mtu(eth_dev, &priv->mtu);
 577         if (err) {
 578                 err = rte_errno;
 579                 goto error;
 580         }
 581         DRV_LOG(DEBUG, "port %u MTU is %u.", eth_dev->data->port_id,
 582                 priv->mtu);
 583         /* Initialize burst functions to prevent crashes before link-up. */
 584         eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
 585         eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
 586         eth_dev->dev_ops = &mlx5_dev_ops;
 587         eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
 588         eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
 589         eth_dev->rx_queue_count = mlx5_rx_queue_count;
 590         /* Register MAC address. */
 591         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
 592         priv->ctrl_flows = 0;
 593         TAILQ_INIT(&priv->flow_meters);
 594         priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR);
 595         if (!priv->mtr_profile_tbl)
 596                 goto error;
 597         /* Bring Ethernet device up. */
 598         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up.",
 599                 eth_dev->data->port_id);
 600         /* nl calls are unsupported - set to -1 not to fail on release */
 601         priv->nl_socket_rdma = -1;
 602         priv->nl_socket_route = -1;
 603         mlx5_set_link_up(eth_dev);
 604         /*
 605          * Even though the interrupt handler is not installed yet,
 606          * interrupts will still trigger on the async_fd from
 607          * Verbs context returned by ibv_open_device().
 608          */
 609         mlx5_link_update(eth_dev, 0);
 610         /* Detect minimal data bytes to inline. */
 611         mlx5_set_min_inline(spawn, config);
 612         /* Store device configuration on private structure. */
 613         priv->config = *config;
 614         for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
 615                 icfg[i].release_mem_en = !!config->reclaim_mode;
 616                 if (config->reclaim_mode)
 617                         icfg[i].per_core_cache = 0;
 618                 priv->flows[i] = mlx5_ipool_create(&icfg[i]);
 619                 if (!priv->flows[i])
 620                         goto error;
 621         }
 622         /* Create context for virtual machine VLAN workaround. */
 623         priv->vmwa_context = NULL;
 624         if (config->dv_flow_en) {
 625                 err = mlx5_alloc_shared_dr(priv);
 626                 if (err)
 627                         goto error;
 628         }
 629         /* No supported flow priority number detection. */
 630         priv->sh->flow_max_priority = -1;
 631         mlx5_set_metadata_mask(eth_dev);
 632         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
 633             !priv->sh->dv_regc0_mask) {
 634                 DRV_LOG(ERR, "metadata mode %u is not supported "
 635                              "(no metadata reg_c[0] is available).",
 636                              priv->config.dv_xmeta_en);
 637                         err = ENOTSUP;
 638                         goto error;
 639         }
 640         priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true,
 641                 mlx5_hrxq_create_cb, mlx5_hrxq_match_cb,
 642                 mlx5_hrxq_remove_cb, mlx5_hrxq_clone_cb,
 643                 mlx5_hrxq_clone_free_cb);
 644         /* Query availability of metadata reg_c's. */
 645         if (!priv->sh->metadata_regc_check_flag) {
 646                 err = mlx5_flow_discover_mreg_c(eth_dev);
 647                 if (err < 0) {
 648                         err = -err;
 649                         goto error;
 650                 }
 651         }
 652         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
 653                 DRV_LOG(DEBUG,
 654                         "port %u extensive metadata register is not supported.",
 655                         eth_dev->data->port_id);
 656                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
 657                         DRV_LOG(ERR, "metadata mode %u is not supported "
 658                                      "(no metadata registers available).",
 659                                      priv->config.dv_xmeta_en);
 660                         err = ENOTSUP;
 661                         goto error;
 662                 }
 663         }
 664         if (sh->devx) {
 665                 priv->obj_ops = devx_obj_ops;
 666         } else {
 667                 DRV_LOG(ERR, "Windows flow must be DevX.");
 668                 err = ENOTSUP;
 669                 goto error;
 670         }
 671         mlx5_flow_counter_mode_config(eth_dev);
 672         mlx5_queue_counter_id_prepare(eth_dev);
 673         return eth_dev;
 674 error:
 675         if (priv) {
 676                 if (priv->mtr_profile_tbl)
 677                         mlx5_l3t_destroy(priv->mtr_profile_tbl);
 678                 if (own_domain_id)
 679                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
 680                 mlx5_free(priv);
 681                 if (eth_dev != NULL)
 682                         eth_dev->data->dev_private = NULL;
 683         }
 684         if (eth_dev != NULL) {
 685                 /* mac_addrs must not be freed alone because part of
 686                  * dev_private
 687                  **/
 688                 eth_dev->data->mac_addrs = NULL;
 689                 rte_eth_dev_release_port(eth_dev);
 690         }
 691         if (sh)
 692                 mlx5_free_shared_dev_ctx(sh);
 693         MLX5_ASSERT(err > 0);
 694         rte_errno = err;
 695         return NULL;
 696 }
 697
 698 /**
 699  * This function should share events between multiple ports of single IB
 700  * device.  Currently it has no support under Windows.
 701  *
 702  * @param sh
 703  *   Pointer to mlx5_dev_ctx_shared object.
 704  */
 705 void
 706 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
 707 {
 708         (void)sh;
 709         DRV_LOG(WARNING, "%s: is not supported", __func__);
 710 }
 711
 712 /**
 713  * This function should share events between multiple ports of single IB
 714  * device.  Currently it has no support under Windows.
 715  *
 716  * @param dev
 717  *   Pointer to mlx5_dev_ctx_shared object.
 718  */
 719 void
 720 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
 721 {
 722         (void)sh;
 723         DRV_LOG(WARNING, "%s: is not supported", __func__);
 724 }
 725
 726 /**
 727  * Read statistics by a named counter.
 728  *
 729  * @param[in] priv
 730  *   Pointer to the private device data structure.
 731  * @param[in] ctr_name
 732  *   Pointer to the name of the statistic counter to read
 733  * @param[out] stat
 734  *   Pointer to read statistic value.
 735  * @return
 736  *   0 on success and stat is valid, non-zero if failed to read the value
 737  *   or counter is not supported.
 738  *   rte_errno is set.
 739  *
 740  */
 741 int
 742 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
 743                       uint64_t *stat)
 744 {
 745         if (priv->q_counters != NULL && strcmp(ctr_name, "out_of_buffer") == 0)
 746                 return mlx5_devx_cmd_queue_counter_query
 747                                 (priv->q_counters, 0, (uint32_t *)stat);
 748         DRV_LOG(WARNING, "%s: is not supported for the %s counter",
 749                 __func__, ctr_name);
 750         return -ENOTSUP;
 751 }
 752
 753 /**
 754  * Flush device MAC addresses
 755  * Currently it has no support under Windows.
 756  *
 757  * @param dev
 758  *   Pointer to Ethernet device structure.
 759  *
 760  */
 761 void
 762 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev)
 763 {
 764         (void)dev;
 765         DRV_LOG(WARNING, "%s: is not supported", __func__);
 766 }
 767
 768 /**
 769  * Remove a MAC address from device
 770  * Currently it has no support under Windows.
 771  *
 772  * @param dev
 773  *   Pointer to Ethernet device structure.
 774  * @param index
 775  *   MAC address index.
 776  */
 777 void
 778 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 779 {
 780         (void)dev;
 781         (void)(index);
 782         DRV_LOG(WARNING, "%s: is not supported", __func__);
 783 }
 784
 785 /**
 786  * Adds a MAC address to the device
 787  * Currently it has no support under Windows.
 788  *
 789  * @param dev
 790  *   Pointer to Ethernet device structure.
 791  * @param mac_addr
 792  *   MAC address to register.
 793  * @param index
 794  *   MAC address index.
 795  *
 796  * @return
 797  *   0 on success, a negative errno value otherwise
 798  */
 799 int
 800 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
 801                      uint32_t index)
 802 {
 803         (void)index;
 804         struct rte_ether_addr lmac;
 805
 806         if (mlx5_get_mac(dev, &lmac.addr_bytes)) {
 807                 DRV_LOG(ERR,
 808                         "port %u cannot get MAC address, is mlx5_en"
 809                         " loaded? (errno: %s)",
 810                         dev->data->port_id, strerror(rte_errno));
 811                 return rte_errno;
 812         }
 813         if (!rte_is_same_ether_addr(&lmac, mac)) {
 814                 DRV_LOG(ERR,
 815                         "adding new mac address to device is unsupported");
 816                 return -ENOTSUP;
 817         }
 818         return 0;
 819 }
 820
 821 /**
 822  * Modify a VF MAC address
 823  * Currently it has no support under Windows.
 824  *
 825  * @param priv
 826  *   Pointer to device private data.
 827  * @param mac_addr
 828  *   MAC address to modify into.
 829  * @param iface_idx
 830  *   Net device interface index
 831  * @param vf_index
 832  *   VF index
 833  *
 834  * @return
 835  *   0 on success, a negative errno value otherwise
 836  */
 837 int
 838 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv,
 839                            unsigned int iface_idx,
 840                            struct rte_ether_addr *mac_addr,
 841                            int vf_index)
 842 {
 843         (void)priv;
 844         (void)iface_idx;
 845         (void)mac_addr;
 846         (void)vf_index;
 847         DRV_LOG(WARNING, "%s: is not supported", __func__);
 848         return -ENOTSUP;
 849 }
 850
 851 /**
 852  * Set device promiscuous mode
 853  * Currently it has no support under Windows.
 854  *
 855  * @param dev
 856  *   Pointer to Ethernet device structure.
 857  * @param enable
 858  *   0 - promiscuous is disabled, otherwise - enabled
 859  *
 860  * @return
 861  *   0 on success, a negative error value otherwise
 862  */
 863 int
 864 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable)
 865 {
 866         (void)dev;
 867         (void)enable;
 868         DRV_LOG(WARNING, "%s: is not supported", __func__);
 869         return -ENOTSUP;
 870 }
 871
 872 /**
 873  * Set device allmulti mode
 874  *
 875  * @param dev
 876  *   Pointer to Ethernet device structure.
 877  * @param enable
 878  *   0 - all multicase is disabled, otherwise - enabled
 879  *
 880  * @return
 881  *   0 on success, a negative error value otherwise
 882  */
 883 int
 884 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)
 885 {
 886         (void)dev;
 887         (void)enable;
 888         DRV_LOG(WARNING, "%s: is not supported", __func__);
 889         return -ENOTSUP;
 890 }
 891
 892 /**
 893  * DPDK callback to register a PCI device.
 894  *
 895  * This function spawns Ethernet devices out of a given device.
 896  *
 897  * @param[in] dev
 898  *   Pointer to the common device.
 899  *
 900  * @return
 901  *   0 on success, a negative errno value otherwise and rte_errno is set.
 902  */
 903 int
 904 mlx5_os_net_probe(struct mlx5_common_device *cdev)
 905 {
 906         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);
 907         struct mlx5_dev_spawn_data spawn = {
 908                 .pf_bond = -1,
 909                 .max_port = 1,
 910                 .phys_port = 1,
 911                 .phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx),
 912                 .pci_dev = pci_dev,
 913                 .cdev = cdev,
 914                 .ifindex = -1, /* Spawn will assign */
 915                 .info = (struct mlx5_switch_info){
 916                         .name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK,
 917                 },
 918         };
 919         struct mlx5_dev_config dev_config = {
 920                 .rx_vec_en = 1,
 921                 .txq_inline_max = MLX5_ARG_UNSET,
 922                 .txq_inline_min = MLX5_ARG_UNSET,
 923                 .txq_inline_mpw = MLX5_ARG_UNSET,
 924                 .txqs_inline = MLX5_ARG_UNSET,
 925                 .mprq = {
 926                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
 927                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
 928                 },
 929                 .dv_flow_en = 1,
 930                 .log_hp_size = MLX5_ARG_UNSET,
 931         };
 932         int ret;
 933         uint32_t restore;
 934
 935         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 936                 DRV_LOG(ERR, "Secondary process is not supported on Windows.");
 937                 return -ENOTSUP;
 938         }
 939         ret = mlx5_init_once();
 940         if (ret) {
 941                 DRV_LOG(ERR, "unable to init PMD global data: %s",
 942                         strerror(rte_errno));
 943                 return -rte_errno;
 944         }
 945         /* Device specific configuration. */
 946         switch (pci_dev->id.device_id) {
 947         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
 948         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
 949         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
 950         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
 951         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
 952         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
 953         case PCI_DEVICE_ID_MELLANOX_CONNECTXVF:
 954                 dev_config.vf = 1;
 955                 break;
 956         default:
 957                 dev_config.vf = 0;
 958                 break;
 959         }
 960         spawn.eth_dev = mlx5_dev_spawn(cdev->dev, &spawn, &dev_config);
 961         if (!spawn.eth_dev)
 962                 return -rte_errno;
 963         restore = spawn.eth_dev->data->dev_flags;
 964         rte_eth_copy_pci_info(spawn.eth_dev, pci_dev);
 965         /* Restore non-PCI flags cleared by the above call. */
 966         spawn.eth_dev->data->dev_flags |= restore;
 967         rte_eth_dev_probing_finish(spawn.eth_dev);
 968         return 0;
 969 }
 970
 971 /**
 972  * Cleanup resources when the last device is closed.
 973  */
 974 void
 975 mlx5_os_net_cleanup(void)
 976 {
 977 }
 978
 979 const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0};