1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
11 #include <rte_windows.h>
12 #include <ethdev_pci.h>
14 #include <mlx5_glue.h>
15 #include <mlx5_devx_cmds.h>
16 #include <mlx5_common.h>
17 #include <mlx5_common_mp.h>
18 #include <mlx5_common_mr.h>
19 #include <mlx5_malloc.h>
21 #include "mlx5_defs.h"
23 #include "mlx5_common_os.h"
24 #include "mlx5_utils.h"
25 #include "mlx5_rxtx.h"
28 #include "mlx5_autoconf.h"
30 #include "mlx5_flow.h"
31 #include "mlx5_devx.h"
33 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
35 /* Spinlock for mlx5_shared_data allocation. */
36 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
38 /* rte flow indexed pool configuration. */
39 static struct mlx5_indexed_pool_config icfg[] = {
41 .size = sizeof(struct rte_flow),
45 .malloc = mlx5_malloc,
48 .type = "ctl_flow_ipool",
51 .size = sizeof(struct rte_flow),
57 .malloc = mlx5_malloc,
59 .per_core_cache = 1 << 14,
60 .type = "rte_flow_ipool",
63 .size = sizeof(struct rte_flow),
69 .malloc = mlx5_malloc,
72 .type = "mcp_flow_ipool",
77 * Initialize shared data between primary and secondary process.
79 * A memzone is reserved by primary process and secondary processes attach to
83 * 0 on success, a negative errno value otherwise and rte_errno is set.
86 mlx5_init_shared_data(void)
88 const struct rte_memzone *mz;
91 rte_spinlock_lock(&mlx5_shared_data_lock);
92 if (mlx5_shared_data == NULL) {
93 /* Allocate shared memory. */
94 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
95 sizeof(*mlx5_shared_data),
99 "Cannot allocate mlx5 shared data");
103 mlx5_shared_data = mz->addr;
104 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
105 rte_spinlock_init(&mlx5_shared_data->lock);
108 rte_spinlock_unlock(&mlx5_shared_data_lock);
113 * PMD global initialization.
115 * Independent from individual device, this function initializes global
116 * per-PMD data structures distinguishing primary and secondary processes.
117 * Hence, each initialization is called once per a process.
120 * 0 on success, a negative errno value otherwise and rte_errno is set.
125 struct mlx5_shared_data *sd;
127 if (mlx5_init_shared_data())
129 sd = mlx5_shared_data;
130 rte_spinlock_lock(&sd->lock);
132 if (!sd->init_done) {
133 LIST_INIT(&sd->mem_event_cb_list);
134 rte_rwlock_init(&sd->mem_event_rwlock);
135 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
136 mlx5_mr_mem_event_cb, NULL);
137 sd->init_done = true;
139 rte_spinlock_unlock(&sd->lock);
144 * Get mlx5 device attributes.
147 * Pointer to device context.
150 * Pointer to mlx5 device attributes.
153 * 0 on success, non zero error number otherwise
156 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)
158 struct mlx5_context *mlx5_ctx;
159 struct mlx5_hca_attr hca_attr;
160 void *pv_iseg = NULL;
166 mlx5_ctx = (struct mlx5_context *)ctx;
167 memset(device_attr, 0, sizeof(*device_attr));
168 err = mlx5_devx_cmd_query_hca_attr(mlx5_ctx, &hca_attr);
170 DRV_LOG(ERR, "Failed to get device hca_cap");
173 device_attr->max_cq = 1 << hca_attr.log_max_cq;
174 device_attr->max_qp = 1 << hca_attr.log_max_qp;
175 device_attr->max_qp_wr = 1 << hca_attr.log_max_qp_sz;
176 device_attr->max_cqe = 1 << hca_attr.log_max_cq_sz;
177 device_attr->max_mr = 1 << hca_attr.log_max_mrw_sz;
178 device_attr->max_pd = 1 << hca_attr.log_max_pd;
179 device_attr->max_srq = 1 << hca_attr.log_max_srq;
180 device_attr->max_srq_wr = 1 << hca_attr.log_max_srq_sz;
181 device_attr->max_tso = 1 << hca_attr.max_lso_cap;
182 if (hca_attr.rss_ind_tbl_cap) {
183 device_attr->max_rwq_indirection_table_size =
184 1 << hca_attr.rss_ind_tbl_cap;
186 device_attr->sw_parsing_offloads =
187 mlx5_get_supported_sw_parsing_offloads(&hca_attr);
188 device_attr->tunnel_offloads_caps =
189 mlx5_get_supported_tunneling_offloads(&hca_attr);
190 pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
191 if (pv_iseg == NULL) {
192 DRV_LOG(ERR, "Failed to get device hca_iseg");
196 snprintf(device_attr->fw_ver, 64, "%x.%x.%04x",
197 MLX5_GET(initial_seg, pv_iseg, fw_rev_major),
198 MLX5_GET(initial_seg, pv_iseg, fw_rev_minor),
199 MLX5_GET(initial_seg, pv_iseg, fw_rev_subminor));
205 * Initialize DR related data within private structure.
206 * Routine checks the reference counter and does actual
207 * resources creation/initialization only if counter is zero.
210 * Pointer to the private device data structure.
213 * Zero on success, positive error code otherwise.
216 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
218 struct mlx5_dev_ctx_shared *sh = priv->sh;
222 err = mlx5_alloc_table_hash_list(priv);
224 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse",
225 (void *)sh->flow_tbls);
229 * Destroy DR related data within private structure.
232 * Pointer to the private device data structure.
235 mlx5_os_free_shared_dr(struct mlx5_priv *priv)
237 mlx5_free_table_hash_list(priv);
241 * Set the completion channel file descriptor interrupt as non-blocking.
242 * Currently it has no support under Windows.
245 * Pointer to RQ channel object, which includes the channel fd
248 * The file descriptor (representing the intetrrupt) used in this channel.
251 * 0 on successfully setting the fd to non-blocking, non-zero otherwise.
254 mlx5_os_set_nonblock_channel_fd(int fd)
257 DRV_LOG(WARNING, "%s: is not supported", __func__);
262 * Function API open device under Windows
264 * This function calls the Windows glue APIs to open a device.
267 * Pointer to the device attributes (name, port, etc).
269 * Pointer to device configuration structure.
271 * Pointer to shared context structure.
274 * 0 on success, a positive error value otherwise.
277 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
278 const struct mlx5_dev_config *config,
279 struct mlx5_dev_ctx_shared *sh)
281 RTE_SET_USED(config);
283 struct mlx5_context *mlx5_ctx;
285 pthread_mutex_init(&sh->txpp.mutex, NULL);
286 /* Set numa node from pci probe */
287 sh->numa_node = spawn->pci_dev->device.numa_node;
289 /* Try to open device with DevX */
291 sh->ctx = mlx5_glue->open_device(spawn->phys_dev);
293 DRV_LOG(ERR, "open_device failed");
298 mlx5_ctx = (struct mlx5_context *)sh->ctx;
299 err = mlx5_glue->query_device(spawn->phys_dev, &mlx5_ctx->mlx5_dev);
301 DRV_LOG(ERR, "Failed to query device context fields.");
306 * DV flow counter mode detect and config.
309 * Pointer to rte_eth_dev structure.
313 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
315 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
316 struct mlx5_priv *priv = dev->data->dev_private;
317 struct mlx5_dev_ctx_shared *sh = priv->sh;
320 #ifndef HAVE_IBV_DEVX_ASYNC
324 if (!priv->config.devx || !priv->config.dv_flow_en ||
325 !priv->config.hca_attr.flow_counters_dump ||
326 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) ||
327 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
331 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
332 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
333 priv->config.hca_attr.flow_counters_dump,
334 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap);
335 /* Initialize fallback mode only on the port initializes sh. */
337 sh->cmng.counter_fallback = fallback;
338 else if (fallback != sh->cmng.counter_fallback)
339 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
340 "with others:%d.", PORT_ID(priv), fallback);
345 * Spawn an Ethernet device from Verbs information.
348 * Backing DPDK device.
350 * Verbs device parameters (name, port, switch_info) to spawn.
352 * Device configuration parameters.
355 * A valid Ethernet device object on success, NULL otherwise and rte_errno
356 * is set. The following errors are defined:
358 * EEXIST: device is already spawned
360 static struct rte_eth_dev *
361 mlx5_dev_spawn(struct rte_device *dpdk_dev,
362 struct mlx5_dev_spawn_data *spawn,
363 struct mlx5_dev_config *config)
365 const struct mlx5_switch_info *switch_info = &spawn->info;
366 struct mlx5_dev_ctx_shared *sh = NULL;
367 struct mlx5_dev_attr device_attr;
368 struct rte_eth_dev *eth_dev = NULL;
369 struct mlx5_priv *priv = NULL;
371 unsigned int cqe_comp;
372 struct rte_ether_addr mac;
373 char name[RTE_ETH_NAME_MAX_LEN];
374 int own_domain_id = 0;
378 /* Build device name. */
379 strlcpy(name, dpdk_dev->name, sizeof(name));
380 /* check if the device is already spawned */
381 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
385 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
387 * Some parameters are needed in advance to create device context. We
388 * process the devargs here to get ones, and later process devargs
389 * again to override some hardware settings.
391 err = mlx5_args(config, dpdk_dev->devargs);
394 DRV_LOG(ERR, "failed to process device arguments: %s",
395 strerror(rte_errno));
398 mlx5_malloc_mem_select(config->sys_mem_en);
399 sh = mlx5_alloc_shared_dev_ctx(spawn, config);
402 config->devx = sh->devx;
403 /* Initialize the shutdown event in mlx5_dev_spawn to
404 * support mlx5_is_removed for Windows.
406 err = mlx5_glue->devx_init_showdown_event(sh->ctx);
408 DRV_LOG(ERR, "failed to init showdown event: %s",
412 DRV_LOG(DEBUG, "MPW isn't supported");
413 mlx5_os_get_dev_attr(sh->ctx, &device_attr);
414 config->swp = device_attr.sw_parsing_offloads &
415 (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
416 MLX5_SW_PARSING_TSO_CAP);
417 config->ind_table_max_size =
418 sh->device_attr.max_rwq_indirection_table_size;
420 config->cqe_comp = cqe_comp;
421 config->tunnel_en = device_attr.tunnel_offloads_caps &
422 (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |
423 MLX5_TUNNELED_OFFLOADS_GRE_CAP |
424 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);
425 if (config->tunnel_en) {
426 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
428 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "",
430 MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "",
432 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""
435 DRV_LOG(DEBUG, "tunnel offloading is not supported");
437 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported");
439 /* Allocate private eth device data. */
440 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
442 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
444 DRV_LOG(ERR, "priv allocation failure");
449 priv->dev_port = spawn->phys_port;
450 priv->pci_dev = spawn->pci_dev;
451 priv->mtu = RTE_ETHER_MTU;
452 priv->mp_id.port_id = port_id;
453 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
454 priv->representor = !!switch_info->representor;
455 priv->master = !!switch_info->master;
456 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
457 priv->vport_meta_tag = 0;
458 priv->vport_meta_mask = 0;
459 priv->pf_bond = spawn->pf_bond;
461 /* representor_id field keeps the unmodified VF index. */
462 priv->representor_id = -1;
464 * Look for sibling devices in order to reuse their switch domain
465 * if any, otherwise allocate one.
467 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
468 const struct mlx5_priv *opriv =
469 rte_eth_devices[port_id].data->dev_private;
472 opriv->sh != priv->sh ||
474 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
476 priv->domain_id = opriv->domain_id;
479 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
480 err = rte_eth_switch_domain_alloc(&priv->domain_id);
483 DRV_LOG(ERR, "unable to allocate switch domain: %s",
484 strerror(rte_errno));
489 /* Override some values set by hardware configuration. */
490 mlx5_args(config, dpdk_dev->devargs);
491 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev);
494 DRV_LOG(DEBUG, "counters are not supported");
495 config->ind_table_max_size =
496 sh->device_attr.max_rwq_indirection_table_size;
498 * Remove this check once DPDK supports larger/variable
499 * indirection tables.
501 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
502 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
503 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
504 config->ind_table_max_size);
505 if (config->hw_padding) {
506 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
507 config->hw_padding = 0;
509 config->tso = (sh->device_attr.max_tso > 0);
511 config->tso_max_payload_sz = sh->device_attr.max_tso;
512 DRV_LOG(DEBUG, "%sMPS is %s.",
513 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
514 config->mps == MLX5_MPW ? "legacy " : "",
515 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
516 if (config->cqe_comp && !cqe_comp) {
517 DRV_LOG(WARNING, "Rx CQE compression isn't supported.");
518 config->cqe_comp = 0;
521 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);
526 /* Check relax ordering support. */
527 sh->cmng.relaxed_ordering_read = 0;
528 sh->cmng.relaxed_ordering_write = 0;
529 if (!haswell_broadwell_cpu) {
530 sh->cmng.relaxed_ordering_write =
531 config->hca_attr.relaxed_ordering_write;
532 sh->cmng.relaxed_ordering_read =
533 config->hca_attr.relaxed_ordering_read;
535 config->hw_csum = config->hca_attr.csum_cap;
536 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
537 (config->hw_csum ? "" : "not "));
538 config->hw_vlan_strip = config->hca_attr.vlan_cap;
539 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
540 (config->hw_vlan_strip ? "" : "not "));
541 config->hw_fcs_strip = config->hca_attr.scatter_fcs;
544 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
546 err = config->hca_attr.access_register_user ?
547 mlx5_devx_cmd_register_read
548 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,
549 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
553 /* MTUTC register is read successfully. */
554 ts_mode = MLX5_GET(register_mtutc, reg,
556 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
557 config->rt_timestamp = 1;
559 /* Kernel does not support register reading. */
560 if (config->hca_attr.dev_freq_khz ==
561 (NS_PER_S / MS_PER_S))
562 config->rt_timestamp = 1;
564 sh->rq_ts_format = config->hca_attr.rq_ts_format;
565 sh->sq_ts_format = config->hca_attr.sq_ts_format;
566 sh->qp_ts_format = config->hca_attr.qp_ts_format;
568 if (config->mprq.enabled) {
569 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
570 config->mprq.enabled = 0;
572 if (config->max_dump_files_num == 0)
573 config->max_dump_files_num = 128;
574 eth_dev = rte_eth_dev_allocate(name);
575 if (eth_dev == NULL) {
576 DRV_LOG(ERR, "can not allocate rte ethdev");
580 if (priv->representor) {
581 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
582 eth_dev->data->representor_id = priv->representor_id;
583 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
584 struct mlx5_priv *opriv =
585 rte_eth_devices[port_id].data->dev_private;
588 opriv->domain_id == priv->domain_id &&
589 opriv->sh == priv->sh) {
590 eth_dev->data->backer_port_id = port_id;
594 if (port_id >= RTE_MAX_ETHPORTS)
595 eth_dev->data->backer_port_id = eth_dev->data->port_id;
598 * Store associated network device interface index. This index
599 * is permanent throughout the lifetime of device. So, we may store
600 * the ifindex here and use the cached value further.
602 MLX5_ASSERT(spawn->ifindex);
603 priv->if_index = spawn->ifindex;
604 eth_dev->data->dev_private = priv;
605 priv->dev_data = eth_dev->data;
606 eth_dev->data->mac_addrs = priv->mac;
607 eth_dev->device = dpdk_dev;
608 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
609 /* Configure the first MAC address by default. */
610 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
612 "port %u cannot get MAC address, is mlx5_en"
613 " loaded? (errno: %s).",
614 eth_dev->data->port_id, strerror(rte_errno));
619 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT,
620 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac));
621 #ifdef RTE_LIBRTE_MLX5_DEBUG
623 char ifname[MLX5_NAMESIZE];
625 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
626 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
627 eth_dev->data->port_id, ifname);
629 DRV_LOG(DEBUG, "port %u ifname is unknown.",
630 eth_dev->data->port_id);
633 /* Get actual MTU if possible. */
634 err = mlx5_get_mtu(eth_dev, &priv->mtu);
639 DRV_LOG(DEBUG, "port %u MTU is %u.", eth_dev->data->port_id,
641 /* Initialize burst functions to prevent crashes before link-up. */
642 eth_dev->rx_pkt_burst = removed_rx_burst;
643 eth_dev->tx_pkt_burst = removed_tx_burst;
644 eth_dev->dev_ops = &mlx5_dev_ops;
645 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
646 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
647 eth_dev->rx_queue_count = mlx5_rx_queue_count;
648 /* Register MAC address. */
649 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
650 priv->ctrl_flows = 0;
651 TAILQ_INIT(&priv->flow_meters);
652 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR);
653 if (!priv->mtr_profile_tbl)
655 /* Bring Ethernet device up. */
656 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up.",
657 eth_dev->data->port_id);
658 /* nl calls are unsupported - set to -1 not to fail on release */
659 priv->nl_socket_rdma = -1;
660 priv->nl_socket_route = -1;
661 mlx5_set_link_up(eth_dev);
663 * Even though the interrupt handler is not installed yet,
664 * interrupts will still trigger on the async_fd from
665 * Verbs context returned by ibv_open_device().
667 mlx5_link_update(eth_dev, 0);
668 config->dv_esw_en = 0;
669 /* Detect minimal data bytes to inline. */
670 mlx5_set_min_inline(spawn, config);
671 /* Store device configuration on private structure. */
672 priv->config = *config;
673 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
674 icfg[i].release_mem_en = !!config->reclaim_mode;
675 if (config->reclaim_mode)
676 icfg[i].per_core_cache = 0;
677 priv->flows[i] = mlx5_ipool_create(&icfg[i]);
681 /* Create context for virtual machine VLAN workaround. */
682 priv->vmwa_context = NULL;
683 if (config->dv_flow_en) {
684 err = mlx5_alloc_shared_dr(priv);
688 /* No supported flow priority number detection. */
689 priv->config.flow_prio = -1;
690 if (!priv->config.dv_esw_en &&
691 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
692 DRV_LOG(WARNING, "metadata mode %u is not supported "
693 "(no E-Switch)", priv->config.dv_xmeta_en);
694 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
696 mlx5_set_metadata_mask(eth_dev);
697 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
698 !priv->sh->dv_regc0_mask) {
699 DRV_LOG(ERR, "metadata mode %u is not supported "
700 "(no metadata reg_c[0] is available).",
701 priv->config.dv_xmeta_en);
705 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true,
706 mlx5_hrxq_create_cb, mlx5_hrxq_match_cb,
707 mlx5_hrxq_remove_cb, mlx5_hrxq_clone_cb,
708 mlx5_hrxq_clone_free_cb);
709 /* Query availability of metadata reg_c's. */
710 err = mlx5_flow_discover_mreg_c(eth_dev);
715 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
717 "port %u extensive metadata register is not supported.",
718 eth_dev->data->port_id);
719 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
720 DRV_LOG(ERR, "metadata mode %u is not supported "
721 "(no metadata registers available).",
722 priv->config.dv_xmeta_en);
727 if (config->devx && config->dv_flow_en) {
728 priv->obj_ops = devx_obj_ops;
730 DRV_LOG(ERR, "Flow mode %u is not supported "
731 "(Windows flow must be DevX with DV flow enabled).",
732 priv->config.dv_flow_en);
736 mlx5_flow_counter_mode_config(eth_dev);
740 if (priv->mtr_profile_tbl)
741 mlx5_l3t_destroy(priv->mtr_profile_tbl);
743 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
746 eth_dev->data->dev_private = NULL;
748 if (eth_dev != NULL) {
749 /* mac_addrs must not be freed alone because part of
752 eth_dev->data->mac_addrs = NULL;
753 rte_eth_dev_release_port(eth_dev);
756 mlx5_free_shared_dev_ctx(sh);
757 MLX5_ASSERT(err > 0);
763 * This function should share events between multiple ports of single IB
764 * device. Currently it has no support under Windows.
767 * Pointer to mlx5_dev_ctx_shared object.
770 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
773 DRV_LOG(WARNING, "%s: is not supported", __func__);
777 * This function should share events between multiple ports of single IB
778 * device. Currently it has no support under Windows.
781 * Pointer to mlx5_dev_ctx_shared object.
784 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
787 DRV_LOG(WARNING, "%s: is not supported", __func__);
791 * Read statistics by a named counter.
794 * Pointer to the private device data structure.
795 * @param[in] ctr_name
796 * Pointer to the name of the statistic counter to read
798 * Pointer to read statistic value.
800 * 0 on success and stat is valud, 1 if failed to read the value
805 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
809 RTE_SET_USED(ctr_name);
811 DRV_LOG(WARNING, "%s: is not supported", __func__);
816 * Flush device MAC addresses
817 * Currently it has no support under Windows.
820 * Pointer to Ethernet device structure.
824 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev)
827 DRV_LOG(WARNING, "%s: is not supported", __func__);
831 * Remove a MAC address from device
832 * Currently it has no support under Windows.
835 * Pointer to Ethernet device structure.
840 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
844 DRV_LOG(WARNING, "%s: is not supported", __func__);
848 * Adds a MAC address to the device
849 * Currently it has no support under Windows.
852 * Pointer to Ethernet device structure.
854 * MAC address to register.
859 * 0 on success, a negative errno value otherwise
862 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
866 struct rte_ether_addr lmac;
868 if (mlx5_get_mac(dev, &lmac.addr_bytes)) {
870 "port %u cannot get MAC address, is mlx5_en"
871 " loaded? (errno: %s)",
872 dev->data->port_id, strerror(rte_errno));
875 if (!rte_is_same_ether_addr(&lmac, mac)) {
877 "adding new mac address to device is unsupported");
884 * Modify a VF MAC address
885 * Currently it has no support under Windows.
888 * Pointer to device private data.
890 * MAC address to modify into.
892 * Net device interface index
897 * 0 on success, a negative errno value otherwise
900 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv,
901 unsigned int iface_idx,
902 struct rte_ether_addr *mac_addr,
909 DRV_LOG(WARNING, "%s: is not supported", __func__);
914 * Set device promiscuous mode
915 * Currently it has no support under Windows.
918 * Pointer to Ethernet device structure.
920 * 0 - promiscuous is disabled, otherwise - enabled
923 * 0 on success, a negative error value otherwise
926 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable)
930 DRV_LOG(WARNING, "%s: is not supported", __func__);
935 * Set device allmulti mode
938 * Pointer to Ethernet device structure.
940 * 0 - all multicase is disabled, otherwise - enabled
943 * 0 on success, a negative error value otherwise
946 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)
950 DRV_LOG(WARNING, "%s: is not supported", __func__);
955 * Detect if a devx_device_bdf object has identical DBDF values to the
956 * rte_pci_addr found in bus/pci probing
958 * @param[in] devx_bdf
959 * Pointer to the devx_device_bdf structure.
961 * Pointer to the rte_pci_addr structure.
964 * 1 on Device match, 0 on mismatch.
967 mlx5_match_devx_bdf_to_addr(struct devx_device_bdf *devx_bdf,
968 struct rte_pci_addr *addr)
970 if (addr->domain != (devx_bdf->bus_id >> 8) ||
971 addr->bus != (devx_bdf->bus_id & 0xff) ||
972 addr->devid != devx_bdf->dev_id ||
973 addr->function != devx_bdf->fnc_id) {
980 * Detect if a devx_device_bdf object matches the rte_pci_addr
981 * found in bus/pci probing
982 * Compare both the Native/PF BDF and the raw_bdf representing a VF BDF.
984 * @param[in] devx_bdf
985 * Pointer to the devx_device_bdf structure.
987 * Pointer to the rte_pci_addr structure.
990 * 1 on Device match, 0 on mismatch, rte_errno code on failure.
993 mlx5_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf,
994 struct rte_pci_addr *addr)
997 struct devx_device mlx5_dev;
999 if (mlx5_match_devx_bdf_to_addr(devx_bdf, addr))
1002 * Didn't match on Native/PF BDF, could still
1003 * Match a VF BDF, check it next
1005 err = mlx5_glue->query_device(devx_bdf, &mlx5_dev);
1007 DRV_LOG(ERR, "query_device failed");
1011 if (mlx5_match_devx_bdf_to_addr(&mlx5_dev.raw_bdf, addr))
1017 * DPDK callback to register a PCI device.
1019 * This function spawns Ethernet devices out of a given device.
1022 * Pointer to the generic device.
1025 * 0 on success, a negative errno value otherwise and rte_errno is set.
1028 mlx5_os_net_probe(struct rte_device *dev)
1030 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
1031 struct devx_device_bdf *devx_bdf_devs, *orig_devx_bdf_devs;
1033 * Number of found IB Devices matching with requested PCI BDF.
1034 * nd != 1 means there are multiple IB devices over the same
1035 * PCI device and we have representors and master.
1037 unsigned int nd = 0;
1039 * Number of found IB device Ports. nd = 1 and np = 1..n means
1040 * we have the single multiport IB device, and there may be
1041 * representors attached to some of found ports.
1042 * Currently not supported.
1043 * unsigned int np = 0;
1047 * Number of DPDK ethernet devices to Spawn - either over
1048 * multiple IB devices or multiple ports of single IB device.
1049 * Actually this is the number of iterations to spawn.
1051 unsigned int ns = 0;
1054 * < 0 - no bonding device (single one)
1055 * >= 0 - bonding device (value is slave PF index)
1058 struct mlx5_dev_spawn_data *list = NULL;
1059 struct mlx5_dev_config dev_config;
1060 unsigned int dev_config_vf;
1064 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1065 DRV_LOG(ERR, "Secondary process is not supported on Windows.");
1068 ret = mlx5_init_once();
1070 DRV_LOG(ERR, "unable to init PMD global data: %s",
1071 strerror(rte_errno));
1075 devx_bdf_devs = mlx5_glue->get_device_list(&ret);
1076 orig_devx_bdf_devs = devx_bdf_devs;
1077 if (!devx_bdf_devs) {
1078 rte_errno = errno ? errno : ENOSYS;
1079 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1083 * First scan the list of all Infiniband devices to find
1084 * matching ones, gathering into the list.
1086 struct devx_device_bdf *devx_bdf_match[ret + 1];
1089 err = mlx5_match_devx_devices_to_addr(devx_bdf_devs,
1099 devx_bdf_match[nd++] = devx_bdf_devs;
1101 devx_bdf_match[nd] = NULL;
1103 /* No device matches, just complain and bail out. */
1105 "no DevX device matches PCI device " PCI_PRI_FMT ","
1106 " is DevX Configured?",
1107 pci_dev->addr.domain, pci_dev->addr.bus,
1108 pci_dev->addr.devid, pci_dev->addr.function);
1114 * Now we can determine the maximal
1115 * amount of devices to be spawned.
1117 list = mlx5_malloc(MLX5_MEM_ZERO,
1118 sizeof(struct mlx5_dev_spawn_data),
1119 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1121 DRV_LOG(ERR, "spawn data array allocation failure");
1126 memset(&list[ns].info, 0, sizeof(list[ns].info));
1127 list[ns].max_port = 1;
1128 list[ns].phys_port = 1;
1129 list[ns].phys_dev = devx_bdf_match[ns];
1130 list[ns].eth_dev = NULL;
1131 list[ns].pci_dev = pci_dev;
1132 list[ns].pf_bond = bd;
1133 list[ns].ifindex = -1; /* Spawn will assign */
1135 (struct mlx5_switch_info){
1138 .name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK,
1142 /* Device specific configuration. */
1143 switch (pci_dev->id.device_id) {
1144 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1145 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1146 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1147 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1148 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
1149 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
1150 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF:
1157 /* Default configuration. */
1158 memset(&dev_config, 0, sizeof(struct mlx5_dev_config));
1159 dev_config.vf = dev_config_vf;
1161 dev_config.dbnc = MLX5_ARG_UNSET;
1162 dev_config.rx_vec_en = 1;
1163 dev_config.txq_inline_max = MLX5_ARG_UNSET;
1164 dev_config.txq_inline_min = MLX5_ARG_UNSET;
1165 dev_config.txq_inline_mpw = MLX5_ARG_UNSET;
1166 dev_config.txqs_inline = MLX5_ARG_UNSET;
1167 dev_config.vf_nl_en = 0;
1168 dev_config.mr_ext_memseg_en = 1;
1169 dev_config.mr_mempool_reg_en = 1;
1170 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;
1171 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;
1172 dev_config.dv_esw_en = 0;
1173 dev_config.dv_flow_en = 1;
1174 dev_config.decap_en = 0;
1175 dev_config.log_hp_size = MLX5_ARG_UNSET;
1176 list[ns].numa_node = pci_dev->device.numa_node;
1177 list[ns].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1180 if (!list[ns].eth_dev)
1182 restore = list[ns].eth_dev->data->dev_flags;
1183 rte_eth_copy_pci_info(list[ns].eth_dev, pci_dev);
1184 /* Restore non-PCI flags cleared by the above call. */
1185 list[ns].eth_dev->data->dev_flags |= restore;
1186 rte_eth_dev_probing_finish(list[ns].eth_dev);
1190 * Do the routine cleanup:
1191 * - free allocated spawn data array
1192 * - free the device list
1196 MLX5_ASSERT(orig_devx_bdf_devs);
1197 mlx5_glue->free_device_list(orig_devx_bdf_devs);
1202 * Set the reg_mr and dereg_mr call backs
1204 * @param reg_mr_cb[out]
1205 * Pointer to reg_mr func
1206 * @param dereg_mr_cb[out]
1207 * Pointer to dereg_mr func
1211 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1212 mlx5_dereg_mr_t *dereg_mr_cb)
1214 *reg_mr_cb = mlx5_os_reg_mr;
1215 *dereg_mr_cb = mlx5_os_dereg_mr;
1219 * Extract pdn of PD object using DevX
1222 * Pointer to the DevX PD object.
1224 * Pointer to the PD object number variable.
1227 * 0 on success, error value otherwise.
1230 mlx5_os_get_pdn(void *pd, uint32_t *pdn)
1235 *pdn = ((struct mlx5_pd *)pd)->pdn;
1239 const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0};