1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
11 #include <rte_windows.h>
12 #include <ethdev_pci.h>
14 #include <mlx5_glue.h>
15 #include <mlx5_devx_cmds.h>
16 #include <mlx5_common.h>
17 #include <mlx5_common_mp.h>
18 #include <mlx5_common_mr.h>
19 #include <mlx5_malloc.h>
21 #include "mlx5_defs.h"
23 #include "mlx5_common_os.h"
24 #include "mlx5_utils.h"
25 #include "mlx5_rxtx.h"
28 #include "mlx5_autoconf.h"
30 #include "mlx5_flow.h"
31 #include "mlx5_devx.h"
33 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
35 /* Spinlock for mlx5_shared_data allocation. */
36 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
38 /* rte flow indexed pool configuration. */
39 static struct mlx5_indexed_pool_config icfg[] = {
41 .size = sizeof(struct rte_flow),
45 .malloc = mlx5_malloc,
48 .type = "ctl_flow_ipool",
51 .size = sizeof(struct rte_flow),
57 .malloc = mlx5_malloc,
59 .per_core_cache = 1 << 14,
60 .type = "rte_flow_ipool",
63 .size = sizeof(struct rte_flow),
69 .malloc = mlx5_malloc,
72 .type = "mcp_flow_ipool",
77 * Initialize shared data between primary and secondary process.
79 * A memzone is reserved by primary process and secondary processes attach to
83 * 0 on success, a negative errno value otherwise and rte_errno is set.
86 mlx5_init_shared_data(void)
88 const struct rte_memzone *mz;
91 rte_spinlock_lock(&mlx5_shared_data_lock);
92 if (mlx5_shared_data == NULL) {
93 /* Allocate shared memory. */
94 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
95 sizeof(*mlx5_shared_data),
99 "Cannot allocate mlx5 shared data");
103 mlx5_shared_data = mz->addr;
104 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
105 rte_spinlock_init(&mlx5_shared_data->lock);
108 rte_spinlock_unlock(&mlx5_shared_data_lock);
113 * PMD global initialization.
115 * Independent from individual device, this function initializes global
116 * per-PMD data structures distinguishing primary and secondary processes.
117 * Hence, each initialization is called once per a process.
120 * 0 on success, a negative errno value otherwise and rte_errno is set.
125 struct mlx5_shared_data *sd;
127 if (mlx5_init_shared_data())
129 sd = mlx5_shared_data;
130 rte_spinlock_lock(&sd->lock);
132 if (!sd->init_done) {
133 LIST_INIT(&sd->mem_event_cb_list);
134 rte_rwlock_init(&sd->mem_event_rwlock);
135 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
136 mlx5_mr_mem_event_cb, NULL);
137 sd->init_done = true;
139 rte_spinlock_unlock(&sd->lock);
144 * Get mlx5 device attributes.
147 * Pointer to device context.
150 * Pointer to mlx5 device attributes.
153 * 0 on success, non zero error number otherwise
156 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)
158 struct mlx5_context *mlx5_ctx;
159 struct mlx5_hca_attr hca_attr;
160 void *pv_iseg = NULL;
166 mlx5_ctx = (struct mlx5_context *)ctx;
167 memset(device_attr, 0, sizeof(*device_attr));
168 err = mlx5_devx_cmd_query_hca_attr(mlx5_ctx, &hca_attr);
170 DRV_LOG(ERR, "Failed to get device hca_cap");
173 device_attr->max_cq = 1 << hca_attr.log_max_cq;
174 device_attr->max_qp = 1 << hca_attr.log_max_qp;
175 device_attr->max_qp_wr = 1 << hca_attr.log_max_qp_sz;
176 device_attr->max_cqe = 1 << hca_attr.log_max_cq_sz;
177 device_attr->max_mr = 1 << hca_attr.log_max_mrw_sz;
178 device_attr->max_pd = 1 << hca_attr.log_max_pd;
179 device_attr->max_srq = 1 << hca_attr.log_max_srq;
180 device_attr->max_srq_wr = 1 << hca_attr.log_max_srq_sz;
181 device_attr->max_tso = 1 << hca_attr.max_lso_cap;
182 if (hca_attr.rss_ind_tbl_cap) {
183 device_attr->max_rwq_indirection_table_size =
184 1 << hca_attr.rss_ind_tbl_cap;
186 device_attr->sw_parsing_offloads =
187 mlx5_get_supported_sw_parsing_offloads(&hca_attr);
188 device_attr->tunnel_offloads_caps =
189 mlx5_get_supported_tunneling_offloads(&hca_attr);
190 pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
191 if (pv_iseg == NULL) {
192 DRV_LOG(ERR, "Failed to get device hca_iseg");
196 snprintf(device_attr->fw_ver, 64, "%x.%x.%04x",
197 MLX5_GET(initial_seg, pv_iseg, fw_rev_major),
198 MLX5_GET(initial_seg, pv_iseg, fw_rev_minor),
199 MLX5_GET(initial_seg, pv_iseg, fw_rev_subminor));
205 * Initialize DR related data within private structure.
206 * Routine checks the reference counter and does actual
207 * resources creation/initialization only if counter is zero.
210 * Pointer to the private device data structure.
213 * Zero on success, positive error code otherwise.
216 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
218 struct mlx5_dev_ctx_shared *sh = priv->sh;
222 err = mlx5_alloc_table_hash_list(priv);
224 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse",
225 (void *)sh->flow_tbls);
229 * Destroy DR related data within private structure.
232 * Pointer to the private device data structure.
235 mlx5_os_free_shared_dr(struct mlx5_priv *priv)
237 mlx5_free_table_hash_list(priv);
241 * Set the completion channel file descriptor interrupt as non-blocking.
242 * Currently it has no support under Windows.
245 * Pointer to RQ channel object, which includes the channel fd
248 * The file descriptor (representing the intetrrupt) used in this channel.
251 * 0 on successfully setting the fd to non-blocking, non-zero otherwise.
254 mlx5_os_set_nonblock_channel_fd(int fd)
257 DRV_LOG(WARNING, "%s: is not supported", __func__);
262 * Function API open device under Windows
264 * This function calls the Windows glue APIs to open a device.
267 * Pointer to the device attributes (name, port, etc).
269 * Pointer to shared context structure.
272 * 0 on success, a positive error value otherwise.
275 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
276 struct mlx5_dev_ctx_shared *sh)
279 struct mlx5_context *mlx5_ctx;
281 pthread_mutex_init(&sh->txpp.mutex, NULL);
282 /* Set numa node from pci probe */
283 sh->numa_node = spawn->pci_dev->device.numa_node;
285 /* Try to open device with DevX */
287 sh->ctx = mlx5_glue->open_device(spawn->phys_dev);
289 DRV_LOG(ERR, "open_device failed");
294 mlx5_ctx = (struct mlx5_context *)sh->ctx;
295 err = mlx5_glue->query_device(spawn->phys_dev, &mlx5_ctx->mlx5_dev);
297 DRV_LOG(ERR, "Failed to query device context fields.");
302 * DV flow counter mode detect and config.
305 * Pointer to rte_eth_dev structure.
309 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
311 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
312 struct mlx5_priv *priv = dev->data->dev_private;
313 struct mlx5_dev_ctx_shared *sh = priv->sh;
316 #ifndef HAVE_IBV_DEVX_ASYNC
320 if (!priv->config.devx || !priv->config.dv_flow_en ||
321 !priv->config.hca_attr.flow_counters_dump ||
322 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) ||
323 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
327 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
328 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
329 priv->config.hca_attr.flow_counters_dump,
330 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap);
331 /* Initialize fallback mode only on the port initializes sh. */
333 sh->cmng.counter_fallback = fallback;
334 else if (fallback != sh->cmng.counter_fallback)
335 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
336 "with others:%d.", PORT_ID(priv), fallback);
341 * Spawn an Ethernet device from DevX information.
344 * Backing DPDK device.
346 * Verbs device parameters (name, port, switch_info) to spawn.
348 * Device configuration parameters.
351 * A valid Ethernet device object on success, NULL otherwise and rte_errno
352 * is set. The following errors are defined:
354 * EEXIST: device is already spawned
356 static struct rte_eth_dev *
357 mlx5_dev_spawn(struct rte_device *dpdk_dev,
358 struct mlx5_dev_spawn_data *spawn,
359 struct mlx5_dev_config *config)
361 const struct mlx5_switch_info *switch_info = &spawn->info;
362 struct mlx5_dev_ctx_shared *sh = NULL;
363 struct mlx5_dev_attr device_attr;
364 struct rte_eth_dev *eth_dev = NULL;
365 struct mlx5_priv *priv = NULL;
367 unsigned int cqe_comp;
368 struct rte_ether_addr mac;
369 char name[RTE_ETH_NAME_MAX_LEN];
370 int own_domain_id = 0;
374 /* Build device name. */
375 strlcpy(name, dpdk_dev->name, sizeof(name));
376 /* check if the device is already spawned */
377 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
381 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
383 * Some parameters are needed in advance to create device context. We
384 * process the devargs here to get ones, and later process devargs
385 * again to override some hardware settings.
387 err = mlx5_args(config, dpdk_dev->devargs);
390 DRV_LOG(ERR, "failed to process device arguments: %s",
391 strerror(rte_errno));
394 sh = mlx5_alloc_shared_dev_ctx(spawn, config);
397 config->devx = sh->devx;
398 /* Initialize the shutdown event in mlx5_dev_spawn to
399 * support mlx5_is_removed for Windows.
401 err = mlx5_glue->devx_init_showdown_event(sh->ctx);
403 DRV_LOG(ERR, "failed to init showdown event: %s",
407 DRV_LOG(DEBUG, "MPW isn't supported");
408 mlx5_os_get_dev_attr(sh->ctx, &device_attr);
409 config->swp = device_attr.sw_parsing_offloads &
410 (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
411 MLX5_SW_PARSING_TSO_CAP);
412 config->ind_table_max_size =
413 sh->device_attr.max_rwq_indirection_table_size;
415 config->cqe_comp = cqe_comp;
416 config->tunnel_en = device_attr.tunnel_offloads_caps &
417 (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |
418 MLX5_TUNNELED_OFFLOADS_GRE_CAP |
419 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);
420 if (config->tunnel_en) {
421 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
423 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "",
425 MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "",
427 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""
430 DRV_LOG(DEBUG, "tunnel offloading is not supported");
432 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported");
434 /* Allocate private eth device data. */
435 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
437 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
439 DRV_LOG(ERR, "priv allocation failure");
444 priv->dev_port = spawn->phys_port;
445 priv->pci_dev = spawn->pci_dev;
446 priv->mtu = RTE_ETHER_MTU;
447 priv->mp_id.port_id = port_id;
448 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
449 priv->representor = !!switch_info->representor;
450 priv->master = !!switch_info->master;
451 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
452 priv->vport_meta_tag = 0;
453 priv->vport_meta_mask = 0;
454 priv->pf_bond = spawn->pf_bond;
456 /* representor_id field keeps the unmodified VF index. */
457 priv->representor_id = -1;
459 * Look for sibling devices in order to reuse their switch domain
460 * if any, otherwise allocate one.
462 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
463 const struct mlx5_priv *opriv =
464 rte_eth_devices[port_id].data->dev_private;
467 opriv->sh != priv->sh ||
469 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
471 priv->domain_id = opriv->domain_id;
474 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
475 err = rte_eth_switch_domain_alloc(&priv->domain_id);
478 DRV_LOG(ERR, "unable to allocate switch domain: %s",
479 strerror(rte_errno));
484 /* Override some values set by hardware configuration. */
485 mlx5_args(config, dpdk_dev->devargs);
486 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev);
489 DRV_LOG(DEBUG, "counters are not supported");
490 config->ind_table_max_size =
491 sh->device_attr.max_rwq_indirection_table_size;
493 * Remove this check once DPDK supports larger/variable
494 * indirection tables.
496 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
497 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
498 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
499 config->ind_table_max_size);
500 if (config->hw_padding) {
501 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
502 config->hw_padding = 0;
504 config->tso = (sh->device_attr.max_tso > 0);
506 config->tso_max_payload_sz = sh->device_attr.max_tso;
507 DRV_LOG(DEBUG, "%sMPS is %s.",
508 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
509 config->mps == MLX5_MPW ? "legacy " : "",
510 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
511 if (config->cqe_comp && !cqe_comp) {
512 DRV_LOG(WARNING, "Rx CQE compression isn't supported.");
513 config->cqe_comp = 0;
516 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);
521 /* Check relax ordering support. */
522 sh->cmng.relaxed_ordering_read = 0;
523 sh->cmng.relaxed_ordering_write = 0;
524 if (!haswell_broadwell_cpu) {
525 sh->cmng.relaxed_ordering_write =
526 config->hca_attr.relaxed_ordering_write;
527 sh->cmng.relaxed_ordering_read =
528 config->hca_attr.relaxed_ordering_read;
530 config->hw_csum = config->hca_attr.csum_cap;
531 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
532 (config->hw_csum ? "" : "not "));
533 config->hw_vlan_strip = config->hca_attr.vlan_cap;
534 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
535 (config->hw_vlan_strip ? "" : "not "));
536 config->hw_fcs_strip = config->hca_attr.scatter_fcs;
539 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
541 err = config->hca_attr.access_register_user ?
542 mlx5_devx_cmd_register_read
543 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,
544 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
548 /* MTUTC register is read successfully. */
549 ts_mode = MLX5_GET(register_mtutc, reg,
551 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
552 config->rt_timestamp = 1;
554 /* Kernel does not support register reading. */
555 if (config->hca_attr.dev_freq_khz ==
556 (NS_PER_S / MS_PER_S))
557 config->rt_timestamp = 1;
559 sh->rq_ts_format = config->hca_attr.rq_ts_format;
560 sh->sq_ts_format = config->hca_attr.sq_ts_format;
561 sh->qp_ts_format = config->hca_attr.qp_ts_format;
563 if (config->mprq.enabled) {
564 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
565 config->mprq.enabled = 0;
567 if (config->max_dump_files_num == 0)
568 config->max_dump_files_num = 128;
569 eth_dev = rte_eth_dev_allocate(name);
570 if (eth_dev == NULL) {
571 DRV_LOG(ERR, "can not allocate rte ethdev");
575 if (priv->representor) {
576 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
577 eth_dev->data->representor_id = priv->representor_id;
578 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
579 struct mlx5_priv *opriv =
580 rte_eth_devices[port_id].data->dev_private;
583 opriv->domain_id == priv->domain_id &&
584 opriv->sh == priv->sh) {
585 eth_dev->data->backer_port_id = port_id;
589 if (port_id >= RTE_MAX_ETHPORTS)
590 eth_dev->data->backer_port_id = eth_dev->data->port_id;
593 * Store associated network device interface index. This index
594 * is permanent throughout the lifetime of device. So, we may store
595 * the ifindex here and use the cached value further.
597 MLX5_ASSERT(spawn->ifindex);
598 priv->if_index = spawn->ifindex;
599 eth_dev->data->dev_private = priv;
600 priv->dev_data = eth_dev->data;
601 eth_dev->data->mac_addrs = priv->mac;
602 eth_dev->device = dpdk_dev;
603 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
604 /* Configure the first MAC address by default. */
605 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
607 "port %u cannot get MAC address, is mlx5_en"
608 " loaded? (errno: %s).",
609 eth_dev->data->port_id, strerror(rte_errno));
614 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT,
615 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac));
616 #ifdef RTE_LIBRTE_MLX5_DEBUG
618 char ifname[MLX5_NAMESIZE];
620 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
621 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
622 eth_dev->data->port_id, ifname);
624 DRV_LOG(DEBUG, "port %u ifname is unknown.",
625 eth_dev->data->port_id);
628 /* Get actual MTU if possible. */
629 err = mlx5_get_mtu(eth_dev, &priv->mtu);
634 DRV_LOG(DEBUG, "port %u MTU is %u.", eth_dev->data->port_id,
636 /* Initialize burst functions to prevent crashes before link-up. */
637 eth_dev->rx_pkt_burst = removed_rx_burst;
638 eth_dev->tx_pkt_burst = removed_tx_burst;
639 eth_dev->dev_ops = &mlx5_dev_ops;
640 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
641 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
642 eth_dev->rx_queue_count = mlx5_rx_queue_count;
643 /* Register MAC address. */
644 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
645 priv->ctrl_flows = 0;
646 TAILQ_INIT(&priv->flow_meters);
647 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR);
648 if (!priv->mtr_profile_tbl)
650 /* Bring Ethernet device up. */
651 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up.",
652 eth_dev->data->port_id);
653 /* nl calls are unsupported - set to -1 not to fail on release */
654 priv->nl_socket_rdma = -1;
655 priv->nl_socket_route = -1;
656 mlx5_set_link_up(eth_dev);
658 * Even though the interrupt handler is not installed yet,
659 * interrupts will still trigger on the async_fd from
660 * Verbs context returned by ibv_open_device().
662 mlx5_link_update(eth_dev, 0);
663 config->dv_esw_en = 0;
664 /* Detect minimal data bytes to inline. */
665 mlx5_set_min_inline(spawn, config);
666 /* Store device configuration on private structure. */
667 priv->config = *config;
668 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
669 icfg[i].release_mem_en = !!config->reclaim_mode;
670 if (config->reclaim_mode)
671 icfg[i].per_core_cache = 0;
672 priv->flows[i] = mlx5_ipool_create(&icfg[i]);
676 /* Create context for virtual machine VLAN workaround. */
677 priv->vmwa_context = NULL;
678 if (config->dv_flow_en) {
679 err = mlx5_alloc_shared_dr(priv);
683 /* No supported flow priority number detection. */
684 priv->config.flow_prio = -1;
685 if (!priv->config.dv_esw_en &&
686 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
687 DRV_LOG(WARNING, "metadata mode %u is not supported "
688 "(no E-Switch)", priv->config.dv_xmeta_en);
689 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
691 mlx5_set_metadata_mask(eth_dev);
692 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
693 !priv->sh->dv_regc0_mask) {
694 DRV_LOG(ERR, "metadata mode %u is not supported "
695 "(no metadata reg_c[0] is available).",
696 priv->config.dv_xmeta_en);
700 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true,
701 mlx5_hrxq_create_cb, mlx5_hrxq_match_cb,
702 mlx5_hrxq_remove_cb, mlx5_hrxq_clone_cb,
703 mlx5_hrxq_clone_free_cb);
704 /* Query availability of metadata reg_c's. */
705 err = mlx5_flow_discover_mreg_c(eth_dev);
710 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
712 "port %u extensive metadata register is not supported.",
713 eth_dev->data->port_id);
714 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
715 DRV_LOG(ERR, "metadata mode %u is not supported "
716 "(no metadata registers available).",
717 priv->config.dv_xmeta_en);
722 if (config->devx && config->dv_flow_en) {
723 priv->obj_ops = devx_obj_ops;
725 DRV_LOG(ERR, "Flow mode %u is not supported "
726 "(Windows flow must be DevX with DV flow enabled).",
727 priv->config.dv_flow_en);
731 mlx5_flow_counter_mode_config(eth_dev);
735 if (priv->mtr_profile_tbl)
736 mlx5_l3t_destroy(priv->mtr_profile_tbl);
738 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
741 eth_dev->data->dev_private = NULL;
743 if (eth_dev != NULL) {
744 /* mac_addrs must not be freed alone because part of
747 eth_dev->data->mac_addrs = NULL;
748 rte_eth_dev_release_port(eth_dev);
751 mlx5_free_shared_dev_ctx(sh);
752 MLX5_ASSERT(err > 0);
758 * This function should share events between multiple ports of single IB
759 * device. Currently it has no support under Windows.
762 * Pointer to mlx5_dev_ctx_shared object.
765 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
768 DRV_LOG(WARNING, "%s: is not supported", __func__);
772 * This function should share events between multiple ports of single IB
773 * device. Currently it has no support under Windows.
776 * Pointer to mlx5_dev_ctx_shared object.
779 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
782 DRV_LOG(WARNING, "%s: is not supported", __func__);
786 * Read statistics by a named counter.
789 * Pointer to the private device data structure.
790 * @param[in] ctr_name
791 * Pointer to the name of the statistic counter to read
793 * Pointer to read statistic value.
795 * 0 on success and stat is valud, 1 if failed to read the value
800 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
804 RTE_SET_USED(ctr_name);
806 DRV_LOG(WARNING, "%s: is not supported", __func__);
811 * Flush device MAC addresses
812 * Currently it has no support under Windows.
815 * Pointer to Ethernet device structure.
819 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev)
822 DRV_LOG(WARNING, "%s: is not supported", __func__);
826 * Remove a MAC address from device
827 * Currently it has no support under Windows.
830 * Pointer to Ethernet device structure.
835 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
839 DRV_LOG(WARNING, "%s: is not supported", __func__);
843 * Adds a MAC address to the device
844 * Currently it has no support under Windows.
847 * Pointer to Ethernet device structure.
849 * MAC address to register.
854 * 0 on success, a negative errno value otherwise
857 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
861 struct rte_ether_addr lmac;
863 if (mlx5_get_mac(dev, &lmac.addr_bytes)) {
865 "port %u cannot get MAC address, is mlx5_en"
866 " loaded? (errno: %s)",
867 dev->data->port_id, strerror(rte_errno));
870 if (!rte_is_same_ether_addr(&lmac, mac)) {
872 "adding new mac address to device is unsupported");
879 * Modify a VF MAC address
880 * Currently it has no support under Windows.
883 * Pointer to device private data.
885 * MAC address to modify into.
887 * Net device interface index
892 * 0 on success, a negative errno value otherwise
895 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv,
896 unsigned int iface_idx,
897 struct rte_ether_addr *mac_addr,
904 DRV_LOG(WARNING, "%s: is not supported", __func__);
909 * Set device promiscuous mode
910 * Currently it has no support under Windows.
913 * Pointer to Ethernet device structure.
915 * 0 - promiscuous is disabled, otherwise - enabled
918 * 0 on success, a negative error value otherwise
921 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable)
925 DRV_LOG(WARNING, "%s: is not supported", __func__);
930 * Set device allmulti mode
933 * Pointer to Ethernet device structure.
935 * 0 - all multicase is disabled, otherwise - enabled
938 * 0 on success, a negative error value otherwise
941 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)
945 DRV_LOG(WARNING, "%s: is not supported", __func__);
950 * Detect if a devx_device_bdf object has identical DBDF values to the
951 * rte_pci_addr found in bus/pci probing
953 * @param[in] devx_bdf
954 * Pointer to the devx_device_bdf structure.
956 * Pointer to the rte_pci_addr structure.
959 * 1 on Device match, 0 on mismatch.
962 mlx5_match_devx_bdf_to_addr(struct devx_device_bdf *devx_bdf,
963 struct rte_pci_addr *addr)
965 if (addr->domain != (devx_bdf->bus_id >> 8) ||
966 addr->bus != (devx_bdf->bus_id & 0xff) ||
967 addr->devid != devx_bdf->dev_id ||
968 addr->function != devx_bdf->fnc_id) {
975 * Detect if a devx_device_bdf object matches the rte_pci_addr
976 * found in bus/pci probing
977 * Compare both the Native/PF BDF and the raw_bdf representing a VF BDF.
979 * @param[in] devx_bdf
980 * Pointer to the devx_device_bdf structure.
982 * Pointer to the rte_pci_addr structure.
985 * 1 on Device match, 0 on mismatch, rte_errno code on failure.
988 mlx5_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf,
989 struct rte_pci_addr *addr)
992 struct devx_device mlx5_dev;
994 if (mlx5_match_devx_bdf_to_addr(devx_bdf, addr))
997 * Didn't match on Native/PF BDF, could still
998 * Match a VF BDF, check it next
1000 err = mlx5_glue->query_device(devx_bdf, &mlx5_dev);
1002 DRV_LOG(ERR, "query_device failed");
1006 if (mlx5_match_devx_bdf_to_addr(&mlx5_dev.raw_bdf, addr))
1012 * DPDK callback to register a PCI device.
1014 * This function spawns Ethernet devices out of a given device.
1017 * Pointer to the common device.
1020 * 0 on success, a negative errno value otherwise and rte_errno is set.
1023 mlx5_os_net_probe(struct mlx5_common_device *cdev)
1025 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);
1026 struct devx_device_bdf *devx_bdf_devs, *orig_devx_bdf_devs;
1028 * Number of found IB Devices matching with requested PCI BDF.
1029 * nd != 1 means there are multiple IB devices over the same
1030 * PCI device and we have representors and master.
1032 unsigned int nd = 0;
1034 * Number of found IB device Ports. nd = 1 and np = 1..n means
1035 * we have the single multiport IB device, and there may be
1036 * representors attached to some of found ports.
1037 * Currently not supported.
1038 * unsigned int np = 0;
1042 * Number of DPDK ethernet devices to Spawn - either over
1043 * multiple IB devices or multiple ports of single IB device.
1044 * Actually this is the number of iterations to spawn.
1046 unsigned int ns = 0;
1049 * < 0 - no bonding device (single one)
1050 * >= 0 - bonding device (value is slave PF index)
1053 struct mlx5_dev_spawn_data *list = NULL;
1054 struct mlx5_dev_config dev_config;
1055 unsigned int dev_config_vf;
1059 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1060 DRV_LOG(ERR, "Secondary process is not supported on Windows.");
1063 ret = mlx5_init_once();
1065 DRV_LOG(ERR, "unable to init PMD global data: %s",
1066 strerror(rte_errno));
1070 devx_bdf_devs = mlx5_glue->get_device_list(&ret);
1071 orig_devx_bdf_devs = devx_bdf_devs;
1072 if (!devx_bdf_devs) {
1073 rte_errno = errno ? errno : ENOSYS;
1074 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1078 * First scan the list of all Infiniband devices to find
1079 * matching ones, gathering into the list.
1081 struct devx_device_bdf *devx_bdf_match[ret + 1];
1084 err = mlx5_match_devx_devices_to_addr(devx_bdf_devs,
1094 devx_bdf_match[nd++] = devx_bdf_devs;
1096 devx_bdf_match[nd] = NULL;
1098 /* No device matches, just complain and bail out. */
1100 "no DevX device matches PCI device " PCI_PRI_FMT ","
1101 " is DevX Configured?",
1102 pci_dev->addr.domain, pci_dev->addr.bus,
1103 pci_dev->addr.devid, pci_dev->addr.function);
1109 * Now we can determine the maximal
1110 * amount of devices to be spawned.
1112 list = mlx5_malloc(MLX5_MEM_ZERO,
1113 sizeof(struct mlx5_dev_spawn_data),
1114 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1116 DRV_LOG(ERR, "spawn data array allocation failure");
1121 memset(&list[ns].info, 0, sizeof(list[ns].info));
1122 list[ns].max_port = 1;
1123 list[ns].phys_port = 1;
1124 list[ns].phys_dev = devx_bdf_match[ns];
1125 list[ns].eth_dev = NULL;
1126 list[ns].pci_dev = pci_dev;
1127 list[ns].cdev = cdev;
1128 list[ns].pf_bond = bd;
1129 list[ns].ifindex = -1; /* Spawn will assign */
1131 (struct mlx5_switch_info){
1134 .name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK,
1138 /* Device specific configuration. */
1139 switch (pci_dev->id.device_id) {
1140 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1141 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1142 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1143 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1144 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
1145 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
1146 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF:
1153 /* Default configuration. */
1154 memset(&dev_config, 0, sizeof(struct mlx5_dev_config));
1155 dev_config.vf = dev_config_vf;
1157 dev_config.rx_vec_en = 1;
1158 dev_config.txq_inline_max = MLX5_ARG_UNSET;
1159 dev_config.txq_inline_min = MLX5_ARG_UNSET;
1160 dev_config.txq_inline_mpw = MLX5_ARG_UNSET;
1161 dev_config.txqs_inline = MLX5_ARG_UNSET;
1162 dev_config.vf_nl_en = 0;
1163 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;
1164 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;
1165 dev_config.dv_esw_en = 0;
1166 dev_config.dv_flow_en = 1;
1167 dev_config.decap_en = 0;
1168 dev_config.log_hp_size = MLX5_ARG_UNSET;
1169 list[ns].eth_dev = mlx5_dev_spawn(cdev->dev, &list[ns], &dev_config);
1170 if (!list[ns].eth_dev)
1172 restore = list[ns].eth_dev->data->dev_flags;
1173 rte_eth_copy_pci_info(list[ns].eth_dev, pci_dev);
1174 /* Restore non-PCI flags cleared by the above call. */
1175 list[ns].eth_dev->data->dev_flags |= restore;
1176 rte_eth_dev_probing_finish(list[ns].eth_dev);
1180 * Do the routine cleanup:
1181 * - free allocated spawn data array
1182 * - free the device list
1186 MLX5_ASSERT(orig_devx_bdf_devs);
1187 mlx5_glue->free_device_list(orig_devx_bdf_devs);
1192 * Set the reg_mr and dereg_mr call backs
1194 * @param reg_mr_cb[out]
1195 * Pointer to reg_mr func
1196 * @param dereg_mr_cb[out]
1197 * Pointer to dereg_mr func
1201 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1202 mlx5_dereg_mr_t *dereg_mr_cb)
1204 *reg_mr_cb = mlx5_os_reg_mr;
1205 *dereg_mr_cb = mlx5_os_dereg_mr;
1209 * Extract pdn of PD object using DevX
1212 * Pointer to the DevX PD object.
1214 * Pointer to the PD object number variable.
1217 * 0 on success, error value otherwise.
1220 mlx5_os_get_pdn(void *pd, uint32_t *pdn)
1225 *pdn = ((struct mlx5_pd *)pd)->pdn;
1229 const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0};