drivers/net/mlx5/windows/mlx5_os.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <errno.h>
   6 #include <stdalign.h>
   7 #include <stddef.h>
   8 #include <stdint.h>
   9 #include <stdlib.h>
  10
  11 #include <rte_windows.h>
  12 #include <ethdev_pci.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_devx_cmds.h>
  16 #include <mlx5_common.h>
  17 #include <mlx5_common_mp.h>
  18 #include <mlx5_common_mr.h>
  19 #include <mlx5_malloc.h>
  20
  21 #include "mlx5_defs.h"
  22 #include "mlx5.h"
  23 #include "mlx5_common_os.h"
  24 #include "mlx5_utils.h"
  25 #include "mlx5_rxtx.h"
  26 #include "mlx5_rx.h"
  27 #include "mlx5_tx.h"
  28 #include "mlx5_autoconf.h"
  29 #include "mlx5_flow.h"
  30 #include "mlx5_devx.h"
  31
  32 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
  33
  34 /* Spinlock for mlx5_shared_data allocation. */
  35 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
  36
  37 /* rte flow indexed pool configuration. */
  38 static struct mlx5_indexed_pool_config icfg[] = {
  39         {
  40                 .size = sizeof(struct rte_flow),
  41                 .trunk_size = 64,
  42                 .need_lock = 1,
  43                 .release_mem_en = 0,
  44                 .malloc = mlx5_malloc,
  45                 .free = mlx5_free,
  46                 .per_core_cache = 0,
  47                 .type = "ctl_flow_ipool",
  48         },
  49         {
  50                 .size = sizeof(struct rte_flow),
  51                 .trunk_size = 64,
  52                 .grow_trunk = 3,
  53                 .grow_shift = 2,
  54                 .need_lock = 1,
  55                 .release_mem_en = 0,
  56                 .malloc = mlx5_malloc,
  57                 .free = mlx5_free,
  58                 .per_core_cache = 1 << 14,
  59                 .type = "rte_flow_ipool",
  60         },
  61         {
  62                 .size = sizeof(struct rte_flow),
  63                 .trunk_size = 64,
  64                 .grow_trunk = 3,
  65                 .grow_shift = 2,
  66                 .need_lock = 1,
  67                 .release_mem_en = 0,
  68                 .malloc = mlx5_malloc,
  69                 .free = mlx5_free,
  70                 .per_core_cache = 0,
  71                 .type = "mcp_flow_ipool",
  72         },
  73 };
  74
  75 static void
  76 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev)
  77 {
  78         struct mlx5_priv *priv = dev->data->dev_private;
  79         void *ctx = priv->sh->cdev->ctx;
  80
  81         priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx);
  82         if (!priv->q_counters) {
  83                 DRV_LOG(ERR, "Port %d queue counter object cannot be created "
  84                         "by DevX - imissed counter will be unavailable",
  85                         dev->data->port_id);
  86                 return;
  87         }
  88         priv->counter_set_id = priv->q_counters->id;
  89 }
  90
  91 /**
  92  * Initialize shared data between primary and secondary process.
  93  *
  94  * A memzone is reserved by primary process and secondary processes attach to
  95  * the memzone.
  96  *
  97  * @return
  98  *   0 on success, a negative errno value otherwise and rte_errno is set.
  99  */
 100 static int
 101 mlx5_init_shared_data(void)
 102 {
 103         const struct rte_memzone *mz;
 104         int ret = 0;
 105
 106         rte_spinlock_lock(&mlx5_shared_data_lock);
 107         if (mlx5_shared_data == NULL) {
 108                 /* Allocate shared memory. */
 109                 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 110                                          sizeof(*mlx5_shared_data),
 111                                          SOCKET_ID_ANY, 0);
 112                 if (mz == NULL) {
 113                         DRV_LOG(ERR,
 114                                 "Cannot allocate mlx5 shared data");
 115                         ret = -rte_errno;
 116                         goto error;
 117                 }
 118                 mlx5_shared_data = mz->addr;
 119                 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 120                 rte_spinlock_init(&mlx5_shared_data->lock);
 121         }
 122 error:
 123         rte_spinlock_unlock(&mlx5_shared_data_lock);
 124         return ret;
 125 }
 126
 127 /**
 128  * PMD global initialization.
 129  *
 130  * Independent from individual device, this function initializes global
 131  * per-PMD data structures distinguishing primary and secondary processes.
 132  * Hence, each initialization is called once per a process.
 133  *
 134  * @return
 135  *   0 on success, a negative errno value otherwise and rte_errno is set.
 136  */
 137 static int
 138 mlx5_init_once(void)
 139 {
 140         if (mlx5_init_shared_data())
 141                 return -rte_errno;
 142         return 0;
 143 }
 144
 145 /**
 146  * Get mlx5 device capabilities.
 147  *
 148  * @param sh
 149  *   Pointer to shared device context.
 150  *
 151  * @return
 152  *   0 on success, a negative errno value otherwise and rte_errno is set.
 153  */
 154 int
 155 mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh)
 156 {
 157         struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;
 158         struct mlx5_context *mlx5_ctx = sh->cdev->ctx;
 159         void *pv_iseg = NULL;
 160         u32 cb_iseg = 0;
 161
 162         pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
 163         if (pv_iseg == NULL) {
 164                 DRV_LOG(ERR, "Failed to get device hca_iseg.");
 165                 rte_errno = errno;
 166                 return -rte_errno;
 167         }
 168         memset(&sh->dev_cap, 0, sizeof(struct mlx5_dev_cap));
 169         sh->dev_cap.max_cq = 1 << hca_attr->log_max_cq;
 170         sh->dev_cap.max_qp = 1 << hca_attr->log_max_qp;
 171         sh->dev_cap.max_qp_wr = 1 << hca_attr->log_max_qp_sz;
 172         sh->dev_cap.max_tso = 1 << hca_attr->max_lso_cap;
 173         if (hca_attr->rss_ind_tbl_cap) {
 174                 sh->dev_cap.max_rwq_indirection_table_size =
 175                         1 << hca_attr->rss_ind_tbl_cap;
 176         }
 177         sh->dev_cap.sw_parsing_offloads =
 178                 mlx5_get_supported_sw_parsing_offloads(hca_attr);
 179         sh->dev_cap.tunnel_offloads_caps =
 180                 mlx5_get_supported_tunneling_offloads(hca_attr);
 181         snprintf(sh->dev_cap.fw_ver, 64, "%x.%x.%04x",
 182                  MLX5_GET(initial_seg, pv_iseg, fw_rev_major),
 183                  MLX5_GET(initial_seg, pv_iseg, fw_rev_minor),
 184                  MLX5_GET(initial_seg, pv_iseg, fw_rev_subminor));
 185         return 0;
 186 }
 187
 188 /**
 189  * Initialize DR related data within private structure.
 190  * Routine checks the reference counter and does actual
 191  * resources creation/initialization only if counter is zero.
 192  *
 193  * @param[in] priv
 194  *   Pointer to the private device data structure.
 195  *
 196  * @return
 197  *   Zero on success, positive error code otherwise.
 198  */
 199 static int
 200 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
 201 {
 202         struct mlx5_dev_ctx_shared *sh = priv->sh;
 203         int err = 0;
 204
 205         if (!sh->flow_tbls)
 206                 err = mlx5_alloc_table_hash_list(priv);
 207         else
 208                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse",
 209                         (void *)sh->flow_tbls);
 210         return err;
 211 }
 212 /**
 213  * Destroy DR related data within private structure.
 214  *
 215  * @param[in] priv
 216  *   Pointer to the private device data structure.
 217  */
 218 void
 219 mlx5_os_free_shared_dr(struct mlx5_priv *priv)
 220 {
 221         mlx5_free_table_hash_list(priv);
 222 }
 223
 224 /**
 225  * Set the completion channel file descriptor interrupt as non-blocking.
 226  * Currently it has no support under Windows.
 227  *
 228  * @param[in] rxq_obj
 229  *   Pointer to RQ channel object, which includes the channel fd
 230  *
 231  * @param[out] fd
 232  *   The file descriptor (representing the interrupt) used in this channel.
 233  *
 234  * @return
 235  *   0 on successfully setting the fd to non-blocking, non-zero otherwise.
 236  */
 237 int
 238 mlx5_os_set_nonblock_channel_fd(int fd)
 239 {
 240         (void)fd;
 241         DRV_LOG(WARNING, "%s: is not supported", __func__);
 242         return -ENOTSUP;
 243 }
 244
 245 /**
 246  * Spawn an Ethernet device from DevX information.
 247  *
 248  * @param dpdk_dev
 249  *   Backing DPDK device.
 250  * @param spawn
 251  *   Verbs device parameters (name, port, switch_info) to spawn.
 252  * @param config
 253  *   Device configuration parameters.
 254  *
 255  * @return
 256  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
 257  *   is set. The following errors are defined:
 258  *
 259  *   EEXIST: device is already spawned
 260  */
 261 static struct rte_eth_dev *
 262 mlx5_dev_spawn(struct rte_device *dpdk_dev,
 263                struct mlx5_dev_spawn_data *spawn,
 264                struct mlx5_dev_config *config)
 265 {
 266         const struct mlx5_switch_info *switch_info = &spawn->info;
 267         struct mlx5_dev_ctx_shared *sh = NULL;
 268         struct mlx5_hca_attr *hca_attr;
 269         struct rte_eth_dev *eth_dev = NULL;
 270         struct mlx5_priv *priv = NULL;
 271         int err = 0;
 272         struct rte_ether_addr mac;
 273         char name[RTE_ETH_NAME_MAX_LEN];
 274         int own_domain_id = 0;
 275         uint16_t port_id;
 276         int i;
 277
 278         /* Build device name. */
 279         strlcpy(name, dpdk_dev->name, sizeof(name));
 280         /* check if the device is already spawned */
 281         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
 282                 rte_errno = EEXIST;
 283                 return NULL;
 284         }
 285         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
 286         /* Process parameters. */
 287         err = mlx5_args(config, dpdk_dev->devargs);
 288         if (err) {
 289                 err = rte_errno;
 290                 DRV_LOG(ERR, "failed to process device arguments: %s",
 291                         strerror(rte_errno));
 292                 goto error;
 293         }
 294         sh = mlx5_alloc_shared_dev_ctx(spawn, config);
 295         if (!sh)
 296                 return NULL;
 297         /* Update final values for devargs before check sibling config. */
 298         config->dv_esw_en = 0;
 299         if (!config->dv_flow_en) {
 300                 DRV_LOG(ERR, "Windows flow mode must be DV flow enable.");
 301                 err = ENOTSUP;
 302                 goto error;
 303         }
 304         if (!config->dv_esw_en &&
 305             config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
 306                 DRV_LOG(WARNING,
 307                         "Metadata mode %u is not supported (no E-Switch).",
 308                         config->dv_xmeta_en);
 309                 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
 310         }
 311         /* Check sibling device configurations. */
 312         err = mlx5_dev_check_sibling_config(sh, config, dpdk_dev);
 313         if (err)
 314                 goto error;
 315         /* Initialize the shutdown event in mlx5_dev_spawn to
 316          * support mlx5_is_removed for Windows.
 317          */
 318         err = mlx5_glue->devx_init_showdown_event(sh->cdev->ctx);
 319         if (err) {
 320                 DRV_LOG(ERR, "failed to init showdown event: %s",
 321                         strerror(errno));
 322                 goto error;
 323         }
 324         DRV_LOG(DEBUG, "MPW isn't supported");
 325         config->swp = sh->dev_cap.sw_parsing_offloads &
 326                 (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
 327                  MLX5_SW_PARSING_TSO_CAP);
 328         config->ind_table_max_size =
 329                 sh->dev_cap.max_rwq_indirection_table_size;
 330         config->tunnel_en = sh->dev_cap.tunnel_offloads_caps &
 331                 (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |
 332                  MLX5_TUNNELED_OFFLOADS_GRE_CAP |
 333                  MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);
 334         if (config->tunnel_en) {
 335                 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
 336                 config->tunnel_en &
 337                 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "",
 338                 config->tunnel_en &
 339                 MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "",
 340                 config->tunnel_en &
 341                 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""
 342                 );
 343         } else {
 344                 DRV_LOG(DEBUG, "tunnel offloading is not supported");
 345         }
 346         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported");
 347         config->mpls_en = 0;
 348         /* Allocate private eth device data. */
 349         priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 350                            sizeof(*priv),
 351                            RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 352         if (priv == NULL) {
 353                 DRV_LOG(ERR, "priv allocation failure");
 354                 err = ENOMEM;
 355                 goto error;
 356         }
 357         priv->sh = sh;
 358         priv->dev_port = spawn->phys_port;
 359         priv->pci_dev = spawn->pci_dev;
 360         priv->mtu = RTE_ETHER_MTU;
 361         priv->mp_id.port_id = port_id;
 362         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
 363         priv->representor = !!switch_info->representor;
 364         priv->master = !!switch_info->master;
 365         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
 366         priv->vport_meta_tag = 0;
 367         priv->vport_meta_mask = 0;
 368         priv->pf_bond = spawn->pf_bond;
 369         priv->vport_id = -1;
 370         /* representor_id field keeps the unmodified VF index. */
 371         priv->representor_id = -1;
 372         /*
 373          * Look for sibling devices in order to reuse their switch domain
 374          * if any, otherwise allocate one.
 375          */
 376         MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
 377                 const struct mlx5_priv *opriv =
 378                         rte_eth_devices[port_id].data->dev_private;
 379
 380                 if (!opriv ||
 381                     opriv->sh != priv->sh ||
 382                         opriv->domain_id ==
 383                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
 384                         continue;
 385                 priv->domain_id = opriv->domain_id;
 386                 break;
 387         }
 388         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
 389                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
 390                 if (err) {
 391                         err = rte_errno;
 392                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
 393                                 strerror(rte_errno));
 394                         goto error;
 395                 }
 396                 own_domain_id = 1;
 397         }
 398         DRV_LOG(DEBUG, "counters are not supported");
 399         config->ind_table_max_size =
 400                 sh->dev_cap.max_rwq_indirection_table_size;
 401         /*
 402          * Remove this check once DPDK supports larger/variable
 403          * indirection tables.
 404          */
 405         if (config->ind_table_max_size > (unsigned int)RTE_ETH_RSS_RETA_SIZE_512)
 406                 config->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512;
 407         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 408                 config->ind_table_max_size);
 409         if (config->hw_padding) {
 410                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
 411                 config->hw_padding = 0;
 412         }
 413         config->tso = (sh->dev_cap.max_tso > 0);
 414         if (config->tso)
 415                 config->tso_max_payload_sz = sh->dev_cap.max_tso;
 416         DRV_LOG(DEBUG, "%sMPS is %s.",
 417                 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
 418                 config->mps == MLX5_MPW ? "legacy " : "",
 419                 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
 420         if (config->cqe_comp) {
 421                 DRV_LOG(WARNING, "Rx CQE compression isn't supported.");
 422                 config->cqe_comp = 0;
 423         }
 424         if (sh->cdev->config.devx) {
 425                 hca_attr = &sh->cdev->config.hca_attr;
 426                 config->hw_csum = hca_attr->csum_cap;
 427                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 428                         (config->hw_csum ? "" : "not "));
 429                 config->hw_vlan_strip = hca_attr->vlan_cap;
 430                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 431                         (config->hw_vlan_strip ? "" : "not "));
 432                 config->hw_fcs_strip = hca_attr->scatter_fcs;
 433                 mlx5_rt_timestamp_config(sh, config, hca_attr);
 434         }
 435         if (config->mprq.enabled) {
 436                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
 437                 config->mprq.enabled = 0;
 438         }
 439         if (config->max_dump_files_num == 0)
 440                 config->max_dump_files_num = 128;
 441         eth_dev = rte_eth_dev_allocate(name);
 442         if (eth_dev == NULL) {
 443                 DRV_LOG(ERR, "can not allocate rte ethdev");
 444                 err = ENOMEM;
 445                 goto error;
 446         }
 447         if (priv->representor) {
 448                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
 449                 eth_dev->data->representor_id = priv->representor_id;
 450                 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
 451                         struct mlx5_priv *opriv =
 452                                 rte_eth_devices[port_id].data->dev_private;
 453                         if (opriv &&
 454                             opriv->master &&
 455                             opriv->domain_id == priv->domain_id &&
 456                             opriv->sh == priv->sh) {
 457                                 eth_dev->data->backer_port_id = port_id;
 458                                 break;
 459                         }
 460                 }
 461                 if (port_id >= RTE_MAX_ETHPORTS)
 462                         eth_dev->data->backer_port_id = eth_dev->data->port_id;
 463         }
 464         /*
 465          * Store associated network device interface index. This index
 466          * is permanent throughout the lifetime of device. So, we may store
 467          * the ifindex here and use the cached value further.
 468          */
 469         MLX5_ASSERT(spawn->ifindex);
 470         priv->if_index = spawn->ifindex;
 471         eth_dev->data->dev_private = priv;
 472         priv->dev_data = eth_dev->data;
 473         eth_dev->data->mac_addrs = priv->mac;
 474         eth_dev->device = dpdk_dev;
 475         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 476         /* Configure the first MAC address by default. */
 477         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
 478                 DRV_LOG(ERR,
 479                         "port %u cannot get MAC address, is mlx5_en"
 480                         " loaded? (errno: %s).",
 481                         eth_dev->data->port_id, strerror(rte_errno));
 482                 err = ENODEV;
 483                 goto error;
 484         }
 485         DRV_LOG(INFO,
 486                 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT,
 487                 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac));
 488 #ifdef RTE_LIBRTE_MLX5_DEBUG
 489         {
 490                 char ifname[MLX5_NAMESIZE];
 491
 492                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
 493                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
 494                                 eth_dev->data->port_id, ifname);
 495                 else
 496                         DRV_LOG(DEBUG, "port %u ifname is unknown.",
 497                                 eth_dev->data->port_id);
 498         }
 499 #endif
 500         /* Get actual MTU if possible. */
 501         err = mlx5_get_mtu(eth_dev, &priv->mtu);
 502         if (err) {
 503                 err = rte_errno;
 504                 goto error;
 505         }
 506         DRV_LOG(DEBUG, "port %u MTU is %u.", eth_dev->data->port_id,
 507                 priv->mtu);
 508         /* Initialize burst functions to prevent crashes before link-up. */
 509         eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
 510         eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
 511         eth_dev->dev_ops = &mlx5_dev_ops;
 512         eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
 513         eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
 514         eth_dev->rx_queue_count = mlx5_rx_queue_count;
 515         /* Register MAC address. */
 516         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
 517         priv->ctrl_flows = 0;
 518         TAILQ_INIT(&priv->flow_meters);
 519         priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR);
 520         if (!priv->mtr_profile_tbl)
 521                 goto error;
 522         /* Bring Ethernet device up. */
 523         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up.",
 524                 eth_dev->data->port_id);
 525         /* nl calls are unsupported - set to -1 not to fail on release */
 526         priv->nl_socket_rdma = -1;
 527         priv->nl_socket_route = -1;
 528         mlx5_set_link_up(eth_dev);
 529         /*
 530          * Even though the interrupt handler is not installed yet,
 531          * interrupts will still trigger on the async_fd from
 532          * Verbs context returned by ibv_open_device().
 533          */
 534         mlx5_link_update(eth_dev, 0);
 535         /* Detect minimal data bytes to inline. */
 536         mlx5_set_min_inline(spawn, config);
 537         /* Store device configuration on private structure. */
 538         priv->config = *config;
 539         for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
 540                 icfg[i].release_mem_en = !!config->reclaim_mode;
 541                 if (config->reclaim_mode)
 542                         icfg[i].per_core_cache = 0;
 543                 priv->flows[i] = mlx5_ipool_create(&icfg[i]);
 544                 if (!priv->flows[i])
 545                         goto error;
 546         }
 547         /* Create context for virtual machine VLAN workaround. */
 548         priv->vmwa_context = NULL;
 549         if (config->dv_flow_en) {
 550                 err = mlx5_alloc_shared_dr(priv);
 551                 if (err)
 552                         goto error;
 553         }
 554         /* No supported flow priority number detection. */
 555         priv->sh->flow_max_priority = -1;
 556         mlx5_set_metadata_mask(eth_dev);
 557         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
 558             !priv->sh->dv_regc0_mask) {
 559                 DRV_LOG(ERR, "metadata mode %u is not supported "
 560                              "(no metadata reg_c[0] is available).",
 561                              priv->config.dv_xmeta_en);
 562                         err = ENOTSUP;
 563                         goto error;
 564         }
 565         priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true,
 566                 mlx5_hrxq_create_cb, mlx5_hrxq_match_cb,
 567                 mlx5_hrxq_remove_cb, mlx5_hrxq_clone_cb,
 568                 mlx5_hrxq_clone_free_cb);
 569         /* Query availability of metadata reg_c's. */
 570         if (!priv->sh->metadata_regc_check_flag) {
 571                 err = mlx5_flow_discover_mreg_c(eth_dev);
 572                 if (err < 0) {
 573                         err = -err;
 574                         goto error;
 575                 }
 576         }
 577         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
 578                 DRV_LOG(DEBUG,
 579                         "port %u extensive metadata register is not supported.",
 580                         eth_dev->data->port_id);
 581                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
 582                         DRV_LOG(ERR, "metadata mode %u is not supported "
 583                                      "(no metadata registers available).",
 584                                      priv->config.dv_xmeta_en);
 585                         err = ENOTSUP;
 586                         goto error;
 587                 }
 588         }
 589         if (sh->cdev->config.devx) {
 590                 priv->obj_ops = devx_obj_ops;
 591         } else {
 592                 DRV_LOG(ERR, "Windows flow must be DevX.");
 593                 err = ENOTSUP;
 594                 goto error;
 595         }
 596         mlx5_flow_counter_mode_config(eth_dev);
 597         mlx5_queue_counter_id_prepare(eth_dev);
 598         return eth_dev;
 599 error:
 600         if (priv) {
 601                 if (priv->mtr_profile_tbl)
 602                         mlx5_l3t_destroy(priv->mtr_profile_tbl);
 603                 if (own_domain_id)
 604                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
 605                 mlx5_free(priv);
 606                 if (eth_dev != NULL)
 607                         eth_dev->data->dev_private = NULL;
 608         }
 609         if (eth_dev != NULL) {
 610                 /* mac_addrs must not be freed alone because part of
 611                  * dev_private
 612                  **/
 613                 eth_dev->data->mac_addrs = NULL;
 614                 rte_eth_dev_release_port(eth_dev);
 615         }
 616         if (sh)
 617                 mlx5_free_shared_dev_ctx(sh);
 618         MLX5_ASSERT(err > 0);
 619         rte_errno = err;
 620         return NULL;
 621 }
 622
 623 /**
 624  * This function should share events between multiple ports of single IB
 625  * device.  Currently it has no support under Windows.
 626  *
 627  * @param sh
 628  *   Pointer to mlx5_dev_ctx_shared object.
 629  */
 630 void
 631 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
 632 {
 633         (void)sh;
 634         DRV_LOG(WARNING, "%s: is not supported", __func__);
 635 }
 636
 637 /**
 638  * This function should share events between multiple ports of single IB
 639  * device.  Currently it has no support under Windows.
 640  *
 641  * @param dev
 642  *   Pointer to mlx5_dev_ctx_shared object.
 643  */
 644 void
 645 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
 646 {
 647         (void)sh;
 648         DRV_LOG(WARNING, "%s: is not supported", __func__);
 649 }
 650
 651 /**
 652  * Read statistics by a named counter.
 653  *
 654  * @param[in] priv
 655  *   Pointer to the private device data structure.
 656  * @param[in] ctr_name
 657  *   Pointer to the name of the statistic counter to read
 658  * @param[out] stat
 659  *   Pointer to read statistic value.
 660  * @return
 661  *   0 on success and stat is valid, non-zero if failed to read the value
 662  *   or counter is not supported.
 663  *   rte_errno is set.
 664  *
 665  */
 666 int
 667 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
 668                       uint64_t *stat)
 669 {
 670         if (priv->q_counters != NULL && strcmp(ctr_name, "out_of_buffer") == 0)
 671                 return mlx5_devx_cmd_queue_counter_query
 672                                 (priv->q_counters, 0, (uint32_t *)stat);
 673         DRV_LOG(WARNING, "%s: is not supported for the %s counter",
 674                 __func__, ctr_name);
 675         return -ENOTSUP;
 676 }
 677
 678 /**
 679  * Flush device MAC addresses
 680  * Currently it has no support under Windows.
 681  *
 682  * @param dev
 683  *   Pointer to Ethernet device structure.
 684  *
 685  */
 686 void
 687 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev)
 688 {
 689         (void)dev;
 690         DRV_LOG(WARNING, "%s: is not supported", __func__);
 691 }
 692
 693 /**
 694  * Remove a MAC address from device
 695  * Currently it has no support under Windows.
 696  *
 697  * @param dev
 698  *   Pointer to Ethernet device structure.
 699  * @param index
 700  *   MAC address index.
 701  */
 702 void
 703 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 704 {
 705         (void)dev;
 706         (void)(index);
 707         DRV_LOG(WARNING, "%s: is not supported", __func__);
 708 }
 709
 710 /**
 711  * Adds a MAC address to the device
 712  * Currently it has no support under Windows.
 713  *
 714  * @param dev
 715  *   Pointer to Ethernet device structure.
 716  * @param mac_addr
 717  *   MAC address to register.
 718  * @param index
 719  *   MAC address index.
 720  *
 721  * @return
 722  *   0 on success, a negative errno value otherwise
 723  */
 724 int
 725 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
 726                      uint32_t index)
 727 {
 728         (void)index;
 729         struct rte_ether_addr lmac;
 730
 731         if (mlx5_get_mac(dev, &lmac.addr_bytes)) {
 732                 DRV_LOG(ERR,
 733                         "port %u cannot get MAC address, is mlx5_en"
 734                         " loaded? (errno: %s)",
 735                         dev->data->port_id, strerror(rte_errno));
 736                 return rte_errno;
 737         }
 738         if (!rte_is_same_ether_addr(&lmac, mac)) {
 739                 DRV_LOG(ERR,
 740                         "adding new mac address to device is unsupported");
 741                 return -ENOTSUP;
 742         }
 743         return 0;
 744 }
 745
 746 /**
 747  * Modify a VF MAC address
 748  * Currently it has no support under Windows.
 749  *
 750  * @param priv
 751  *   Pointer to device private data.
 752  * @param mac_addr
 753  *   MAC address to modify into.
 754  * @param iface_idx
 755  *   Net device interface index
 756  * @param vf_index
 757  *   VF index
 758  *
 759  * @return
 760  *   0 on success, a negative errno value otherwise
 761  */
 762 int
 763 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv,
 764                            unsigned int iface_idx,
 765                            struct rte_ether_addr *mac_addr,
 766                            int vf_index)
 767 {
 768         (void)priv;
 769         (void)iface_idx;
 770         (void)mac_addr;
 771         (void)vf_index;
 772         DRV_LOG(WARNING, "%s: is not supported", __func__);
 773         return -ENOTSUP;
 774 }
 775
 776 /**
 777  * Set device promiscuous mode
 778  * Currently it has no support under Windows.
 779  *
 780  * @param dev
 781  *   Pointer to Ethernet device structure.
 782  * @param enable
 783  *   0 - promiscuous is disabled, otherwise - enabled
 784  *
 785  * @return
 786  *   0 on success, a negative error value otherwise
 787  */
 788 int
 789 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable)
 790 {
 791         (void)dev;
 792         (void)enable;
 793         DRV_LOG(WARNING, "%s: is not supported", __func__);
 794         return -ENOTSUP;
 795 }
 796
 797 /**
 798  * Set device allmulti mode
 799  *
 800  * @param dev
 801  *   Pointer to Ethernet device structure.
 802  * @param enable
 803  *   0 - all multicase is disabled, otherwise - enabled
 804  *
 805  * @return
 806  *   0 on success, a negative error value otherwise
 807  */
 808 int
 809 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)
 810 {
 811         (void)dev;
 812         (void)enable;
 813         DRV_LOG(WARNING, "%s: is not supported", __func__);
 814         return -ENOTSUP;
 815 }
 816
 817 /**
 818  * DPDK callback to register a PCI device.
 819  *
 820  * This function spawns Ethernet devices out of a given device.
 821  *
 822  * @param[in] dev
 823  *   Pointer to the common device.
 824  *
 825  * @return
 826  *   0 on success, a negative errno value otherwise and rte_errno is set.
 827  */
 828 int
 829 mlx5_os_net_probe(struct mlx5_common_device *cdev)
 830 {
 831         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);
 832         struct mlx5_dev_spawn_data spawn = {
 833                 .pf_bond = -1,
 834                 .max_port = 1,
 835                 .phys_port = 1,
 836                 .phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx),
 837                 .pci_dev = pci_dev,
 838                 .cdev = cdev,
 839                 .ifindex = -1, /* Spawn will assign */
 840                 .info = (struct mlx5_switch_info){
 841                         .name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK,
 842                 },
 843         };
 844         struct mlx5_dev_config dev_config = {
 845                 .rx_vec_en = 1,
 846                 .txq_inline_max = MLX5_ARG_UNSET,
 847                 .txq_inline_min = MLX5_ARG_UNSET,
 848                 .txq_inline_mpw = MLX5_ARG_UNSET,
 849                 .txqs_inline = MLX5_ARG_UNSET,
 850                 .mprq = {
 851                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
 852                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
 853                 },
 854                 .dv_flow_en = 1,
 855                 .log_hp_size = MLX5_ARG_UNSET,
 856                 .vf = mlx5_dev_is_vf_pci(pci_dev),
 857         };
 858         int ret;
 859         uint32_t restore;
 860
 861         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 862                 DRV_LOG(ERR, "Secondary process is not supported on Windows.");
 863                 return -ENOTSUP;
 864         }
 865         ret = mlx5_init_once();
 866         if (ret) {
 867                 DRV_LOG(ERR, "unable to init PMD global data: %s",
 868                         strerror(rte_errno));
 869                 return -rte_errno;
 870         }
 871         spawn.eth_dev = mlx5_dev_spawn(cdev->dev, &spawn, &dev_config);
 872         if (!spawn.eth_dev)
 873                 return -rte_errno;
 874         restore = spawn.eth_dev->data->dev_flags;
 875         rte_eth_copy_pci_info(spawn.eth_dev, pci_dev);
 876         /* Restore non-PCI flags cleared by the above call. */
 877         spawn.eth_dev->data->dev_flags |= restore;
 878         rte_eth_dev_probing_finish(spawn.eth_dev);
 879         return 0;
 880 }
 881
 882 /**
 883  * Cleanup resources when the last device is closed.
 884  */
 885 void
 886 mlx5_os_net_cleanup(void)
 887 {
 888 }
 889
 890 const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0};