drivers/net/mlx5/windows/mlx5_os.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <errno.h>
   6 #include <stdalign.h>
   7 #include <stddef.h>
   8 #include <stdint.h>
   9 #include <stdlib.h>
  10
  11 #include <rte_windows.h>
  12 #include <ethdev_pci.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_devx_cmds.h>
  16 #include <mlx5_common.h>
  17 #include <mlx5_common_mp.h>
  18 #include <mlx5_common_mr.h>
  19 #include <mlx5_malloc.h>
  20
  21 #include "mlx5_defs.h"
  22 #include "mlx5.h"
  23 #include "mlx5_common_os.h"
  24 #include "mlx5_utils.h"
  25 #include "mlx5_rxtx.h"
  26 #include "mlx5_rx.h"
  27 #include "mlx5_tx.h"
  28 #include "mlx5_autoconf.h"
  29 #include "mlx5_flow.h"
  30 #include "mlx5_devx.h"
  31
  32 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
  33
  34 /* Spinlock for mlx5_shared_data allocation. */
  35 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
  36
  37 /* rte flow indexed pool configuration. */
  38 static struct mlx5_indexed_pool_config icfg[] = {
  39         {
  40                 .size = sizeof(struct rte_flow),
  41                 .trunk_size = 64,
  42                 .need_lock = 1,
  43                 .release_mem_en = 0,
  44                 .malloc = mlx5_malloc,
  45                 .free = mlx5_free,
  46                 .per_core_cache = 0,
  47                 .type = "ctl_flow_ipool",
  48         },
  49         {
  50                 .size = sizeof(struct rte_flow),
  51                 .trunk_size = 64,
  52                 .grow_trunk = 3,
  53                 .grow_shift = 2,
  54                 .need_lock = 1,
  55                 .release_mem_en = 0,
  56                 .malloc = mlx5_malloc,
  57                 .free = mlx5_free,
  58                 .per_core_cache = 1 << 14,
  59                 .type = "rte_flow_ipool",
  60         },
  61         {
  62                 .size = sizeof(struct rte_flow),
  63                 .trunk_size = 64,
  64                 .grow_trunk = 3,
  65                 .grow_shift = 2,
  66                 .need_lock = 1,
  67                 .release_mem_en = 0,
  68                 .malloc = mlx5_malloc,
  69                 .free = mlx5_free,
  70                 .per_core_cache = 0,
  71                 .type = "mcp_flow_ipool",
  72         },
  73 };
  74
  75 static void
  76 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev)
  77 {
  78         struct mlx5_priv *priv = dev->data->dev_private;
  79         void *ctx = priv->sh->cdev->ctx;
  80
  81         priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx);
  82         if (!priv->q_counters) {
  83                 DRV_LOG(ERR, "Port %d queue counter object cannot be created "
  84                         "by DevX - imissed counter will be unavailable",
  85                         dev->data->port_id);
  86                 return;
  87         }
  88         priv->counter_set_id = priv->q_counters->id;
  89 }
  90
  91 /**
  92  * Initialize shared data between primary and secondary process.
  93  *
  94  * A memzone is reserved by primary process and secondary processes attach to
  95  * the memzone.
  96  *
  97  * @return
  98  *   0 on success, a negative errno value otherwise and rte_errno is set.
  99  */
 100 static int
 101 mlx5_init_shared_data(void)
 102 {
 103         const struct rte_memzone *mz;
 104         int ret = 0;
 105
 106         rte_spinlock_lock(&mlx5_shared_data_lock);
 107         if (mlx5_shared_data == NULL) {
 108                 /* Allocate shared memory. */
 109                 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 110                                          sizeof(*mlx5_shared_data),
 111                                          SOCKET_ID_ANY, 0);
 112                 if (mz == NULL) {
 113                         DRV_LOG(ERR,
 114                                 "Cannot allocate mlx5 shared data");
 115                         ret = -rte_errno;
 116                         goto error;
 117                 }
 118                 mlx5_shared_data = mz->addr;
 119                 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 120                 rte_spinlock_init(&mlx5_shared_data->lock);
 121         }
 122 error:
 123         rte_spinlock_unlock(&mlx5_shared_data_lock);
 124         return ret;
 125 }
 126
 127 /**
 128  * PMD global initialization.
 129  *
 130  * Independent from individual device, this function initializes global
 131  * per-PMD data structures distinguishing primary and secondary processes.
 132  * Hence, each initialization is called once per a process.
 133  *
 134  * @return
 135  *   0 on success, a negative errno value otherwise and rte_errno is set.
 136  */
 137 static int
 138 mlx5_init_once(void)
 139 {
 140         if (mlx5_init_shared_data())
 141                 return -rte_errno;
 142         return 0;
 143 }
 144
 145 /**
 146  * Get mlx5 device attributes.
 147  *
 148  * @param cdev
 149  *   Pointer to mlx5 device.
 150  *
 151  * @param device_attr
 152  *   Pointer to mlx5 device attributes.
 153  *
 154  * @return
 155  *   0 on success, a negative errno value otherwise and rte_errno is set.
 156  */
 157 int
 158 mlx5_os_get_dev_attr(struct mlx5_common_device *cdev,
 159                      struct mlx5_dev_attr *device_attr)
 160 {
 161         struct mlx5_context *mlx5_ctx;
 162         void *pv_iseg = NULL;
 163         u32 cb_iseg = 0;
 164
 165         if (!cdev || !cdev->ctx) {
 166                 rte_errno = EINVAL;
 167                 return -rte_errno;
 168         }
 169         mlx5_ctx = (struct mlx5_context *)cdev->ctx;
 170         memset(device_attr, 0, sizeof(*device_attr));
 171         device_attr->max_cq = 1 << cdev->config.hca_attr.log_max_cq;
 172         device_attr->max_qp = 1 << cdev->config.hca_attr.log_max_qp;
 173         device_attr->max_qp_wr = 1 << cdev->config.hca_attr.log_max_qp_sz;
 174         device_attr->max_cqe = 1 << cdev->config.hca_attr.log_max_cq_sz;
 175         device_attr->max_mr = 1 << cdev->config.hca_attr.log_max_mrw_sz;
 176         device_attr->max_pd = 1 << cdev->config.hca_attr.log_max_pd;
 177         device_attr->max_srq = 1 << cdev->config.hca_attr.log_max_srq;
 178         device_attr->max_srq_wr = 1 << cdev->config.hca_attr.log_max_srq_sz;
 179         device_attr->max_tso = 1 << cdev->config.hca_attr.max_lso_cap;
 180         if (cdev->config.hca_attr.rss_ind_tbl_cap) {
 181                 device_attr->max_rwq_indirection_table_size =
 182                         1 << cdev->config.hca_attr.rss_ind_tbl_cap;
 183         }
 184         device_attr->sw_parsing_offloads =
 185                 mlx5_get_supported_sw_parsing_offloads(&cdev->config.hca_attr);
 186         device_attr->tunnel_offloads_caps =
 187                 mlx5_get_supported_tunneling_offloads(&cdev->config.hca_attr);
 188         pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
 189         if (pv_iseg == NULL) {
 190                 DRV_LOG(ERR, "Failed to get device hca_iseg");
 191                 rte_errno = errno;
 192                 return -rte_errno;
 193         }
 194         snprintf(device_attr->fw_ver, 64, "%x.%x.%04x",
 195                  MLX5_GET(initial_seg, pv_iseg, fw_rev_major),
 196                  MLX5_GET(initial_seg, pv_iseg, fw_rev_minor),
 197                  MLX5_GET(initial_seg, pv_iseg, fw_rev_subminor));
 198         return 0;
 199 }
 200
 201 /**
 202  * Initialize DR related data within private structure.
 203  * Routine checks the reference counter and does actual
 204  * resources creation/initialization only if counter is zero.
 205  *
 206  * @param[in] priv
 207  *   Pointer to the private device data structure.
 208  *
 209  * @return
 210  *   Zero on success, positive error code otherwise.
 211  */
 212 static int
 213 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
 214 {
 215         struct mlx5_dev_ctx_shared *sh = priv->sh;
 216         int err = 0;
 217
 218         if (!sh->flow_tbls)
 219                 err = mlx5_alloc_table_hash_list(priv);
 220         else
 221                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse",
 222                         (void *)sh->flow_tbls);
 223         return err;
 224 }
 225 /**
 226  * Destroy DR related data within private structure.
 227  *
 228  * @param[in] priv
 229  *   Pointer to the private device data structure.
 230  */
 231 void
 232 mlx5_os_free_shared_dr(struct mlx5_priv *priv)
 233 {
 234         mlx5_free_table_hash_list(priv);
 235 }
 236
 237 /**
 238  * Set the completion channel file descriptor interrupt as non-blocking.
 239  * Currently it has no support under Windows.
 240  *
 241  * @param[in] rxq_obj
 242  *   Pointer to RQ channel object, which includes the channel fd
 243  *
 244  * @param[out] fd
 245  *   The file descriptor (representing the interrupt) used in this channel.
 246  *
 247  * @return
 248  *   0 on successfully setting the fd to non-blocking, non-zero otherwise.
 249  */
 250 int
 251 mlx5_os_set_nonblock_channel_fd(int fd)
 252 {
 253         (void)fd;
 254         DRV_LOG(WARNING, "%s: is not supported", __func__);
 255         return -ENOTSUP;
 256 }
 257
 258 /**
 259  * DV flow counter mode detect and config.
 260  *
 261  * @param dev
 262  *   Pointer to rte_eth_dev structure.
 263  *
 264  */
 265 static void
 266 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
 267 {
 268 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 269         struct mlx5_priv *priv = dev->data->dev_private;
 270         struct mlx5_dev_ctx_shared *sh = priv->sh;
 271         struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;
 272         bool fallback;
 273
 274 #ifndef HAVE_IBV_DEVX_ASYNC
 275         fallback = true;
 276 #else
 277         fallback = false;
 278         if (!sh->cdev->config.devx || !priv->config.dv_flow_en ||
 279             !hca_attr->flow_counters_dump ||
 280             !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||
 281             (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
 282                 fallback = true;
 283 #endif
 284         if (fallback)
 285                 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
 286                         "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
 287                         hca_attr->flow_counters_dump,
 288                         hca_attr->flow_counter_bulk_alloc_bitmap);
 289         /* Initialize fallback mode only on the port initializes sh. */
 290         if (sh->refcnt == 1)
 291                 sh->cmng.counter_fallback = fallback;
 292         else if (fallback != sh->cmng.counter_fallback)
 293                 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
 294                         "with others:%d.", PORT_ID(priv), fallback);
 295 #endif
 296 }
 297
 298 /**
 299  * Spawn an Ethernet device from DevX information.
 300  *
 301  * @param dpdk_dev
 302  *   Backing DPDK device.
 303  * @param spawn
 304  *   Verbs device parameters (name, port, switch_info) to spawn.
 305  * @param config
 306  *   Device configuration parameters.
 307  *
 308  * @return
 309  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
 310  *   is set. The following errors are defined:
 311  *
 312  *   EEXIST: device is already spawned
 313  */
 314 static struct rte_eth_dev *
 315 mlx5_dev_spawn(struct rte_device *dpdk_dev,
 316                struct mlx5_dev_spawn_data *spawn,
 317                struct mlx5_dev_config *config)
 318 {
 319         const struct mlx5_switch_info *switch_info = &spawn->info;
 320         struct mlx5_dev_ctx_shared *sh = NULL;
 321         struct mlx5_hca_attr *hca_attr;
 322         struct rte_eth_dev *eth_dev = NULL;
 323         struct mlx5_priv *priv = NULL;
 324         int err = 0;
 325         struct rte_ether_addr mac;
 326         char name[RTE_ETH_NAME_MAX_LEN];
 327         int own_domain_id = 0;
 328         uint16_t port_id;
 329         int i;
 330
 331         /* Build device name. */
 332         strlcpy(name, dpdk_dev->name, sizeof(name));
 333         /* check if the device is already spawned */
 334         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
 335                 rte_errno = EEXIST;
 336                 return NULL;
 337         }
 338         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
 339         /* Process parameters. */
 340         err = mlx5_args(config, dpdk_dev->devargs);
 341         if (err) {
 342                 err = rte_errno;
 343                 DRV_LOG(ERR, "failed to process device arguments: %s",
 344                         strerror(rte_errno));
 345                 goto error;
 346         }
 347         sh = mlx5_alloc_shared_dev_ctx(spawn, config);
 348         if (!sh)
 349                 return NULL;
 350         /* Update final values for devargs before check sibling config. */
 351         config->dv_esw_en = 0;
 352         if (!config->dv_flow_en) {
 353                 DRV_LOG(ERR, "Windows flow mode must be DV flow enable.");
 354                 err = ENOTSUP;
 355                 goto error;
 356         }
 357         if (!config->dv_esw_en &&
 358             config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
 359                 DRV_LOG(WARNING,
 360                         "Metadata mode %u is not supported (no E-Switch).",
 361                         config->dv_xmeta_en);
 362                 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
 363         }
 364         /* Check sibling device configurations. */
 365         err = mlx5_dev_check_sibling_config(sh, config, dpdk_dev);
 366         if (err)
 367                 goto error;
 368         /* Initialize the shutdown event in mlx5_dev_spawn to
 369          * support mlx5_is_removed for Windows.
 370          */
 371         err = mlx5_glue->devx_init_showdown_event(sh->cdev->ctx);
 372         if (err) {
 373                 DRV_LOG(ERR, "failed to init showdown event: %s",
 374                         strerror(errno));
 375                 goto error;
 376         }
 377         DRV_LOG(DEBUG, "MPW isn't supported");
 378         config->swp = sh->device_attr.sw_parsing_offloads &
 379                 (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
 380                  MLX5_SW_PARSING_TSO_CAP);
 381         config->ind_table_max_size =
 382                 sh->device_attr.max_rwq_indirection_table_size;
 383         config->tunnel_en = sh->device_attr.tunnel_offloads_caps &
 384                 (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |
 385                  MLX5_TUNNELED_OFFLOADS_GRE_CAP |
 386                  MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);
 387         if (config->tunnel_en) {
 388                 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
 389                 config->tunnel_en &
 390                 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "",
 391                 config->tunnel_en &
 392                 MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "",
 393                 config->tunnel_en &
 394                 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""
 395                 );
 396         } else {
 397                 DRV_LOG(DEBUG, "tunnel offloading is not supported");
 398         }
 399         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported");
 400         config->mpls_en = 0;
 401         /* Allocate private eth device data. */
 402         priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 403                            sizeof(*priv),
 404                            RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 405         if (priv == NULL) {
 406                 DRV_LOG(ERR, "priv allocation failure");
 407                 err = ENOMEM;
 408                 goto error;
 409         }
 410         priv->sh = sh;
 411         priv->dev_port = spawn->phys_port;
 412         priv->pci_dev = spawn->pci_dev;
 413         priv->mtu = RTE_ETHER_MTU;
 414         priv->mp_id.port_id = port_id;
 415         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
 416         priv->representor = !!switch_info->representor;
 417         priv->master = !!switch_info->master;
 418         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
 419         priv->vport_meta_tag = 0;
 420         priv->vport_meta_mask = 0;
 421         priv->pf_bond = spawn->pf_bond;
 422         priv->vport_id = -1;
 423         /* representor_id field keeps the unmodified VF index. */
 424         priv->representor_id = -1;
 425         /*
 426          * Look for sibling devices in order to reuse their switch domain
 427          * if any, otherwise allocate one.
 428          */
 429         MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
 430                 const struct mlx5_priv *opriv =
 431                         rte_eth_devices[port_id].data->dev_private;
 432
 433                 if (!opriv ||
 434                     opriv->sh != priv->sh ||
 435                         opriv->domain_id ==
 436                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
 437                         continue;
 438                 priv->domain_id = opriv->domain_id;
 439                 break;
 440         }
 441         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
 442                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
 443                 if (err) {
 444                         err = rte_errno;
 445                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
 446                                 strerror(rte_errno));
 447                         goto error;
 448                 }
 449                 own_domain_id = 1;
 450         }
 451         DRV_LOG(DEBUG, "counters are not supported");
 452         config->ind_table_max_size =
 453                 sh->device_attr.max_rwq_indirection_table_size;
 454         /*
 455          * Remove this check once DPDK supports larger/variable
 456          * indirection tables.
 457          */
 458         if (config->ind_table_max_size > (unsigned int)RTE_ETH_RSS_RETA_SIZE_512)
 459                 config->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512;
 460         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 461                 config->ind_table_max_size);
 462         if (config->hw_padding) {
 463                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
 464                 config->hw_padding = 0;
 465         }
 466         config->tso = (sh->device_attr.max_tso > 0);
 467         if (config->tso)
 468                 config->tso_max_payload_sz = sh->device_attr.max_tso;
 469         DRV_LOG(DEBUG, "%sMPS is %s.",
 470                 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
 471                 config->mps == MLX5_MPW ? "legacy " : "",
 472                 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
 473         if (config->cqe_comp) {
 474                 DRV_LOG(WARNING, "Rx CQE compression isn't supported.");
 475                 config->cqe_comp = 0;
 476         }
 477         if (sh->cdev->config.devx) {
 478                 hca_attr = &sh->cdev->config.hca_attr;
 479                 config->hw_csum = hca_attr->csum_cap;
 480                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 481                         (config->hw_csum ? "" : "not "));
 482                 config->hw_vlan_strip = hca_attr->vlan_cap;
 483                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 484                         (config->hw_vlan_strip ? "" : "not "));
 485                 config->hw_fcs_strip = hca_attr->scatter_fcs;
 486         }
 487         if (sh->devx) {
 488                 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
 489
 490                 err = hca_attr->access_register_user ?
 491                         mlx5_devx_cmd_register_read
 492                                 (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,
 493                                 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
 494                 if (!err) {
 495                         uint32_t ts_mode;
 496
 497                         /* MTUTC register is read successfully. */
 498                         ts_mode = MLX5_GET(register_mtutc, reg,
 499                                            time_stamp_mode);
 500                         if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
 501                                 config->rt_timestamp = 1;
 502                 } else {
 503                         /* Kernel does not support register reading. */
 504                         if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))
 505                                 config->rt_timestamp = 1;
 506                 }
 507         }
 508         if (config->mprq.enabled) {
 509                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
 510                 config->mprq.enabled = 0;
 511         }
 512         if (config->max_dump_files_num == 0)
 513                 config->max_dump_files_num = 128;
 514         eth_dev = rte_eth_dev_allocate(name);
 515         if (eth_dev == NULL) {
 516                 DRV_LOG(ERR, "can not allocate rte ethdev");
 517                 err = ENOMEM;
 518                 goto error;
 519         }
 520         if (priv->representor) {
 521                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
 522                 eth_dev->data->representor_id = priv->representor_id;
 523                 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
 524                         struct mlx5_priv *opriv =
 525                                 rte_eth_devices[port_id].data->dev_private;
 526                         if (opriv &&
 527                             opriv->master &&
 528                             opriv->domain_id == priv->domain_id &&
 529                             opriv->sh == priv->sh) {
 530                                 eth_dev->data->backer_port_id = port_id;
 531                                 break;
 532                         }
 533                 }
 534                 if (port_id >= RTE_MAX_ETHPORTS)
 535                         eth_dev->data->backer_port_id = eth_dev->data->port_id;
 536         }
 537         /*
 538          * Store associated network device interface index. This index
 539          * is permanent throughout the lifetime of device. So, we may store
 540          * the ifindex here and use the cached value further.
 541          */
 542         MLX5_ASSERT(spawn->ifindex);
 543         priv->if_index = spawn->ifindex;
 544         eth_dev->data->dev_private = priv;
 545         priv->dev_data = eth_dev->data;
 546         eth_dev->data->mac_addrs = priv->mac;
 547         eth_dev->device = dpdk_dev;
 548         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 549         /* Configure the first MAC address by default. */
 550         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
 551                 DRV_LOG(ERR,
 552                         "port %u cannot get MAC address, is mlx5_en"
 553                         " loaded? (errno: %s).",
 554                         eth_dev->data->port_id, strerror(rte_errno));
 555                 err = ENODEV;
 556                 goto error;
 557         }
 558         DRV_LOG(INFO,
 559                 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT,
 560                 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac));
 561 #ifdef RTE_LIBRTE_MLX5_DEBUG
 562         {
 563                 char ifname[MLX5_NAMESIZE];
 564
 565                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
 566                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
 567                                 eth_dev->data->port_id, ifname);
 568                 else
 569                         DRV_LOG(DEBUG, "port %u ifname is unknown.",
 570                                 eth_dev->data->port_id);
 571         }
 572 #endif
 573         /* Get actual MTU if possible. */
 574         err = mlx5_get_mtu(eth_dev, &priv->mtu);
 575         if (err) {
 576                 err = rte_errno;
 577                 goto error;
 578         }
 579         DRV_LOG(DEBUG, "port %u MTU is %u.", eth_dev->data->port_id,
 580                 priv->mtu);
 581         /* Initialize burst functions to prevent crashes before link-up. */
 582         eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
 583         eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
 584         eth_dev->dev_ops = &mlx5_dev_ops;
 585         eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
 586         eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
 587         eth_dev->rx_queue_count = mlx5_rx_queue_count;
 588         /* Register MAC address. */
 589         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
 590         priv->ctrl_flows = 0;
 591         TAILQ_INIT(&priv->flow_meters);
 592         priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR);
 593         if (!priv->mtr_profile_tbl)
 594                 goto error;
 595         /* Bring Ethernet device up. */
 596         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up.",
 597                 eth_dev->data->port_id);
 598         /* nl calls are unsupported - set to -1 not to fail on release */
 599         priv->nl_socket_rdma = -1;
 600         priv->nl_socket_route = -1;
 601         mlx5_set_link_up(eth_dev);
 602         /*
 603          * Even though the interrupt handler is not installed yet,
 604          * interrupts will still trigger on the async_fd from
 605          * Verbs context returned by ibv_open_device().
 606          */
 607         mlx5_link_update(eth_dev, 0);
 608         /* Detect minimal data bytes to inline. */
 609         mlx5_set_min_inline(spawn, config);
 610         /* Store device configuration on private structure. */
 611         priv->config = *config;
 612         for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
 613                 icfg[i].release_mem_en = !!config->reclaim_mode;
 614                 if (config->reclaim_mode)
 615                         icfg[i].per_core_cache = 0;
 616                 priv->flows[i] = mlx5_ipool_create(&icfg[i]);
 617                 if (!priv->flows[i])
 618                         goto error;
 619         }
 620         /* Create context for virtual machine VLAN workaround. */
 621         priv->vmwa_context = NULL;
 622         if (config->dv_flow_en) {
 623                 err = mlx5_alloc_shared_dr(priv);
 624                 if (err)
 625                         goto error;
 626         }
 627         /* No supported flow priority number detection. */
 628         priv->sh->flow_max_priority = -1;
 629         mlx5_set_metadata_mask(eth_dev);
 630         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
 631             !priv->sh->dv_regc0_mask) {
 632                 DRV_LOG(ERR, "metadata mode %u is not supported "
 633                              "(no metadata reg_c[0] is available).",
 634                              priv->config.dv_xmeta_en);
 635                         err = ENOTSUP;
 636                         goto error;
 637         }
 638         priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true,
 639                 mlx5_hrxq_create_cb, mlx5_hrxq_match_cb,
 640                 mlx5_hrxq_remove_cb, mlx5_hrxq_clone_cb,
 641                 mlx5_hrxq_clone_free_cb);
 642         /* Query availability of metadata reg_c's. */
 643         if (!priv->sh->metadata_regc_check_flag) {
 644                 err = mlx5_flow_discover_mreg_c(eth_dev);
 645                 if (err < 0) {
 646                         err = -err;
 647                         goto error;
 648                 }
 649         }
 650         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
 651                 DRV_LOG(DEBUG,
 652                         "port %u extensive metadata register is not supported.",
 653                         eth_dev->data->port_id);
 654                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
 655                         DRV_LOG(ERR, "metadata mode %u is not supported "
 656                                      "(no metadata registers available).",
 657                                      priv->config.dv_xmeta_en);
 658                         err = ENOTSUP;
 659                         goto error;
 660                 }
 661         }
 662         if (sh->cdev->config.devx) {
 663                 priv->obj_ops = devx_obj_ops;
 664         } else {
 665                 DRV_LOG(ERR, "Windows flow must be DevX.");
 666                 err = ENOTSUP;
 667                 goto error;
 668         }
 669         mlx5_flow_counter_mode_config(eth_dev);
 670         mlx5_queue_counter_id_prepare(eth_dev);
 671         return eth_dev;
 672 error:
 673         if (priv) {
 674                 if (priv->mtr_profile_tbl)
 675                         mlx5_l3t_destroy(priv->mtr_profile_tbl);
 676                 if (own_domain_id)
 677                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
 678                 mlx5_free(priv);
 679                 if (eth_dev != NULL)
 680                         eth_dev->data->dev_private = NULL;
 681         }
 682         if (eth_dev != NULL) {
 683                 /* mac_addrs must not be freed alone because part of
 684                  * dev_private
 685                  **/
 686                 eth_dev->data->mac_addrs = NULL;
 687                 rte_eth_dev_release_port(eth_dev);
 688         }
 689         if (sh)
 690                 mlx5_free_shared_dev_ctx(sh);
 691         MLX5_ASSERT(err > 0);
 692         rte_errno = err;
 693         return NULL;
 694 }
 695
 696 /**
 697  * This function should share events between multiple ports of single IB
 698  * device.  Currently it has no support under Windows.
 699  *
 700  * @param sh
 701  *   Pointer to mlx5_dev_ctx_shared object.
 702  */
 703 void
 704 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
 705 {
 706         (void)sh;
 707         DRV_LOG(WARNING, "%s: is not supported", __func__);
 708 }
 709
 710 /**
 711  * This function should share events between multiple ports of single IB
 712  * device.  Currently it has no support under Windows.
 713  *
 714  * @param dev
 715  *   Pointer to mlx5_dev_ctx_shared object.
 716  */
 717 void
 718 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
 719 {
 720         (void)sh;
 721         DRV_LOG(WARNING, "%s: is not supported", __func__);
 722 }
 723
 724 /**
 725  * Read statistics by a named counter.
 726  *
 727  * @param[in] priv
 728  *   Pointer to the private device data structure.
 729  * @param[in] ctr_name
 730  *   Pointer to the name of the statistic counter to read
 731  * @param[out] stat
 732  *   Pointer to read statistic value.
 733  * @return
 734  *   0 on success and stat is valid, non-zero if failed to read the value
 735  *   or counter is not supported.
 736  *   rte_errno is set.
 737  *
 738  */
 739 int
 740 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
 741                       uint64_t *stat)
 742 {
 743         if (priv->q_counters != NULL && strcmp(ctr_name, "out_of_buffer") == 0)
 744                 return mlx5_devx_cmd_queue_counter_query
 745                                 (priv->q_counters, 0, (uint32_t *)stat);
 746         DRV_LOG(WARNING, "%s: is not supported for the %s counter",
 747                 __func__, ctr_name);
 748         return -ENOTSUP;
 749 }
 750
 751 /**
 752  * Flush device MAC addresses
 753  * Currently it has no support under Windows.
 754  *
 755  * @param dev
 756  *   Pointer to Ethernet device structure.
 757  *
 758  */
 759 void
 760 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev)
 761 {
 762         (void)dev;
 763         DRV_LOG(WARNING, "%s: is not supported", __func__);
 764 }
 765
 766 /**
 767  * Remove a MAC address from device
 768  * Currently it has no support under Windows.
 769  *
 770  * @param dev
 771  *   Pointer to Ethernet device structure.
 772  * @param index
 773  *   MAC address index.
 774  */
 775 void
 776 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 777 {
 778         (void)dev;
 779         (void)(index);
 780         DRV_LOG(WARNING, "%s: is not supported", __func__);
 781 }
 782
 783 /**
 784  * Adds a MAC address to the device
 785  * Currently it has no support under Windows.
 786  *
 787  * @param dev
 788  *   Pointer to Ethernet device structure.
 789  * @param mac_addr
 790  *   MAC address to register.
 791  * @param index
 792  *   MAC address index.
 793  *
 794  * @return
 795  *   0 on success, a negative errno value otherwise
 796  */
 797 int
 798 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
 799                      uint32_t index)
 800 {
 801         (void)index;
 802         struct rte_ether_addr lmac;
 803
 804         if (mlx5_get_mac(dev, &lmac.addr_bytes)) {
 805                 DRV_LOG(ERR,
 806                         "port %u cannot get MAC address, is mlx5_en"
 807                         " loaded? (errno: %s)",
 808                         dev->data->port_id, strerror(rte_errno));
 809                 return rte_errno;
 810         }
 811         if (!rte_is_same_ether_addr(&lmac, mac)) {
 812                 DRV_LOG(ERR,
 813                         "adding new mac address to device is unsupported");
 814                 return -ENOTSUP;
 815         }
 816         return 0;
 817 }
 818
 819 /**
 820  * Modify a VF MAC address
 821  * Currently it has no support under Windows.
 822  *
 823  * @param priv
 824  *   Pointer to device private data.
 825  * @param mac_addr
 826  *   MAC address to modify into.
 827  * @param iface_idx
 828  *   Net device interface index
 829  * @param vf_index
 830  *   VF index
 831  *
 832  * @return
 833  *   0 on success, a negative errno value otherwise
 834  */
 835 int
 836 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv,
 837                            unsigned int iface_idx,
 838                            struct rte_ether_addr *mac_addr,
 839                            int vf_index)
 840 {
 841         (void)priv;
 842         (void)iface_idx;
 843         (void)mac_addr;
 844         (void)vf_index;
 845         DRV_LOG(WARNING, "%s: is not supported", __func__);
 846         return -ENOTSUP;
 847 }
 848
 849 /**
 850  * Set device promiscuous mode
 851  * Currently it has no support under Windows.
 852  *
 853  * @param dev
 854  *   Pointer to Ethernet device structure.
 855  * @param enable
 856  *   0 - promiscuous is disabled, otherwise - enabled
 857  *
 858  * @return
 859  *   0 on success, a negative error value otherwise
 860  */
 861 int
 862 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable)
 863 {
 864         (void)dev;
 865         (void)enable;
 866         DRV_LOG(WARNING, "%s: is not supported", __func__);
 867         return -ENOTSUP;
 868 }
 869
 870 /**
 871  * Set device allmulti mode
 872  *
 873  * @param dev
 874  *   Pointer to Ethernet device structure.
 875  * @param enable
 876  *   0 - all multicase is disabled, otherwise - enabled
 877  *
 878  * @return
 879  *   0 on success, a negative error value otherwise
 880  */
 881 int
 882 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)
 883 {
 884         (void)dev;
 885         (void)enable;
 886         DRV_LOG(WARNING, "%s: is not supported", __func__);
 887         return -ENOTSUP;
 888 }
 889
 890 /**
 891  * DPDK callback to register a PCI device.
 892  *
 893  * This function spawns Ethernet devices out of a given device.
 894  *
 895  * @param[in] dev
 896  *   Pointer to the common device.
 897  *
 898  * @return
 899  *   0 on success, a negative errno value otherwise and rte_errno is set.
 900  */
 901 int
 902 mlx5_os_net_probe(struct mlx5_common_device *cdev)
 903 {
 904         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);
 905         struct mlx5_dev_spawn_data spawn = {
 906                 .pf_bond = -1,
 907                 .max_port = 1,
 908                 .phys_port = 1,
 909                 .phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx),
 910                 .pci_dev = pci_dev,
 911                 .cdev = cdev,
 912                 .ifindex = -1, /* Spawn will assign */
 913                 .info = (struct mlx5_switch_info){
 914                         .name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK,
 915                 },
 916         };
 917         struct mlx5_dev_config dev_config = {
 918                 .rx_vec_en = 1,
 919                 .txq_inline_max = MLX5_ARG_UNSET,
 920                 .txq_inline_min = MLX5_ARG_UNSET,
 921                 .txq_inline_mpw = MLX5_ARG_UNSET,
 922                 .txqs_inline = MLX5_ARG_UNSET,
 923                 .mprq = {
 924                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
 925                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
 926                 },
 927                 .dv_flow_en = 1,
 928                 .log_hp_size = MLX5_ARG_UNSET,
 929                 .vf = mlx5_dev_is_vf_pci(pci_dev),
 930         };
 931         int ret;
 932         uint32_t restore;
 933
 934         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 935                 DRV_LOG(ERR, "Secondary process is not supported on Windows.");
 936                 return -ENOTSUP;
 937         }
 938         ret = mlx5_init_once();
 939         if (ret) {
 940                 DRV_LOG(ERR, "unable to init PMD global data: %s",
 941                         strerror(rte_errno));
 942                 return -rte_errno;
 943         }
 944         spawn.eth_dev = mlx5_dev_spawn(cdev->dev, &spawn, &dev_config);
 945         if (!spawn.eth_dev)
 946                 return -rte_errno;
 947         restore = spawn.eth_dev->data->dev_flags;
 948         rte_eth_copy_pci_info(spawn.eth_dev, pci_dev);
 949         /* Restore non-PCI flags cleared by the above call. */
 950         spawn.eth_dev->data->dev_flags |= restore;
 951         rte_eth_dev_probing_finish(spawn.eth_dev);
 952         return 0;
 953 }
 954
 955 /**
 956  * Cleanup resources when the last device is closed.
 957  */
 958 void
 959 mlx5_os_net_cleanup(void)
 960 {
 961 }
 962
 963 const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0};