1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
11 #include <rte_windows.h>
12 #include <ethdev_pci.h>
14 #include <mlx5_glue.h>
15 #include <mlx5_devx_cmds.h>
16 #include <mlx5_common.h>
17 #include <mlx5_common_mp.h>
18 #include <mlx5_common_mr.h>
19 #include <mlx5_malloc.h>
21 #include "mlx5_defs.h"
23 #include "mlx5_common_os.h"
24 #include "mlx5_utils.h"
25 #include "mlx5_rxtx.h"
28 #include "mlx5_autoconf.h"
30 #include "mlx5_flow.h"
31 #include "mlx5_devx.h"
33 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
35 /* Spinlock for mlx5_shared_data allocation. */
36 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
38 /* rte flow indexed pool configuration. */
39 static struct mlx5_indexed_pool_config icfg[] = {
41 .size = sizeof(struct rte_flow),
45 .malloc = mlx5_malloc,
48 .type = "ctl_flow_ipool",
51 .size = sizeof(struct rte_flow),
57 .malloc = mlx5_malloc,
59 .per_core_cache = 1 << 14,
60 .type = "rte_flow_ipool",
63 .size = sizeof(struct rte_flow),
69 .malloc = mlx5_malloc,
72 .type = "mcp_flow_ipool",
77 * Initialize shared data between primary and secondary process.
79 * A memzone is reserved by primary process and secondary processes attach to
83 * 0 on success, a negative errno value otherwise and rte_errno is set.
86 mlx5_init_shared_data(void)
88 const struct rte_memzone *mz;
91 rte_spinlock_lock(&mlx5_shared_data_lock);
92 if (mlx5_shared_data == NULL) {
93 /* Allocate shared memory. */
94 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
95 sizeof(*mlx5_shared_data),
99 "Cannot allocate mlx5 shared data");
103 mlx5_shared_data = mz->addr;
104 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
105 rte_spinlock_init(&mlx5_shared_data->lock);
108 rte_spinlock_unlock(&mlx5_shared_data_lock);
113 * PMD global initialization.
115 * Independent from individual device, this function initializes global
116 * per-PMD data structures distinguishing primary and secondary processes.
117 * Hence, each initialization is called once per a process.
120 * 0 on success, a negative errno value otherwise and rte_errno is set.
125 if (mlx5_init_shared_data())
131 * Get mlx5 device attributes.
134 * Pointer to device context.
137 * Pointer to mlx5 device attributes.
140 * 0 on success, non zero error number otherwise
143 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)
145 struct mlx5_context *mlx5_ctx;
146 struct mlx5_hca_attr hca_attr;
147 void *pv_iseg = NULL;
153 mlx5_ctx = (struct mlx5_context *)ctx;
154 memset(device_attr, 0, sizeof(*device_attr));
155 err = mlx5_devx_cmd_query_hca_attr(mlx5_ctx, &hca_attr);
157 DRV_LOG(ERR, "Failed to get device hca_cap");
160 device_attr->max_cq = 1 << hca_attr.log_max_cq;
161 device_attr->max_qp = 1 << hca_attr.log_max_qp;
162 device_attr->max_qp_wr = 1 << hca_attr.log_max_qp_sz;
163 device_attr->max_cqe = 1 << hca_attr.log_max_cq_sz;
164 device_attr->max_mr = 1 << hca_attr.log_max_mrw_sz;
165 device_attr->max_pd = 1 << hca_attr.log_max_pd;
166 device_attr->max_srq = 1 << hca_attr.log_max_srq;
167 device_attr->max_srq_wr = 1 << hca_attr.log_max_srq_sz;
168 if (hca_attr.rss_ind_tbl_cap) {
169 device_attr->max_rwq_indirection_table_size =
170 1 << hca_attr.rss_ind_tbl_cap;
172 device_attr->sw_parsing_offloads =
173 mlx5_get_supported_sw_parsing_offloads(&hca_attr);
174 pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
175 if (pv_iseg == NULL) {
176 DRV_LOG(ERR, "Failed to get device hca_iseg");
180 snprintf(device_attr->fw_ver, 64, "%x.%x.%04x",
181 MLX5_GET(initial_seg, pv_iseg, fw_rev_major),
182 MLX5_GET(initial_seg, pv_iseg, fw_rev_minor),
183 MLX5_GET(initial_seg, pv_iseg, fw_rev_subminor));
189 * Initialize DR related data within private structure.
190 * Routine checks the reference counter and does actual
191 * resources creation/initialization only if counter is zero.
194 * Pointer to the private device data structure.
197 * Zero on success, positive error code otherwise.
200 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
202 struct mlx5_dev_ctx_shared *sh = priv->sh;
206 err = mlx5_alloc_table_hash_list(priv);
208 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse",
209 (void *)sh->flow_tbls);
213 * Destroy DR related data within private structure.
216 * Pointer to the private device data structure.
219 mlx5_os_free_shared_dr(struct mlx5_priv *priv)
221 mlx5_free_table_hash_list(priv);
225 * Set the completion channel file descriptor interrupt as non-blocking.
226 * Currently it has no support under Windows.
229 * Pointer to RQ channel object, which includes the channel fd
232 * The file descriptor (representing the intetrrupt) used in this channel.
235 * 0 on successfully setting the fd to non-blocking, non-zero otherwise.
238 mlx5_os_set_nonblock_channel_fd(int fd)
241 DRV_LOG(WARNING, "%s: is not supported", __func__);
246 * Function API open device under Windows
248 * This function calls the Windows glue APIs to open a device.
251 * Pointer to the device attributes (name, port, etc).
253 * Pointer to device configuration structure.
255 * Pointer to shared context structure.
258 * 0 on success, a positive error value otherwise.
261 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
262 const struct mlx5_dev_config *config,
263 struct mlx5_dev_ctx_shared *sh)
265 RTE_SET_USED(config);
267 struct mlx5_context *mlx5_ctx;
269 pthread_mutex_init(&sh->txpp.mutex, NULL);
270 /* Set numa node from pci probe */
271 sh->numa_node = spawn->pci_dev->device.numa_node;
273 /* Try to open device with DevX */
275 sh->ctx = mlx5_glue->open_device(spawn->phys_dev);
277 DRV_LOG(ERR, "open_device failed");
282 mlx5_ctx = (struct mlx5_context *)sh->ctx;
283 err = mlx5_glue->query_device(spawn->phys_dev, &mlx5_ctx->mlx5_dev);
285 DRV_LOG(ERR, "Failed to query device context fields.");
290 * DV flow counter mode detect and config.
293 * Pointer to rte_eth_dev structure.
297 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
299 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
300 struct mlx5_priv *priv = dev->data->dev_private;
301 struct mlx5_dev_ctx_shared *sh = priv->sh;
304 #ifndef HAVE_IBV_DEVX_ASYNC
308 if (!priv->config.devx || !priv->config.dv_flow_en ||
309 !priv->config.hca_attr.flow_counters_dump ||
310 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) ||
311 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
315 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
316 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
317 priv->config.hca_attr.flow_counters_dump,
318 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap);
319 /* Initialize fallback mode only on the port initializes sh. */
321 sh->cmng.counter_fallback = fallback;
322 else if (fallback != sh->cmng.counter_fallback)
323 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
324 "with others:%d.", PORT_ID(priv), fallback);
329 * Spawn an Ethernet device from Verbs information.
332 * Backing DPDK device.
334 * Verbs device parameters (name, port, switch_info) to spawn.
336 * Device configuration parameters.
339 * A valid Ethernet device object on success, NULL otherwise and rte_errno
340 * is set. The following errors are defined:
342 * EEXIST: device is already spawned
344 static struct rte_eth_dev *
345 mlx5_dev_spawn(struct rte_device *dpdk_dev,
346 struct mlx5_dev_spawn_data *spawn,
347 struct mlx5_dev_config *config)
349 const struct mlx5_switch_info *switch_info = &spawn->info;
350 struct mlx5_dev_ctx_shared *sh = NULL;
351 struct mlx5_dev_attr device_attr;
352 struct rte_eth_dev *eth_dev = NULL;
353 struct mlx5_priv *priv = NULL;
355 unsigned int cqe_comp;
356 struct rte_ether_addr mac;
357 char name[RTE_ETH_NAME_MAX_LEN];
358 int own_domain_id = 0;
362 /* Build device name. */
363 strlcpy(name, dpdk_dev->name, sizeof(name));
364 /* check if the device is already spawned */
365 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
369 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
371 * Some parameters are needed in advance to create device context. We
372 * process the devargs here to get ones, and later process devargs
373 * again to override some hardware settings.
375 err = mlx5_args(config, dpdk_dev->devargs);
378 DRV_LOG(ERR, "failed to process device arguments: %s",
379 strerror(rte_errno));
382 mlx5_malloc_mem_select(config->sys_mem_en);
383 sh = mlx5_alloc_shared_dev_ctx(spawn, config);
386 config->devx = sh->devx;
387 /* Initialize the shutdown event in mlx5_dev_spawn to
388 * support mlx5_is_removed for Windows.
390 err = mlx5_glue->devx_init_showdown_event(sh->ctx);
392 DRV_LOG(ERR, "failed to init showdown event: %s",
396 DRV_LOG(DEBUG, "MPW isn't supported");
397 mlx5_os_get_dev_attr(sh->ctx, &device_attr);
398 config->swp = device_attr.sw_parsing_offloads &
399 (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
400 MLX5_SW_PARSING_TSO_CAP);
401 config->ind_table_max_size =
402 sh->device_attr.max_rwq_indirection_table_size;
404 config->cqe_comp = cqe_comp;
405 DRV_LOG(DEBUG, "tunnel offloading is not supported");
406 config->tunnel_en = 0;
407 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported");
409 /* Allocate private eth device data. */
410 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
412 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
414 DRV_LOG(ERR, "priv allocation failure");
419 priv->dev_port = spawn->phys_port;
420 priv->pci_dev = spawn->pci_dev;
421 priv->mtu = RTE_ETHER_MTU;
422 priv->mp_id.port_id = port_id;
423 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
424 priv->representor = !!switch_info->representor;
425 priv->master = !!switch_info->master;
426 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
427 priv->vport_meta_tag = 0;
428 priv->vport_meta_mask = 0;
429 priv->pf_bond = spawn->pf_bond;
431 /* representor_id field keeps the unmodified VF index. */
432 priv->representor_id = -1;
434 * Look for sibling devices in order to reuse their switch domain
435 * if any, otherwise allocate one.
437 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
438 const struct mlx5_priv *opriv =
439 rte_eth_devices[port_id].data->dev_private;
442 opriv->sh != priv->sh ||
444 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
446 priv->domain_id = opriv->domain_id;
449 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
450 err = rte_eth_switch_domain_alloc(&priv->domain_id);
453 DRV_LOG(ERR, "unable to allocate switch domain: %s",
454 strerror(rte_errno));
459 /* Override some values set by hardware configuration. */
460 mlx5_args(config, dpdk_dev->devargs);
461 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev);
464 DRV_LOG(DEBUG, "counters are not supported");
465 config->ind_table_max_size =
466 sh->device_attr.max_rwq_indirection_table_size;
468 * Remove this check once DPDK supports larger/variable
469 * indirection tables.
471 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
472 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
473 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
474 config->ind_table_max_size);
475 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
476 (config->hw_vlan_strip ? "" : "not "));
477 if (config->hw_padding) {
478 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
479 config->hw_padding = 0;
482 config->tso_max_payload_sz = sh->device_attr.max_tso;
483 DRV_LOG(DEBUG, "%sMPS is %s.",
484 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
485 config->mps == MLX5_MPW ? "legacy " : "",
486 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
487 if (config->cqe_comp && !cqe_comp) {
488 DRV_LOG(WARNING, "Rx CQE compression isn't supported.");
489 config->cqe_comp = 0;
492 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);
497 /* Check relax ordering support. */
498 sh->cmng.relaxed_ordering_read = 0;
499 sh->cmng.relaxed_ordering_write = 0;
500 if (!haswell_broadwell_cpu) {
501 sh->cmng.relaxed_ordering_write =
502 config->hca_attr.relaxed_ordering_write;
503 sh->cmng.relaxed_ordering_read =
504 config->hca_attr.relaxed_ordering_read;
506 config->hw_csum = config->hca_attr.csum_cap;
507 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
508 (config->hw_csum ? "" : "not "));
511 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
513 err = config->hca_attr.access_register_user ?
514 mlx5_devx_cmd_register_read
515 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,
516 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
520 /* MTUTC register is read successfully. */
521 ts_mode = MLX5_GET(register_mtutc, reg,
523 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
524 config->rt_timestamp = 1;
526 /* Kernel does not support register reading. */
527 if (config->hca_attr.dev_freq_khz ==
528 (NS_PER_S / MS_PER_S))
529 config->rt_timestamp = 1;
531 sh->rq_ts_format = config->hca_attr.rq_ts_format;
532 sh->sq_ts_format = config->hca_attr.sq_ts_format;
533 sh->qp_ts_format = config->hca_attr.qp_ts_format;
535 if (config->mprq.enabled) {
536 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
537 config->mprq.enabled = 0;
539 if (config->max_dump_files_num == 0)
540 config->max_dump_files_num = 128;
541 eth_dev = rte_eth_dev_allocate(name);
542 if (eth_dev == NULL) {
543 DRV_LOG(ERR, "can not allocate rte ethdev");
547 if (priv->representor) {
548 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
549 eth_dev->data->representor_id = priv->representor_id;
550 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
551 struct mlx5_priv *opriv =
552 rte_eth_devices[port_id].data->dev_private;
555 opriv->domain_id == priv->domain_id &&
556 opriv->sh == priv->sh) {
557 eth_dev->data->backer_port_id = port_id;
561 if (port_id >= RTE_MAX_ETHPORTS)
562 eth_dev->data->backer_port_id = eth_dev->data->port_id;
565 * Store associated network device interface index. This index
566 * is permanent throughout the lifetime of device. So, we may store
567 * the ifindex here and use the cached value further.
569 MLX5_ASSERT(spawn->ifindex);
570 priv->if_index = spawn->ifindex;
571 eth_dev->data->dev_private = priv;
572 priv->dev_data = eth_dev->data;
573 eth_dev->data->mac_addrs = priv->mac;
574 eth_dev->device = dpdk_dev;
575 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
576 /* Configure the first MAC address by default. */
577 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
579 "port %u cannot get MAC address, is mlx5_en"
580 " loaded? (errno: %s).",
581 eth_dev->data->port_id, strerror(rte_errno));
586 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT,
587 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac));
588 #ifdef RTE_LIBRTE_MLX5_DEBUG
590 char ifname[MLX5_NAMESIZE];
592 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
593 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
594 eth_dev->data->port_id, ifname);
596 DRV_LOG(DEBUG, "port %u ifname is unknown.",
597 eth_dev->data->port_id);
600 /* Get actual MTU if possible. */
601 err = mlx5_get_mtu(eth_dev, &priv->mtu);
606 DRV_LOG(DEBUG, "port %u MTU is %u.", eth_dev->data->port_id,
608 /* Initialize burst functions to prevent crashes before link-up. */
609 eth_dev->rx_pkt_burst = removed_rx_burst;
610 eth_dev->tx_pkt_burst = removed_tx_burst;
611 eth_dev->dev_ops = &mlx5_dev_ops;
612 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
613 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
614 eth_dev->rx_queue_count = mlx5_rx_queue_count;
615 /* Register MAC address. */
616 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
617 priv->ctrl_flows = 0;
618 TAILQ_INIT(&priv->flow_meters);
619 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR);
620 if (!priv->mtr_profile_tbl)
622 /* Bring Ethernet device up. */
623 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up.",
624 eth_dev->data->port_id);
625 /* nl calls are unsupported - set to -1 not to fail on release */
626 priv->nl_socket_rdma = -1;
627 priv->nl_socket_route = -1;
628 mlx5_set_link_up(eth_dev);
630 * Even though the interrupt handler is not installed yet,
631 * interrupts will still trigger on the async_fd from
632 * Verbs context returned by ibv_open_device().
634 mlx5_link_update(eth_dev, 0);
635 config->dv_esw_en = 0;
636 /* Detect minimal data bytes to inline. */
637 mlx5_set_min_inline(spawn, config);
638 /* Store device configuration on private structure. */
639 priv->config = *config;
640 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
641 icfg[i].release_mem_en = !!config->reclaim_mode;
642 if (config->reclaim_mode)
643 icfg[i].per_core_cache = 0;
644 priv->flows[i] = mlx5_ipool_create(&icfg[i]);
648 /* Create context for virtual machine VLAN workaround. */
649 priv->vmwa_context = NULL;
650 if (config->dv_flow_en) {
651 err = mlx5_alloc_shared_dr(priv);
655 /* No supported flow priority number detection. */
656 priv->config.flow_prio = -1;
657 if (!priv->config.dv_esw_en &&
658 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
659 DRV_LOG(WARNING, "metadata mode %u is not supported "
660 "(no E-Switch)", priv->config.dv_xmeta_en);
661 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
663 mlx5_set_metadata_mask(eth_dev);
664 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
665 !priv->sh->dv_regc0_mask) {
666 DRV_LOG(ERR, "metadata mode %u is not supported "
667 "(no metadata reg_c[0] is available).",
668 priv->config.dv_xmeta_en);
672 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true,
673 mlx5_hrxq_create_cb, mlx5_hrxq_match_cb,
674 mlx5_hrxq_remove_cb, mlx5_hrxq_clone_cb,
675 mlx5_hrxq_clone_free_cb);
676 /* Query availability of metadata reg_c's. */
677 err = mlx5_flow_discover_mreg_c(eth_dev);
682 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
684 "port %u extensive metadata register is not supported.",
685 eth_dev->data->port_id);
686 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
687 DRV_LOG(ERR, "metadata mode %u is not supported "
688 "(no metadata registers available).",
689 priv->config.dv_xmeta_en);
694 if (config->devx && config->dv_flow_en) {
695 priv->obj_ops = devx_obj_ops;
697 DRV_LOG(ERR, "Flow mode %u is not supported "
698 "(Windows flow must be DevX with DV flow enabled).",
699 priv->config.dv_flow_en);
703 mlx5_flow_counter_mode_config(eth_dev);
707 if (priv->mtr_profile_tbl)
708 mlx5_l3t_destroy(priv->mtr_profile_tbl);
710 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
713 eth_dev->data->dev_private = NULL;
715 if (eth_dev != NULL) {
716 /* mac_addrs must not be freed alone because part of
719 eth_dev->data->mac_addrs = NULL;
720 rte_eth_dev_release_port(eth_dev);
723 mlx5_free_shared_dev_ctx(sh);
724 MLX5_ASSERT(err > 0);
730 * This function should share events between multiple ports of single IB
731 * device. Currently it has no support under Windows.
734 * Pointer to mlx5_dev_ctx_shared object.
737 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
740 DRV_LOG(WARNING, "%s: is not supported", __func__);
744 * This function should share events between multiple ports of single IB
745 * device. Currently it has no support under Windows.
748 * Pointer to mlx5_dev_ctx_shared object.
751 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
754 DRV_LOG(WARNING, "%s: is not supported", __func__);
758 * Read statistics by a named counter.
761 * Pointer to the private device data structure.
762 * @param[in] ctr_name
763 * Pointer to the name of the statistic counter to read
765 * Pointer to read statistic value.
767 * 0 on success and stat is valud, 1 if failed to read the value
772 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
776 RTE_SET_USED(ctr_name);
778 DRV_LOG(WARNING, "%s: is not supported", __func__);
783 * Flush device MAC addresses
784 * Currently it has no support under Windows.
787 * Pointer to Ethernet device structure.
791 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev)
794 DRV_LOG(WARNING, "%s: is not supported", __func__);
798 * Remove a MAC address from device
799 * Currently it has no support under Windows.
802 * Pointer to Ethernet device structure.
807 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
811 DRV_LOG(WARNING, "%s: is not supported", __func__);
815 * Adds a MAC address to the device
816 * Currently it has no support under Windows.
819 * Pointer to Ethernet device structure.
821 * MAC address to register.
826 * 0 on success, a negative errno value otherwise
829 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
833 struct rte_ether_addr lmac;
835 if (mlx5_get_mac(dev, &lmac.addr_bytes)) {
837 "port %u cannot get MAC address, is mlx5_en"
838 " loaded? (errno: %s)",
839 dev->data->port_id, strerror(rte_errno));
842 if (!rte_is_same_ether_addr(&lmac, mac)) {
844 "adding new mac address to device is unsupported");
851 * Modify a VF MAC address
852 * Currently it has no support under Windows.
855 * Pointer to device private data.
857 * MAC address to modify into.
859 * Net device interface index
864 * 0 on success, a negative errno value otherwise
867 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv,
868 unsigned int iface_idx,
869 struct rte_ether_addr *mac_addr,
876 DRV_LOG(WARNING, "%s: is not supported", __func__);
881 * Set device promiscuous mode
882 * Currently it has no support under Windows.
885 * Pointer to Ethernet device structure.
887 * 0 - promiscuous is disabled, otherwise - enabled
890 * 0 on success, a negative error value otherwise
893 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable)
897 DRV_LOG(WARNING, "%s: is not supported", __func__);
902 * Set device allmulti mode
905 * Pointer to Ethernet device structure.
907 * 0 - all multicase is disabled, otherwise - enabled
910 * 0 on success, a negative error value otherwise
913 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)
917 DRV_LOG(WARNING, "%s: is not supported", __func__);
922 * Detect if a devx_device_bdf object has identical DBDF values to the
923 * rte_pci_addr found in bus/pci probing
925 * @param[in] devx_bdf
926 * Pointer to the devx_device_bdf structure.
928 * Pointer to the rte_pci_addr structure.
931 * 1 on Device match, 0 on mismatch.
934 mlx5_match_devx_bdf_to_addr(struct devx_device_bdf *devx_bdf,
935 struct rte_pci_addr *addr)
937 if (addr->domain != (devx_bdf->bus_id >> 8) ||
938 addr->bus != (devx_bdf->bus_id & 0xff) ||
939 addr->devid != devx_bdf->dev_id ||
940 addr->function != devx_bdf->fnc_id) {
947 * Detect if a devx_device_bdf object matches the rte_pci_addr
948 * found in bus/pci probing
949 * Compare both the Native/PF BDF and the raw_bdf representing a VF BDF.
951 * @param[in] devx_bdf
952 * Pointer to the devx_device_bdf structure.
954 * Pointer to the rte_pci_addr structure.
957 * 1 on Device match, 0 on mismatch, rte_errno code on failure.
960 mlx5_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf,
961 struct rte_pci_addr *addr)
964 struct devx_device mlx5_dev;
966 if (mlx5_match_devx_bdf_to_addr(devx_bdf, addr))
969 * Didn't match on Native/PF BDF, could still
970 * Match a VF BDF, check it next
972 err = mlx5_glue->query_device(devx_bdf, &mlx5_dev);
974 DRV_LOG(ERR, "query_device failed");
978 if (mlx5_match_devx_bdf_to_addr(&mlx5_dev.raw_bdf, addr))
984 * DPDK callback to register a PCI device.
986 * This function spawns Ethernet devices out of a given device.
989 * Pointer to the generic device.
992 * 0 on success, a negative errno value otherwise and rte_errno is set.
995 mlx5_os_net_probe(struct rte_device *dev)
997 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
998 struct devx_device_bdf *devx_bdf_devs, *orig_devx_bdf_devs;
1000 * Number of found IB Devices matching with requested PCI BDF.
1001 * nd != 1 means there are multiple IB devices over the same
1002 * PCI device and we have representors and master.
1004 unsigned int nd = 0;
1006 * Number of found IB device Ports. nd = 1 and np = 1..n means
1007 * we have the single multiport IB device, and there may be
1008 * representors attached to some of found ports.
1009 * Currently not supported.
1010 * unsigned int np = 0;
1014 * Number of DPDK ethernet devices to Spawn - either over
1015 * multiple IB devices or multiple ports of single IB device.
1016 * Actually this is the number of iterations to spawn.
1018 unsigned int ns = 0;
1021 * < 0 - no bonding device (single one)
1022 * >= 0 - bonding device (value is slave PF index)
1025 struct mlx5_dev_spawn_data *list = NULL;
1026 struct mlx5_dev_config dev_config;
1027 unsigned int dev_config_vf;
1031 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1032 DRV_LOG(ERR, "Secondary process is not supported on Windows.");
1035 ret = mlx5_init_once();
1037 DRV_LOG(ERR, "unable to init PMD global data: %s",
1038 strerror(rte_errno));
1042 devx_bdf_devs = mlx5_glue->get_device_list(&ret);
1043 orig_devx_bdf_devs = devx_bdf_devs;
1044 if (!devx_bdf_devs) {
1045 rte_errno = errno ? errno : ENOSYS;
1046 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1050 * First scan the list of all Infiniband devices to find
1051 * matching ones, gathering into the list.
1053 struct devx_device_bdf *devx_bdf_match[ret + 1];
1056 err = mlx5_match_devx_devices_to_addr(devx_bdf_devs,
1066 devx_bdf_match[nd++] = devx_bdf_devs;
1068 devx_bdf_match[nd] = NULL;
1070 /* No device matches, just complain and bail out. */
1072 "no DevX device matches PCI device " PCI_PRI_FMT ","
1073 " is DevX Configured?",
1074 pci_dev->addr.domain, pci_dev->addr.bus,
1075 pci_dev->addr.devid, pci_dev->addr.function);
1081 * Now we can determine the maximal
1082 * amount of devices to be spawned.
1084 list = mlx5_malloc(MLX5_MEM_ZERO,
1085 sizeof(struct mlx5_dev_spawn_data),
1086 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1088 DRV_LOG(ERR, "spawn data array allocation failure");
1093 memset(&list[ns].info, 0, sizeof(list[ns].info));
1094 list[ns].max_port = 1;
1095 list[ns].phys_port = 1;
1096 list[ns].phys_dev = devx_bdf_match[ns];
1097 list[ns].eth_dev = NULL;
1098 list[ns].pci_dev = pci_dev;
1099 list[ns].pf_bond = bd;
1100 list[ns].ifindex = -1; /* Spawn will assign */
1102 (struct mlx5_switch_info){
1105 .name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK,
1109 /* Device specific configuration. */
1110 switch (pci_dev->id.device_id) {
1111 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1112 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1113 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1114 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1115 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
1116 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
1117 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF:
1124 /* Default configuration. */
1125 memset(&dev_config, 0, sizeof(struct mlx5_dev_config));
1126 dev_config.vf = dev_config_vf;
1128 dev_config.dbnc = MLX5_ARG_UNSET;
1129 dev_config.rx_vec_en = 1;
1130 dev_config.txq_inline_max = MLX5_ARG_UNSET;
1131 dev_config.txq_inline_min = MLX5_ARG_UNSET;
1132 dev_config.txq_inline_mpw = MLX5_ARG_UNSET;
1133 dev_config.txqs_inline = MLX5_ARG_UNSET;
1134 dev_config.vf_nl_en = 0;
1135 dev_config.mr_ext_memseg_en = 1;
1136 dev_config.mr_mempool_reg_en = 1;
1137 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;
1138 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;
1139 dev_config.dv_esw_en = 0;
1140 dev_config.dv_flow_en = 1;
1141 dev_config.decap_en = 0;
1142 dev_config.log_hp_size = MLX5_ARG_UNSET;
1143 list[ns].numa_node = pci_dev->device.numa_node;
1144 list[ns].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1147 if (!list[ns].eth_dev)
1149 restore = list[ns].eth_dev->data->dev_flags;
1150 rte_eth_copy_pci_info(list[ns].eth_dev, pci_dev);
1151 /* Restore non-PCI flags cleared by the above call. */
1152 list[ns].eth_dev->data->dev_flags |= restore;
1153 rte_eth_dev_probing_finish(list[ns].eth_dev);
1157 * Do the routine cleanup:
1158 * - free allocated spawn data array
1159 * - free the device list
1163 MLX5_ASSERT(orig_devx_bdf_devs);
1164 mlx5_glue->free_device_list(orig_devx_bdf_devs);
1169 * Set the reg_mr and dereg_mr call backs
1171 * @param reg_mr_cb[out]
1172 * Pointer to reg_mr func
1173 * @param dereg_mr_cb[out]
1174 * Pointer to dereg_mr func
1178 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1179 mlx5_dereg_mr_t *dereg_mr_cb)
1181 *reg_mr_cb = mlx5_os_reg_mr;
1182 *dereg_mr_cb = mlx5_os_dereg_mr;
1186 * Extract pdn of PD object using DevX
1189 * Pointer to the DevX PD object.
1191 * Pointer to the PD object number variable.
1194 * 0 on success, error value otherwise.
1197 mlx5_os_get_pdn(void *pd, uint32_t *pdn)
1202 *pdn = ((struct mlx5_pd *)pd)->pdn;
1206 const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0};