1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
11 #include <rte_windows.h>
12 #include <ethdev_pci.h>
14 #include <mlx5_glue.h>
15 #include <mlx5_devx_cmds.h>
16 #include <mlx5_common.h>
17 #include <mlx5_common_mp.h>
18 #include <mlx5_common_mr.h>
19 #include <mlx5_malloc.h>
21 #include "mlx5_defs.h"
23 #include "mlx5_common_os.h"
24 #include "mlx5_utils.h"
25 #include "mlx5_rxtx.h"
28 #include "mlx5_autoconf.h"
30 #include "mlx5_flow.h"
31 #include "mlx5_devx.h"
33 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
35 /* Spinlock for mlx5_shared_data allocation. */
36 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
38 /* rte flow indexed pool configuration. */
39 static struct mlx5_indexed_pool_config icfg[] = {
41 .size = sizeof(struct rte_flow),
45 .malloc = mlx5_malloc,
48 .type = "ctl_flow_ipool",
51 .size = sizeof(struct rte_flow),
57 .malloc = mlx5_malloc,
59 .per_core_cache = 1 << 14,
60 .type = "rte_flow_ipool",
63 .size = sizeof(struct rte_flow),
69 .malloc = mlx5_malloc,
72 .type = "mcp_flow_ipool",
77 * Initialize shared data between primary and secondary process.
79 * A memzone is reserved by primary process and secondary processes attach to
83 * 0 on success, a negative errno value otherwise and rte_errno is set.
86 mlx5_init_shared_data(void)
88 const struct rte_memzone *mz;
91 rte_spinlock_lock(&mlx5_shared_data_lock);
92 if (mlx5_shared_data == NULL) {
93 /* Allocate shared memory. */
94 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
95 sizeof(*mlx5_shared_data),
99 "Cannot allocate mlx5 shared data");
103 mlx5_shared_data = mz->addr;
104 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
105 rte_spinlock_init(&mlx5_shared_data->lock);
108 rte_spinlock_unlock(&mlx5_shared_data_lock);
113 * PMD global initialization.
115 * Independent from individual device, this function initializes global
116 * per-PMD data structures distinguishing primary and secondary processes.
117 * Hence, each initialization is called once per a process.
120 * 0 on success, a negative errno value otherwise and rte_errno is set.
125 struct mlx5_shared_data *sd;
127 if (mlx5_init_shared_data())
129 sd = mlx5_shared_data;
130 rte_spinlock_lock(&sd->lock);
132 if (!sd->init_done) {
133 LIST_INIT(&sd->mem_event_cb_list);
134 rte_rwlock_init(&sd->mem_event_rwlock);
135 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
136 mlx5_mr_mem_event_cb, NULL);
137 sd->init_done = true;
139 rte_spinlock_unlock(&sd->lock);
144 * Get mlx5 device attributes.
147 * Pointer to mlx5 device.
150 * Pointer to mlx5 device attributes.
153 * 0 on success, non zero error number otherwise.
156 mlx5_os_get_dev_attr(struct mlx5_common_device *cdev,
157 struct mlx5_dev_attr *device_attr)
159 struct mlx5_context *mlx5_ctx;
160 void *pv_iseg = NULL;
164 if (!cdev || !cdev->ctx)
166 mlx5_ctx = (struct mlx5_context *)cdev->ctx;
167 memset(device_attr, 0, sizeof(*device_attr));
168 device_attr->max_cq = 1 << cdev->config.hca_attr.log_max_cq;
169 device_attr->max_qp = 1 << cdev->config.hca_attr.log_max_qp;
170 device_attr->max_qp_wr = 1 << cdev->config.hca_attr.log_max_qp_sz;
171 device_attr->max_cqe = 1 << cdev->config.hca_attr.log_max_cq_sz;
172 device_attr->max_mr = 1 << cdev->config.hca_attr.log_max_mrw_sz;
173 device_attr->max_pd = 1 << cdev->config.hca_attr.log_max_pd;
174 device_attr->max_srq = 1 << cdev->config.hca_attr.log_max_srq;
175 device_attr->max_srq_wr = 1 << cdev->config.hca_attr.log_max_srq_sz;
176 device_attr->max_tso = 1 << cdev->config.hca_attr.max_lso_cap;
177 if (cdev->config.hca_attr.rss_ind_tbl_cap) {
178 device_attr->max_rwq_indirection_table_size =
179 1 << cdev->config.hca_attr.rss_ind_tbl_cap;
181 device_attr->sw_parsing_offloads =
182 mlx5_get_supported_sw_parsing_offloads(&cdev->config.hca_attr);
183 device_attr->tunnel_offloads_caps =
184 mlx5_get_supported_tunneling_offloads(&cdev->config.hca_attr);
185 pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
186 if (pv_iseg == NULL) {
187 DRV_LOG(ERR, "Failed to get device hca_iseg");
191 snprintf(device_attr->fw_ver, 64, "%x.%x.%04x",
192 MLX5_GET(initial_seg, pv_iseg, fw_rev_major),
193 MLX5_GET(initial_seg, pv_iseg, fw_rev_minor),
194 MLX5_GET(initial_seg, pv_iseg, fw_rev_subminor));
200 * Initialize DR related data within private structure.
201 * Routine checks the reference counter and does actual
202 * resources creation/initialization only if counter is zero.
205 * Pointer to the private device data structure.
208 * Zero on success, positive error code otherwise.
211 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
213 struct mlx5_dev_ctx_shared *sh = priv->sh;
217 err = mlx5_alloc_table_hash_list(priv);
219 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse",
220 (void *)sh->flow_tbls);
224 * Destroy DR related data within private structure.
227 * Pointer to the private device data structure.
230 mlx5_os_free_shared_dr(struct mlx5_priv *priv)
232 mlx5_free_table_hash_list(priv);
236 * Set the completion channel file descriptor interrupt as non-blocking.
237 * Currently it has no support under Windows.
240 * Pointer to RQ channel object, which includes the channel fd
243 * The file descriptor (representing the intetrrupt) used in this channel.
246 * 0 on successfully setting the fd to non-blocking, non-zero otherwise.
249 mlx5_os_set_nonblock_channel_fd(int fd)
252 DRV_LOG(WARNING, "%s: is not supported", __func__);
257 * DV flow counter mode detect and config.
260 * Pointer to rte_eth_dev structure.
264 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
266 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
267 struct mlx5_priv *priv = dev->data->dev_private;
268 struct mlx5_dev_ctx_shared *sh = priv->sh;
271 #ifndef HAVE_IBV_DEVX_ASYNC
275 if (!sh->devx || !priv->config.dv_flow_en ||
276 !priv->config.hca_attr.flow_counters_dump ||
277 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) ||
278 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
282 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
283 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
284 priv->config.hca_attr.flow_counters_dump,
285 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap);
286 /* Initialize fallback mode only on the port initializes sh. */
288 sh->cmng.counter_fallback = fallback;
289 else if (fallback != sh->cmng.counter_fallback)
290 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
291 "with others:%d.", PORT_ID(priv), fallback);
296 * Spawn an Ethernet device from DevX information.
299 * Backing DPDK device.
301 * Verbs device parameters (name, port, switch_info) to spawn.
303 * Device configuration parameters.
306 * A valid Ethernet device object on success, NULL otherwise and rte_errno
307 * is set. The following errors are defined:
309 * EEXIST: device is already spawned
311 static struct rte_eth_dev *
312 mlx5_dev_spawn(struct rte_device *dpdk_dev,
313 struct mlx5_dev_spawn_data *spawn,
314 struct mlx5_dev_config *config)
316 const struct mlx5_switch_info *switch_info = &spawn->info;
317 struct mlx5_dev_ctx_shared *sh = NULL;
318 struct mlx5_dev_attr device_attr;
319 struct rte_eth_dev *eth_dev = NULL;
320 struct mlx5_priv *priv = NULL;
322 unsigned int cqe_comp;
323 struct rte_ether_addr mac;
324 char name[RTE_ETH_NAME_MAX_LEN];
325 int own_domain_id = 0;
329 /* Build device name. */
330 strlcpy(name, dpdk_dev->name, sizeof(name));
331 /* check if the device is already spawned */
332 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
336 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
338 * Some parameters are needed in advance to create device context. We
339 * process the devargs here to get ones, and later process devargs
340 * again to override some hardware settings.
342 err = mlx5_args(config, dpdk_dev->devargs);
345 DRV_LOG(ERR, "failed to process device arguments: %s",
346 strerror(rte_errno));
349 sh = mlx5_alloc_shared_dev_ctx(spawn, config);
352 /* Initialize the shutdown event in mlx5_dev_spawn to
353 * support mlx5_is_removed for Windows.
355 err = mlx5_glue->devx_init_showdown_event(sh->cdev->ctx);
357 DRV_LOG(ERR, "failed to init showdown event: %s",
361 DRV_LOG(DEBUG, "MPW isn't supported");
362 mlx5_os_get_dev_attr(sh->cdev, &device_attr);
363 config->swp = device_attr.sw_parsing_offloads &
364 (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
365 MLX5_SW_PARSING_TSO_CAP);
366 config->ind_table_max_size =
367 sh->device_attr.max_rwq_indirection_table_size;
369 config->cqe_comp = cqe_comp;
370 config->tunnel_en = device_attr.tunnel_offloads_caps &
371 (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |
372 MLX5_TUNNELED_OFFLOADS_GRE_CAP |
373 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);
374 if (config->tunnel_en) {
375 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
377 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "",
379 MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "",
381 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""
384 DRV_LOG(DEBUG, "tunnel offloading is not supported");
386 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported");
388 /* Allocate private eth device data. */
389 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
391 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
393 DRV_LOG(ERR, "priv allocation failure");
398 priv->dev_port = spawn->phys_port;
399 priv->pci_dev = spawn->pci_dev;
400 priv->mtu = RTE_ETHER_MTU;
401 priv->mp_id.port_id = port_id;
402 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
403 priv->representor = !!switch_info->representor;
404 priv->master = !!switch_info->master;
405 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
406 priv->vport_meta_tag = 0;
407 priv->vport_meta_mask = 0;
408 priv->pf_bond = spawn->pf_bond;
410 /* representor_id field keeps the unmodified VF index. */
411 priv->representor_id = -1;
413 * Look for sibling devices in order to reuse their switch domain
414 * if any, otherwise allocate one.
416 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
417 const struct mlx5_priv *opriv =
418 rte_eth_devices[port_id].data->dev_private;
421 opriv->sh != priv->sh ||
423 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
425 priv->domain_id = opriv->domain_id;
428 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
429 err = rte_eth_switch_domain_alloc(&priv->domain_id);
432 DRV_LOG(ERR, "unable to allocate switch domain: %s",
433 strerror(rte_errno));
438 /* Override some values set by hardware configuration. */
439 mlx5_args(config, dpdk_dev->devargs);
440 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev);
443 DRV_LOG(DEBUG, "counters are not supported");
444 config->ind_table_max_size =
445 sh->device_attr.max_rwq_indirection_table_size;
447 * Remove this check once DPDK supports larger/variable
448 * indirection tables.
450 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
451 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
452 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
453 config->ind_table_max_size);
454 if (config->hw_padding) {
455 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
456 config->hw_padding = 0;
458 config->tso = (sh->device_attr.max_tso > 0);
460 config->tso_max_payload_sz = sh->device_attr.max_tso;
461 DRV_LOG(DEBUG, "%sMPS is %s.",
462 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
463 config->mps == MLX5_MPW ? "legacy " : "",
464 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
465 if (config->cqe_comp && !cqe_comp) {
466 DRV_LOG(WARNING, "Rx CQE compression isn't supported.");
467 config->cqe_comp = 0;
470 config->hca_attr = sh->cdev->config.hca_attr;
471 config->hw_csum = config->hca_attr.csum_cap;
472 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
473 (config->hw_csum ? "" : "not "));
474 config->hw_vlan_strip = config->hca_attr.vlan_cap;
475 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
476 (config->hw_vlan_strip ? "" : "not "));
477 config->hw_fcs_strip = config->hca_attr.scatter_fcs;
480 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
482 err = config->hca_attr.access_register_user ?
483 mlx5_devx_cmd_register_read
484 (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,
485 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
489 /* MTUTC register is read successfully. */
490 ts_mode = MLX5_GET(register_mtutc, reg,
492 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
493 config->rt_timestamp = 1;
495 /* Kernel does not support register reading. */
496 if (config->hca_attr.dev_freq_khz ==
497 (NS_PER_S / MS_PER_S))
498 config->rt_timestamp = 1;
501 if (config->mprq.enabled) {
502 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
503 config->mprq.enabled = 0;
505 if (config->max_dump_files_num == 0)
506 config->max_dump_files_num = 128;
507 eth_dev = rte_eth_dev_allocate(name);
508 if (eth_dev == NULL) {
509 DRV_LOG(ERR, "can not allocate rte ethdev");
513 if (priv->representor) {
514 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
515 eth_dev->data->representor_id = priv->representor_id;
516 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
517 struct mlx5_priv *opriv =
518 rte_eth_devices[port_id].data->dev_private;
521 opriv->domain_id == priv->domain_id &&
522 opriv->sh == priv->sh) {
523 eth_dev->data->backer_port_id = port_id;
527 if (port_id >= RTE_MAX_ETHPORTS)
528 eth_dev->data->backer_port_id = eth_dev->data->port_id;
531 * Store associated network device interface index. This index
532 * is permanent throughout the lifetime of device. So, we may store
533 * the ifindex here and use the cached value further.
535 MLX5_ASSERT(spawn->ifindex);
536 priv->if_index = spawn->ifindex;
537 eth_dev->data->dev_private = priv;
538 priv->dev_data = eth_dev->data;
539 eth_dev->data->mac_addrs = priv->mac;
540 eth_dev->device = dpdk_dev;
541 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
542 /* Configure the first MAC address by default. */
543 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
545 "port %u cannot get MAC address, is mlx5_en"
546 " loaded? (errno: %s).",
547 eth_dev->data->port_id, strerror(rte_errno));
552 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT,
553 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac));
554 #ifdef RTE_LIBRTE_MLX5_DEBUG
556 char ifname[MLX5_NAMESIZE];
558 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
559 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
560 eth_dev->data->port_id, ifname);
562 DRV_LOG(DEBUG, "port %u ifname is unknown.",
563 eth_dev->data->port_id);
566 /* Get actual MTU if possible. */
567 err = mlx5_get_mtu(eth_dev, &priv->mtu);
572 DRV_LOG(DEBUG, "port %u MTU is %u.", eth_dev->data->port_id,
574 /* Initialize burst functions to prevent crashes before link-up. */
575 eth_dev->rx_pkt_burst = removed_rx_burst;
576 eth_dev->tx_pkt_burst = removed_tx_burst;
577 eth_dev->dev_ops = &mlx5_dev_ops;
578 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
579 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
580 eth_dev->rx_queue_count = mlx5_rx_queue_count;
581 /* Register MAC address. */
582 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
583 priv->ctrl_flows = 0;
584 TAILQ_INIT(&priv->flow_meters);
585 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR);
586 if (!priv->mtr_profile_tbl)
588 /* Bring Ethernet device up. */
589 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up.",
590 eth_dev->data->port_id);
591 /* nl calls are unsupported - set to -1 not to fail on release */
592 priv->nl_socket_rdma = -1;
593 priv->nl_socket_route = -1;
594 mlx5_set_link_up(eth_dev);
596 * Even though the interrupt handler is not installed yet,
597 * interrupts will still trigger on the async_fd from
598 * Verbs context returned by ibv_open_device().
600 mlx5_link_update(eth_dev, 0);
601 config->dv_esw_en = 0;
602 /* Detect minimal data bytes to inline. */
603 mlx5_set_min_inline(spawn, config);
604 /* Store device configuration on private structure. */
605 priv->config = *config;
606 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
607 icfg[i].release_mem_en = !!config->reclaim_mode;
608 if (config->reclaim_mode)
609 icfg[i].per_core_cache = 0;
610 priv->flows[i] = mlx5_ipool_create(&icfg[i]);
614 /* Create context for virtual machine VLAN workaround. */
615 priv->vmwa_context = NULL;
616 if (config->dv_flow_en) {
617 err = mlx5_alloc_shared_dr(priv);
621 /* No supported flow priority number detection. */
622 priv->config.flow_prio = -1;
623 if (!priv->config.dv_esw_en &&
624 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
625 DRV_LOG(WARNING, "metadata mode %u is not supported "
626 "(no E-Switch)", priv->config.dv_xmeta_en);
627 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
629 mlx5_set_metadata_mask(eth_dev);
630 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
631 !priv->sh->dv_regc0_mask) {
632 DRV_LOG(ERR, "metadata mode %u is not supported "
633 "(no metadata reg_c[0] is available).",
634 priv->config.dv_xmeta_en);
638 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true,
639 mlx5_hrxq_create_cb, mlx5_hrxq_match_cb,
640 mlx5_hrxq_remove_cb, mlx5_hrxq_clone_cb,
641 mlx5_hrxq_clone_free_cb);
642 /* Query availability of metadata reg_c's. */
643 err = mlx5_flow_discover_mreg_c(eth_dev);
648 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
650 "port %u extensive metadata register is not supported.",
651 eth_dev->data->port_id);
652 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
653 DRV_LOG(ERR, "metadata mode %u is not supported "
654 "(no metadata registers available).",
655 priv->config.dv_xmeta_en);
660 if (sh->devx && config->dv_flow_en) {
661 priv->obj_ops = devx_obj_ops;
663 DRV_LOG(ERR, "Flow mode %u is not supported "
664 "(Windows flow must be DevX with DV flow enabled).",
665 priv->config.dv_flow_en);
669 mlx5_flow_counter_mode_config(eth_dev);
673 if (priv->mtr_profile_tbl)
674 mlx5_l3t_destroy(priv->mtr_profile_tbl);
676 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
679 eth_dev->data->dev_private = NULL;
681 if (eth_dev != NULL) {
682 /* mac_addrs must not be freed alone because part of
685 eth_dev->data->mac_addrs = NULL;
686 rte_eth_dev_release_port(eth_dev);
689 mlx5_free_shared_dev_ctx(sh);
690 MLX5_ASSERT(err > 0);
696 * This function should share events between multiple ports of single IB
697 * device. Currently it has no support under Windows.
700 * Pointer to mlx5_dev_ctx_shared object.
703 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
706 DRV_LOG(WARNING, "%s: is not supported", __func__);
710 * This function should share events between multiple ports of single IB
711 * device. Currently it has no support under Windows.
714 * Pointer to mlx5_dev_ctx_shared object.
717 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
720 DRV_LOG(WARNING, "%s: is not supported", __func__);
724 * Read statistics by a named counter.
727 * Pointer to the private device data structure.
728 * @param[in] ctr_name
729 * Pointer to the name of the statistic counter to read
731 * Pointer to read statistic value.
733 * 0 on success and stat is valud, 1 if failed to read the value
738 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
742 RTE_SET_USED(ctr_name);
744 DRV_LOG(WARNING, "%s: is not supported", __func__);
749 * Flush device MAC addresses
750 * Currently it has no support under Windows.
753 * Pointer to Ethernet device structure.
757 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev)
760 DRV_LOG(WARNING, "%s: is not supported", __func__);
764 * Remove a MAC address from device
765 * Currently it has no support under Windows.
768 * Pointer to Ethernet device structure.
773 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
777 DRV_LOG(WARNING, "%s: is not supported", __func__);
781 * Adds a MAC address to the device
782 * Currently it has no support under Windows.
785 * Pointer to Ethernet device structure.
787 * MAC address to register.
792 * 0 on success, a negative errno value otherwise
795 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
799 struct rte_ether_addr lmac;
801 if (mlx5_get_mac(dev, &lmac.addr_bytes)) {
803 "port %u cannot get MAC address, is mlx5_en"
804 " loaded? (errno: %s)",
805 dev->data->port_id, strerror(rte_errno));
808 if (!rte_is_same_ether_addr(&lmac, mac)) {
810 "adding new mac address to device is unsupported");
817 * Modify a VF MAC address
818 * Currently it has no support under Windows.
821 * Pointer to device private data.
823 * MAC address to modify into.
825 * Net device interface index
830 * 0 on success, a negative errno value otherwise
833 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv,
834 unsigned int iface_idx,
835 struct rte_ether_addr *mac_addr,
842 DRV_LOG(WARNING, "%s: is not supported", __func__);
847 * Set device promiscuous mode
848 * Currently it has no support under Windows.
851 * Pointer to Ethernet device structure.
853 * 0 - promiscuous is disabled, otherwise - enabled
856 * 0 on success, a negative error value otherwise
859 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable)
863 DRV_LOG(WARNING, "%s: is not supported", __func__);
868 * Set device allmulti mode
871 * Pointer to Ethernet device structure.
873 * 0 - all multicase is disabled, otherwise - enabled
876 * 0 on success, a negative error value otherwise
879 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)
883 DRV_LOG(WARNING, "%s: is not supported", __func__);
888 * DPDK callback to register a PCI device.
890 * This function spawns Ethernet devices out of a given device.
893 * Pointer to the common device.
896 * 0 on success, a negative errno value otherwise and rte_errno is set.
899 mlx5_os_net_probe(struct mlx5_common_device *cdev)
901 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);
902 struct mlx5_dev_spawn_data spawn = {
906 .phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx),
909 .ifindex = -1, /* Spawn will assign */
910 .info = (struct mlx5_switch_info){
911 .name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK,
914 struct mlx5_dev_config dev_config = {
916 .txq_inline_max = MLX5_ARG_UNSET,
917 .txq_inline_min = MLX5_ARG_UNSET,
918 .txq_inline_mpw = MLX5_ARG_UNSET,
919 .txqs_inline = MLX5_ARG_UNSET,
921 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
922 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
925 .log_hp_size = MLX5_ARG_UNSET,
930 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
931 DRV_LOG(ERR, "Secondary process is not supported on Windows.");
934 ret = mlx5_init_once();
936 DRV_LOG(ERR, "unable to init PMD global data: %s",
937 strerror(rte_errno));
940 /* Device specific configuration. */
941 switch (pci_dev->id.device_id) {
942 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
943 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
944 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
945 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
946 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
947 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
948 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF:
955 spawn.eth_dev = mlx5_dev_spawn(cdev->dev, &spawn, &dev_config);
958 restore = spawn.eth_dev->data->dev_flags;
959 rte_eth_copy_pci_info(spawn.eth_dev, pci_dev);
960 /* Restore non-PCI flags cleared by the above call. */
961 spawn.eth_dev->data->dev_flags |= restore;
962 rte_eth_dev_probing_finish(spawn.eth_dev);
967 * Set the reg_mr and dereg_mr call backs
969 * @param reg_mr_cb[out]
970 * Pointer to reg_mr func
971 * @param dereg_mr_cb[out]
972 * Pointer to dereg_mr func
976 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
977 mlx5_dereg_mr_t *dereg_mr_cb)
979 *reg_mr_cb = mlx5_os_reg_mr;
980 *dereg_mr_cb = mlx5_os_dereg_mr;
983 const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0};