4 * Copyright(c) 2015 EZchip Semiconductor Ltd. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of EZchip Semiconductor nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <rte_eal_memconfig.h>
38 #include <rte_ethdev.h>
39 #include <rte_malloc.h>
40 #include <rte_cycles.h>
42 #include <arch/mpipe_xaui_def.h>
43 #include <arch/mpipe_gbe_def.h>
45 #include <gxio/mpipe.h>
47 #ifdef RTE_LIBRTE_MPIPE_PMD_DEBUG
48 #define PMD_DEBUG_RX(...) RTE_LOG(DEBUG, PMD, __VA_ARGS__)
49 #define PMD_DEBUG_TX(...) RTE_LOG(DEBUG, PMD, __VA_ARGS__)
51 #define PMD_DEBUG_RX(...)
52 #define PMD_DEBUG_TX(...)
55 #define MPIPE_MAX_CHANNELS 128
56 #define MPIPE_TX_MAX_QUEUES 128
57 #define MPIPE_RX_MAX_QUEUES 16
58 #define MPIPE_TX_DESCS 512
59 #define MPIPE_RX_BUCKETS 256
60 #define MPIPE_RX_STACK_SIZE 65536
61 #define MPIPE_RX_IP_ALIGN 2
62 #define MPIPE_BSM_ALIGN 128
64 #define MPIPE_LINK_UPDATE_TIMEOUT 10 /* s */
65 #define MPIPE_LINK_UPDATE_INTERVAL 100000 /* us */
67 struct mpipe_channel_config {
72 gxio_mpipe_rules_stacks_t stacks;
75 struct mpipe_context {
77 gxio_mpipe_context_t context;
78 struct mpipe_channel_config channels[MPIPE_MAX_CHANNELS];
81 static struct mpipe_context mpipe_contexts[GXIO_MPIPE_INSTANCE_MAX];
82 static int mpipe_instances;
83 static const char *drivername = "MPIPE PMD";
85 /* Per queue statistics. */
86 struct mpipe_queue_stats {
87 uint64_t packets, bytes, errors, nomem;
90 /* Common tx/rx queue fields. */
92 struct mpipe_dev_priv *priv; /* "priv" data of its device. */
93 uint16_t nb_desc; /* Number of tx descriptors. */
94 uint16_t port_id; /* Device index. */
95 uint16_t stat_idx; /* Queue stats index. */
96 uint8_t queue_idx; /* Queue index. */
97 uint8_t link_status; /* 0 = link down. */
98 struct mpipe_queue_stats stats; /* Stat data for the queue. */
101 /* Transmit queue description. */
102 struct mpipe_tx_queue {
103 struct mpipe_queue q; /* Common stuff. */
106 /* Receive queue description. */
107 struct mpipe_rx_queue {
108 struct mpipe_queue q; /* Common stuff. */
109 gxio_mpipe_iqueue_t iqueue; /* mPIPE iqueue. */
110 gxio_mpipe_idesc_t *next_desc; /* Next idesc to process. */
111 int avail_descs; /* Number of available descs. */
112 void *rx_ring_mem; /* DMA ring memory. */
115 struct mpipe_dev_priv {
116 gxio_mpipe_context_t *context; /* mPIPE context. */
117 gxio_mpipe_link_t link; /* mPIPE link for the device. */
118 gxio_mpipe_equeue_t equeue; /* mPIPE equeue. */
119 unsigned equeue_size; /* mPIPE equeue desc count. */
120 int instance; /* mPIPE instance. */
121 int ering; /* mPIPE eDMA ring. */
122 int stack; /* mPIPE buffer stack. */
123 int channel; /* Device channel. */
124 int port_id; /* DPDK port index. */
125 struct rte_eth_dev *eth_dev; /* DPDK device. */
126 struct rte_pci_device pci_dev; /* PCI device data. */
127 struct rte_mbuf **tx_comps; /* TX completion array. */
128 struct rte_mempool *rx_mpool; /* mpool used by the rx queues. */
129 unsigned rx_offset; /* Receive head room. */
130 unsigned rx_size_code; /* mPIPE rx buffer size code. */
131 unsigned rx_buffers; /* receive buffers on stack. */
132 int is_xaui:1, /* Is this an xgbe or gbe? */
133 initialized:1, /* Initialized port? */
134 running:1; /* Running port? */
135 struct ether_addr mac_addr; /* MAC address. */
136 unsigned nb_rx_queues; /* Configured tx queues. */
137 unsigned nb_tx_queues; /* Configured rx queues. */
138 int first_bucket; /* mPIPE bucket start index. */
139 int first_ring; /* mPIPE notif ring start index. */
140 int notif_group; /* mPIPE notif group. */
141 rte_atomic32_t dp_count; /* Active datapath thread count. */
142 int tx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];
143 int rx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];
146 #define mpipe_priv(dev) \
147 ((struct mpipe_dev_priv*)(dev)->data->dev_private)
149 #define mpipe_name(priv) \
150 ((priv)->eth_dev->data->name)
152 #define mpipe_rx_queue(priv, n) \
153 ((struct mpipe_rx_queue *)(priv)->eth_dev->data->rx_queues[n])
155 #define mpipe_tx_queue(priv, n) \
156 ((struct mpipe_tx_queue *)(priv)->eth_dev->data->tx_queues[n])
159 mpipe_xmit_flush(struct mpipe_dev_priv *priv);
162 mpipe_recv_flush(struct mpipe_dev_priv *priv);
164 static int mpipe_equeue_sizes[] = {
165 [GXIO_MPIPE_EQUEUE_ENTRY_512] = 512,
166 [GXIO_MPIPE_EQUEUE_ENTRY_2K] = 2048,
167 [GXIO_MPIPE_EQUEUE_ENTRY_8K] = 8192,
168 [GXIO_MPIPE_EQUEUE_ENTRY_64K] = 65536,
171 static int mpipe_iqueue_sizes[] = {
172 [GXIO_MPIPE_IQUEUE_ENTRY_128] = 128,
173 [GXIO_MPIPE_IQUEUE_ENTRY_512] = 512,
174 [GXIO_MPIPE_IQUEUE_ENTRY_2K] = 2048,
175 [GXIO_MPIPE_IQUEUE_ENTRY_64K] = 65536,
178 static int mpipe_buffer_sizes[] = {
179 [GXIO_MPIPE_BUFFER_SIZE_128] = 128,
180 [GXIO_MPIPE_BUFFER_SIZE_256] = 256,
181 [GXIO_MPIPE_BUFFER_SIZE_512] = 512,
182 [GXIO_MPIPE_BUFFER_SIZE_1024] = 1024,
183 [GXIO_MPIPE_BUFFER_SIZE_1664] = 1664,
184 [GXIO_MPIPE_BUFFER_SIZE_4096] = 4096,
185 [GXIO_MPIPE_BUFFER_SIZE_10368] = 10368,
186 [GXIO_MPIPE_BUFFER_SIZE_16384] = 16384,
189 static gxio_mpipe_context_t *
190 mpipe_context(int instance)
192 if (instance < 0 || instance >= mpipe_instances)
194 return &mpipe_contexts[instance].context;
197 static int mpipe_channel_config(int instance, int channel,
198 struct mpipe_channel_config *config)
200 struct mpipe_channel_config *data;
201 struct mpipe_context *context;
202 gxio_mpipe_rules_t rules;
205 if (instance < 0 || instance >= mpipe_instances ||
206 channel < 0 || channel >= MPIPE_MAX_CHANNELS)
209 context = &mpipe_contexts[instance];
211 rte_spinlock_lock(&context->lock);
213 gxio_mpipe_rules_init(&rules, &context->context);
215 for (idx = 0; idx < MPIPE_MAX_CHANNELS; idx++) {
216 data = (channel == idx) ? config : &context->channels[idx];
221 rc = gxio_mpipe_rules_begin(&rules, data->first_bucket,
222 data->num_buckets, &data->stacks);
227 rc = gxio_mpipe_rules_add_channel(&rules, idx);
232 rc = gxio_mpipe_rules_set_headroom(&rules, data->head_room);
238 rc = gxio_mpipe_rules_commit(&rules);
240 memcpy(&context->channels[channel], config, sizeof(*config));
244 rte_spinlock_unlock(&context->lock);
250 mpipe_get_size_index(int *array, int count, int size,
255 for (i = 0; i < count && array[i] < size; i++) {
261 return i < count ? (int)i : -ENOENT;
263 return last >= 0 ? last : -ENOENT;
267 mpipe_calc_size(int *array, int count, int size)
269 int index = mpipe_get_size_index(array, count, size, 1);
270 return index < 0 ? index : array[index];
273 static int mpipe_equeue_size(int size)
276 result = mpipe_calc_size(mpipe_equeue_sizes,
277 RTE_DIM(mpipe_equeue_sizes), size);
281 static int mpipe_iqueue_size(int size)
284 result = mpipe_calc_size(mpipe_iqueue_sizes,
285 RTE_DIM(mpipe_iqueue_sizes), size);
289 static int mpipe_buffer_size_index(int size)
292 result = mpipe_get_size_index(mpipe_buffer_sizes,
293 RTE_DIM(mpipe_buffer_sizes), size, 0);
298 mpipe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
299 struct rte_eth_link *link)
301 struct rte_eth_link *dst = link;
302 struct rte_eth_link *src = &(dev->data->dev_link);
304 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
305 *(uint64_t *)src) == 0)
312 mpipe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
313 struct rte_eth_link *link)
315 struct rte_eth_link *dst = &(dev->data->dev_link);
316 struct rte_eth_link *src = link;
318 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
319 *(uint64_t *)src) == 0)
326 mpipe_infos_get(struct rte_eth_dev *dev __rte_unused,
327 struct rte_eth_dev_info *dev_info)
329 dev_info->min_rx_bufsize = 128;
330 dev_info->max_rx_pktlen = 1518;
331 dev_info->max_tx_queues = MPIPE_TX_MAX_QUEUES;
332 dev_info->max_rx_queues = MPIPE_RX_MAX_QUEUES;
333 dev_info->max_mac_addrs = 1;
334 dev_info->rx_offload_capa = 0;
335 dev_info->tx_offload_capa = 0;
339 mpipe_configure(struct rte_eth_dev *dev)
341 struct mpipe_dev_priv *priv = mpipe_priv(dev);
343 if (dev->data->nb_tx_queues > MPIPE_TX_MAX_QUEUES) {
344 RTE_LOG(ERR, PMD, "%s: Too many tx queues: %d > %d\n",
345 mpipe_name(priv), dev->data->nb_tx_queues,
346 MPIPE_TX_MAX_QUEUES);
349 priv->nb_tx_queues = dev->data->nb_tx_queues;
351 if (dev->data->nb_rx_queues > MPIPE_RX_MAX_QUEUES) {
352 RTE_LOG(ERR, PMD, "%s: Too many rx queues: %d > %d\n",
353 mpipe_name(priv), dev->data->nb_rx_queues,
354 MPIPE_RX_MAX_QUEUES);
356 priv->nb_rx_queues = dev->data->nb_rx_queues;
362 mpipe_link_compare(struct rte_eth_link *link1,
363 struct rte_eth_link *link2)
365 return ((*(uint64_t *)link1 == *(uint64_t *)link2)
370 mpipe_link_update(struct rte_eth_dev *dev, int wait_to_complete)
372 struct mpipe_dev_priv *priv = mpipe_priv(dev);
373 struct rte_eth_link old, new;
374 int64_t state, speed;
377 memset(&old, 0, sizeof(old));
378 memset(&new, 0, sizeof(new));
379 mpipe_dev_atomic_read_link_status(dev, &old);
381 for (count = 0, rc = 0; count < MPIPE_LINK_UPDATE_TIMEOUT; count++) {
382 if (!priv->initialized)
385 state = gxio_mpipe_link_get_attr(&priv->link,
386 GXIO_MPIPE_LINK_CURRENT_STATE);
390 speed = state & GXIO_MPIPE_LINK_SPEED_MASK;
392 if (speed == GXIO_MPIPE_LINK_1G) {
393 new.link_speed = ETH_LINK_SPEED_1000;
394 new.link_duplex = ETH_LINK_FULL_DUPLEX;
396 } else if (speed == GXIO_MPIPE_LINK_10G) {
397 new.link_speed = ETH_LINK_SPEED_10000;
398 new.link_duplex = ETH_LINK_FULL_DUPLEX;
402 rc = mpipe_link_compare(&old, &new);
403 if (rc == 0 || !wait_to_complete)
406 rte_delay_us(MPIPE_LINK_UPDATE_INTERVAL);
409 mpipe_dev_atomic_write_link_status(dev, &new);
414 mpipe_set_link(struct rte_eth_dev *dev, int up)
416 struct mpipe_dev_priv *priv = mpipe_priv(dev);
419 rc = gxio_mpipe_link_set_attr(&priv->link,
420 GXIO_MPIPE_LINK_DESIRED_STATE,
421 up ? GXIO_MPIPE_LINK_ANYSPEED : 0);
423 RTE_LOG(ERR, PMD, "%s: Failed to set link %s.\n",
424 mpipe_name(priv), up ? "up" : "down");
426 mpipe_link_update(dev, 0);
433 mpipe_set_link_up(struct rte_eth_dev *dev)
435 return mpipe_set_link(dev, 1);
439 mpipe_set_link_down(struct rte_eth_dev *dev)
441 return mpipe_set_link(dev, 0);
445 mpipe_dp_enter(struct mpipe_dev_priv *priv)
447 __insn_mtspr(SPR_DSTREAM_PF, 0);
448 rte_atomic32_inc(&priv->dp_count);
452 mpipe_dp_exit(struct mpipe_dev_priv *priv)
454 rte_atomic32_dec(&priv->dp_count);
458 mpipe_dp_wait(struct mpipe_dev_priv *priv)
460 while (rte_atomic32_read(&priv->dp_count) != 0) {
465 static inline struct rte_mbuf *
466 mpipe_recv_mbuf(struct mpipe_dev_priv *priv, gxio_mpipe_idesc_t *idesc,
469 void *va = gxio_mpipe_idesc_get_va(idesc);
470 uint16_t size = gxio_mpipe_idesc_get_xfer_size(idesc);
471 struct rte_mbuf *mbuf = RTE_PTR_SUB(va, priv->rx_offset);
473 rte_pktmbuf_reset(mbuf);
474 mbuf->data_off = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;
475 mbuf->port = in_port;
476 mbuf->data_len = size;
477 mbuf->pkt_len = size;
478 mbuf->hash.rss = gxio_mpipe_idesc_get_flow_hash(idesc);
480 PMD_DEBUG_RX("%s: RX mbuf %p, buffer %p, buf_addr %p, size %d\n",
481 mpipe_name(priv), mbuf, va, mbuf->buf_addr, size);
487 mpipe_recv_push(struct mpipe_dev_priv *priv, struct rte_mbuf *mbuf)
489 const int offset = RTE_PKTMBUF_HEADROOM + MPIPE_RX_IP_ALIGN;
490 void *buf_addr = RTE_PTR_ADD(mbuf->buf_addr, offset);
492 gxio_mpipe_push_buffer(priv->context, priv->stack, buf_addr);
493 PMD_DEBUG_RX("%s: Pushed mbuf %p, buffer %p into stack %d\n",
494 mpipe_name(priv), mbuf, buf_addr, priv->stack);
498 mpipe_recv_fill_stack(struct mpipe_dev_priv *priv, int count)
500 struct rte_mbuf *mbuf;
503 for (i = 0; i < count; i++) {
504 mbuf = __rte_mbuf_raw_alloc(priv->rx_mpool);
507 mpipe_recv_push(priv, mbuf);
510 priv->rx_buffers += count;
511 PMD_DEBUG_RX("%s: Filled %d/%d buffers\n", mpipe_name(priv), i, count);
515 mpipe_recv_flush_stack(struct mpipe_dev_priv *priv)
517 const int offset = priv->rx_offset & ~RTE_MEMPOOL_ALIGN_MASK;
518 uint8_t in_port = priv->port_id;
519 struct rte_mbuf *mbuf;
523 for (count = 0; count < priv->rx_buffers; count++) {
524 va = gxio_mpipe_pop_buffer(priv->context, priv->stack);
527 mbuf = RTE_PTR_SUB(va, offset);
529 PMD_DEBUG_RX("%s: Flushing mbuf %p, va %p\n",
530 mpipe_name(priv), mbuf, va);
532 mbuf->data_off = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;
535 mbuf->port = in_port;
536 mbuf->packet_type = 0;
540 __rte_mbuf_raw_free(mbuf);
543 PMD_DEBUG_RX("%s: Returned %d/%d buffers\n",
544 mpipe_name(priv), count, priv->rx_buffers);
545 priv->rx_buffers -= count;
549 mpipe_register_segment(struct mpipe_dev_priv *priv, const struct rte_memseg *ms)
551 size_t size = ms->hugepage_sz;
555 for (addr = ms->addr, end = addr + ms->len; addr < end; addr += size) {
556 rc = gxio_mpipe_register_page(priv->context, priv->stack, addr,
563 RTE_LOG(ERR, PMD, "%s: Could not register memseg @%p, %d.\n",
564 mpipe_name(priv), ms->addr, rc);
566 RTE_LOG(DEBUG, PMD, "%s: Registered segment %p - %p\n",
567 mpipe_name(priv), ms->addr,
568 RTE_PTR_ADD(ms->addr, ms->len - 1));
573 mpipe_recv_init(struct mpipe_dev_priv *priv)
575 const struct rte_memseg *seg = rte_eal_get_physmem_layout();
580 if (!priv->rx_mpool) {
581 RTE_LOG(ERR, PMD, "%s: No buffer pool.\n",
586 /* Allocate one NotifRing for each queue. */
587 rc = gxio_mpipe_alloc_notif_rings(priv->context, MPIPE_RX_MAX_QUEUES,
590 RTE_LOG(ERR, PMD, "%s: Failed to allocate notif rings.\n",
594 priv->first_ring = rc;
596 /* Allocate a NotifGroup. */
597 rc = gxio_mpipe_alloc_notif_groups(priv->context, 1, 0, 0);
599 RTE_LOG(ERR, PMD, "%s: Failed to allocate rx group.\n",
603 priv->notif_group = rc;
605 /* Allocate required buckets. */
606 rc = gxio_mpipe_alloc_buckets(priv->context, MPIPE_RX_BUCKETS, 0, 0);
608 RTE_LOG(ERR, PMD, "%s: Failed to allocate buckets.\n",
612 priv->first_bucket = rc;
614 rc = gxio_mpipe_alloc_buffer_stacks(priv->context, 1, 0, 0);
616 RTE_LOG(ERR, PMD, "%s: Failed to allocate buffer stack.\n",
622 while (seg && seg->addr)
623 mpipe_register_segment(priv, seg++);
625 stack_size = gxio_mpipe_calc_buffer_stack_bytes(MPIPE_RX_STACK_SIZE);
626 stack_mem = rte_zmalloc(NULL, stack_size, 65536);
628 RTE_LOG(ERR, PMD, "%s: Failed to allocate buffer memory.\n",
632 RTE_LOG(DEBUG, PMD, "%s: Buffer stack memory %p - %p.\n",
633 mpipe_name(priv), stack_mem,
634 RTE_PTR_ADD(stack_mem, stack_size - 1));
637 rc = gxio_mpipe_init_buffer_stack(priv->context, priv->stack,
638 priv->rx_size_code, stack_mem,
641 RTE_LOG(ERR, PMD, "%s: Failed to initialize buffer stack.\n",
650 mpipe_xmit_init(struct mpipe_dev_priv *priv)
656 /* Allocate eDMA ring. */
657 rc = gxio_mpipe_alloc_edma_rings(priv->context, 1, 0, 0);
659 RTE_LOG(ERR, PMD, "%s: Failed to alloc tx ring.\n",
665 rc = mpipe_equeue_size(MPIPE_TX_DESCS);
667 RTE_LOG(ERR, PMD, "%s: Cannot allocate %d equeue descs.\n",
668 mpipe_name(priv), (int)MPIPE_TX_DESCS);
671 priv->equeue_size = rc;
673 /* Initialize completion array. */
674 ring_size = sizeof(priv->tx_comps[0]) * priv->equeue_size;
675 priv->tx_comps = rte_zmalloc(NULL, ring_size, RTE_CACHE_LINE_SIZE);
676 if (!priv->tx_comps) {
677 RTE_LOG(ERR, PMD, "%s: Failed to allocate egress comps.\n",
682 /* Allocate eDMA ring memory. */
683 ring_size = sizeof(gxio_mpipe_edesc_t) * priv->equeue_size;
684 ring_mem = rte_zmalloc(NULL, ring_size, ring_size);
686 RTE_LOG(ERR, PMD, "%s: Failed to allocate egress descs.\n",
690 RTE_LOG(DEBUG, PMD, "%s: eDMA ring memory %p - %p.\n",
691 mpipe_name(priv), ring_mem,
692 RTE_PTR_ADD(ring_mem, ring_size - 1));
695 /* Initialize eDMA ring. */
696 rc = gxio_mpipe_equeue_init(&priv->equeue, priv->context, priv->ering,
697 priv->channel, ring_mem, ring_size, 0);
699 RTE_LOG(ERR, PMD, "%s: Failed to init equeue\n",
708 mpipe_link_init(struct mpipe_dev_priv *priv)
713 rc = gxio_mpipe_link_open(&priv->link, priv->context,
714 mpipe_name(priv), GXIO_MPIPE_LINK_AUTO_NONE);
716 RTE_LOG(ERR, PMD, "%s: Failed to open link.\n",
721 /* Get the channel index. */
722 rc = gxio_mpipe_link_channel(&priv->link);
724 RTE_LOG(ERR, PMD, "%s: Bad channel\n",
734 mpipe_init(struct mpipe_dev_priv *priv)
738 if (priv->initialized)
741 rc = mpipe_link_init(priv);
743 RTE_LOG(ERR, PMD, "%s: Failed to init link.\n",
748 rc = mpipe_recv_init(priv);
750 RTE_LOG(ERR, PMD, "%s: Failed to init rx.\n",
755 rc = mpipe_xmit_init(priv);
757 RTE_LOG(ERR, PMD, "%s: Failed to init tx.\n",
763 priv->initialized = 1;
769 mpipe_start(struct rte_eth_dev *dev)
771 struct mpipe_dev_priv *priv = mpipe_priv(dev);
772 struct mpipe_channel_config config;
773 struct mpipe_rx_queue *rx_queue;
774 struct rte_eth_link eth_link;
775 unsigned queue, buffers = 0;
780 memset(ð_link, 0, sizeof(eth_link));
781 mpipe_dev_atomic_write_link_status(dev, ð_link);
783 rc = mpipe_init(priv);
787 /* Initialize NotifRings. */
788 for (queue = 0; queue < priv->nb_rx_queues; queue++) {
789 rx_queue = mpipe_rx_queue(priv, queue);
790 ring_size = rx_queue->q.nb_desc * sizeof(gxio_mpipe_idesc_t);
792 ring_mem = rte_malloc(NULL, ring_size, ring_size);
794 RTE_LOG(ERR, PMD, "%s: Failed to alloc rx descs.\n",
798 RTE_LOG(DEBUG, PMD, "%s: iDMA ring %d memory %p - %p.\n",
799 mpipe_name(priv), queue, ring_mem,
800 RTE_PTR_ADD(ring_mem, ring_size - 1));
803 rc = gxio_mpipe_iqueue_init(&rx_queue->iqueue, priv->context,
804 priv->first_ring + queue, ring_mem,
807 RTE_LOG(ERR, PMD, "%s: Failed to init rx queue.\n",
812 rx_queue->rx_ring_mem = ring_mem;
813 buffers += rx_queue->q.nb_desc;
816 /* Initialize ingress NotifGroup and buckets. */
817 rc = gxio_mpipe_init_notif_group_and_buckets(priv->context,
818 priv->notif_group, priv->first_ring, priv->nb_rx_queues,
819 priv->first_bucket, MPIPE_RX_BUCKETS,
820 GXIO_MPIPE_BUCKET_STATIC_FLOW_AFFINITY);
822 RTE_LOG(ERR, PMD, "%s: Failed to init group and buckets.\n",
827 /* Configure the classifier to deliver packets from this port. */
829 config.first_bucket = priv->first_bucket;
830 config.num_buckets = MPIPE_RX_BUCKETS;
831 memset(&config.stacks, 0xff, sizeof(config.stacks));
832 config.stacks.stacks[priv->rx_size_code] = priv->stack;
833 config.head_room = priv->rx_offset & RTE_MEMPOOL_ALIGN_MASK;
835 rc = mpipe_channel_config(priv->instance, priv->channel,
838 RTE_LOG(ERR, PMD, "%s: Failed to setup classifier.\n",
843 /* Fill empty buffers into the buffer stack. */
844 mpipe_recv_fill_stack(priv, buffers);
846 /* Bring up the link. */
847 mpipe_set_link_up(dev);
849 /* Start xmit/recv on queues. */
850 for (queue = 0; queue < priv->nb_tx_queues; queue++)
851 mpipe_tx_queue(priv, queue)->q.link_status = 1;
852 for (queue = 0; queue < priv->nb_rx_queues; queue++)
853 mpipe_rx_queue(priv, queue)->q.link_status = 1;
860 mpipe_stop(struct rte_eth_dev *dev)
862 struct mpipe_dev_priv *priv = mpipe_priv(dev);
863 struct mpipe_channel_config config;
867 for (queue = 0; queue < priv->nb_tx_queues; queue++)
868 mpipe_tx_queue(priv, queue)->q.link_status = 0;
869 for (queue = 0; queue < priv->nb_rx_queues; queue++)
870 mpipe_rx_queue(priv, queue)->q.link_status = 0;
872 /* Make sure the link_status writes land. */
876 * Wait for link_status change to register with straggling datapath
881 /* Bring down the link. */
882 mpipe_set_link_down(dev);
884 /* Remove classifier rules. */
885 memset(&config, 0, sizeof(config));
886 rc = mpipe_channel_config(priv->instance, priv->channel,
889 RTE_LOG(ERR, PMD, "%s: Failed to stop classifier.\n",
893 /* Flush completed xmit packets. */
894 mpipe_xmit_flush(priv);
896 /* Flush buffer stacks. */
897 mpipe_recv_flush(priv);
903 mpipe_close(struct rte_eth_dev *dev)
905 struct mpipe_dev_priv *priv = mpipe_priv(dev);
911 mpipe_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
913 struct mpipe_dev_priv *priv = mpipe_priv(dev);
914 struct mpipe_tx_queue *tx_queue;
915 struct mpipe_rx_queue *rx_queue;
919 memset(stats, 0, sizeof(*stats));
921 for (i = 0; i < priv->nb_tx_queues; i++) {
922 tx_queue = mpipe_tx_queue(priv, i);
924 stats->opackets += tx_queue->q.stats.packets;
925 stats->obytes += tx_queue->q.stats.bytes;
926 stats->oerrors += tx_queue->q.stats.errors;
928 idx = tx_queue->q.stat_idx;
929 if (idx != (uint16_t)-1) {
930 stats->q_opackets[idx] += tx_queue->q.stats.packets;
931 stats->q_obytes[idx] += tx_queue->q.stats.bytes;
932 stats->q_errors[idx] += tx_queue->q.stats.errors;
936 for (i = 0; i < priv->nb_rx_queues; i++) {
937 rx_queue = mpipe_rx_queue(priv, i);
939 stats->ipackets += rx_queue->q.stats.packets;
940 stats->ibytes += rx_queue->q.stats.bytes;
941 stats->ierrors += rx_queue->q.stats.errors;
942 stats->rx_nombuf += rx_queue->q.stats.nomem;
944 idx = rx_queue->q.stat_idx;
945 if (idx != (uint16_t)-1) {
946 stats->q_ipackets[idx] += rx_queue->q.stats.packets;
947 stats->q_ibytes[idx] += rx_queue->q.stats.bytes;
948 stats->q_errors[idx] += rx_queue->q.stats.errors;
954 mpipe_stats_reset(struct rte_eth_dev *dev)
956 struct mpipe_dev_priv *priv = mpipe_priv(dev);
957 struct mpipe_tx_queue *tx_queue;
958 struct mpipe_rx_queue *rx_queue;
961 for (i = 0; i < priv->nb_tx_queues; i++) {
962 tx_queue = mpipe_tx_queue(priv, i);
963 memset(&tx_queue->q.stats, 0, sizeof(tx_queue->q.stats));
966 for (i = 0; i < priv->nb_rx_queues; i++) {
967 rx_queue = mpipe_rx_queue(priv, i);
968 memset(&rx_queue->q.stats, 0, sizeof(rx_queue->q.stats));
973 mpipe_queue_stats_mapping_set(struct rte_eth_dev *dev, uint16_t queue_id,
974 uint8_t stat_idx, uint8_t is_rx)
976 struct mpipe_dev_priv *priv = mpipe_priv(dev);
979 priv->rx_stat_mapping[stat_idx] = queue_id;
981 priv->tx_stat_mapping[stat_idx] = queue_id;
988 mpipe_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
989 uint16_t nb_desc, unsigned int socket_id __rte_unused,
990 const struct rte_eth_txconf *tx_conf __rte_unused)
992 struct mpipe_tx_queue *tx_queue = dev->data->tx_queues[queue_idx];
993 struct mpipe_dev_priv *priv = mpipe_priv(dev);
996 tx_queue = rte_realloc(tx_queue, sizeof(*tx_queue),
997 RTE_CACHE_LINE_SIZE);
999 RTE_LOG(ERR, PMD, "%s: Failed to allocate TX queue.\n",
1004 memset(&tx_queue->q, 0, sizeof(tx_queue->q));
1005 tx_queue->q.priv = priv;
1006 tx_queue->q.queue_idx = queue_idx;
1007 tx_queue->q.port_id = dev->data->port_id;
1008 tx_queue->q.nb_desc = nb_desc;
1010 tx_queue->q.stat_idx = -1;
1011 for (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {
1012 if (priv->tx_stat_mapping[idx] == queue_idx)
1013 tx_queue->q.stat_idx = idx;
1016 dev->data->tx_queues[queue_idx] = tx_queue;
1022 mpipe_tx_queue_release(void *_txq)
1028 mpipe_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1029 uint16_t nb_desc, unsigned int socket_id __rte_unused,
1030 const struct rte_eth_rxconf *rx_conf __rte_unused,
1031 struct rte_mempool *mp)
1033 struct mpipe_rx_queue *rx_queue = dev->data->rx_queues[queue_idx];
1034 struct mpipe_dev_priv *priv = mpipe_priv(dev);
1038 rc = mpipe_iqueue_size(nb_desc);
1040 RTE_LOG(ERR, PMD, "%s: Cannot allocate %d iqueue descs.\n",
1041 mpipe_name(priv), (int)nb_desc);
1045 if (rc != nb_desc) {
1046 RTE_LOG(WARNING, PMD, "%s: Extending RX descs from %d to %d.\n",
1047 mpipe_name(priv), (int)nb_desc, rc);
1051 size = sizeof(*rx_queue);
1052 rx_queue = rte_realloc(rx_queue, size, RTE_CACHE_LINE_SIZE);
1054 RTE_LOG(ERR, PMD, "%s: Failed to allocate RX queue.\n",
1059 memset(&rx_queue->q, 0, sizeof(rx_queue->q));
1060 rx_queue->q.priv = priv;
1061 rx_queue->q.nb_desc = nb_desc;
1062 rx_queue->q.port_id = dev->data->port_id;
1063 rx_queue->q.queue_idx = queue_idx;
1065 if (!priv->rx_mpool) {
1066 int size = (rte_pktmbuf_data_room_size(mp) -
1067 RTE_PKTMBUF_HEADROOM -
1070 priv->rx_offset = (sizeof(struct rte_mbuf) +
1071 rte_pktmbuf_priv_size(mp) +
1072 RTE_PKTMBUF_HEADROOM +
1075 RTE_LOG(ERR, PMD, "%s: Bad buffer size %d.\n",
1077 rte_pktmbuf_data_room_size(mp));
1081 priv->rx_size_code = mpipe_buffer_size_index(size);
1082 priv->rx_mpool = mp;
1085 if (priv->rx_mpool != mp) {
1086 RTE_LOG(WARNING, PMD, "%s: Ignoring multiple buffer pools.\n",
1090 rx_queue->q.stat_idx = -1;
1091 for (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {
1092 if (priv->rx_stat_mapping[idx] == queue_idx)
1093 rx_queue->q.stat_idx = idx;
1096 dev->data->rx_queues[queue_idx] = rx_queue;
1102 mpipe_rx_queue_release(void *_rxq)
1107 #define MPIPE_XGBE_ENA_HASH_MULTI \
1108 (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_MULTI_SHIFT)
1109 #define MPIPE_XGBE_ENA_HASH_UNI \
1110 (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_UNI_SHIFT)
1111 #define MPIPE_XGBE_COPY_ALL \
1112 (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__COPY_ALL_SHIFT)
1113 #define MPIPE_GBE_ENA_MULTI_HASH \
1114 (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__MULTI_HASH_ENA_SHIFT)
1115 #define MPIPE_GBE_ENA_UNI_HASH \
1116 (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__UNI_HASH_ENA_SHIFT)
1117 #define MPIPE_GBE_COPY_ALL \
1118 (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__COPY_ALL_SHIFT)
1121 mpipe_promiscuous_enable(struct rte_eth_dev *dev)
1123 struct mpipe_dev_priv *priv = mpipe_priv(dev);
1127 if (priv->is_xaui) {
1128 addr = MPIPE_XAUI_RECEIVE_CONFIGURATION;
1129 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1130 reg &= ~MPIPE_XGBE_ENA_HASH_MULTI;
1131 reg &= ~MPIPE_XGBE_ENA_HASH_UNI;
1132 reg |= MPIPE_XGBE_COPY_ALL;
1133 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1135 addr = MPIPE_GBE_NETWORK_CONFIGURATION;
1136 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1137 reg &= ~MPIPE_GBE_ENA_MULTI_HASH;
1138 reg &= ~MPIPE_GBE_ENA_UNI_HASH;
1139 reg |= MPIPE_GBE_COPY_ALL;
1140 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1145 mpipe_promiscuous_disable(struct rte_eth_dev *dev)
1147 struct mpipe_dev_priv *priv = mpipe_priv(dev);
1151 if (priv->is_xaui) {
1152 addr = MPIPE_XAUI_RECEIVE_CONFIGURATION;
1153 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1154 reg |= MPIPE_XGBE_ENA_HASH_MULTI;
1155 reg |= MPIPE_XGBE_ENA_HASH_UNI;
1156 reg &= ~MPIPE_XGBE_COPY_ALL;
1157 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1159 addr = MPIPE_GBE_NETWORK_CONFIGURATION;
1160 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1161 reg |= MPIPE_GBE_ENA_MULTI_HASH;
1162 reg |= MPIPE_GBE_ENA_UNI_HASH;
1163 reg &= ~MPIPE_GBE_COPY_ALL;
1164 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1168 static struct eth_dev_ops mpipe_dev_ops = {
1169 .dev_infos_get = mpipe_infos_get,
1170 .dev_configure = mpipe_configure,
1171 .dev_start = mpipe_start,
1172 .dev_stop = mpipe_stop,
1173 .dev_close = mpipe_close,
1174 .stats_get = mpipe_stats_get,
1175 .stats_reset = mpipe_stats_reset,
1176 .queue_stats_mapping_set = mpipe_queue_stats_mapping_set,
1177 .tx_queue_setup = mpipe_tx_queue_setup,
1178 .rx_queue_setup = mpipe_rx_queue_setup,
1179 .tx_queue_release = mpipe_tx_queue_release,
1180 .rx_queue_release = mpipe_rx_queue_release,
1181 .link_update = mpipe_link_update,
1182 .dev_set_link_up = mpipe_set_link_up,
1183 .dev_set_link_down = mpipe_set_link_down,
1184 .promiscuous_enable = mpipe_promiscuous_enable,
1185 .promiscuous_disable = mpipe_promiscuous_disable,
1189 mpipe_xmit_null(struct mpipe_dev_priv *priv, int64_t start, int64_t end)
1191 gxio_mpipe_edesc_t null_desc = { { .bound = 1, .ns = 1 } };
1192 gxio_mpipe_equeue_t *equeue = &priv->equeue;
1195 for (slot = start; slot < end; slot++) {
1196 gxio_mpipe_equeue_put_at(equeue, null_desc, slot);
1201 mpipe_xmit_flush(struct mpipe_dev_priv *priv)
1203 gxio_mpipe_equeue_t *equeue = &priv->equeue;
1206 /* Post a dummy descriptor and wait for its return. */
1207 slot = gxio_mpipe_equeue_reserve(equeue, 1);
1209 RTE_LOG(ERR, PMD, "%s: Failed to reserve stop slot.\n",
1214 mpipe_xmit_null(priv, slot, slot + 1);
1216 while (!gxio_mpipe_equeue_is_complete(equeue, slot, 1)) {
1220 for (slot = 0; slot < priv->equeue_size; slot++) {
1221 if (priv->tx_comps[slot])
1222 rte_pktmbuf_free_seg(priv->tx_comps[slot]);
1227 mpipe_recv_flush(struct mpipe_dev_priv *priv)
1229 uint8_t in_port = priv->port_id;
1230 struct mpipe_rx_queue *rx_queue;
1231 gxio_mpipe_iqueue_t *iqueue;
1232 gxio_mpipe_idesc_t idesc;
1233 struct rte_mbuf *mbuf;
1238 mpipe_recv_flush_stack(priv);
1240 /* Flush packets sitting in recv queues. */
1241 for (queue = 0; queue < priv->nb_rx_queues; queue++) {
1242 rx_queue = mpipe_rx_queue(priv, queue);
1243 iqueue = &rx_queue->iqueue;
1244 while (gxio_mpipe_iqueue_try_get(iqueue, &idesc) >= 0) {
1245 mbuf = mpipe_recv_mbuf(priv, &idesc, in_port);
1246 rte_pktmbuf_free(mbuf);
1249 rte_free(rx_queue->rx_ring_mem);
1251 } while (retries++ < 10 && priv->rx_buffers);
1253 if (priv->rx_buffers) {
1254 RTE_LOG(ERR, PMD, "%s: Leaked %d receive buffers.\n",
1255 mpipe_name(priv), priv->rx_buffers);
1257 PMD_DEBUG_RX("%s: Returned all receive buffers.\n",
1262 static inline uint16_t
1263 mpipe_do_xmit(struct mpipe_tx_queue *tx_queue, struct rte_mbuf **tx_pkts,
1266 struct mpipe_dev_priv *priv = tx_queue->q.priv;
1267 gxio_mpipe_equeue_t *equeue = &priv->equeue;
1268 unsigned nb_bytes = 0;
1269 unsigned nb_sent = 0;
1272 PMD_DEBUG_TX("Trying to transmit %d packets on %s:%d.\n",
1273 nb_pkts, mpipe_name(tx_queue->q.priv),
1274 tx_queue->q.queue_idx);
1276 /* Optimistic assumption that we need exactly one slot per packet. */
1277 nb_slots = RTE_MIN(nb_pkts, MPIPE_TX_DESCS / 2);
1280 struct rte_mbuf *mbuf = NULL, *pkt = NULL;
1283 /* Reserve eDMA ring slots. */
1284 slot = gxio_mpipe_equeue_try_reserve_fast(equeue, nb_slots);
1285 if (unlikely(slot < 0)) {
1289 for (i = 0; i < nb_slots; i++) {
1290 unsigned idx = (slot + i) & (priv->equeue_size - 1);
1291 rte_prefetch0(priv->tx_comps[idx]);
1294 /* Fill up slots with descriptor and completion info. */
1295 for (i = 0; i < nb_slots; i++) {
1296 unsigned idx = (slot + i) & (priv->equeue_size - 1);
1297 gxio_mpipe_edesc_t desc;
1298 struct rte_mbuf *next;
1300 /* Starting on a new packet? */
1301 if (likely(!mbuf)) {
1302 int room = nb_slots - i;
1304 pkt = mbuf = tx_pkts[nb_sent];
1306 /* Bail out if we run out of descs. */
1307 if (unlikely(pkt->nb_segs > room))
1313 /* We have a segment to send. */
1316 if (priv->tx_comps[idx])
1317 rte_pktmbuf_free_seg(priv->tx_comps[idx]);
1319 desc = (gxio_mpipe_edesc_t) { {
1320 .va = rte_pktmbuf_mtod(mbuf, uintptr_t),
1321 .xfer_size = rte_pktmbuf_data_len(mbuf),
1322 .bound = next ? 0 : 1,
1325 nb_bytes += mbuf->data_len;
1326 priv->tx_comps[idx] = mbuf;
1327 gxio_mpipe_equeue_put_at(equeue, desc, slot + i);
1329 PMD_DEBUG_TX("%s:%d: Sending packet %p, len %d\n",
1331 tx_queue->q.queue_idx,
1332 rte_pktmbuf_mtod(mbuf, void *),
1333 rte_pktmbuf_data_len(mbuf));
1338 if (unlikely(nb_sent < nb_pkts)) {
1340 /* Fill remaining slots with null descriptors. */
1341 mpipe_xmit_null(priv, slot + i, slot + nb_slots);
1344 * Calculate exact number of descriptors needed for
1345 * the next go around.
1348 for (i = nb_sent; i < nb_pkts; i++) {
1349 nb_slots += tx_pkts[i]->nb_segs;
1352 nb_slots = RTE_MIN(nb_slots, MPIPE_TX_DESCS / 2);
1354 } while (nb_sent < nb_pkts);
1356 tx_queue->q.stats.packets += nb_sent;
1357 tx_queue->q.stats.bytes += nb_bytes;
1362 static inline uint16_t
1363 mpipe_do_recv(struct mpipe_rx_queue *rx_queue, struct rte_mbuf **rx_pkts,
1366 struct mpipe_dev_priv *priv = rx_queue->q.priv;
1367 gxio_mpipe_iqueue_t *iqueue = &rx_queue->iqueue;
1368 gxio_mpipe_idesc_t *first_idesc, *idesc, *last_idesc;
1369 uint8_t in_port = rx_queue->q.port_id;
1370 const unsigned look_ahead = 8;
1371 int room = nb_pkts, rc = 0;
1372 unsigned nb_packets = 0;
1373 unsigned nb_dropped = 0;
1374 unsigned nb_nomem = 0;
1375 unsigned nb_bytes = 0;
1376 unsigned nb_descs, i;
1378 while (room && !rc) {
1379 if (rx_queue->avail_descs < room) {
1380 rc = gxio_mpipe_iqueue_try_peek(iqueue,
1381 &rx_queue->next_desc);
1382 rx_queue->avail_descs = rc < 0 ? 0 : rc;
1385 if (unlikely(!rx_queue->avail_descs)) {
1389 nb_descs = RTE_MIN(room, rx_queue->avail_descs);
1391 first_idesc = rx_queue->next_desc;
1392 last_idesc = first_idesc + nb_descs;
1394 rx_queue->next_desc += nb_descs;
1395 rx_queue->avail_descs -= nb_descs;
1397 for (i = 1; i < look_ahead; i++) {
1398 rte_prefetch0(first_idesc + i);
1401 PMD_DEBUG_RX("%s:%d: Trying to receive %d packets\n",
1402 mpipe_name(rx_queue->q.priv),
1403 rx_queue->q.queue_idx,
1406 for (idesc = first_idesc; idesc < last_idesc; idesc++) {
1407 struct rte_mbuf *mbuf;
1409 PMD_DEBUG_RX("%s:%d: processing idesc %d/%d\n",
1411 rx_queue->q.queue_idx,
1412 nb_packets, nb_descs);
1414 rte_prefetch0(idesc + look_ahead);
1416 PMD_DEBUG_RX("%s:%d: idesc %p, %s%s%s%s%s%s%s%s%s%s"
1417 "size: %d, bkt: %d, chan: %d, ring: %d, sqn: %lu, va: %lu\n",
1419 rx_queue->q.queue_idx,
1421 idesc->me ? "me, " : "",
1422 idesc->tr ? "tr, " : "",
1423 idesc->ce ? "ce, " : "",
1424 idesc->ct ? "ct, " : "",
1425 idesc->cs ? "cs, " : "",
1426 idesc->nr ? "nr, " : "",
1427 idesc->sq ? "sq, " : "",
1428 idesc->ts ? "ts, " : "",
1429 idesc->ps ? "ps, " : "",
1430 idesc->be ? "be, " : "",
1435 (unsigned long)idesc->packet_sqn,
1436 (unsigned long)idesc->va);
1438 if (unlikely(gxio_mpipe_idesc_has_error(idesc))) {
1440 gxio_mpipe_iqueue_drop(iqueue, idesc);
1441 PMD_DEBUG_RX("%s:%d: Descriptor error\n",
1442 mpipe_name(rx_queue->q.priv),
1443 rx_queue->q.queue_idx);
1447 mbuf = __rte_mbuf_raw_alloc(priv->rx_mpool);
1448 if (unlikely(!mbuf)) {
1450 gxio_mpipe_iqueue_drop(iqueue, idesc);
1451 PMD_DEBUG_RX("%s:%d: RX alloc failure\n",
1452 mpipe_name(rx_queue->q.priv),
1453 rx_queue->q.queue_idx);
1457 mpipe_recv_push(priv, mbuf);
1459 /* Get and setup the mbuf for the received packet. */
1460 mbuf = mpipe_recv_mbuf(priv, idesc, in_port);
1462 /* Update results and statistics counters. */
1463 rx_pkts[nb_packets] = mbuf;
1464 nb_bytes += mbuf->pkt_len;
1469 * We release the ring in bursts, but do not track and release
1470 * buckets. This therefore breaks dynamic flow affinity, but
1471 * we always operate in static affinity mode, and so we're OK
1472 * with this optimization.
1474 gxio_mpipe_iqueue_advance(iqueue, nb_descs);
1475 gxio_mpipe_credit(iqueue->context, iqueue->ring, -1, nb_descs);
1478 * Go around once more if we haven't yet peeked the queue, and
1479 * if we have more room to receive.
1481 room = nb_pkts - nb_packets;
1484 rx_queue->q.stats.packets += nb_packets;
1485 rx_queue->q.stats.bytes += nb_bytes;
1486 rx_queue->q.stats.errors += nb_dropped;
1487 rx_queue->q.stats.nomem += nb_nomem;
1489 PMD_DEBUG_RX("%s:%d: RX: %d/%d pkts/bytes, %d/%d drops/nomem\n",
1490 mpipe_name(rx_queue->q.priv), rx_queue->q.queue_idx,
1491 nb_packets, nb_bytes, nb_dropped, nb_nomem);
1497 mpipe_recv_pkts(void *_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1499 struct mpipe_rx_queue *rx_queue = _rxq;
1500 uint16_t result = 0;
1503 mpipe_dp_enter(rx_queue->q.priv);
1504 if (likely(rx_queue->q.link_status))
1505 result = mpipe_do_recv(rx_queue, rx_pkts, nb_pkts);
1506 mpipe_dp_exit(rx_queue->q.priv);
1513 mpipe_xmit_pkts(void *_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1515 struct mpipe_tx_queue *tx_queue = _txq;
1516 uint16_t result = 0;
1519 mpipe_dp_enter(tx_queue->q.priv);
1520 if (likely(tx_queue->q.link_status))
1521 result = mpipe_do_xmit(tx_queue, tx_pkts, nb_pkts);
1522 mpipe_dp_exit(tx_queue->q.priv);
1529 mpipe_link_mac(const char *ifname, uint8_t *mac)
1532 char name[GXIO_MPIPE_LINK_NAME_LEN];
1534 for (idx = 0, rc = 0; !rc; idx++) {
1535 rc = gxio_mpipe_link_enumerate_mac(idx, name, mac);
1536 if (!rc && !strncmp(name, ifname, GXIO_MPIPE_LINK_NAME_LEN))
1543 rte_pmd_mpipe_devinit(const char *ifname,
1544 const char *params __rte_unused)
1546 gxio_mpipe_context_t *context;
1547 struct rte_eth_dev *eth_dev;
1548 struct mpipe_dev_priv *priv;
1552 /* Get the mPIPE instance that the device belongs to. */
1553 instance = gxio_mpipe_link_instance(ifname);
1554 context = mpipe_context(instance);
1556 RTE_LOG(ERR, PMD, "%s: No device for link.\n", ifname);
1560 priv = rte_zmalloc(NULL, sizeof(*priv), 0);
1562 RTE_LOG(ERR, PMD, "%s: Failed to allocate priv.\n", ifname);
1566 memset(&priv->tx_stat_mapping, 0xff, sizeof(priv->tx_stat_mapping));
1567 memset(&priv->rx_stat_mapping, 0xff, sizeof(priv->rx_stat_mapping));
1568 priv->context = context;
1569 priv->instance = instance;
1570 priv->is_xaui = (strncmp(ifname, "xgbe", 4) == 0);
1571 priv->pci_dev.numa_node = instance;
1574 mac = priv->mac_addr.addr_bytes;
1575 rc = mpipe_link_mac(ifname, mac);
1577 RTE_LOG(ERR, PMD, "%s: Failed to enumerate link.\n", ifname);
1582 eth_dev = rte_eth_dev_allocate(ifname, RTE_ETH_DEV_VIRTUAL);
1584 RTE_LOG(ERR, PMD, "%s: Failed to allocate device.\n", ifname);
1589 RTE_LOG(INFO, PMD, "%s: Initialized mpipe device"
1590 "(mac %02x:%02x:%02x:%02x:%02x:%02x).\n",
1591 ifname, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
1593 priv->eth_dev = eth_dev;
1594 priv->port_id = eth_dev->data->port_id;
1595 eth_dev->data->dev_private = priv;
1596 eth_dev->pci_dev = &priv->pci_dev;
1597 eth_dev->data->mac_addrs = &priv->mac_addr;
1599 eth_dev->data->dev_flags = 0;
1600 eth_dev->data->kdrv = RTE_KDRV_NONE;
1601 eth_dev->driver = NULL;
1602 eth_dev->data->drv_name = drivername;
1603 eth_dev->data->numa_node = instance;
1605 eth_dev->dev_ops = &mpipe_dev_ops;
1606 eth_dev->rx_pkt_burst = &mpipe_recv_pkts;
1607 eth_dev->tx_pkt_burst = &mpipe_xmit_pkts;
1612 static struct rte_driver pmd_mpipe_xgbe_drv = {
1615 .init = rte_pmd_mpipe_devinit,
1618 static struct rte_driver pmd_mpipe_gbe_drv = {
1621 .init = rte_pmd_mpipe_devinit,
1624 PMD_REGISTER_DRIVER(pmd_mpipe_xgbe_drv);
1625 PMD_REGISTER_DRIVER(pmd_mpipe_gbe_drv);
1627 static void __attribute__((constructor, used))
1628 mpipe_init_contexts(void)
1630 struct mpipe_context *context;
1633 for (instance = 0; instance < GXIO_MPIPE_INSTANCE_MAX; instance++) {
1634 context = &mpipe_contexts[instance];
1636 rte_spinlock_init(&context->lock);
1637 rc = gxio_mpipe_init(&context->context, instance);
1642 mpipe_instances = instance;