4 * Copyright(c) 2015 EZchip Semiconductor Ltd. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of EZchip Semiconductor nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <rte_eal_memconfig.h>
38 #include <rte_ethdev.h>
39 #include <rte_malloc.h>
40 #include <rte_cycles.h>
42 #include <arch/mpipe_xaui_def.h>
43 #include <arch/mpipe_gbe_def.h>
45 #include <gxio/mpipe.h>
47 #ifdef RTE_LIBRTE_MPIPE_PMD_DEBUG
48 #define PMD_DEBUG_RX(...) RTE_LOG(DEBUG, PMD, __VA_ARGS__)
49 #define PMD_DEBUG_TX(...) RTE_LOG(DEBUG, PMD, __VA_ARGS__)
51 #define PMD_DEBUG_RX(...)
52 #define PMD_DEBUG_TX(...)
55 #define MPIPE_MAX_CHANNELS 128
56 #define MPIPE_TX_MAX_QUEUES 128
57 #define MPIPE_RX_MAX_QUEUES 16
58 #define MPIPE_TX_DESCS 512
59 #define MPIPE_RX_BUCKETS 256
60 #define MPIPE_RX_STACK_SIZE 65536
61 #define MPIPE_RX_IP_ALIGN 2
62 #define MPIPE_BSM_ALIGN 128
64 #define MPIPE_LINK_UPDATE_TIMEOUT 10 /* s */
65 #define MPIPE_LINK_UPDATE_INTERVAL 100000 /* us */
67 struct mpipe_channel_config {
72 gxio_mpipe_rules_stacks_t stacks;
75 struct mpipe_context {
77 gxio_mpipe_context_t context;
78 struct mpipe_channel_config channels[MPIPE_MAX_CHANNELS];
81 /* Per-core local data. */
83 int mbuf_push_debt[RTE_MAX_ETHPORTS]; /* Buffer push debt. */
84 } __rte_cache_aligned;
86 #define MPIPE_BUF_DEBT_THRESHOLD 32
87 static __thread struct mpipe_local mpipe_local;
88 static struct mpipe_context mpipe_contexts[GXIO_MPIPE_INSTANCE_MAX];
89 static int mpipe_instances;
91 /* Per queue statistics. */
92 struct mpipe_queue_stats {
93 uint64_t packets, bytes, errors, nomem;
96 /* Common tx/rx queue fields. */
98 struct mpipe_dev_priv *priv; /* "priv" data of its device. */
99 uint16_t nb_desc; /* Number of tx descriptors. */
100 uint16_t port_id; /* Device index. */
101 uint16_t stat_idx; /* Queue stats index. */
102 uint8_t queue_idx; /* Queue index. */
103 uint8_t link_status; /* 0 = link down. */
104 struct mpipe_queue_stats stats; /* Stat data for the queue. */
107 /* Transmit queue description. */
108 struct mpipe_tx_queue {
109 struct mpipe_queue q; /* Common stuff. */
112 /* Receive queue description. */
113 struct mpipe_rx_queue {
114 struct mpipe_queue q; /* Common stuff. */
115 gxio_mpipe_iqueue_t iqueue; /* mPIPE iqueue. */
116 gxio_mpipe_idesc_t *next_desc; /* Next idesc to process. */
117 int avail_descs; /* Number of available descs. */
118 void *rx_ring_mem; /* DMA ring memory. */
121 struct mpipe_dev_priv {
122 gxio_mpipe_context_t *context; /* mPIPE context. */
123 gxio_mpipe_link_t link; /* mPIPE link for the device. */
124 gxio_mpipe_equeue_t equeue; /* mPIPE equeue. */
125 unsigned equeue_size; /* mPIPE equeue desc count. */
126 int instance; /* mPIPE instance. */
127 int ering; /* mPIPE eDMA ring. */
128 int stack; /* mPIPE buffer stack. */
129 int channel; /* Device channel. */
130 int port_id; /* DPDK port index. */
131 struct rte_eth_dev *eth_dev; /* DPDK device. */
132 struct rte_mbuf **tx_comps; /* TX completion array. */
133 struct rte_mempool *rx_mpool; /* mpool used by the rx queues. */
134 unsigned rx_offset; /* Receive head room. */
135 unsigned rx_size_code; /* mPIPE rx buffer size code. */
136 int is_xaui:1, /* Is this an xgbe or gbe? */
137 initialized:1, /* Initialized port? */
138 running:1; /* Running port? */
139 struct ether_addr mac_addr; /* MAC address. */
140 unsigned nb_rx_queues; /* Configured tx queues. */
141 unsigned nb_tx_queues; /* Configured rx queues. */
142 int first_bucket; /* mPIPE bucket start index. */
143 int first_ring; /* mPIPE notif ring start index. */
144 int notif_group; /* mPIPE notif group. */
145 rte_atomic32_t dp_count __rte_cache_aligned; /* DP Entry count. */
146 int tx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];
147 int rx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];
150 #define mpipe_priv(dev) \
151 ((struct mpipe_dev_priv*)(dev)->data->dev_private)
153 #define mpipe_name(priv) \
154 ((priv)->eth_dev->data->name)
156 #define mpipe_rx_queue(priv, n) \
157 ((struct mpipe_rx_queue *)(priv)->eth_dev->data->rx_queues[n])
159 #define mpipe_tx_queue(priv, n) \
160 ((struct mpipe_tx_queue *)(priv)->eth_dev->data->tx_queues[n])
163 mpipe_xmit_flush(struct mpipe_dev_priv *priv);
166 mpipe_recv_flush(struct mpipe_dev_priv *priv);
168 static int mpipe_equeue_sizes[] = {
169 [GXIO_MPIPE_EQUEUE_ENTRY_512] = 512,
170 [GXIO_MPIPE_EQUEUE_ENTRY_2K] = 2048,
171 [GXIO_MPIPE_EQUEUE_ENTRY_8K] = 8192,
172 [GXIO_MPIPE_EQUEUE_ENTRY_64K] = 65536,
175 static int mpipe_iqueue_sizes[] = {
176 [GXIO_MPIPE_IQUEUE_ENTRY_128] = 128,
177 [GXIO_MPIPE_IQUEUE_ENTRY_512] = 512,
178 [GXIO_MPIPE_IQUEUE_ENTRY_2K] = 2048,
179 [GXIO_MPIPE_IQUEUE_ENTRY_64K] = 65536,
182 static int mpipe_buffer_sizes[] = {
183 [GXIO_MPIPE_BUFFER_SIZE_128] = 128,
184 [GXIO_MPIPE_BUFFER_SIZE_256] = 256,
185 [GXIO_MPIPE_BUFFER_SIZE_512] = 512,
186 [GXIO_MPIPE_BUFFER_SIZE_1024] = 1024,
187 [GXIO_MPIPE_BUFFER_SIZE_1664] = 1664,
188 [GXIO_MPIPE_BUFFER_SIZE_4096] = 4096,
189 [GXIO_MPIPE_BUFFER_SIZE_10368] = 10368,
190 [GXIO_MPIPE_BUFFER_SIZE_16384] = 16384,
193 static gxio_mpipe_context_t *
194 mpipe_context(int instance)
196 if (instance < 0 || instance >= mpipe_instances)
198 return &mpipe_contexts[instance].context;
201 static int mpipe_channel_config(int instance, int channel,
202 struct mpipe_channel_config *config)
204 struct mpipe_channel_config *data;
205 struct mpipe_context *context;
206 gxio_mpipe_rules_t rules;
209 if (instance < 0 || instance >= mpipe_instances ||
210 channel < 0 || channel >= MPIPE_MAX_CHANNELS)
213 context = &mpipe_contexts[instance];
215 rte_spinlock_lock(&context->lock);
217 gxio_mpipe_rules_init(&rules, &context->context);
219 for (idx = 0; idx < MPIPE_MAX_CHANNELS; idx++) {
220 data = (channel == idx) ? config : &context->channels[idx];
225 rc = gxio_mpipe_rules_begin(&rules, data->first_bucket,
226 data->num_buckets, &data->stacks);
231 rc = gxio_mpipe_rules_add_channel(&rules, idx);
236 rc = gxio_mpipe_rules_set_headroom(&rules, data->head_room);
242 rc = gxio_mpipe_rules_commit(&rules);
244 memcpy(&context->channels[channel], config, sizeof(*config));
248 rte_spinlock_unlock(&context->lock);
254 mpipe_get_size_index(int *array, int count, int size,
259 for (i = 0; i < count && array[i] < size; i++) {
265 return i < count ? (int)i : -ENOENT;
267 return last >= 0 ? last : -ENOENT;
271 mpipe_calc_size(int *array, int count, int size)
273 int index = mpipe_get_size_index(array, count, size, 1);
274 return index < 0 ? index : array[index];
277 static int mpipe_equeue_size(int size)
280 result = mpipe_calc_size(mpipe_equeue_sizes,
281 RTE_DIM(mpipe_equeue_sizes), size);
285 static int mpipe_iqueue_size(int size)
288 result = mpipe_calc_size(mpipe_iqueue_sizes,
289 RTE_DIM(mpipe_iqueue_sizes), size);
293 static int mpipe_buffer_size_index(int size)
296 result = mpipe_get_size_index(mpipe_buffer_sizes,
297 RTE_DIM(mpipe_buffer_sizes), size, 0);
302 mpipe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
303 struct rte_eth_link *link)
305 struct rte_eth_link *dst = link;
306 struct rte_eth_link *src = &(dev->data->dev_link);
308 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
309 *(uint64_t *)src) == 0)
316 mpipe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
317 struct rte_eth_link *link)
319 struct rte_eth_link *dst = &(dev->data->dev_link);
320 struct rte_eth_link *src = link;
322 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
323 *(uint64_t *)src) == 0)
330 mpipe_infos_get(struct rte_eth_dev *dev __rte_unused,
331 struct rte_eth_dev_info *dev_info)
333 dev_info->min_rx_bufsize = 128;
334 dev_info->max_rx_pktlen = 1518;
335 dev_info->max_tx_queues = MPIPE_TX_MAX_QUEUES;
336 dev_info->max_rx_queues = MPIPE_RX_MAX_QUEUES;
337 dev_info->max_mac_addrs = 1;
338 dev_info->rx_offload_capa = 0;
339 dev_info->tx_offload_capa = 0;
343 mpipe_configure(struct rte_eth_dev *dev)
345 struct mpipe_dev_priv *priv = mpipe_priv(dev);
347 if (dev->data->nb_tx_queues > MPIPE_TX_MAX_QUEUES) {
348 RTE_LOG(ERR, PMD, "%s: Too many tx queues: %d > %d\n",
349 mpipe_name(priv), dev->data->nb_tx_queues,
350 MPIPE_TX_MAX_QUEUES);
353 priv->nb_tx_queues = dev->data->nb_tx_queues;
355 if (dev->data->nb_rx_queues > MPIPE_RX_MAX_QUEUES) {
356 RTE_LOG(ERR, PMD, "%s: Too many rx queues: %d > %d\n",
357 mpipe_name(priv), dev->data->nb_rx_queues,
358 MPIPE_RX_MAX_QUEUES);
360 priv->nb_rx_queues = dev->data->nb_rx_queues;
366 mpipe_link_compare(struct rte_eth_link *link1,
367 struct rte_eth_link *link2)
369 return (*(uint64_t *)link1 == *(uint64_t *)link2)
374 mpipe_link_update(struct rte_eth_dev *dev, int wait_to_complete)
376 struct mpipe_dev_priv *priv = mpipe_priv(dev);
377 struct rte_eth_link old, new;
378 int64_t state, speed;
381 memset(&old, 0, sizeof(old));
382 memset(&new, 0, sizeof(new));
383 mpipe_dev_atomic_read_link_status(dev, &old);
385 for (count = 0, rc = 0; count < MPIPE_LINK_UPDATE_TIMEOUT; count++) {
386 if (!priv->initialized)
389 state = gxio_mpipe_link_get_attr(&priv->link,
390 GXIO_MPIPE_LINK_CURRENT_STATE);
394 speed = state & GXIO_MPIPE_LINK_SPEED_MASK;
396 new.link_autoneg = (dev->data->dev_conf.link_speeds &
397 ETH_LINK_SPEED_AUTONEG);
398 if (speed == GXIO_MPIPE_LINK_1G) {
399 new.link_speed = ETH_SPEED_NUM_1G;
400 new.link_duplex = ETH_LINK_FULL_DUPLEX;
401 new.link_status = ETH_LINK_UP;
402 } else if (speed == GXIO_MPIPE_LINK_10G) {
403 new.link_speed = ETH_SPEED_NUM_10G;
404 new.link_duplex = ETH_LINK_FULL_DUPLEX;
405 new.link_status = ETH_LINK_UP;
408 rc = mpipe_link_compare(&old, &new);
409 if (rc == 0 || !wait_to_complete)
412 rte_delay_us(MPIPE_LINK_UPDATE_INTERVAL);
415 mpipe_dev_atomic_write_link_status(dev, &new);
420 mpipe_set_link(struct rte_eth_dev *dev, int up)
422 struct mpipe_dev_priv *priv = mpipe_priv(dev);
425 rc = gxio_mpipe_link_set_attr(&priv->link,
426 GXIO_MPIPE_LINK_DESIRED_STATE,
427 up ? GXIO_MPIPE_LINK_ANYSPEED : 0);
429 RTE_LOG(ERR, PMD, "%s: Failed to set link %s.\n",
430 mpipe_name(priv), up ? "up" : "down");
432 mpipe_link_update(dev, 0);
439 mpipe_set_link_up(struct rte_eth_dev *dev)
441 return mpipe_set_link(dev, 1);
445 mpipe_set_link_down(struct rte_eth_dev *dev)
447 return mpipe_set_link(dev, 0);
451 mpipe_dp_enter(struct mpipe_dev_priv *priv)
453 __insn_mtspr(SPR_DSTREAM_PF, 0);
454 rte_atomic32_inc(&priv->dp_count);
458 mpipe_dp_exit(struct mpipe_dev_priv *priv)
460 rte_atomic32_dec(&priv->dp_count);
464 mpipe_dp_wait(struct mpipe_dev_priv *priv)
466 while (rte_atomic32_read(&priv->dp_count) != 0) {
472 mpipe_mbuf_stack_index(struct mpipe_dev_priv *priv, struct rte_mbuf *mbuf)
474 return (mbuf->port < RTE_MAX_ETHPORTS) ?
475 mpipe_priv(&rte_eth_devices[mbuf->port])->stack :
479 static inline struct rte_mbuf *
480 mpipe_recv_mbuf(struct mpipe_dev_priv *priv, gxio_mpipe_idesc_t *idesc,
483 void *va = gxio_mpipe_idesc_get_va(idesc);
484 uint16_t size = gxio_mpipe_idesc_get_xfer_size(idesc);
485 struct rte_mbuf *mbuf = RTE_PTR_SUB(va, priv->rx_offset);
487 rte_pktmbuf_reset(mbuf);
488 mbuf->data_off = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;
489 mbuf->port = in_port;
490 mbuf->data_len = size;
491 mbuf->pkt_len = size;
492 mbuf->hash.rss = gxio_mpipe_idesc_get_flow_hash(idesc);
494 PMD_DEBUG_RX("%s: RX mbuf %p, buffer %p, buf_addr %p, size %d\n",
495 mpipe_name(priv), mbuf, va, mbuf->buf_addr, size);
501 mpipe_recv_push(struct mpipe_dev_priv *priv, struct rte_mbuf *mbuf)
503 const int offset = RTE_PKTMBUF_HEADROOM + MPIPE_RX_IP_ALIGN;
504 void *buf_addr = RTE_PTR_ADD(mbuf->buf_addr, offset);
506 gxio_mpipe_push_buffer(priv->context, priv->stack, buf_addr);
507 PMD_DEBUG_RX("%s: Pushed mbuf %p, buffer %p into stack %d\n",
508 mpipe_name(priv), mbuf, buf_addr, priv->stack);
512 mpipe_recv_fill_stack(struct mpipe_dev_priv *priv, int count)
514 struct rte_mbuf *mbuf;
517 for (i = 0; i < count; i++) {
518 mbuf = rte_mbuf_raw_alloc(priv->rx_mpool);
521 mpipe_recv_push(priv, mbuf);
524 PMD_DEBUG_RX("%s: Filled %d/%d buffers\n", mpipe_name(priv), i, count);
528 mpipe_recv_flush_stack(struct mpipe_dev_priv *priv)
530 const int offset = priv->rx_offset & ~RTE_MEMPOOL_ALIGN_MASK;
531 uint8_t in_port = priv->port_id;
532 struct rte_mbuf *mbuf;
536 va = gxio_mpipe_pop_buffer(priv->context, priv->stack);
539 mbuf = RTE_PTR_SUB(va, offset);
541 PMD_DEBUG_RX("%s: Flushing mbuf %p, va %p\n",
542 mpipe_name(priv), mbuf, va);
544 mbuf->data_off = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;
547 mbuf->port = in_port;
548 mbuf->packet_type = 0;
552 __rte_mbuf_raw_free(mbuf);
557 mpipe_register_segment(struct mpipe_dev_priv *priv, const struct rte_memseg *ms)
559 size_t size = ms->hugepage_sz;
563 for (addr = ms->addr, end = addr + ms->len; addr < end; addr += size) {
564 rc = gxio_mpipe_register_page(priv->context, priv->stack, addr,
571 RTE_LOG(ERR, PMD, "%s: Could not register memseg @%p, %d.\n",
572 mpipe_name(priv), ms->addr, rc);
574 RTE_LOG(DEBUG, PMD, "%s: Registered segment %p - %p\n",
575 mpipe_name(priv), ms->addr,
576 RTE_PTR_ADD(ms->addr, ms->len - 1));
581 mpipe_recv_init(struct mpipe_dev_priv *priv)
583 const struct rte_memseg *seg = rte_eal_get_physmem_layout();
588 if (!priv->rx_mpool) {
589 RTE_LOG(ERR, PMD, "%s: No buffer pool.\n",
594 /* Allocate one NotifRing for each queue. */
595 rc = gxio_mpipe_alloc_notif_rings(priv->context, MPIPE_RX_MAX_QUEUES,
598 RTE_LOG(ERR, PMD, "%s: Failed to allocate notif rings.\n",
602 priv->first_ring = rc;
604 /* Allocate a NotifGroup. */
605 rc = gxio_mpipe_alloc_notif_groups(priv->context, 1, 0, 0);
607 RTE_LOG(ERR, PMD, "%s: Failed to allocate rx group.\n",
611 priv->notif_group = rc;
613 /* Allocate required buckets. */
614 rc = gxio_mpipe_alloc_buckets(priv->context, MPIPE_RX_BUCKETS, 0, 0);
616 RTE_LOG(ERR, PMD, "%s: Failed to allocate buckets.\n",
620 priv->first_bucket = rc;
622 rc = gxio_mpipe_alloc_buffer_stacks(priv->context, 1, 0, 0);
624 RTE_LOG(ERR, PMD, "%s: Failed to allocate buffer stack.\n",
630 while (seg && seg->addr)
631 mpipe_register_segment(priv, seg++);
633 stack_size = gxio_mpipe_calc_buffer_stack_bytes(MPIPE_RX_STACK_SIZE);
634 stack_mem = rte_zmalloc(NULL, stack_size, 65536);
636 RTE_LOG(ERR, PMD, "%s: Failed to allocate buffer memory.\n",
640 RTE_LOG(DEBUG, PMD, "%s: Buffer stack memory %p - %p.\n",
641 mpipe_name(priv), stack_mem,
642 RTE_PTR_ADD(stack_mem, stack_size - 1));
645 rc = gxio_mpipe_init_buffer_stack(priv->context, priv->stack,
646 priv->rx_size_code, stack_mem,
649 RTE_LOG(ERR, PMD, "%s: Failed to initialize buffer stack.\n",
658 mpipe_xmit_init(struct mpipe_dev_priv *priv)
664 /* Allocate eDMA ring. */
665 rc = gxio_mpipe_alloc_edma_rings(priv->context, 1, 0, 0);
667 RTE_LOG(ERR, PMD, "%s: Failed to alloc tx ring.\n",
673 rc = mpipe_equeue_size(MPIPE_TX_DESCS);
675 RTE_LOG(ERR, PMD, "%s: Cannot allocate %d equeue descs.\n",
676 mpipe_name(priv), (int)MPIPE_TX_DESCS);
679 priv->equeue_size = rc;
681 /* Initialize completion array. */
682 ring_size = sizeof(priv->tx_comps[0]) * priv->equeue_size;
683 priv->tx_comps = rte_zmalloc(NULL, ring_size, RTE_CACHE_LINE_SIZE);
684 if (!priv->tx_comps) {
685 RTE_LOG(ERR, PMD, "%s: Failed to allocate egress comps.\n",
690 /* Allocate eDMA ring memory. */
691 ring_size = sizeof(gxio_mpipe_edesc_t) * priv->equeue_size;
692 ring_mem = rte_zmalloc(NULL, ring_size, ring_size);
694 RTE_LOG(ERR, PMD, "%s: Failed to allocate egress descs.\n",
698 RTE_LOG(DEBUG, PMD, "%s: eDMA ring memory %p - %p.\n",
699 mpipe_name(priv), ring_mem,
700 RTE_PTR_ADD(ring_mem, ring_size - 1));
703 /* Initialize eDMA ring. */
704 rc = gxio_mpipe_equeue_init(&priv->equeue, priv->context, priv->ering,
705 priv->channel, ring_mem, ring_size, 0);
707 RTE_LOG(ERR, PMD, "%s: Failed to init equeue\n",
716 mpipe_link_init(struct mpipe_dev_priv *priv)
721 rc = gxio_mpipe_link_open(&priv->link, priv->context,
722 mpipe_name(priv), GXIO_MPIPE_LINK_AUTO_NONE);
724 RTE_LOG(ERR, PMD, "%s: Failed to open link.\n",
729 /* Get the channel index. */
730 rc = gxio_mpipe_link_channel(&priv->link);
732 RTE_LOG(ERR, PMD, "%s: Bad channel\n",
742 mpipe_init(struct mpipe_dev_priv *priv)
746 if (priv->initialized)
749 rc = mpipe_recv_init(priv);
751 RTE_LOG(ERR, PMD, "%s: Failed to init rx.\n",
756 rc = mpipe_xmit_init(priv);
758 RTE_LOG(ERR, PMD, "%s: Failed to init tx.\n",
764 priv->initialized = 1;
770 mpipe_start(struct rte_eth_dev *dev)
772 struct mpipe_dev_priv *priv = mpipe_priv(dev);
773 struct mpipe_channel_config config;
774 struct mpipe_rx_queue *rx_queue;
775 struct rte_eth_link eth_link;
776 unsigned queue, buffers = 0;
781 memset(ð_link, 0, sizeof(eth_link));
782 mpipe_dev_atomic_write_link_status(dev, ð_link);
784 rc = mpipe_init(priv);
788 /* Initialize NotifRings. */
789 for (queue = 0; queue < priv->nb_rx_queues; queue++) {
790 rx_queue = mpipe_rx_queue(priv, queue);
791 ring_size = rx_queue->q.nb_desc * sizeof(gxio_mpipe_idesc_t);
793 ring_mem = rte_malloc(NULL, ring_size, ring_size);
795 RTE_LOG(ERR, PMD, "%s: Failed to alloc rx descs.\n",
799 RTE_LOG(DEBUG, PMD, "%s: iDMA ring %d memory %p - %p.\n",
800 mpipe_name(priv), queue, ring_mem,
801 RTE_PTR_ADD(ring_mem, ring_size - 1));
804 rc = gxio_mpipe_iqueue_init(&rx_queue->iqueue, priv->context,
805 priv->first_ring + queue, ring_mem,
808 RTE_LOG(ERR, PMD, "%s: Failed to init rx queue.\n",
813 rx_queue->rx_ring_mem = ring_mem;
814 buffers += rx_queue->q.nb_desc;
817 /* Initialize ingress NotifGroup and buckets. */
818 rc = gxio_mpipe_init_notif_group_and_buckets(priv->context,
819 priv->notif_group, priv->first_ring, priv->nb_rx_queues,
820 priv->first_bucket, MPIPE_RX_BUCKETS,
821 GXIO_MPIPE_BUCKET_STATIC_FLOW_AFFINITY);
823 RTE_LOG(ERR, PMD, "%s: Failed to init group and buckets.\n",
828 /* Configure the classifier to deliver packets from this port. */
830 config.first_bucket = priv->first_bucket;
831 config.num_buckets = MPIPE_RX_BUCKETS;
832 memset(&config.stacks, 0xff, sizeof(config.stacks));
833 config.stacks.stacks[priv->rx_size_code] = priv->stack;
834 config.head_room = priv->rx_offset & RTE_MEMPOOL_ALIGN_MASK;
836 rc = mpipe_channel_config(priv->instance, priv->channel,
839 RTE_LOG(ERR, PMD, "%s: Failed to setup classifier.\n",
844 /* Fill empty buffers into the buffer stack. */
845 mpipe_recv_fill_stack(priv, buffers);
847 /* Bring up the link. */
848 mpipe_set_link_up(dev);
850 /* Start xmit/recv on queues. */
851 for (queue = 0; queue < priv->nb_tx_queues; queue++)
852 mpipe_tx_queue(priv, queue)->q.link_status = ETH_LINK_UP;
853 for (queue = 0; queue < priv->nb_rx_queues; queue++)
854 mpipe_rx_queue(priv, queue)->q.link_status = ETH_LINK_UP;
861 mpipe_stop(struct rte_eth_dev *dev)
863 struct mpipe_dev_priv *priv = mpipe_priv(dev);
864 struct mpipe_channel_config config;
868 for (queue = 0; queue < priv->nb_tx_queues; queue++)
869 mpipe_tx_queue(priv, queue)->q.link_status = ETH_LINK_DOWN;
870 for (queue = 0; queue < priv->nb_rx_queues; queue++)
871 mpipe_rx_queue(priv, queue)->q.link_status = ETH_LINK_DOWN;
873 /* Make sure the link_status writes land. */
877 * Wait for link_status change to register with straggling datapath
882 /* Bring down the link. */
883 mpipe_set_link_down(dev);
885 /* Remove classifier rules. */
886 memset(&config, 0, sizeof(config));
887 rc = mpipe_channel_config(priv->instance, priv->channel,
890 RTE_LOG(ERR, PMD, "%s: Failed to stop classifier.\n",
894 /* Flush completed xmit packets. */
895 mpipe_xmit_flush(priv);
897 /* Flush buffer stacks. */
898 mpipe_recv_flush(priv);
904 mpipe_close(struct rte_eth_dev *dev)
906 struct mpipe_dev_priv *priv = mpipe_priv(dev);
912 mpipe_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
914 struct mpipe_dev_priv *priv = mpipe_priv(dev);
915 struct mpipe_tx_queue *tx_queue;
916 struct mpipe_rx_queue *rx_queue;
920 memset(stats, 0, sizeof(*stats));
922 for (i = 0; i < priv->nb_tx_queues; i++) {
923 tx_queue = mpipe_tx_queue(priv, i);
925 stats->opackets += tx_queue->q.stats.packets;
926 stats->obytes += tx_queue->q.stats.bytes;
927 stats->oerrors += tx_queue->q.stats.errors;
929 idx = tx_queue->q.stat_idx;
930 if (idx != (uint16_t)-1) {
931 stats->q_opackets[idx] += tx_queue->q.stats.packets;
932 stats->q_obytes[idx] += tx_queue->q.stats.bytes;
933 stats->q_errors[idx] += tx_queue->q.stats.errors;
937 for (i = 0; i < priv->nb_rx_queues; i++) {
938 rx_queue = mpipe_rx_queue(priv, i);
940 stats->ipackets += rx_queue->q.stats.packets;
941 stats->ibytes += rx_queue->q.stats.bytes;
942 stats->ierrors += rx_queue->q.stats.errors;
943 stats->rx_nombuf += rx_queue->q.stats.nomem;
945 idx = rx_queue->q.stat_idx;
946 if (idx != (uint16_t)-1) {
947 stats->q_ipackets[idx] += rx_queue->q.stats.packets;
948 stats->q_ibytes[idx] += rx_queue->q.stats.bytes;
949 stats->q_errors[idx] += rx_queue->q.stats.errors;
955 mpipe_stats_reset(struct rte_eth_dev *dev)
957 struct mpipe_dev_priv *priv = mpipe_priv(dev);
958 struct mpipe_tx_queue *tx_queue;
959 struct mpipe_rx_queue *rx_queue;
962 for (i = 0; i < priv->nb_tx_queues; i++) {
963 tx_queue = mpipe_tx_queue(priv, i);
964 memset(&tx_queue->q.stats, 0, sizeof(tx_queue->q.stats));
967 for (i = 0; i < priv->nb_rx_queues; i++) {
968 rx_queue = mpipe_rx_queue(priv, i);
969 memset(&rx_queue->q.stats, 0, sizeof(rx_queue->q.stats));
974 mpipe_queue_stats_mapping_set(struct rte_eth_dev *dev, uint16_t queue_id,
975 uint8_t stat_idx, uint8_t is_rx)
977 struct mpipe_dev_priv *priv = mpipe_priv(dev);
980 priv->rx_stat_mapping[stat_idx] = queue_id;
982 priv->tx_stat_mapping[stat_idx] = queue_id;
989 mpipe_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
990 uint16_t nb_desc, unsigned int socket_id __rte_unused,
991 const struct rte_eth_txconf *tx_conf __rte_unused)
993 struct mpipe_tx_queue *tx_queue = dev->data->tx_queues[queue_idx];
994 struct mpipe_dev_priv *priv = mpipe_priv(dev);
997 tx_queue = rte_realloc(tx_queue, sizeof(*tx_queue),
998 RTE_CACHE_LINE_SIZE);
1000 RTE_LOG(ERR, PMD, "%s: Failed to allocate TX queue.\n",
1005 memset(&tx_queue->q, 0, sizeof(tx_queue->q));
1006 tx_queue->q.priv = priv;
1007 tx_queue->q.queue_idx = queue_idx;
1008 tx_queue->q.port_id = dev->data->port_id;
1009 tx_queue->q.nb_desc = nb_desc;
1011 tx_queue->q.stat_idx = -1;
1012 for (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {
1013 if (priv->tx_stat_mapping[idx] == queue_idx)
1014 tx_queue->q.stat_idx = idx;
1017 dev->data->tx_queues[queue_idx] = tx_queue;
1023 mpipe_tx_queue_release(void *_txq)
1029 mpipe_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1030 uint16_t nb_desc, unsigned int socket_id __rte_unused,
1031 const struct rte_eth_rxconf *rx_conf __rte_unused,
1032 struct rte_mempool *mp)
1034 struct mpipe_rx_queue *rx_queue = dev->data->rx_queues[queue_idx];
1035 struct mpipe_dev_priv *priv = mpipe_priv(dev);
1039 rc = mpipe_iqueue_size(nb_desc);
1041 RTE_LOG(ERR, PMD, "%s: Cannot allocate %d iqueue descs.\n",
1042 mpipe_name(priv), (int)nb_desc);
1046 if (rc != nb_desc) {
1047 RTE_LOG(WARNING, PMD, "%s: Extending RX descs from %d to %d.\n",
1048 mpipe_name(priv), (int)nb_desc, rc);
1052 size = sizeof(*rx_queue);
1053 rx_queue = rte_realloc(rx_queue, size, RTE_CACHE_LINE_SIZE);
1055 RTE_LOG(ERR, PMD, "%s: Failed to allocate RX queue.\n",
1060 memset(&rx_queue->q, 0, sizeof(rx_queue->q));
1061 rx_queue->q.priv = priv;
1062 rx_queue->q.nb_desc = nb_desc;
1063 rx_queue->q.port_id = dev->data->port_id;
1064 rx_queue->q.queue_idx = queue_idx;
1066 if (!priv->rx_mpool) {
1067 int size = (rte_pktmbuf_data_room_size(mp) -
1068 RTE_PKTMBUF_HEADROOM -
1071 priv->rx_offset = (sizeof(struct rte_mbuf) +
1072 rte_pktmbuf_priv_size(mp) +
1073 RTE_PKTMBUF_HEADROOM +
1076 RTE_LOG(ERR, PMD, "%s: Bad buffer size %d.\n",
1078 rte_pktmbuf_data_room_size(mp));
1082 priv->rx_size_code = mpipe_buffer_size_index(size);
1083 priv->rx_mpool = mp;
1086 if (priv->rx_mpool != mp) {
1087 RTE_LOG(WARNING, PMD, "%s: Ignoring multiple buffer pools.\n",
1091 rx_queue->q.stat_idx = -1;
1092 for (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {
1093 if (priv->rx_stat_mapping[idx] == queue_idx)
1094 rx_queue->q.stat_idx = idx;
1097 dev->data->rx_queues[queue_idx] = rx_queue;
1103 mpipe_rx_queue_release(void *_rxq)
1108 #define MPIPE_XGBE_ENA_HASH_MULTI \
1109 (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_MULTI_SHIFT)
1110 #define MPIPE_XGBE_ENA_HASH_UNI \
1111 (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_UNI_SHIFT)
1112 #define MPIPE_XGBE_COPY_ALL \
1113 (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__COPY_ALL_SHIFT)
1114 #define MPIPE_GBE_ENA_MULTI_HASH \
1115 (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__MULTI_HASH_ENA_SHIFT)
1116 #define MPIPE_GBE_ENA_UNI_HASH \
1117 (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__UNI_HASH_ENA_SHIFT)
1118 #define MPIPE_GBE_COPY_ALL \
1119 (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__COPY_ALL_SHIFT)
1122 mpipe_promiscuous_enable(struct rte_eth_dev *dev)
1124 struct mpipe_dev_priv *priv = mpipe_priv(dev);
1128 if (priv->is_xaui) {
1129 addr = MPIPE_XAUI_RECEIVE_CONFIGURATION;
1130 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1131 reg &= ~MPIPE_XGBE_ENA_HASH_MULTI;
1132 reg &= ~MPIPE_XGBE_ENA_HASH_UNI;
1133 reg |= MPIPE_XGBE_COPY_ALL;
1134 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1136 addr = MPIPE_GBE_NETWORK_CONFIGURATION;
1137 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1138 reg &= ~MPIPE_GBE_ENA_MULTI_HASH;
1139 reg &= ~MPIPE_GBE_ENA_UNI_HASH;
1140 reg |= MPIPE_GBE_COPY_ALL;
1141 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1146 mpipe_promiscuous_disable(struct rte_eth_dev *dev)
1148 struct mpipe_dev_priv *priv = mpipe_priv(dev);
1152 if (priv->is_xaui) {
1153 addr = MPIPE_XAUI_RECEIVE_CONFIGURATION;
1154 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1155 reg |= MPIPE_XGBE_ENA_HASH_MULTI;
1156 reg |= MPIPE_XGBE_ENA_HASH_UNI;
1157 reg &= ~MPIPE_XGBE_COPY_ALL;
1158 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1160 addr = MPIPE_GBE_NETWORK_CONFIGURATION;
1161 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1162 reg |= MPIPE_GBE_ENA_MULTI_HASH;
1163 reg |= MPIPE_GBE_ENA_UNI_HASH;
1164 reg &= ~MPIPE_GBE_COPY_ALL;
1165 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1169 static const struct eth_dev_ops mpipe_dev_ops = {
1170 .dev_infos_get = mpipe_infos_get,
1171 .dev_configure = mpipe_configure,
1172 .dev_start = mpipe_start,
1173 .dev_stop = mpipe_stop,
1174 .dev_close = mpipe_close,
1175 .stats_get = mpipe_stats_get,
1176 .stats_reset = mpipe_stats_reset,
1177 .queue_stats_mapping_set = mpipe_queue_stats_mapping_set,
1178 .tx_queue_setup = mpipe_tx_queue_setup,
1179 .rx_queue_setup = mpipe_rx_queue_setup,
1180 .tx_queue_release = mpipe_tx_queue_release,
1181 .rx_queue_release = mpipe_rx_queue_release,
1182 .link_update = mpipe_link_update,
1183 .dev_set_link_up = mpipe_set_link_up,
1184 .dev_set_link_down = mpipe_set_link_down,
1185 .promiscuous_enable = mpipe_promiscuous_enable,
1186 .promiscuous_disable = mpipe_promiscuous_disable,
1190 mpipe_xmit_null(struct mpipe_dev_priv *priv, int64_t start, int64_t end)
1192 gxio_mpipe_edesc_t null_desc = { { .bound = 1, .ns = 1 } };
1193 gxio_mpipe_equeue_t *equeue = &priv->equeue;
1196 for (slot = start; slot < end; slot++) {
1197 gxio_mpipe_equeue_put_at(equeue, null_desc, slot);
1202 mpipe_xmit_flush(struct mpipe_dev_priv *priv)
1204 gxio_mpipe_equeue_t *equeue = &priv->equeue;
1207 /* Post a dummy descriptor and wait for its return. */
1208 slot = gxio_mpipe_equeue_reserve(equeue, 1);
1210 RTE_LOG(ERR, PMD, "%s: Failed to reserve stop slot.\n",
1215 mpipe_xmit_null(priv, slot, slot + 1);
1217 while (!gxio_mpipe_equeue_is_complete(equeue, slot, 1)) {
1221 for (slot = 0; slot < priv->equeue_size; slot++) {
1222 if (priv->tx_comps[slot])
1223 rte_pktmbuf_free_seg(priv->tx_comps[slot]);
1228 mpipe_recv_flush(struct mpipe_dev_priv *priv)
1230 uint8_t in_port = priv->port_id;
1231 struct mpipe_rx_queue *rx_queue;
1232 gxio_mpipe_iqueue_t *iqueue;
1233 gxio_mpipe_idesc_t idesc;
1234 struct rte_mbuf *mbuf;
1237 /* Release packets on the buffer stack. */
1238 mpipe_recv_flush_stack(priv);
1240 /* Flush packets sitting in recv queues. */
1241 for (queue = 0; queue < priv->nb_rx_queues; queue++) {
1242 rx_queue = mpipe_rx_queue(priv, queue);
1243 iqueue = &rx_queue->iqueue;
1244 while (gxio_mpipe_iqueue_try_get(iqueue, &idesc) >= 0) {
1245 /* Skip idesc with the 'buffer error' bit set. */
1248 mbuf = mpipe_recv_mbuf(priv, &idesc, in_port);
1249 rte_pktmbuf_free(mbuf);
1251 rte_free(rx_queue->rx_ring_mem);
1255 static inline uint16_t
1256 mpipe_do_xmit(struct mpipe_tx_queue *tx_queue, struct rte_mbuf **tx_pkts,
1259 struct mpipe_dev_priv *priv = tx_queue->q.priv;
1260 gxio_mpipe_equeue_t *equeue = &priv->equeue;
1261 unsigned nb_bytes = 0;
1262 unsigned nb_sent = 0;
1266 PMD_DEBUG_TX("Trying to transmit %d packets on %s:%d.\n",
1267 nb_pkts, mpipe_name(tx_queue->q.priv),
1268 tx_queue->q.queue_idx);
1270 /* Optimistic assumption that we need exactly one slot per packet. */
1271 nb_slots = RTE_MIN(nb_pkts, MPIPE_TX_DESCS / 2);
1274 struct rte_mbuf *mbuf = NULL, *pkt = NULL;
1277 /* Reserve eDMA ring slots. */
1278 slot = gxio_mpipe_equeue_try_reserve_fast(equeue, nb_slots);
1279 if (unlikely(slot < 0)) {
1283 for (i = 0; i < nb_slots; i++) {
1284 unsigned idx = (slot + i) & (priv->equeue_size - 1);
1285 rte_prefetch0(priv->tx_comps[idx]);
1288 /* Fill up slots with descriptor and completion info. */
1289 for (i = 0; i < nb_slots; i++) {
1290 unsigned idx = (slot + i) & (priv->equeue_size - 1);
1291 gxio_mpipe_edesc_t desc;
1292 struct rte_mbuf *next;
1294 /* Starting on a new packet? */
1295 if (likely(!mbuf)) {
1296 int room = nb_slots - i;
1298 pkt = mbuf = tx_pkts[nb_sent];
1300 /* Bail out if we run out of descs. */
1301 if (unlikely(pkt->nb_segs > room))
1307 /* We have a segment to send. */
1310 if (priv->tx_comps[idx])
1311 rte_pktmbuf_free_seg(priv->tx_comps[idx]);
1313 port_id = (mbuf->port < RTE_MAX_ETHPORTS) ?
1314 mbuf->port : priv->port_id;
1315 desc = (gxio_mpipe_edesc_t) { {
1316 .va = rte_pktmbuf_mtod(mbuf, uintptr_t),
1317 .xfer_size = rte_pktmbuf_data_len(mbuf),
1318 .bound = next ? 0 : 1,
1319 .stack_idx = mpipe_mbuf_stack_index(priv, mbuf),
1320 .size = priv->rx_size_code,
1322 if (mpipe_local.mbuf_push_debt[port_id] > 0) {
1323 mpipe_local.mbuf_push_debt[port_id]--;
1325 priv->tx_comps[idx] = NULL;
1327 priv->tx_comps[idx] = mbuf;
1329 nb_bytes += mbuf->data_len;
1330 gxio_mpipe_equeue_put_at(equeue, desc, slot + i);
1332 PMD_DEBUG_TX("%s:%d: Sending packet %p, len %d\n",
1334 tx_queue->q.queue_idx,
1335 rte_pktmbuf_mtod(mbuf, void *),
1336 rte_pktmbuf_data_len(mbuf));
1341 if (unlikely(nb_sent < nb_pkts)) {
1343 /* Fill remaining slots with null descriptors. */
1344 mpipe_xmit_null(priv, slot + i, slot + nb_slots);
1347 * Calculate exact number of descriptors needed for
1348 * the next go around.
1351 for (i = nb_sent; i < nb_pkts; i++) {
1352 nb_slots += tx_pkts[i]->nb_segs;
1355 nb_slots = RTE_MIN(nb_slots, MPIPE_TX_DESCS / 2);
1357 } while (nb_sent < nb_pkts);
1359 tx_queue->q.stats.packets += nb_sent;
1360 tx_queue->q.stats.bytes += nb_bytes;
1365 static inline uint16_t
1366 mpipe_do_recv(struct mpipe_rx_queue *rx_queue, struct rte_mbuf **rx_pkts,
1369 struct mpipe_dev_priv *priv = rx_queue->q.priv;
1370 gxio_mpipe_iqueue_t *iqueue = &rx_queue->iqueue;
1371 gxio_mpipe_idesc_t *first_idesc, *idesc, *last_idesc;
1372 uint8_t in_port = rx_queue->q.port_id;
1373 const unsigned look_ahead = 8;
1374 int room = nb_pkts, rc = 0;
1375 unsigned nb_packets = 0;
1376 unsigned nb_dropped = 0;
1377 unsigned nb_nomem = 0;
1378 unsigned nb_bytes = 0;
1379 unsigned nb_descs, i;
1381 while (room && !rc) {
1382 if (rx_queue->avail_descs < room) {
1383 rc = gxio_mpipe_iqueue_try_peek(iqueue,
1384 &rx_queue->next_desc);
1385 rx_queue->avail_descs = rc < 0 ? 0 : rc;
1388 if (unlikely(!rx_queue->avail_descs)) {
1392 nb_descs = RTE_MIN(room, rx_queue->avail_descs);
1394 first_idesc = rx_queue->next_desc;
1395 last_idesc = first_idesc + nb_descs;
1397 rx_queue->next_desc += nb_descs;
1398 rx_queue->avail_descs -= nb_descs;
1400 for (i = 1; i < look_ahead; i++) {
1401 rte_prefetch0(first_idesc + i);
1404 PMD_DEBUG_RX("%s:%d: Trying to receive %d packets\n",
1405 mpipe_name(rx_queue->q.priv),
1406 rx_queue->q.queue_idx,
1409 for (idesc = first_idesc; idesc < last_idesc; idesc++) {
1410 struct rte_mbuf *mbuf;
1412 PMD_DEBUG_RX("%s:%d: processing idesc %d/%d\n",
1414 rx_queue->q.queue_idx,
1415 nb_packets, nb_descs);
1417 rte_prefetch0(idesc + look_ahead);
1419 PMD_DEBUG_RX("%s:%d: idesc %p, %s%s%s%s%s%s%s%s%s%s"
1420 "size: %d, bkt: %d, chan: %d, ring: %d, sqn: %lu, va: %lu\n",
1422 rx_queue->q.queue_idx,
1424 idesc->me ? "me, " : "",
1425 idesc->tr ? "tr, " : "",
1426 idesc->ce ? "ce, " : "",
1427 idesc->ct ? "ct, " : "",
1428 idesc->cs ? "cs, " : "",
1429 idesc->nr ? "nr, " : "",
1430 idesc->sq ? "sq, " : "",
1431 idesc->ts ? "ts, " : "",
1432 idesc->ps ? "ps, " : "",
1433 idesc->be ? "be, " : "",
1438 (unsigned long)idesc->packet_sqn,
1439 (unsigned long)idesc->va);
1441 if (unlikely(gxio_mpipe_idesc_has_error(idesc))) {
1443 gxio_mpipe_iqueue_drop(iqueue, idesc);
1444 PMD_DEBUG_RX("%s:%d: Descriptor error\n",
1445 mpipe_name(rx_queue->q.priv),
1446 rx_queue->q.queue_idx);
1450 if (mpipe_local.mbuf_push_debt[in_port] <
1451 MPIPE_BUF_DEBT_THRESHOLD)
1452 mpipe_local.mbuf_push_debt[in_port]++;
1454 mbuf = rte_mbuf_raw_alloc(priv->rx_mpool);
1455 if (unlikely(!mbuf)) {
1457 gxio_mpipe_iqueue_drop(iqueue, idesc);
1458 PMD_DEBUG_RX("%s:%d: alloc failure\n",
1459 mpipe_name(rx_queue->q.priv),
1460 rx_queue->q.queue_idx);
1464 mpipe_recv_push(priv, mbuf);
1467 /* Get and setup the mbuf for the received packet. */
1468 mbuf = mpipe_recv_mbuf(priv, idesc, in_port);
1470 /* Update results and statistics counters. */
1471 rx_pkts[nb_packets] = mbuf;
1472 nb_bytes += mbuf->pkt_len;
1477 * We release the ring in bursts, but do not track and release
1478 * buckets. This therefore breaks dynamic flow affinity, but
1479 * we always operate in static affinity mode, and so we're OK
1480 * with this optimization.
1482 gxio_mpipe_iqueue_advance(iqueue, nb_descs);
1483 gxio_mpipe_credit(iqueue->context, iqueue->ring, -1, nb_descs);
1486 * Go around once more if we haven't yet peeked the queue, and
1487 * if we have more room to receive.
1489 room = nb_pkts - nb_packets;
1492 rx_queue->q.stats.packets += nb_packets;
1493 rx_queue->q.stats.bytes += nb_bytes;
1494 rx_queue->q.stats.errors += nb_dropped;
1495 rx_queue->q.stats.nomem += nb_nomem;
1497 PMD_DEBUG_RX("%s:%d: RX: %d/%d pkts/bytes, %d/%d drops/nomem\n",
1498 mpipe_name(rx_queue->q.priv), rx_queue->q.queue_idx,
1499 nb_packets, nb_bytes, nb_dropped, nb_nomem);
1505 mpipe_recv_pkts(void *_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1507 struct mpipe_rx_queue *rx_queue = _rxq;
1508 uint16_t result = 0;
1511 mpipe_dp_enter(rx_queue->q.priv);
1512 if (likely(rx_queue->q.link_status))
1513 result = mpipe_do_recv(rx_queue, rx_pkts, nb_pkts);
1514 mpipe_dp_exit(rx_queue->q.priv);
1521 mpipe_xmit_pkts(void *_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1523 struct mpipe_tx_queue *tx_queue = _txq;
1524 uint16_t result = 0;
1527 mpipe_dp_enter(tx_queue->q.priv);
1528 if (likely(tx_queue->q.link_status))
1529 result = mpipe_do_xmit(tx_queue, tx_pkts, nb_pkts);
1530 mpipe_dp_exit(tx_queue->q.priv);
1537 mpipe_link_mac(const char *ifname, uint8_t *mac)
1540 char name[GXIO_MPIPE_LINK_NAME_LEN];
1542 for (idx = 0, rc = 0; !rc; idx++) {
1543 rc = gxio_mpipe_link_enumerate_mac(idx, name, mac);
1544 if (!rc && !strncmp(name, ifname, GXIO_MPIPE_LINK_NAME_LEN))
1551 rte_pmd_mpipe_probe_common(struct rte_vdev_driver *drv, const char *ifname,
1552 const char *params __rte_unused)
1554 gxio_mpipe_context_t *context;
1555 struct rte_eth_dev *eth_dev;
1556 struct mpipe_dev_priv *priv;
1560 /* Get the mPIPE instance that the device belongs to. */
1561 instance = gxio_mpipe_link_instance(ifname);
1562 context = mpipe_context(instance);
1564 RTE_LOG(ERR, PMD, "%s: No device for link.\n", ifname);
1568 priv = rte_zmalloc(NULL, sizeof(*priv), 0);
1570 RTE_LOG(ERR, PMD, "%s: Failed to allocate priv.\n", ifname);
1574 memset(&priv->tx_stat_mapping, 0xff, sizeof(priv->tx_stat_mapping));
1575 memset(&priv->rx_stat_mapping, 0xff, sizeof(priv->rx_stat_mapping));
1576 priv->context = context;
1577 priv->instance = instance;
1578 priv->is_xaui = (strncmp(ifname, "xgbe", 4) == 0);
1581 mac = priv->mac_addr.addr_bytes;
1582 rc = mpipe_link_mac(ifname, mac);
1584 RTE_LOG(ERR, PMD, "%s: Failed to enumerate link.\n", ifname);
1589 eth_dev = rte_eth_dev_allocate(ifname);
1591 RTE_LOG(ERR, PMD, "%s: Failed to allocate device.\n", ifname);
1596 RTE_LOG(INFO, PMD, "%s: Initialized mpipe device"
1597 "(mac %02x:%02x:%02x:%02x:%02x:%02x).\n",
1598 ifname, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
1600 priv->eth_dev = eth_dev;
1601 priv->port_id = eth_dev->data->port_id;
1602 eth_dev->data->dev_private = priv;
1603 eth_dev->data->mac_addrs = &priv->mac_addr;
1605 eth_dev->data->kdrv = RTE_KDRV_NONE;
1606 eth_dev->driver = NULL;
1607 eth_dev->data->drv_name = drv->driver.name;
1608 eth_dev->data->numa_node = instance;
1610 eth_dev->dev_ops = &mpipe_dev_ops;
1611 eth_dev->rx_pkt_burst = &mpipe_recv_pkts;
1612 eth_dev->tx_pkt_burst = &mpipe_xmit_pkts;
1614 rc = mpipe_link_init(priv);
1616 RTE_LOG(ERR, PMD, "%s: Failed to init link.\n",
1625 rte_pmd_mpipe_xgbe_probe(const char *ifname, const char *params __rte_unused)
1627 return rte_pmd_mpipe_probe_common(&pmd_mpipe_xgbe_drv, ifname, params);
1631 rte_pmd_mpipe_gbe_probe(const char *ifname, const char *params __rte_unused)
1633 return rte_pmd_mpipe_probe_common(&pmd_mpipe_gbe_drv, ifname, params);
1636 static struct rte_vdev_driver pmd_mpipe_xgbe_drv = {
1637 .probe = rte_pmd_mpipe_xgbe_probe,
1640 static struct rte_vdev_driver pmd_mpipe_gbe_drv = {
1641 .probe = rte_pmd_mpipe_gbe_probe,
1644 RTE_PMD_REGISTER_VDEV(net_mpipe_xgbe, pmd_mpipe_xgbe_drv);
1645 RTE_PMD_REGISTER_ALIAS(net_mpipe_xgbe, xgbe);
1646 RTE_PMD_REGISTER_VDEV(net_mpipe_gbe, pmd_mpipe_gbe_drv);
1647 RTE_PMD_REGISTER_ALIAS(net_mpipe_gbe, gbe);
1649 static void __attribute__((constructor, used))
1650 mpipe_init_contexts(void)
1652 struct mpipe_context *context;
1655 for (instance = 0; instance < GXIO_MPIPE_INSTANCE_MAX; instance++) {
1656 context = &mpipe_contexts[instance];
1658 rte_spinlock_init(&context->lock);
1659 rc = gxio_mpipe_init(&context->context, instance);
1664 mpipe_instances = instance;