4 * Copyright(c) 2015 EZchip Semiconductor Ltd. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of EZchip Semiconductor nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <rte_eal_memconfig.h>
38 #include <rte_ethdev.h>
39 #include <rte_malloc.h>
40 #include <rte_cycles.h>
42 #include <arch/mpipe_xaui_def.h>
43 #include <arch/mpipe_gbe_def.h>
45 #include <gxio/mpipe.h>
47 #ifdef RTE_LIBRTE_MPIPE_PMD_DEBUG
48 #define PMD_DEBUG_RX(...) RTE_LOG(DEBUG, PMD, __VA_ARGS__)
49 #define PMD_DEBUG_TX(...) RTE_LOG(DEBUG, PMD, __VA_ARGS__)
51 #define PMD_DEBUG_RX(...)
52 #define PMD_DEBUG_TX(...)
55 #define MPIPE_MAX_CHANNELS 128
56 #define MPIPE_TX_MAX_QUEUES 128
57 #define MPIPE_RX_MAX_QUEUES 16
58 #define MPIPE_TX_DESCS 512
59 #define MPIPE_RX_BUCKETS 256
60 #define MPIPE_RX_STACK_SIZE 65536
61 #define MPIPE_RX_IP_ALIGN 2
62 #define MPIPE_BSM_ALIGN 128
64 #define MPIPE_LINK_UPDATE_TIMEOUT 10 /* s */
65 #define MPIPE_LINK_UPDATE_INTERVAL 100000 /* us */
67 struct mpipe_channel_config {
72 gxio_mpipe_rules_stacks_t stacks;
75 struct mpipe_context {
77 gxio_mpipe_context_t context;
78 struct mpipe_channel_config channels[MPIPE_MAX_CHANNELS];
81 /* Per-core local data. */
83 int mbuf_push_debt[RTE_MAX_ETHPORTS]; /* Buffer push debt. */
84 } __rte_cache_aligned;
86 #define MPIPE_BUF_DEBT_THRESHOLD 32
87 static __thread struct mpipe_local mpipe_local;
88 static struct mpipe_context mpipe_contexts[GXIO_MPIPE_INSTANCE_MAX];
89 static int mpipe_instances;
90 static const char *drivername = "MPIPE PMD";
92 /* Per queue statistics. */
93 struct mpipe_queue_stats {
94 uint64_t packets, bytes, errors, nomem;
97 /* Common tx/rx queue fields. */
99 struct mpipe_dev_priv *priv; /* "priv" data of its device. */
100 uint16_t nb_desc; /* Number of tx descriptors. */
101 uint16_t port_id; /* Device index. */
102 uint16_t stat_idx; /* Queue stats index. */
103 uint8_t queue_idx; /* Queue index. */
104 uint8_t link_status; /* 0 = link down. */
105 struct mpipe_queue_stats stats; /* Stat data for the queue. */
108 /* Transmit queue description. */
109 struct mpipe_tx_queue {
110 struct mpipe_queue q; /* Common stuff. */
113 /* Receive queue description. */
114 struct mpipe_rx_queue {
115 struct mpipe_queue q; /* Common stuff. */
116 gxio_mpipe_iqueue_t iqueue; /* mPIPE iqueue. */
117 gxio_mpipe_idesc_t *next_desc; /* Next idesc to process. */
118 int avail_descs; /* Number of available descs. */
119 void *rx_ring_mem; /* DMA ring memory. */
122 struct mpipe_dev_priv {
123 gxio_mpipe_context_t *context; /* mPIPE context. */
124 gxio_mpipe_link_t link; /* mPIPE link for the device. */
125 gxio_mpipe_equeue_t equeue; /* mPIPE equeue. */
126 unsigned equeue_size; /* mPIPE equeue desc count. */
127 int instance; /* mPIPE instance. */
128 int ering; /* mPIPE eDMA ring. */
129 int stack; /* mPIPE buffer stack. */
130 int channel; /* Device channel. */
131 int port_id; /* DPDK port index. */
132 struct rte_eth_dev *eth_dev; /* DPDK device. */
133 struct rte_mbuf **tx_comps; /* TX completion array. */
134 struct rte_mempool *rx_mpool; /* mpool used by the rx queues. */
135 unsigned rx_offset; /* Receive head room. */
136 unsigned rx_size_code; /* mPIPE rx buffer size code. */
137 int is_xaui:1, /* Is this an xgbe or gbe? */
138 initialized:1, /* Initialized port? */
139 running:1; /* Running port? */
140 struct ether_addr mac_addr; /* MAC address. */
141 unsigned nb_rx_queues; /* Configured tx queues. */
142 unsigned nb_tx_queues; /* Configured rx queues. */
143 int first_bucket; /* mPIPE bucket start index. */
144 int first_ring; /* mPIPE notif ring start index. */
145 int notif_group; /* mPIPE notif group. */
146 rte_atomic32_t dp_count __rte_cache_aligned; /* DP Entry count. */
147 int tx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];
148 int rx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];
151 #define mpipe_priv(dev) \
152 ((struct mpipe_dev_priv*)(dev)->data->dev_private)
154 #define mpipe_name(priv) \
155 ((priv)->eth_dev->data->name)
157 #define mpipe_rx_queue(priv, n) \
158 ((struct mpipe_rx_queue *)(priv)->eth_dev->data->rx_queues[n])
160 #define mpipe_tx_queue(priv, n) \
161 ((struct mpipe_tx_queue *)(priv)->eth_dev->data->tx_queues[n])
164 mpipe_xmit_flush(struct mpipe_dev_priv *priv);
167 mpipe_recv_flush(struct mpipe_dev_priv *priv);
169 static int mpipe_equeue_sizes[] = {
170 [GXIO_MPIPE_EQUEUE_ENTRY_512] = 512,
171 [GXIO_MPIPE_EQUEUE_ENTRY_2K] = 2048,
172 [GXIO_MPIPE_EQUEUE_ENTRY_8K] = 8192,
173 [GXIO_MPIPE_EQUEUE_ENTRY_64K] = 65536,
176 static int mpipe_iqueue_sizes[] = {
177 [GXIO_MPIPE_IQUEUE_ENTRY_128] = 128,
178 [GXIO_MPIPE_IQUEUE_ENTRY_512] = 512,
179 [GXIO_MPIPE_IQUEUE_ENTRY_2K] = 2048,
180 [GXIO_MPIPE_IQUEUE_ENTRY_64K] = 65536,
183 static int mpipe_buffer_sizes[] = {
184 [GXIO_MPIPE_BUFFER_SIZE_128] = 128,
185 [GXIO_MPIPE_BUFFER_SIZE_256] = 256,
186 [GXIO_MPIPE_BUFFER_SIZE_512] = 512,
187 [GXIO_MPIPE_BUFFER_SIZE_1024] = 1024,
188 [GXIO_MPIPE_BUFFER_SIZE_1664] = 1664,
189 [GXIO_MPIPE_BUFFER_SIZE_4096] = 4096,
190 [GXIO_MPIPE_BUFFER_SIZE_10368] = 10368,
191 [GXIO_MPIPE_BUFFER_SIZE_16384] = 16384,
194 static gxio_mpipe_context_t *
195 mpipe_context(int instance)
197 if (instance < 0 || instance >= mpipe_instances)
199 return &mpipe_contexts[instance].context;
202 static int mpipe_channel_config(int instance, int channel,
203 struct mpipe_channel_config *config)
205 struct mpipe_channel_config *data;
206 struct mpipe_context *context;
207 gxio_mpipe_rules_t rules;
210 if (instance < 0 || instance >= mpipe_instances ||
211 channel < 0 || channel >= MPIPE_MAX_CHANNELS)
214 context = &mpipe_contexts[instance];
216 rte_spinlock_lock(&context->lock);
218 gxio_mpipe_rules_init(&rules, &context->context);
220 for (idx = 0; idx < MPIPE_MAX_CHANNELS; idx++) {
221 data = (channel == idx) ? config : &context->channels[idx];
226 rc = gxio_mpipe_rules_begin(&rules, data->first_bucket,
227 data->num_buckets, &data->stacks);
232 rc = gxio_mpipe_rules_add_channel(&rules, idx);
237 rc = gxio_mpipe_rules_set_headroom(&rules, data->head_room);
243 rc = gxio_mpipe_rules_commit(&rules);
245 memcpy(&context->channels[channel], config, sizeof(*config));
249 rte_spinlock_unlock(&context->lock);
255 mpipe_get_size_index(int *array, int count, int size,
260 for (i = 0; i < count && array[i] < size; i++) {
266 return i < count ? (int)i : -ENOENT;
268 return last >= 0 ? last : -ENOENT;
272 mpipe_calc_size(int *array, int count, int size)
274 int index = mpipe_get_size_index(array, count, size, 1);
275 return index < 0 ? index : array[index];
278 static int mpipe_equeue_size(int size)
281 result = mpipe_calc_size(mpipe_equeue_sizes,
282 RTE_DIM(mpipe_equeue_sizes), size);
286 static int mpipe_iqueue_size(int size)
289 result = mpipe_calc_size(mpipe_iqueue_sizes,
290 RTE_DIM(mpipe_iqueue_sizes), size);
294 static int mpipe_buffer_size_index(int size)
297 result = mpipe_get_size_index(mpipe_buffer_sizes,
298 RTE_DIM(mpipe_buffer_sizes), size, 0);
303 mpipe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
304 struct rte_eth_link *link)
306 struct rte_eth_link *dst = link;
307 struct rte_eth_link *src = &(dev->data->dev_link);
309 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
310 *(uint64_t *)src) == 0)
317 mpipe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
318 struct rte_eth_link *link)
320 struct rte_eth_link *dst = &(dev->data->dev_link);
321 struct rte_eth_link *src = link;
323 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
324 *(uint64_t *)src) == 0)
331 mpipe_infos_get(struct rte_eth_dev *dev __rte_unused,
332 struct rte_eth_dev_info *dev_info)
334 dev_info->min_rx_bufsize = 128;
335 dev_info->max_rx_pktlen = 1518;
336 dev_info->max_tx_queues = MPIPE_TX_MAX_QUEUES;
337 dev_info->max_rx_queues = MPIPE_RX_MAX_QUEUES;
338 dev_info->max_mac_addrs = 1;
339 dev_info->rx_offload_capa = 0;
340 dev_info->tx_offload_capa = 0;
344 mpipe_configure(struct rte_eth_dev *dev)
346 struct mpipe_dev_priv *priv = mpipe_priv(dev);
348 if (dev->data->nb_tx_queues > MPIPE_TX_MAX_QUEUES) {
349 RTE_LOG(ERR, PMD, "%s: Too many tx queues: %d > %d\n",
350 mpipe_name(priv), dev->data->nb_tx_queues,
351 MPIPE_TX_MAX_QUEUES);
354 priv->nb_tx_queues = dev->data->nb_tx_queues;
356 if (dev->data->nb_rx_queues > MPIPE_RX_MAX_QUEUES) {
357 RTE_LOG(ERR, PMD, "%s: Too many rx queues: %d > %d\n",
358 mpipe_name(priv), dev->data->nb_rx_queues,
359 MPIPE_RX_MAX_QUEUES);
361 priv->nb_rx_queues = dev->data->nb_rx_queues;
367 mpipe_link_compare(struct rte_eth_link *link1,
368 struct rte_eth_link *link2)
370 return (*(uint64_t *)link1 == *(uint64_t *)link2)
375 mpipe_link_update(struct rte_eth_dev *dev, int wait_to_complete)
377 struct mpipe_dev_priv *priv = mpipe_priv(dev);
378 struct rte_eth_link old, new;
379 int64_t state, speed;
382 memset(&old, 0, sizeof(old));
383 memset(&new, 0, sizeof(new));
384 mpipe_dev_atomic_read_link_status(dev, &old);
386 for (count = 0, rc = 0; count < MPIPE_LINK_UPDATE_TIMEOUT; count++) {
387 if (!priv->initialized)
390 state = gxio_mpipe_link_get_attr(&priv->link,
391 GXIO_MPIPE_LINK_CURRENT_STATE);
395 speed = state & GXIO_MPIPE_LINK_SPEED_MASK;
397 if (speed == GXIO_MPIPE_LINK_1G) {
398 new.link_speed = ETH_LINK_SPEED_1000;
399 new.link_duplex = ETH_LINK_FULL_DUPLEX;
401 } else if (speed == GXIO_MPIPE_LINK_10G) {
402 new.link_speed = ETH_LINK_SPEED_10000;
403 new.link_duplex = ETH_LINK_FULL_DUPLEX;
407 rc = mpipe_link_compare(&old, &new);
408 if (rc == 0 || !wait_to_complete)
411 rte_delay_us(MPIPE_LINK_UPDATE_INTERVAL);
414 mpipe_dev_atomic_write_link_status(dev, &new);
419 mpipe_set_link(struct rte_eth_dev *dev, int up)
421 struct mpipe_dev_priv *priv = mpipe_priv(dev);
424 rc = gxio_mpipe_link_set_attr(&priv->link,
425 GXIO_MPIPE_LINK_DESIRED_STATE,
426 up ? GXIO_MPIPE_LINK_ANYSPEED : 0);
428 RTE_LOG(ERR, PMD, "%s: Failed to set link %s.\n",
429 mpipe_name(priv), up ? "up" : "down");
431 mpipe_link_update(dev, 0);
438 mpipe_set_link_up(struct rte_eth_dev *dev)
440 return mpipe_set_link(dev, 1);
444 mpipe_set_link_down(struct rte_eth_dev *dev)
446 return mpipe_set_link(dev, 0);
450 mpipe_dp_enter(struct mpipe_dev_priv *priv)
452 __insn_mtspr(SPR_DSTREAM_PF, 0);
453 rte_atomic32_inc(&priv->dp_count);
457 mpipe_dp_exit(struct mpipe_dev_priv *priv)
459 rte_atomic32_dec(&priv->dp_count);
463 mpipe_dp_wait(struct mpipe_dev_priv *priv)
465 while (rte_atomic32_read(&priv->dp_count) != 0) {
471 mpipe_mbuf_stack_index(struct mpipe_dev_priv *priv, struct rte_mbuf *mbuf)
473 return (mbuf->port < RTE_MAX_ETHPORTS) ?
474 mpipe_priv(&rte_eth_devices[mbuf->port])->stack :
478 static inline struct rte_mbuf *
479 mpipe_recv_mbuf(struct mpipe_dev_priv *priv, gxio_mpipe_idesc_t *idesc,
482 void *va = gxio_mpipe_idesc_get_va(idesc);
483 uint16_t size = gxio_mpipe_idesc_get_xfer_size(idesc);
484 struct rte_mbuf *mbuf = RTE_PTR_SUB(va, priv->rx_offset);
486 rte_pktmbuf_reset(mbuf);
487 mbuf->data_off = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;
488 mbuf->port = in_port;
489 mbuf->data_len = size;
490 mbuf->pkt_len = size;
491 mbuf->hash.rss = gxio_mpipe_idesc_get_flow_hash(idesc);
493 PMD_DEBUG_RX("%s: RX mbuf %p, buffer %p, buf_addr %p, size %d\n",
494 mpipe_name(priv), mbuf, va, mbuf->buf_addr, size);
500 mpipe_recv_push(struct mpipe_dev_priv *priv, struct rte_mbuf *mbuf)
502 const int offset = RTE_PKTMBUF_HEADROOM + MPIPE_RX_IP_ALIGN;
503 void *buf_addr = RTE_PTR_ADD(mbuf->buf_addr, offset);
505 gxio_mpipe_push_buffer(priv->context, priv->stack, buf_addr);
506 PMD_DEBUG_RX("%s: Pushed mbuf %p, buffer %p into stack %d\n",
507 mpipe_name(priv), mbuf, buf_addr, priv->stack);
511 mpipe_recv_fill_stack(struct mpipe_dev_priv *priv, int count)
513 struct rte_mbuf *mbuf;
516 for (i = 0; i < count; i++) {
517 mbuf = __rte_mbuf_raw_alloc(priv->rx_mpool);
520 mpipe_recv_push(priv, mbuf);
523 PMD_DEBUG_RX("%s: Filled %d/%d buffers\n", mpipe_name(priv), i, count);
527 mpipe_recv_flush_stack(struct mpipe_dev_priv *priv)
529 const int offset = priv->rx_offset & ~RTE_MEMPOOL_ALIGN_MASK;
530 uint8_t in_port = priv->port_id;
531 struct rte_mbuf *mbuf;
535 va = gxio_mpipe_pop_buffer(priv->context, priv->stack);
538 mbuf = RTE_PTR_SUB(va, offset);
540 PMD_DEBUG_RX("%s: Flushing mbuf %p, va %p\n",
541 mpipe_name(priv), mbuf, va);
543 mbuf->data_off = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;
546 mbuf->port = in_port;
547 mbuf->packet_type = 0;
551 __rte_mbuf_raw_free(mbuf);
556 mpipe_register_segment(struct mpipe_dev_priv *priv, const struct rte_memseg *ms)
558 size_t size = ms->hugepage_sz;
562 for (addr = ms->addr, end = addr + ms->len; addr < end; addr += size) {
563 rc = gxio_mpipe_register_page(priv->context, priv->stack, addr,
570 RTE_LOG(ERR, PMD, "%s: Could not register memseg @%p, %d.\n",
571 mpipe_name(priv), ms->addr, rc);
573 RTE_LOG(DEBUG, PMD, "%s: Registered segment %p - %p\n",
574 mpipe_name(priv), ms->addr,
575 RTE_PTR_ADD(ms->addr, ms->len - 1));
580 mpipe_recv_init(struct mpipe_dev_priv *priv)
582 const struct rte_memseg *seg = rte_eal_get_physmem_layout();
587 if (!priv->rx_mpool) {
588 RTE_LOG(ERR, PMD, "%s: No buffer pool.\n",
593 /* Allocate one NotifRing for each queue. */
594 rc = gxio_mpipe_alloc_notif_rings(priv->context, MPIPE_RX_MAX_QUEUES,
597 RTE_LOG(ERR, PMD, "%s: Failed to allocate notif rings.\n",
601 priv->first_ring = rc;
603 /* Allocate a NotifGroup. */
604 rc = gxio_mpipe_alloc_notif_groups(priv->context, 1, 0, 0);
606 RTE_LOG(ERR, PMD, "%s: Failed to allocate rx group.\n",
610 priv->notif_group = rc;
612 /* Allocate required buckets. */
613 rc = gxio_mpipe_alloc_buckets(priv->context, MPIPE_RX_BUCKETS, 0, 0);
615 RTE_LOG(ERR, PMD, "%s: Failed to allocate buckets.\n",
619 priv->first_bucket = rc;
621 rc = gxio_mpipe_alloc_buffer_stacks(priv->context, 1, 0, 0);
623 RTE_LOG(ERR, PMD, "%s: Failed to allocate buffer stack.\n",
629 while (seg && seg->addr)
630 mpipe_register_segment(priv, seg++);
632 stack_size = gxio_mpipe_calc_buffer_stack_bytes(MPIPE_RX_STACK_SIZE);
633 stack_mem = rte_zmalloc(NULL, stack_size, 65536);
635 RTE_LOG(ERR, PMD, "%s: Failed to allocate buffer memory.\n",
639 RTE_LOG(DEBUG, PMD, "%s: Buffer stack memory %p - %p.\n",
640 mpipe_name(priv), stack_mem,
641 RTE_PTR_ADD(stack_mem, stack_size - 1));
644 rc = gxio_mpipe_init_buffer_stack(priv->context, priv->stack,
645 priv->rx_size_code, stack_mem,
648 RTE_LOG(ERR, PMD, "%s: Failed to initialize buffer stack.\n",
657 mpipe_xmit_init(struct mpipe_dev_priv *priv)
663 /* Allocate eDMA ring. */
664 rc = gxio_mpipe_alloc_edma_rings(priv->context, 1, 0, 0);
666 RTE_LOG(ERR, PMD, "%s: Failed to alloc tx ring.\n",
672 rc = mpipe_equeue_size(MPIPE_TX_DESCS);
674 RTE_LOG(ERR, PMD, "%s: Cannot allocate %d equeue descs.\n",
675 mpipe_name(priv), (int)MPIPE_TX_DESCS);
678 priv->equeue_size = rc;
680 /* Initialize completion array. */
681 ring_size = sizeof(priv->tx_comps[0]) * priv->equeue_size;
682 priv->tx_comps = rte_zmalloc(NULL, ring_size, RTE_CACHE_LINE_SIZE);
683 if (!priv->tx_comps) {
684 RTE_LOG(ERR, PMD, "%s: Failed to allocate egress comps.\n",
689 /* Allocate eDMA ring memory. */
690 ring_size = sizeof(gxio_mpipe_edesc_t) * priv->equeue_size;
691 ring_mem = rte_zmalloc(NULL, ring_size, ring_size);
693 RTE_LOG(ERR, PMD, "%s: Failed to allocate egress descs.\n",
697 RTE_LOG(DEBUG, PMD, "%s: eDMA ring memory %p - %p.\n",
698 mpipe_name(priv), ring_mem,
699 RTE_PTR_ADD(ring_mem, ring_size - 1));
702 /* Initialize eDMA ring. */
703 rc = gxio_mpipe_equeue_init(&priv->equeue, priv->context, priv->ering,
704 priv->channel, ring_mem, ring_size, 0);
706 RTE_LOG(ERR, PMD, "%s: Failed to init equeue\n",
715 mpipe_link_init(struct mpipe_dev_priv *priv)
720 rc = gxio_mpipe_link_open(&priv->link, priv->context,
721 mpipe_name(priv), GXIO_MPIPE_LINK_AUTO_NONE);
723 RTE_LOG(ERR, PMD, "%s: Failed to open link.\n",
728 /* Get the channel index. */
729 rc = gxio_mpipe_link_channel(&priv->link);
731 RTE_LOG(ERR, PMD, "%s: Bad channel\n",
741 mpipe_init(struct mpipe_dev_priv *priv)
745 if (priv->initialized)
748 rc = mpipe_recv_init(priv);
750 RTE_LOG(ERR, PMD, "%s: Failed to init rx.\n",
755 rc = mpipe_xmit_init(priv);
757 RTE_LOG(ERR, PMD, "%s: Failed to init tx.\n",
763 priv->initialized = 1;
769 mpipe_start(struct rte_eth_dev *dev)
771 struct mpipe_dev_priv *priv = mpipe_priv(dev);
772 struct mpipe_channel_config config;
773 struct mpipe_rx_queue *rx_queue;
774 struct rte_eth_link eth_link;
775 unsigned queue, buffers = 0;
780 memset(ð_link, 0, sizeof(eth_link));
781 mpipe_dev_atomic_write_link_status(dev, ð_link);
783 rc = mpipe_init(priv);
787 /* Initialize NotifRings. */
788 for (queue = 0; queue < priv->nb_rx_queues; queue++) {
789 rx_queue = mpipe_rx_queue(priv, queue);
790 ring_size = rx_queue->q.nb_desc * sizeof(gxio_mpipe_idesc_t);
792 ring_mem = rte_malloc(NULL, ring_size, ring_size);
794 RTE_LOG(ERR, PMD, "%s: Failed to alloc rx descs.\n",
798 RTE_LOG(DEBUG, PMD, "%s: iDMA ring %d memory %p - %p.\n",
799 mpipe_name(priv), queue, ring_mem,
800 RTE_PTR_ADD(ring_mem, ring_size - 1));
803 rc = gxio_mpipe_iqueue_init(&rx_queue->iqueue, priv->context,
804 priv->first_ring + queue, ring_mem,
807 RTE_LOG(ERR, PMD, "%s: Failed to init rx queue.\n",
812 rx_queue->rx_ring_mem = ring_mem;
813 buffers += rx_queue->q.nb_desc;
816 /* Initialize ingress NotifGroup and buckets. */
817 rc = gxio_mpipe_init_notif_group_and_buckets(priv->context,
818 priv->notif_group, priv->first_ring, priv->nb_rx_queues,
819 priv->first_bucket, MPIPE_RX_BUCKETS,
820 GXIO_MPIPE_BUCKET_STATIC_FLOW_AFFINITY);
822 RTE_LOG(ERR, PMD, "%s: Failed to init group and buckets.\n",
827 /* Configure the classifier to deliver packets from this port. */
829 config.first_bucket = priv->first_bucket;
830 config.num_buckets = MPIPE_RX_BUCKETS;
831 memset(&config.stacks, 0xff, sizeof(config.stacks));
832 config.stacks.stacks[priv->rx_size_code] = priv->stack;
833 config.head_room = priv->rx_offset & RTE_MEMPOOL_ALIGN_MASK;
835 rc = mpipe_channel_config(priv->instance, priv->channel,
838 RTE_LOG(ERR, PMD, "%s: Failed to setup classifier.\n",
843 /* Fill empty buffers into the buffer stack. */
844 mpipe_recv_fill_stack(priv, buffers);
846 /* Bring up the link. */
847 mpipe_set_link_up(dev);
849 /* Start xmit/recv on queues. */
850 for (queue = 0; queue < priv->nb_tx_queues; queue++)
851 mpipe_tx_queue(priv, queue)->q.link_status = 1;
852 for (queue = 0; queue < priv->nb_rx_queues; queue++)
853 mpipe_rx_queue(priv, queue)->q.link_status = 1;
860 mpipe_stop(struct rte_eth_dev *dev)
862 struct mpipe_dev_priv *priv = mpipe_priv(dev);
863 struct mpipe_channel_config config;
867 for (queue = 0; queue < priv->nb_tx_queues; queue++)
868 mpipe_tx_queue(priv, queue)->q.link_status = 0;
869 for (queue = 0; queue < priv->nb_rx_queues; queue++)
870 mpipe_rx_queue(priv, queue)->q.link_status = 0;
872 /* Make sure the link_status writes land. */
876 * Wait for link_status change to register with straggling datapath
881 /* Bring down the link. */
882 mpipe_set_link_down(dev);
884 /* Remove classifier rules. */
885 memset(&config, 0, sizeof(config));
886 rc = mpipe_channel_config(priv->instance, priv->channel,
889 RTE_LOG(ERR, PMD, "%s: Failed to stop classifier.\n",
893 /* Flush completed xmit packets. */
894 mpipe_xmit_flush(priv);
896 /* Flush buffer stacks. */
897 mpipe_recv_flush(priv);
903 mpipe_close(struct rte_eth_dev *dev)
905 struct mpipe_dev_priv *priv = mpipe_priv(dev);
911 mpipe_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
913 struct mpipe_dev_priv *priv = mpipe_priv(dev);
914 struct mpipe_tx_queue *tx_queue;
915 struct mpipe_rx_queue *rx_queue;
919 memset(stats, 0, sizeof(*stats));
921 for (i = 0; i < priv->nb_tx_queues; i++) {
922 tx_queue = mpipe_tx_queue(priv, i);
924 stats->opackets += tx_queue->q.stats.packets;
925 stats->obytes += tx_queue->q.stats.bytes;
926 stats->oerrors += tx_queue->q.stats.errors;
928 idx = tx_queue->q.stat_idx;
929 if (idx != (uint16_t)-1) {
930 stats->q_opackets[idx] += tx_queue->q.stats.packets;
931 stats->q_obytes[idx] += tx_queue->q.stats.bytes;
932 stats->q_errors[idx] += tx_queue->q.stats.errors;
936 for (i = 0; i < priv->nb_rx_queues; i++) {
937 rx_queue = mpipe_rx_queue(priv, i);
939 stats->ipackets += rx_queue->q.stats.packets;
940 stats->ibytes += rx_queue->q.stats.bytes;
941 stats->ierrors += rx_queue->q.stats.errors;
942 stats->rx_nombuf += rx_queue->q.stats.nomem;
944 idx = rx_queue->q.stat_idx;
945 if (idx != (uint16_t)-1) {
946 stats->q_ipackets[idx] += rx_queue->q.stats.packets;
947 stats->q_ibytes[idx] += rx_queue->q.stats.bytes;
948 stats->q_errors[idx] += rx_queue->q.stats.errors;
954 mpipe_stats_reset(struct rte_eth_dev *dev)
956 struct mpipe_dev_priv *priv = mpipe_priv(dev);
957 struct mpipe_tx_queue *tx_queue;
958 struct mpipe_rx_queue *rx_queue;
961 for (i = 0; i < priv->nb_tx_queues; i++) {
962 tx_queue = mpipe_tx_queue(priv, i);
963 memset(&tx_queue->q.stats, 0, sizeof(tx_queue->q.stats));
966 for (i = 0; i < priv->nb_rx_queues; i++) {
967 rx_queue = mpipe_rx_queue(priv, i);
968 memset(&rx_queue->q.stats, 0, sizeof(rx_queue->q.stats));
973 mpipe_queue_stats_mapping_set(struct rte_eth_dev *dev, uint16_t queue_id,
974 uint8_t stat_idx, uint8_t is_rx)
976 struct mpipe_dev_priv *priv = mpipe_priv(dev);
979 priv->rx_stat_mapping[stat_idx] = queue_id;
981 priv->tx_stat_mapping[stat_idx] = queue_id;
988 mpipe_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
989 uint16_t nb_desc, unsigned int socket_id __rte_unused,
990 const struct rte_eth_txconf *tx_conf __rte_unused)
992 struct mpipe_tx_queue *tx_queue = dev->data->tx_queues[queue_idx];
993 struct mpipe_dev_priv *priv = mpipe_priv(dev);
996 tx_queue = rte_realloc(tx_queue, sizeof(*tx_queue),
997 RTE_CACHE_LINE_SIZE);
999 RTE_LOG(ERR, PMD, "%s: Failed to allocate TX queue.\n",
1004 memset(&tx_queue->q, 0, sizeof(tx_queue->q));
1005 tx_queue->q.priv = priv;
1006 tx_queue->q.queue_idx = queue_idx;
1007 tx_queue->q.port_id = dev->data->port_id;
1008 tx_queue->q.nb_desc = nb_desc;
1010 tx_queue->q.stat_idx = -1;
1011 for (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {
1012 if (priv->tx_stat_mapping[idx] == queue_idx)
1013 tx_queue->q.stat_idx = idx;
1016 dev->data->tx_queues[queue_idx] = tx_queue;
1022 mpipe_tx_queue_release(void *_txq)
1028 mpipe_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1029 uint16_t nb_desc, unsigned int socket_id __rte_unused,
1030 const struct rte_eth_rxconf *rx_conf __rte_unused,
1031 struct rte_mempool *mp)
1033 struct mpipe_rx_queue *rx_queue = dev->data->rx_queues[queue_idx];
1034 struct mpipe_dev_priv *priv = mpipe_priv(dev);
1038 rc = mpipe_iqueue_size(nb_desc);
1040 RTE_LOG(ERR, PMD, "%s: Cannot allocate %d iqueue descs.\n",
1041 mpipe_name(priv), (int)nb_desc);
1045 if (rc != nb_desc) {
1046 RTE_LOG(WARNING, PMD, "%s: Extending RX descs from %d to %d.\n",
1047 mpipe_name(priv), (int)nb_desc, rc);
1051 size = sizeof(*rx_queue);
1052 rx_queue = rte_realloc(rx_queue, size, RTE_CACHE_LINE_SIZE);
1054 RTE_LOG(ERR, PMD, "%s: Failed to allocate RX queue.\n",
1059 memset(&rx_queue->q, 0, sizeof(rx_queue->q));
1060 rx_queue->q.priv = priv;
1061 rx_queue->q.nb_desc = nb_desc;
1062 rx_queue->q.port_id = dev->data->port_id;
1063 rx_queue->q.queue_idx = queue_idx;
1065 if (!priv->rx_mpool) {
1066 int size = (rte_pktmbuf_data_room_size(mp) -
1067 RTE_PKTMBUF_HEADROOM -
1070 priv->rx_offset = (sizeof(struct rte_mbuf) +
1071 rte_pktmbuf_priv_size(mp) +
1072 RTE_PKTMBUF_HEADROOM +
1075 RTE_LOG(ERR, PMD, "%s: Bad buffer size %d.\n",
1077 rte_pktmbuf_data_room_size(mp));
1081 priv->rx_size_code = mpipe_buffer_size_index(size);
1082 priv->rx_mpool = mp;
1085 if (priv->rx_mpool != mp) {
1086 RTE_LOG(WARNING, PMD, "%s: Ignoring multiple buffer pools.\n",
1090 rx_queue->q.stat_idx = -1;
1091 for (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {
1092 if (priv->rx_stat_mapping[idx] == queue_idx)
1093 rx_queue->q.stat_idx = idx;
1096 dev->data->rx_queues[queue_idx] = rx_queue;
1102 mpipe_rx_queue_release(void *_rxq)
1107 #define MPIPE_XGBE_ENA_HASH_MULTI \
1108 (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_MULTI_SHIFT)
1109 #define MPIPE_XGBE_ENA_HASH_UNI \
1110 (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_UNI_SHIFT)
1111 #define MPIPE_XGBE_COPY_ALL \
1112 (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__COPY_ALL_SHIFT)
1113 #define MPIPE_GBE_ENA_MULTI_HASH \
1114 (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__MULTI_HASH_ENA_SHIFT)
1115 #define MPIPE_GBE_ENA_UNI_HASH \
1116 (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__UNI_HASH_ENA_SHIFT)
1117 #define MPIPE_GBE_COPY_ALL \
1118 (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__COPY_ALL_SHIFT)
1121 mpipe_promiscuous_enable(struct rte_eth_dev *dev)
1123 struct mpipe_dev_priv *priv = mpipe_priv(dev);
1127 if (priv->is_xaui) {
1128 addr = MPIPE_XAUI_RECEIVE_CONFIGURATION;
1129 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1130 reg &= ~MPIPE_XGBE_ENA_HASH_MULTI;
1131 reg &= ~MPIPE_XGBE_ENA_HASH_UNI;
1132 reg |= MPIPE_XGBE_COPY_ALL;
1133 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1135 addr = MPIPE_GBE_NETWORK_CONFIGURATION;
1136 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1137 reg &= ~MPIPE_GBE_ENA_MULTI_HASH;
1138 reg &= ~MPIPE_GBE_ENA_UNI_HASH;
1139 reg |= MPIPE_GBE_COPY_ALL;
1140 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1145 mpipe_promiscuous_disable(struct rte_eth_dev *dev)
1147 struct mpipe_dev_priv *priv = mpipe_priv(dev);
1151 if (priv->is_xaui) {
1152 addr = MPIPE_XAUI_RECEIVE_CONFIGURATION;
1153 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1154 reg |= MPIPE_XGBE_ENA_HASH_MULTI;
1155 reg |= MPIPE_XGBE_ENA_HASH_UNI;
1156 reg &= ~MPIPE_XGBE_COPY_ALL;
1157 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1159 addr = MPIPE_GBE_NETWORK_CONFIGURATION;
1160 reg = gxio_mpipe_link_mac_rd(&priv->link, addr);
1161 reg |= MPIPE_GBE_ENA_MULTI_HASH;
1162 reg |= MPIPE_GBE_ENA_UNI_HASH;
1163 reg &= ~MPIPE_GBE_COPY_ALL;
1164 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1168 static struct eth_dev_ops mpipe_dev_ops = {
1169 .dev_infos_get = mpipe_infos_get,
1170 .dev_configure = mpipe_configure,
1171 .dev_start = mpipe_start,
1172 .dev_stop = mpipe_stop,
1173 .dev_close = mpipe_close,
1174 .stats_get = mpipe_stats_get,
1175 .stats_reset = mpipe_stats_reset,
1176 .queue_stats_mapping_set = mpipe_queue_stats_mapping_set,
1177 .tx_queue_setup = mpipe_tx_queue_setup,
1178 .rx_queue_setup = mpipe_rx_queue_setup,
1179 .tx_queue_release = mpipe_tx_queue_release,
1180 .rx_queue_release = mpipe_rx_queue_release,
1181 .link_update = mpipe_link_update,
1182 .dev_set_link_up = mpipe_set_link_up,
1183 .dev_set_link_down = mpipe_set_link_down,
1184 .promiscuous_enable = mpipe_promiscuous_enable,
1185 .promiscuous_disable = mpipe_promiscuous_disable,
1189 mpipe_xmit_null(struct mpipe_dev_priv *priv, int64_t start, int64_t end)
1191 gxio_mpipe_edesc_t null_desc = { { .bound = 1, .ns = 1 } };
1192 gxio_mpipe_equeue_t *equeue = &priv->equeue;
1195 for (slot = start; slot < end; slot++) {
1196 gxio_mpipe_equeue_put_at(equeue, null_desc, slot);
1201 mpipe_xmit_flush(struct mpipe_dev_priv *priv)
1203 gxio_mpipe_equeue_t *equeue = &priv->equeue;
1206 /* Post a dummy descriptor and wait for its return. */
1207 slot = gxio_mpipe_equeue_reserve(equeue, 1);
1209 RTE_LOG(ERR, PMD, "%s: Failed to reserve stop slot.\n",
1214 mpipe_xmit_null(priv, slot, slot + 1);
1216 while (!gxio_mpipe_equeue_is_complete(equeue, slot, 1)) {
1220 for (slot = 0; slot < priv->equeue_size; slot++) {
1221 if (priv->tx_comps[slot])
1222 rte_pktmbuf_free_seg(priv->tx_comps[slot]);
1227 mpipe_recv_flush(struct mpipe_dev_priv *priv)
1229 uint8_t in_port = priv->port_id;
1230 struct mpipe_rx_queue *rx_queue;
1231 gxio_mpipe_iqueue_t *iqueue;
1232 gxio_mpipe_idesc_t idesc;
1233 struct rte_mbuf *mbuf;
1236 /* Release packets on the buffer stack. */
1237 mpipe_recv_flush_stack(priv);
1239 /* Flush packets sitting in recv queues. */
1240 for (queue = 0; queue < priv->nb_rx_queues; queue++) {
1241 rx_queue = mpipe_rx_queue(priv, queue);
1242 iqueue = &rx_queue->iqueue;
1243 while (gxio_mpipe_iqueue_try_get(iqueue, &idesc) >= 0) {
1244 /* Skip idesc with the 'buffer error' bit set. */
1247 mbuf = mpipe_recv_mbuf(priv, &idesc, in_port);
1248 rte_pktmbuf_free(mbuf);
1250 rte_free(rx_queue->rx_ring_mem);
1254 static inline uint16_t
1255 mpipe_do_xmit(struct mpipe_tx_queue *tx_queue, struct rte_mbuf **tx_pkts,
1258 struct mpipe_dev_priv *priv = tx_queue->q.priv;
1259 gxio_mpipe_equeue_t *equeue = &priv->equeue;
1260 unsigned nb_bytes = 0;
1261 unsigned nb_sent = 0;
1265 PMD_DEBUG_TX("Trying to transmit %d packets on %s:%d.\n",
1266 nb_pkts, mpipe_name(tx_queue->q.priv),
1267 tx_queue->q.queue_idx);
1269 /* Optimistic assumption that we need exactly one slot per packet. */
1270 nb_slots = RTE_MIN(nb_pkts, MPIPE_TX_DESCS / 2);
1273 struct rte_mbuf *mbuf = NULL, *pkt = NULL;
1276 /* Reserve eDMA ring slots. */
1277 slot = gxio_mpipe_equeue_try_reserve_fast(equeue, nb_slots);
1278 if (unlikely(slot < 0)) {
1282 for (i = 0; i < nb_slots; i++) {
1283 unsigned idx = (slot + i) & (priv->equeue_size - 1);
1284 rte_prefetch0(priv->tx_comps[idx]);
1287 /* Fill up slots with descriptor and completion info. */
1288 for (i = 0; i < nb_slots; i++) {
1289 unsigned idx = (slot + i) & (priv->equeue_size - 1);
1290 gxio_mpipe_edesc_t desc;
1291 struct rte_mbuf *next;
1293 /* Starting on a new packet? */
1294 if (likely(!mbuf)) {
1295 int room = nb_slots - i;
1297 pkt = mbuf = tx_pkts[nb_sent];
1299 /* Bail out if we run out of descs. */
1300 if (unlikely(pkt->nb_segs > room))
1306 /* We have a segment to send. */
1309 if (priv->tx_comps[idx])
1310 rte_pktmbuf_free_seg(priv->tx_comps[idx]);
1312 port_id = (mbuf->port < RTE_MAX_ETHPORTS) ?
1313 mbuf->port : priv->port_id;
1314 desc = (gxio_mpipe_edesc_t) { {
1315 .va = rte_pktmbuf_mtod(mbuf, uintptr_t),
1316 .xfer_size = rte_pktmbuf_data_len(mbuf),
1317 .bound = next ? 0 : 1,
1318 .stack_idx = mpipe_mbuf_stack_index(priv, mbuf),
1319 .size = priv->rx_size_code,
1321 if (mpipe_local.mbuf_push_debt[port_id] > 0) {
1322 mpipe_local.mbuf_push_debt[port_id]--;
1324 priv->tx_comps[idx] = NULL;
1326 priv->tx_comps[idx] = mbuf;
1328 nb_bytes += mbuf->data_len;
1329 gxio_mpipe_equeue_put_at(equeue, desc, slot + i);
1331 PMD_DEBUG_TX("%s:%d: Sending packet %p, len %d\n",
1333 tx_queue->q.queue_idx,
1334 rte_pktmbuf_mtod(mbuf, void *),
1335 rte_pktmbuf_data_len(mbuf));
1340 if (unlikely(nb_sent < nb_pkts)) {
1342 /* Fill remaining slots with null descriptors. */
1343 mpipe_xmit_null(priv, slot + i, slot + nb_slots);
1346 * Calculate exact number of descriptors needed for
1347 * the next go around.
1350 for (i = nb_sent; i < nb_pkts; i++) {
1351 nb_slots += tx_pkts[i]->nb_segs;
1354 nb_slots = RTE_MIN(nb_slots, MPIPE_TX_DESCS / 2);
1356 } while (nb_sent < nb_pkts);
1358 tx_queue->q.stats.packets += nb_sent;
1359 tx_queue->q.stats.bytes += nb_bytes;
1364 static inline uint16_t
1365 mpipe_do_recv(struct mpipe_rx_queue *rx_queue, struct rte_mbuf **rx_pkts,
1368 struct mpipe_dev_priv *priv = rx_queue->q.priv;
1369 gxio_mpipe_iqueue_t *iqueue = &rx_queue->iqueue;
1370 gxio_mpipe_idesc_t *first_idesc, *idesc, *last_idesc;
1371 uint8_t in_port = rx_queue->q.port_id;
1372 const unsigned look_ahead = 8;
1373 int room = nb_pkts, rc = 0;
1374 unsigned nb_packets = 0;
1375 unsigned nb_dropped = 0;
1376 unsigned nb_nomem = 0;
1377 unsigned nb_bytes = 0;
1378 unsigned nb_descs, i;
1380 while (room && !rc) {
1381 if (rx_queue->avail_descs < room) {
1382 rc = gxio_mpipe_iqueue_try_peek(iqueue,
1383 &rx_queue->next_desc);
1384 rx_queue->avail_descs = rc < 0 ? 0 : rc;
1387 if (unlikely(!rx_queue->avail_descs)) {
1391 nb_descs = RTE_MIN(room, rx_queue->avail_descs);
1393 first_idesc = rx_queue->next_desc;
1394 last_idesc = first_idesc + nb_descs;
1396 rx_queue->next_desc += nb_descs;
1397 rx_queue->avail_descs -= nb_descs;
1399 for (i = 1; i < look_ahead; i++) {
1400 rte_prefetch0(first_idesc + i);
1403 PMD_DEBUG_RX("%s:%d: Trying to receive %d packets\n",
1404 mpipe_name(rx_queue->q.priv),
1405 rx_queue->q.queue_idx,
1408 for (idesc = first_idesc; idesc < last_idesc; idesc++) {
1409 struct rte_mbuf *mbuf;
1411 PMD_DEBUG_RX("%s:%d: processing idesc %d/%d\n",
1413 rx_queue->q.queue_idx,
1414 nb_packets, nb_descs);
1416 rte_prefetch0(idesc + look_ahead);
1418 PMD_DEBUG_RX("%s:%d: idesc %p, %s%s%s%s%s%s%s%s%s%s"
1419 "size: %d, bkt: %d, chan: %d, ring: %d, sqn: %lu, va: %lu\n",
1421 rx_queue->q.queue_idx,
1423 idesc->me ? "me, " : "",
1424 idesc->tr ? "tr, " : "",
1425 idesc->ce ? "ce, " : "",
1426 idesc->ct ? "ct, " : "",
1427 idesc->cs ? "cs, " : "",
1428 idesc->nr ? "nr, " : "",
1429 idesc->sq ? "sq, " : "",
1430 idesc->ts ? "ts, " : "",
1431 idesc->ps ? "ps, " : "",
1432 idesc->be ? "be, " : "",
1437 (unsigned long)idesc->packet_sqn,
1438 (unsigned long)idesc->va);
1440 if (unlikely(gxio_mpipe_idesc_has_error(idesc))) {
1442 gxio_mpipe_iqueue_drop(iqueue, idesc);
1443 PMD_DEBUG_RX("%s:%d: Descriptor error\n",
1444 mpipe_name(rx_queue->q.priv),
1445 rx_queue->q.queue_idx);
1449 if (mpipe_local.mbuf_push_debt[in_port] <
1450 MPIPE_BUF_DEBT_THRESHOLD)
1451 mpipe_local.mbuf_push_debt[in_port]++;
1453 mbuf = __rte_mbuf_raw_alloc(priv->rx_mpool);
1454 if (unlikely(!mbuf)) {
1456 gxio_mpipe_iqueue_drop(iqueue, idesc);
1457 PMD_DEBUG_RX("%s:%d: alloc failure\n",
1458 mpipe_name(rx_queue->q.priv),
1459 rx_queue->q.queue_idx);
1463 mpipe_recv_push(priv, mbuf);
1466 /* Get and setup the mbuf for the received packet. */
1467 mbuf = mpipe_recv_mbuf(priv, idesc, in_port);
1469 /* Update results and statistics counters. */
1470 rx_pkts[nb_packets] = mbuf;
1471 nb_bytes += mbuf->pkt_len;
1476 * We release the ring in bursts, but do not track and release
1477 * buckets. This therefore breaks dynamic flow affinity, but
1478 * we always operate in static affinity mode, and so we're OK
1479 * with this optimization.
1481 gxio_mpipe_iqueue_advance(iqueue, nb_descs);
1482 gxio_mpipe_credit(iqueue->context, iqueue->ring, -1, nb_descs);
1485 * Go around once more if we haven't yet peeked the queue, and
1486 * if we have more room to receive.
1488 room = nb_pkts - nb_packets;
1491 rx_queue->q.stats.packets += nb_packets;
1492 rx_queue->q.stats.bytes += nb_bytes;
1493 rx_queue->q.stats.errors += nb_dropped;
1494 rx_queue->q.stats.nomem += nb_nomem;
1496 PMD_DEBUG_RX("%s:%d: RX: %d/%d pkts/bytes, %d/%d drops/nomem\n",
1497 mpipe_name(rx_queue->q.priv), rx_queue->q.queue_idx,
1498 nb_packets, nb_bytes, nb_dropped, nb_nomem);
1504 mpipe_recv_pkts(void *_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1506 struct mpipe_rx_queue *rx_queue = _rxq;
1507 uint16_t result = 0;
1510 mpipe_dp_enter(rx_queue->q.priv);
1511 if (likely(rx_queue->q.link_status))
1512 result = mpipe_do_recv(rx_queue, rx_pkts, nb_pkts);
1513 mpipe_dp_exit(rx_queue->q.priv);
1520 mpipe_xmit_pkts(void *_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1522 struct mpipe_tx_queue *tx_queue = _txq;
1523 uint16_t result = 0;
1526 mpipe_dp_enter(tx_queue->q.priv);
1527 if (likely(tx_queue->q.link_status))
1528 result = mpipe_do_xmit(tx_queue, tx_pkts, nb_pkts);
1529 mpipe_dp_exit(tx_queue->q.priv);
1536 mpipe_link_mac(const char *ifname, uint8_t *mac)
1539 char name[GXIO_MPIPE_LINK_NAME_LEN];
1541 for (idx = 0, rc = 0; !rc; idx++) {
1542 rc = gxio_mpipe_link_enumerate_mac(idx, name, mac);
1543 if (!rc && !strncmp(name, ifname, GXIO_MPIPE_LINK_NAME_LEN))
1550 rte_pmd_mpipe_devinit(const char *ifname,
1551 const char *params __rte_unused)
1553 gxio_mpipe_context_t *context;
1554 struct rte_eth_dev *eth_dev;
1555 struct mpipe_dev_priv *priv;
1559 /* Get the mPIPE instance that the device belongs to. */
1560 instance = gxio_mpipe_link_instance(ifname);
1561 context = mpipe_context(instance);
1563 RTE_LOG(ERR, PMD, "%s: No device for link.\n", ifname);
1567 priv = rte_zmalloc(NULL, sizeof(*priv), 0);
1569 RTE_LOG(ERR, PMD, "%s: Failed to allocate priv.\n", ifname);
1573 memset(&priv->tx_stat_mapping, 0xff, sizeof(priv->tx_stat_mapping));
1574 memset(&priv->rx_stat_mapping, 0xff, sizeof(priv->rx_stat_mapping));
1575 priv->context = context;
1576 priv->instance = instance;
1577 priv->is_xaui = (strncmp(ifname, "xgbe", 4) == 0);
1580 mac = priv->mac_addr.addr_bytes;
1581 rc = mpipe_link_mac(ifname, mac);
1583 RTE_LOG(ERR, PMD, "%s: Failed to enumerate link.\n", ifname);
1588 eth_dev = rte_eth_dev_allocate(ifname, RTE_ETH_DEV_VIRTUAL);
1590 RTE_LOG(ERR, PMD, "%s: Failed to allocate device.\n", ifname);
1595 RTE_LOG(INFO, PMD, "%s: Initialized mpipe device"
1596 "(mac %02x:%02x:%02x:%02x:%02x:%02x).\n",
1597 ifname, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
1599 priv->eth_dev = eth_dev;
1600 priv->port_id = eth_dev->data->port_id;
1601 eth_dev->data->dev_private = priv;
1602 eth_dev->data->mac_addrs = &priv->mac_addr;
1604 eth_dev->data->dev_flags = 0;
1605 eth_dev->data->kdrv = RTE_KDRV_NONE;
1606 eth_dev->driver = NULL;
1607 eth_dev->data->drv_name = drivername;
1608 eth_dev->data->numa_node = instance;
1610 eth_dev->dev_ops = &mpipe_dev_ops;
1611 eth_dev->rx_pkt_burst = &mpipe_recv_pkts;
1612 eth_dev->tx_pkt_burst = &mpipe_xmit_pkts;
1614 rc = mpipe_link_init(priv);
1616 RTE_LOG(ERR, PMD, "%s: Failed to init link.\n",
1624 static struct rte_driver pmd_mpipe_xgbe_drv = {
1627 .init = rte_pmd_mpipe_devinit,
1630 static struct rte_driver pmd_mpipe_gbe_drv = {
1633 .init = rte_pmd_mpipe_devinit,
1636 PMD_REGISTER_DRIVER(pmd_mpipe_xgbe_drv);
1637 PMD_REGISTER_DRIVER(pmd_mpipe_gbe_drv);
1639 static void __attribute__((constructor, used))
1640 mpipe_init_contexts(void)
1642 struct mpipe_context *context;
1645 for (instance = 0; instance < GXIO_MPIPE_INSTANCE_MAX; instance++) {
1646 context = &mpipe_contexts[instance];
1648 rte_spinlock_init(&context->lock);
1649 rc = gxio_mpipe_init(&context->context, instance);
1654 mpipe_instances = instance;