drivers/net/mpipe/mpipe_tilegx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2015 EZchip Semiconductor Ltd. All rights reserved.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of EZchip Semiconductor nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <unistd.h>
  34
  35 #include <rte_eal.h>
  36 #include <rte_dev.h>
  37 #include <rte_eal_memconfig.h>
  38 #include <rte_ethdev.h>
  39 #include <rte_malloc.h>
  40 #include <rte_cycles.h>
  41
  42 #include <arch/mpipe_xaui_def.h>
  43 #include <arch/mpipe_gbe_def.h>
  44
  45 #include <gxio/mpipe.h>
  46
  47 #ifdef RTE_LIBRTE_MPIPE_PMD_DEBUG
  48 #define PMD_DEBUG_RX(...)       RTE_LOG(DEBUG, PMD, __VA_ARGS__)
  49 #define PMD_DEBUG_TX(...)       RTE_LOG(DEBUG, PMD, __VA_ARGS__)
  50 #else
  51 #define PMD_DEBUG_RX(...)
  52 #define PMD_DEBUG_TX(...)
  53 #endif
  54
  55 #define MPIPE_MAX_CHANNELS              128
  56 #define MPIPE_TX_MAX_QUEUES             128
  57 #define MPIPE_RX_MAX_QUEUES             16
  58 #define MPIPE_TX_DESCS                  512
  59 #define MPIPE_RX_BUCKETS                256
  60 #define MPIPE_RX_STACK_SIZE             65536
  61 #define MPIPE_RX_IP_ALIGN               2
  62 #define MPIPE_BSM_ALIGN                 128
  63
  64 #define MPIPE_LINK_UPDATE_TIMEOUT       10      /*  s */
  65 #define MPIPE_LINK_UPDATE_INTERVAL      100000  /* us */
  66
  67 struct mpipe_channel_config {
  68         int enable;
  69         int first_bucket;
  70         int num_buckets;
  71         int head_room;
  72         gxio_mpipe_rules_stacks_t stacks;
  73 };
  74
  75 struct mpipe_context {
  76         rte_spinlock_t        lock;
  77         gxio_mpipe_context_t  context;
  78         struct mpipe_channel_config channels[MPIPE_MAX_CHANNELS];
  79 };
  80
  81 /* Per-core local data. */
  82 struct mpipe_local {
  83         int mbuf_push_debt[RTE_MAX_ETHPORTS];   /* Buffer push debt. */
  84 } __rte_cache_aligned;
  85
  86 #define MPIPE_BUF_DEBT_THRESHOLD        32
  87 static __thread struct mpipe_local mpipe_local;
  88 static struct mpipe_context mpipe_contexts[GXIO_MPIPE_INSTANCE_MAX];
  89 static int mpipe_instances;
  90 static const char *drivername = "MPIPE PMD";
  91
  92 /* Per queue statistics. */
  93 struct mpipe_queue_stats {
  94         uint64_t packets, bytes, errors, nomem;
  95 };
  96
  97 /* Common tx/rx queue fields. */
  98 struct mpipe_queue {
  99         struct mpipe_dev_priv *priv;    /* "priv" data of its device. */
 100         uint16_t nb_desc;               /* Number of tx descriptors. */
 101         uint16_t port_id;               /* Device index. */
 102         uint16_t stat_idx;              /* Queue stats index. */
 103         uint8_t queue_idx;              /* Queue index. */
 104         uint8_t link_status;            /* 0 = link down. */
 105         struct mpipe_queue_stats stats; /* Stat data for the queue. */
 106 };
 107
 108 /* Transmit queue description. */
 109 struct mpipe_tx_queue {
 110         struct mpipe_queue q;           /* Common stuff. */
 111 };
 112
 113 /* Receive queue description. */
 114 struct mpipe_rx_queue {
 115         struct mpipe_queue q;           /* Common stuff. */
 116         gxio_mpipe_iqueue_t iqueue;     /* mPIPE iqueue. */
 117         gxio_mpipe_idesc_t *next_desc;  /* Next idesc to process. */
 118         int avail_descs;                /* Number of available descs. */
 119         void *rx_ring_mem;              /* DMA ring memory. */
 120 };
 121
 122 struct mpipe_dev_priv {
 123         gxio_mpipe_context_t *context;  /* mPIPE context. */
 124         gxio_mpipe_link_t link;         /* mPIPE link for the device. */
 125         gxio_mpipe_equeue_t equeue;     /* mPIPE equeue. */
 126         unsigned equeue_size;           /* mPIPE equeue desc count. */
 127         int instance;                   /* mPIPE instance. */
 128         int ering;                      /* mPIPE eDMA ring. */
 129         int stack;                      /* mPIPE buffer stack. */
 130         int channel;                    /* Device channel. */
 131         int port_id;                    /* DPDK port index. */
 132         struct rte_eth_dev *eth_dev;    /* DPDK device. */
 133         struct rte_mbuf **tx_comps;     /* TX completion array. */
 134         struct rte_mempool *rx_mpool;   /* mpool used by the rx queues. */
 135         unsigned rx_offset;             /* Receive head room. */
 136         unsigned rx_size_code;          /* mPIPE rx buffer size code. */
 137         unsigned rx_buffers;            /* receive buffers on stack. */
 138         int is_xaui:1,                  /* Is this an xgbe or gbe? */
 139             initialized:1,              /* Initialized port? */
 140             running:1;                  /* Running port? */
 141         struct ether_addr mac_addr;     /* MAC address. */
 142         unsigned nb_rx_queues;          /* Configured tx queues. */
 143         unsigned nb_tx_queues;          /* Configured rx queues. */
 144         int first_bucket;               /* mPIPE bucket start index. */
 145         int first_ring;                 /* mPIPE notif ring start index. */
 146         int notif_group;                /* mPIPE notif group. */
 147         rte_atomic32_t dp_count __rte_cache_aligned;    /* DP Entry count. */
 148         int tx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 149         int rx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];
 150 };
 151
 152 #define mpipe_priv(dev)                 \
 153         ((struct mpipe_dev_priv*)(dev)->data->dev_private)
 154
 155 #define mpipe_name(priv)                \
 156         ((priv)->eth_dev->data->name)
 157
 158 #define mpipe_rx_queue(priv, n)         \
 159         ((struct mpipe_rx_queue *)(priv)->eth_dev->data->rx_queues[n])
 160
 161 #define mpipe_tx_queue(priv, n)         \
 162         ((struct mpipe_tx_queue *)(priv)->eth_dev->data->tx_queues[n])
 163
 164 static void
 165 mpipe_xmit_flush(struct mpipe_dev_priv *priv);
 166
 167 static void
 168 mpipe_recv_flush(struct mpipe_dev_priv *priv);
 169
 170 static int mpipe_equeue_sizes[] = {
 171         [GXIO_MPIPE_EQUEUE_ENTRY_512]   = 512,
 172         [GXIO_MPIPE_EQUEUE_ENTRY_2K]    = 2048,
 173         [GXIO_MPIPE_EQUEUE_ENTRY_8K]    = 8192,
 174         [GXIO_MPIPE_EQUEUE_ENTRY_64K]   = 65536,
 175 };
 176
 177 static int mpipe_iqueue_sizes[] = {
 178         [GXIO_MPIPE_IQUEUE_ENTRY_128]   = 128,
 179         [GXIO_MPIPE_IQUEUE_ENTRY_512]   = 512,
 180         [GXIO_MPIPE_IQUEUE_ENTRY_2K]    = 2048,
 181         [GXIO_MPIPE_IQUEUE_ENTRY_64K]   = 65536,
 182 };
 183
 184 static int mpipe_buffer_sizes[] = {
 185         [GXIO_MPIPE_BUFFER_SIZE_128]    = 128,
 186         [GXIO_MPIPE_BUFFER_SIZE_256]    = 256,
 187         [GXIO_MPIPE_BUFFER_SIZE_512]    = 512,
 188         [GXIO_MPIPE_BUFFER_SIZE_1024]   = 1024,
 189         [GXIO_MPIPE_BUFFER_SIZE_1664]   = 1664,
 190         [GXIO_MPIPE_BUFFER_SIZE_4096]   = 4096,
 191         [GXIO_MPIPE_BUFFER_SIZE_10368]  = 10368,
 192         [GXIO_MPIPE_BUFFER_SIZE_16384]  = 16384,
 193 };
 194
 195 static gxio_mpipe_context_t *
 196 mpipe_context(int instance)
 197 {
 198         if (instance < 0 || instance >= mpipe_instances)
 199                 return NULL;
 200         return &mpipe_contexts[instance].context;
 201 }
 202
 203 static int mpipe_channel_config(int instance, int channel,
 204                                 struct mpipe_channel_config *config)
 205 {
 206         struct mpipe_channel_config *data;
 207         struct mpipe_context *context;
 208         gxio_mpipe_rules_t rules;
 209         int idx, rc = 0;
 210
 211         if (instance < 0 || instance >= mpipe_instances ||
 212             channel < 0 || channel >= MPIPE_MAX_CHANNELS)
 213                 return -EINVAL;
 214
 215         context = &mpipe_contexts[instance];
 216
 217         rte_spinlock_lock(&context->lock);
 218
 219         gxio_mpipe_rules_init(&rules, &context->context);
 220
 221         for (idx = 0; idx < MPIPE_MAX_CHANNELS; idx++) {
 222                 data = (channel == idx) ? config : &context->channels[idx];
 223
 224                 if (!data->enable)
 225                         continue;
 226
 227                 rc = gxio_mpipe_rules_begin(&rules, data->first_bucket,
 228                                             data->num_buckets, &data->stacks);
 229                 if (rc < 0) {
 230                         goto done;
 231                 }
 232
 233                 rc = gxio_mpipe_rules_add_channel(&rules, idx);
 234                 if (rc < 0) {
 235                         goto done;
 236                 }
 237
 238                 rc = gxio_mpipe_rules_set_headroom(&rules, data->head_room);
 239                 if (rc < 0) {
 240                         goto done;
 241                 }
 242         }
 243
 244         rc = gxio_mpipe_rules_commit(&rules);
 245         if (rc == 0) {
 246                 memcpy(&context->channels[channel], config, sizeof(*config));
 247         }
 248
 249 done:
 250         rte_spinlock_unlock(&context->lock);
 251
 252         return rc;
 253 }
 254
 255 static int
 256 mpipe_get_size_index(int *array, int count, int size,
 257                      bool roundup)
 258 {
 259         int i, last = -1;
 260
 261         for (i = 0; i < count && array[i] < size; i++) {
 262                 if (array[i])
 263                         last = i;
 264         }
 265
 266         if (roundup)
 267                 return i < count ? (int)i : -ENOENT;
 268         else
 269                 return last >= 0 ? last : -ENOENT;
 270 }
 271
 272 static int
 273 mpipe_calc_size(int *array, int count, int size)
 274 {
 275         int index = mpipe_get_size_index(array, count, size, 1);
 276         return index < 0 ? index : array[index];
 277 }
 278
 279 static int mpipe_equeue_size(int size)
 280 {
 281         int result;
 282         result = mpipe_calc_size(mpipe_equeue_sizes,
 283                                  RTE_DIM(mpipe_equeue_sizes), size);
 284         return result;
 285 }
 286
 287 static int mpipe_iqueue_size(int size)
 288 {
 289         int result;
 290         result = mpipe_calc_size(mpipe_iqueue_sizes,
 291                                  RTE_DIM(mpipe_iqueue_sizes), size);
 292         return result;
 293 }
 294
 295 static int mpipe_buffer_size_index(int size)
 296 {
 297         int result;
 298         result = mpipe_get_size_index(mpipe_buffer_sizes,
 299                                       RTE_DIM(mpipe_buffer_sizes), size, 0);
 300         return result;
 301 }
 302
 303 static inline int
 304 mpipe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 305                                   struct rte_eth_link *link)
 306 {
 307         struct rte_eth_link *dst = link;
 308         struct rte_eth_link *src = &(dev->data->dev_link);
 309
 310         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 311                                 *(uint64_t *)src) == 0)
 312                 return -1;
 313
 314         return 0;
 315 }
 316
 317 static inline int
 318 mpipe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 319                                    struct rte_eth_link *link)
 320 {
 321         struct rte_eth_link *dst = &(dev->data->dev_link);
 322         struct rte_eth_link *src = link;
 323
 324         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 325                                 *(uint64_t *)src) == 0)
 326                 return -1;
 327
 328         return 0;
 329 }
 330
 331 static void
 332 mpipe_infos_get(struct rte_eth_dev *dev __rte_unused,
 333                 struct rte_eth_dev_info *dev_info)
 334 {
 335         dev_info->min_rx_bufsize  = 128;
 336         dev_info->max_rx_pktlen   = 1518;
 337         dev_info->max_tx_queues   = MPIPE_TX_MAX_QUEUES;
 338         dev_info->max_rx_queues   = MPIPE_RX_MAX_QUEUES;
 339         dev_info->max_mac_addrs   = 1;
 340         dev_info->rx_offload_capa = 0;
 341         dev_info->tx_offload_capa = 0;
 342 }
 343
 344 static int
 345 mpipe_configure(struct rte_eth_dev *dev)
 346 {
 347         struct mpipe_dev_priv *priv = mpipe_priv(dev);
 348
 349         if (dev->data->nb_tx_queues > MPIPE_TX_MAX_QUEUES) {
 350                 RTE_LOG(ERR, PMD, "%s: Too many tx queues: %d > %d\n",
 351                         mpipe_name(priv), dev->data->nb_tx_queues,
 352                         MPIPE_TX_MAX_QUEUES);
 353                 return -EINVAL;
 354         }
 355         priv->nb_tx_queues = dev->data->nb_tx_queues;
 356
 357         if (dev->data->nb_rx_queues > MPIPE_RX_MAX_QUEUES) {
 358                 RTE_LOG(ERR, PMD, "%s: Too many rx queues: %d > %d\n",
 359                         mpipe_name(priv), dev->data->nb_rx_queues,
 360                         MPIPE_RX_MAX_QUEUES);
 361         }
 362         priv->nb_rx_queues = dev->data->nb_rx_queues;
 363
 364         return 0;
 365 }
 366
 367 static inline int
 368 mpipe_link_compare(struct rte_eth_link *link1,
 369                    struct rte_eth_link *link2)
 370 {
 371         return (*(uint64_t *)link1 == *(uint64_t *)link2)
 372                 ? -1 : 0;
 373 }
 374
 375 static int
 376 mpipe_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 377 {
 378         struct mpipe_dev_priv *priv = mpipe_priv(dev);
 379         struct rte_eth_link old, new;
 380         int64_t state, speed;
 381         int count, rc;
 382
 383         memset(&old, 0, sizeof(old));
 384         memset(&new, 0, sizeof(new));
 385         mpipe_dev_atomic_read_link_status(dev, &old);
 386
 387         for (count = 0, rc = 0; count < MPIPE_LINK_UPDATE_TIMEOUT; count++) {
 388                 if (!priv->initialized)
 389                         break;
 390
 391                 state = gxio_mpipe_link_get_attr(&priv->link,
 392                                                  GXIO_MPIPE_LINK_CURRENT_STATE);
 393                 if (state < 0)
 394                         break;
 395
 396                 speed = state & GXIO_MPIPE_LINK_SPEED_MASK;
 397
 398                 if (speed == GXIO_MPIPE_LINK_1G) {
 399                         new.link_speed = ETH_LINK_SPEED_1000;
 400                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 401                         new.link_status = 1;
 402                 } else if (speed == GXIO_MPIPE_LINK_10G) {
 403                         new.link_speed = ETH_LINK_SPEED_10000;
 404                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 405                         new.link_status = 1;
 406                 }
 407
 408                 rc = mpipe_link_compare(&old, &new);
 409                 if (rc == 0 || !wait_to_complete)
 410                         break;
 411
 412                 rte_delay_us(MPIPE_LINK_UPDATE_INTERVAL);
 413         }
 414
 415         mpipe_dev_atomic_write_link_status(dev, &new);
 416         return rc;
 417 }
 418
 419 static int
 420 mpipe_set_link(struct rte_eth_dev *dev, int up)
 421 {
 422         struct mpipe_dev_priv *priv = mpipe_priv(dev);
 423         int rc;
 424
 425         rc = gxio_mpipe_link_set_attr(&priv->link,
 426                                       GXIO_MPIPE_LINK_DESIRED_STATE,
 427                                       up ? GXIO_MPIPE_LINK_ANYSPEED : 0);
 428         if (rc < 0) {
 429                 RTE_LOG(ERR, PMD, "%s: Failed to set link %s.\n",
 430                         mpipe_name(priv), up ? "up" : "down");
 431         } else {
 432                 mpipe_link_update(dev, 0);
 433         }
 434
 435         return rc;
 436 }
 437
 438 static int
 439 mpipe_set_link_up(struct rte_eth_dev *dev)
 440 {
 441         return mpipe_set_link(dev, 1);
 442 }
 443
 444 static int
 445 mpipe_set_link_down(struct rte_eth_dev *dev)
 446 {
 447         return mpipe_set_link(dev, 0);
 448 }
 449
 450 static inline void
 451 mpipe_dp_enter(struct mpipe_dev_priv *priv)
 452 {
 453         __insn_mtspr(SPR_DSTREAM_PF, 0);
 454         rte_atomic32_inc(&priv->dp_count);
 455 }
 456
 457 static inline void
 458 mpipe_dp_exit(struct mpipe_dev_priv *priv)
 459 {
 460         rte_atomic32_dec(&priv->dp_count);
 461 }
 462
 463 static inline void
 464 mpipe_dp_wait(struct mpipe_dev_priv *priv)
 465 {
 466         while (rte_atomic32_read(&priv->dp_count) != 0) {
 467                 rte_pause();
 468         }
 469 }
 470
 471 static inline int
 472 mpipe_mbuf_stack_index(struct mpipe_dev_priv *priv, struct rte_mbuf *mbuf)
 473 {
 474         return (mbuf->port < RTE_MAX_ETHPORTS) ?
 475                 mpipe_priv(&rte_eth_devices[mbuf->port])->stack :
 476                 priv->stack;
 477 }
 478
 479 static inline struct rte_mbuf *
 480 mpipe_recv_mbuf(struct mpipe_dev_priv *priv, gxio_mpipe_idesc_t *idesc,
 481                 int in_port)
 482 {
 483         void *va = gxio_mpipe_idesc_get_va(idesc);
 484         uint16_t size = gxio_mpipe_idesc_get_xfer_size(idesc);
 485         struct rte_mbuf *mbuf = RTE_PTR_SUB(va, priv->rx_offset);
 486
 487         rte_pktmbuf_reset(mbuf);
 488         mbuf->data_off = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;
 489         mbuf->port     = in_port;
 490         mbuf->data_len = size;
 491         mbuf->pkt_len  = size;
 492         mbuf->hash.rss = gxio_mpipe_idesc_get_flow_hash(idesc);
 493
 494         PMD_DEBUG_RX("%s: RX mbuf %p, buffer %p, buf_addr %p, size %d\n",
 495                      mpipe_name(priv), mbuf, va, mbuf->buf_addr, size);
 496
 497         return mbuf;
 498 }
 499
 500 static inline void
 501 mpipe_recv_push(struct mpipe_dev_priv *priv, struct rte_mbuf *mbuf)
 502 {
 503         const int offset = RTE_PKTMBUF_HEADROOM + MPIPE_RX_IP_ALIGN;
 504         void *buf_addr = RTE_PTR_ADD(mbuf->buf_addr, offset);
 505
 506         gxio_mpipe_push_buffer(priv->context, priv->stack, buf_addr);
 507         PMD_DEBUG_RX("%s: Pushed mbuf %p, buffer %p into stack %d\n",
 508                      mpipe_name(priv), mbuf, buf_addr, priv->stack);
 509 }
 510
 511 static inline void
 512 mpipe_recv_fill_stack(struct mpipe_dev_priv *priv, int count)
 513 {
 514         struct rte_mbuf *mbuf;
 515         int i;
 516
 517         for (i = 0; i < count; i++) {
 518                 mbuf = __rte_mbuf_raw_alloc(priv->rx_mpool);
 519                 if (!mbuf)
 520                         break;
 521                 mpipe_recv_push(priv, mbuf);
 522         }
 523
 524         priv->rx_buffers += count;
 525         PMD_DEBUG_RX("%s: Filled %d/%d buffers\n", mpipe_name(priv), i, count);
 526 }
 527
 528 static inline void
 529 mpipe_recv_flush_stack(struct mpipe_dev_priv *priv)
 530 {
 531         const int offset = priv->rx_offset & ~RTE_MEMPOOL_ALIGN_MASK;
 532         uint8_t in_port = priv->port_id;
 533         struct rte_mbuf *mbuf;
 534         unsigned count;
 535         void *va;
 536
 537         for (count = 0; count < priv->rx_buffers; count++) {
 538                 va = gxio_mpipe_pop_buffer(priv->context, priv->stack);
 539                 if (!va)
 540                         break;
 541                 mbuf = RTE_PTR_SUB(va, offset);
 542
 543                 PMD_DEBUG_RX("%s: Flushing mbuf %p, va %p\n",
 544                              mpipe_name(priv), mbuf, va);
 545
 546                 mbuf->data_off    = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;
 547                 mbuf->refcnt      = 1;
 548                 mbuf->nb_segs     = 1;
 549                 mbuf->port        = in_port;
 550                 mbuf->packet_type = 0;
 551                 mbuf->data_len    = 0;
 552                 mbuf->pkt_len     = 0;
 553
 554                 __rte_mbuf_raw_free(mbuf);
 555         }
 556
 557         PMD_DEBUG_RX("%s: Returned %d/%d buffers\n",
 558                      mpipe_name(priv), count, priv->rx_buffers);
 559         priv->rx_buffers -= count;
 560 }
 561
 562 static void
 563 mpipe_register_segment(struct mpipe_dev_priv *priv, const struct rte_memseg *ms)
 564 {
 565         size_t size = ms->hugepage_sz;
 566         uint8_t *addr, *end;
 567         int rc;
 568
 569         for (addr = ms->addr, end = addr + ms->len; addr < end; addr += size) {
 570                 rc = gxio_mpipe_register_page(priv->context, priv->stack, addr,
 571                                               size, 0);
 572                 if (rc < 0)
 573                         break;
 574         }
 575
 576         if (rc < 0) {
 577                 RTE_LOG(ERR, PMD, "%s: Could not register memseg @%p, %d.\n",
 578                         mpipe_name(priv), ms->addr, rc);
 579         } else {
 580                 RTE_LOG(DEBUG, PMD, "%s: Registered segment %p - %p\n",
 581                         mpipe_name(priv), ms->addr,
 582                         RTE_PTR_ADD(ms->addr, ms->len - 1));
 583         }
 584 }
 585
 586 static int
 587 mpipe_recv_init(struct mpipe_dev_priv *priv)
 588 {
 589         const struct rte_memseg *seg = rte_eal_get_physmem_layout();
 590         size_t stack_size;
 591         void *stack_mem;
 592         int rc;
 593
 594         if (!priv->rx_mpool) {
 595                 RTE_LOG(ERR, PMD, "%s: No buffer pool.\n",
 596                         mpipe_name(priv));
 597                 return -ENODEV;
 598         }
 599
 600         /* Allocate one NotifRing for each queue. */
 601         rc = gxio_mpipe_alloc_notif_rings(priv->context, MPIPE_RX_MAX_QUEUES,
 602                                           0, 0);
 603         if (rc < 0) {
 604                 RTE_LOG(ERR, PMD, "%s: Failed to allocate notif rings.\n",
 605                         mpipe_name(priv));
 606                 return rc;
 607         }
 608         priv->first_ring = rc;
 609
 610         /* Allocate a NotifGroup. */
 611         rc = gxio_mpipe_alloc_notif_groups(priv->context, 1, 0, 0);
 612         if (rc < 0) {
 613                 RTE_LOG(ERR, PMD, "%s: Failed to allocate rx group.\n",
 614                         mpipe_name(priv));
 615                 return rc;
 616         }
 617         priv->notif_group = rc;
 618
 619         /* Allocate required buckets. */
 620         rc = gxio_mpipe_alloc_buckets(priv->context, MPIPE_RX_BUCKETS, 0, 0);
 621         if (rc < 0) {
 622                 RTE_LOG(ERR, PMD, "%s: Failed to allocate buckets.\n",
 623                         mpipe_name(priv));
 624                 return rc;
 625         }
 626         priv->first_bucket = rc;
 627
 628         rc = gxio_mpipe_alloc_buffer_stacks(priv->context, 1, 0, 0);
 629         if (rc < 0) {
 630                 RTE_LOG(ERR, PMD, "%s: Failed to allocate buffer stack.\n",
 631                         mpipe_name(priv));
 632                 return rc;
 633         }
 634         priv->stack = rc;
 635
 636         while (seg && seg->addr)
 637                 mpipe_register_segment(priv, seg++);
 638
 639         stack_size = gxio_mpipe_calc_buffer_stack_bytes(MPIPE_RX_STACK_SIZE);
 640         stack_mem = rte_zmalloc(NULL, stack_size, 65536);
 641         if (!stack_mem) {
 642                 RTE_LOG(ERR, PMD, "%s: Failed to allocate buffer memory.\n",
 643                         mpipe_name(priv));
 644                 return -ENOMEM;
 645         } else {
 646                 RTE_LOG(DEBUG, PMD, "%s: Buffer stack memory %p - %p.\n",
 647                         mpipe_name(priv), stack_mem,
 648                         RTE_PTR_ADD(stack_mem, stack_size - 1));
 649         }
 650
 651         rc = gxio_mpipe_init_buffer_stack(priv->context, priv->stack,
 652                                           priv->rx_size_code, stack_mem,
 653                                           stack_size, 0);
 654         if (rc < 0) {
 655                 RTE_LOG(ERR, PMD, "%s: Failed to initialize buffer stack.\n",
 656                         mpipe_name(priv));
 657                 return rc;
 658         }
 659
 660         return 0;
 661 }
 662
 663 static int
 664 mpipe_xmit_init(struct mpipe_dev_priv *priv)
 665 {
 666         size_t ring_size;
 667         void *ring_mem;
 668         int rc;
 669
 670         /* Allocate eDMA ring. */
 671         rc = gxio_mpipe_alloc_edma_rings(priv->context, 1, 0, 0);
 672         if (rc < 0) {
 673                 RTE_LOG(ERR, PMD, "%s: Failed to alloc tx ring.\n",
 674                         mpipe_name(priv));
 675                 return rc;
 676         }
 677         priv->ering = rc;
 678
 679         rc = mpipe_equeue_size(MPIPE_TX_DESCS);
 680         if (rc < 0) {
 681                 RTE_LOG(ERR, PMD, "%s: Cannot allocate %d equeue descs.\n",
 682                         mpipe_name(priv), (int)MPIPE_TX_DESCS);
 683                 return -ENOMEM;
 684         }
 685         priv->equeue_size = rc;
 686
 687         /* Initialize completion array. */
 688         ring_size = sizeof(priv->tx_comps[0]) * priv->equeue_size;
 689         priv->tx_comps = rte_zmalloc(NULL, ring_size, RTE_CACHE_LINE_SIZE);
 690         if (!priv->tx_comps) {
 691                 RTE_LOG(ERR, PMD, "%s: Failed to allocate egress comps.\n",
 692                         mpipe_name(priv));
 693                 return -ENOMEM;
 694         }
 695
 696         /* Allocate eDMA ring memory. */
 697         ring_size = sizeof(gxio_mpipe_edesc_t) * priv->equeue_size;
 698         ring_mem = rte_zmalloc(NULL, ring_size, ring_size);
 699         if (!ring_mem) {
 700                 RTE_LOG(ERR, PMD, "%s: Failed to allocate egress descs.\n",
 701                         mpipe_name(priv));
 702                 return -ENOMEM;
 703         } else {
 704                 RTE_LOG(DEBUG, PMD, "%s: eDMA ring memory %p - %p.\n",
 705                         mpipe_name(priv), ring_mem,
 706                         RTE_PTR_ADD(ring_mem, ring_size - 1));
 707         }
 708
 709         /* Initialize eDMA ring. */
 710         rc = gxio_mpipe_equeue_init(&priv->equeue, priv->context, priv->ering,
 711                                     priv->channel, ring_mem, ring_size, 0);
 712         if (rc < 0) {
 713                 RTE_LOG(ERR, PMD, "%s: Failed to init equeue\n",
 714                         mpipe_name(priv));
 715                 return rc;
 716         }
 717
 718         return 0;
 719 }
 720
 721 static int
 722 mpipe_link_init(struct mpipe_dev_priv *priv)
 723 {
 724         int rc;
 725
 726         /* Open the link. */
 727         rc = gxio_mpipe_link_open(&priv->link, priv->context,
 728                                   mpipe_name(priv), GXIO_MPIPE_LINK_AUTO_NONE);
 729         if (rc < 0) {
 730                 RTE_LOG(ERR, PMD, "%s: Failed to open link.\n",
 731                         mpipe_name(priv));
 732                 return rc;
 733         }
 734
 735         /* Get the channel index. */
 736         rc = gxio_mpipe_link_channel(&priv->link);
 737         if (rc < 0) {
 738                 RTE_LOG(ERR, PMD, "%s: Bad channel\n",
 739                         mpipe_name(priv));
 740                 return rc;
 741         }
 742         priv->channel = rc;
 743
 744         return 0;
 745 }
 746
 747 static int
 748 mpipe_init(struct mpipe_dev_priv *priv)
 749 {
 750         int rc;
 751
 752         if (priv->initialized)
 753                 return 0;
 754
 755         rc = mpipe_recv_init(priv);
 756         if (rc < 0) {
 757                 RTE_LOG(ERR, PMD, "%s: Failed to init rx.\n",
 758                         mpipe_name(priv));
 759                 return rc;
 760         }
 761
 762         rc = mpipe_xmit_init(priv);
 763         if (rc < 0) {
 764                 RTE_LOG(ERR, PMD, "%s: Failed to init tx.\n",
 765                         mpipe_name(priv));
 766                 rte_free(priv);
 767                 return rc;
 768         }
 769
 770         priv->initialized = 1;
 771
 772         return 0;
 773 }
 774
 775 static int
 776 mpipe_start(struct rte_eth_dev *dev)
 777 {
 778         struct mpipe_dev_priv *priv = mpipe_priv(dev);
 779         struct mpipe_channel_config config;
 780         struct mpipe_rx_queue *rx_queue;
 781         struct rte_eth_link eth_link;
 782         unsigned queue, buffers = 0;
 783         size_t ring_size;
 784         void *ring_mem;
 785         int rc;
 786
 787         memset(&eth_link, 0, sizeof(eth_link));
 788         mpipe_dev_atomic_write_link_status(dev, &eth_link);
 789
 790         rc = mpipe_init(priv);
 791         if (rc < 0)
 792                 return rc;
 793
 794         /* Initialize NotifRings. */
 795         for (queue = 0; queue < priv->nb_rx_queues; queue++) {
 796                 rx_queue = mpipe_rx_queue(priv, queue);
 797                 ring_size = rx_queue->q.nb_desc * sizeof(gxio_mpipe_idesc_t);
 798
 799                 ring_mem = rte_malloc(NULL, ring_size, ring_size);
 800                 if (!ring_mem) {
 801                         RTE_LOG(ERR, PMD, "%s: Failed to alloc rx descs.\n",
 802                                 mpipe_name(priv));
 803                         return -ENOMEM;
 804                 } else {
 805                         RTE_LOG(DEBUG, PMD, "%s: iDMA ring %d memory %p - %p.\n",
 806                                 mpipe_name(priv), queue, ring_mem,
 807                                 RTE_PTR_ADD(ring_mem, ring_size - 1));
 808                 }
 809
 810                 rc = gxio_mpipe_iqueue_init(&rx_queue->iqueue, priv->context,
 811                                             priv->first_ring + queue, ring_mem,
 812                                             ring_size, 0);
 813                 if (rc < 0) {
 814                         RTE_LOG(ERR, PMD, "%s: Failed to init rx queue.\n",
 815                                 mpipe_name(priv));
 816                         return rc;
 817                 }
 818
 819                 rx_queue->rx_ring_mem = ring_mem;
 820                 buffers += rx_queue->q.nb_desc;
 821         }
 822
 823         /* Initialize ingress NotifGroup and buckets. */
 824         rc = gxio_mpipe_init_notif_group_and_buckets(priv->context,
 825                         priv->notif_group, priv->first_ring, priv->nb_rx_queues,
 826                         priv->first_bucket, MPIPE_RX_BUCKETS,
 827                         GXIO_MPIPE_BUCKET_STATIC_FLOW_AFFINITY);
 828         if (rc < 0) {
 829                 RTE_LOG(ERR, PMD, "%s: Failed to init group and buckets.\n",
 830                         mpipe_name(priv));
 831                 return rc;
 832         }
 833
 834         /* Configure the classifier to deliver packets from this port. */
 835         config.enable = 1;
 836         config.first_bucket = priv->first_bucket;
 837         config.num_buckets = MPIPE_RX_BUCKETS;
 838         memset(&config.stacks, 0xff, sizeof(config.stacks));
 839         config.stacks.stacks[priv->rx_size_code] = priv->stack;
 840         config.head_room = priv->rx_offset & RTE_MEMPOOL_ALIGN_MASK;
 841
 842         rc = mpipe_channel_config(priv->instance, priv->channel,
 843                                   &config);
 844         if (rc < 0) {
 845                 RTE_LOG(ERR, PMD, "%s: Failed to setup classifier.\n",
 846                         mpipe_name(priv));
 847                 return rc;
 848         }
 849
 850         /* Fill empty buffers into the buffer stack. */
 851         mpipe_recv_fill_stack(priv, buffers);
 852
 853         /* Bring up the link. */
 854         mpipe_set_link_up(dev);
 855
 856         /* Start xmit/recv on queues. */
 857         for (queue = 0; queue < priv->nb_tx_queues; queue++)
 858                 mpipe_tx_queue(priv, queue)->q.link_status = 1;
 859         for (queue = 0; queue < priv->nb_rx_queues; queue++)
 860                 mpipe_rx_queue(priv, queue)->q.link_status = 1;
 861         priv->running = 1;
 862
 863         return 0;
 864 }
 865
 866 static void
 867 mpipe_stop(struct rte_eth_dev *dev)
 868 {
 869         struct mpipe_dev_priv *priv = mpipe_priv(dev);
 870         struct mpipe_channel_config config;
 871         unsigned queue;
 872         int rc;
 873
 874         for (queue = 0; queue < priv->nb_tx_queues; queue++)
 875                 mpipe_tx_queue(priv, queue)->q.link_status = 0;
 876         for (queue = 0; queue < priv->nb_rx_queues; queue++)
 877                 mpipe_rx_queue(priv, queue)->q.link_status = 0;
 878
 879         /* Make sure the link_status writes land. */
 880         rte_wmb();
 881
 882         /*
 883          * Wait for link_status change to register with straggling datapath
 884          * threads.
 885          */
 886         mpipe_dp_wait(priv);
 887
 888         /* Bring down the link. */
 889         mpipe_set_link_down(dev);
 890
 891         /* Remove classifier rules. */
 892         memset(&config, 0, sizeof(config));
 893         rc = mpipe_channel_config(priv->instance, priv->channel,
 894                                   &config);
 895         if (rc < 0) {
 896                 RTE_LOG(ERR, PMD, "%s: Failed to stop classifier.\n",
 897                         mpipe_name(priv));
 898         }
 899
 900         /* Flush completed xmit packets. */
 901         mpipe_xmit_flush(priv);
 902
 903         /* Flush buffer stacks. */
 904         mpipe_recv_flush(priv);
 905
 906         priv->running = 0;
 907 }
 908
 909 static void
 910 mpipe_close(struct rte_eth_dev *dev)
 911 {
 912         struct mpipe_dev_priv *priv = mpipe_priv(dev);
 913         if (priv->running)
 914                 mpipe_stop(dev);
 915 }
 916
 917 static void
 918 mpipe_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 919 {
 920         struct mpipe_dev_priv *priv = mpipe_priv(dev);
 921         struct mpipe_tx_queue *tx_queue;
 922         struct mpipe_rx_queue *rx_queue;
 923         unsigned i;
 924         uint16_t idx;
 925
 926         memset(stats, 0, sizeof(*stats));
 927
 928         for (i = 0; i < priv->nb_tx_queues; i++) {
 929                 tx_queue = mpipe_tx_queue(priv, i);
 930
 931                 stats->opackets += tx_queue->q.stats.packets;
 932                 stats->obytes   += tx_queue->q.stats.bytes;
 933                 stats->oerrors  += tx_queue->q.stats.errors;
 934
 935                 idx = tx_queue->q.stat_idx;
 936                 if (idx != (uint16_t)-1) {
 937                         stats->q_opackets[idx] += tx_queue->q.stats.packets;
 938                         stats->q_obytes[idx]   += tx_queue->q.stats.bytes;
 939                         stats->q_errors[idx]   += tx_queue->q.stats.errors;
 940                 }
 941         }
 942
 943         for (i = 0; i < priv->nb_rx_queues; i++) {
 944                 rx_queue = mpipe_rx_queue(priv, i);
 945
 946                 stats->ipackets  += rx_queue->q.stats.packets;
 947                 stats->ibytes    += rx_queue->q.stats.bytes;
 948                 stats->ierrors   += rx_queue->q.stats.errors;
 949                 stats->rx_nombuf += rx_queue->q.stats.nomem;
 950
 951                 idx = rx_queue->q.stat_idx;
 952                 if (idx != (uint16_t)-1) {
 953                         stats->q_ipackets[idx] += rx_queue->q.stats.packets;
 954                         stats->q_ibytes[idx]   += rx_queue->q.stats.bytes;
 955                         stats->q_errors[idx]   += rx_queue->q.stats.errors;
 956                 }
 957         }
 958 }
 959
 960 static void
 961 mpipe_stats_reset(struct rte_eth_dev *dev)
 962 {
 963         struct mpipe_dev_priv *priv = mpipe_priv(dev);
 964         struct mpipe_tx_queue *tx_queue;
 965         struct mpipe_rx_queue *rx_queue;
 966         unsigned i;
 967
 968         for (i = 0; i < priv->nb_tx_queues; i++) {
 969                 tx_queue = mpipe_tx_queue(priv, i);
 970                 memset(&tx_queue->q.stats, 0, sizeof(tx_queue->q.stats));
 971         }
 972
 973         for (i = 0; i < priv->nb_rx_queues; i++) {
 974                 rx_queue = mpipe_rx_queue(priv, i);
 975                 memset(&rx_queue->q.stats, 0, sizeof(rx_queue->q.stats));
 976         }
 977 }
 978
 979 static int
 980 mpipe_queue_stats_mapping_set(struct rte_eth_dev *dev, uint16_t queue_id,
 981                               uint8_t stat_idx, uint8_t is_rx)
 982 {
 983         struct mpipe_dev_priv *priv = mpipe_priv(dev);
 984
 985         if (is_rx) {
 986                 priv->rx_stat_mapping[stat_idx] = queue_id;
 987         } else {
 988                 priv->tx_stat_mapping[stat_idx] = queue_id;
 989         }
 990
 991         return 0;
 992 }
 993
 994 static int
 995 mpipe_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 996                      uint16_t nb_desc, unsigned int socket_id __rte_unused,
 997                      const struct rte_eth_txconf *tx_conf __rte_unused)
 998 {
 999         struct mpipe_tx_queue *tx_queue = dev->data->tx_queues[queue_idx];
1000         struct mpipe_dev_priv *priv = mpipe_priv(dev);
1001         uint16_t idx;
1002
1003         tx_queue = rte_realloc(tx_queue, sizeof(*tx_queue),
1004                                RTE_CACHE_LINE_SIZE);
1005         if (!tx_queue) {
1006                 RTE_LOG(ERR, PMD, "%s: Failed to allocate TX queue.\n",
1007                         mpipe_name(priv));
1008                 return -ENOMEM;
1009         }
1010
1011         memset(&tx_queue->q, 0, sizeof(tx_queue->q));
1012         tx_queue->q.priv = priv;
1013         tx_queue->q.queue_idx = queue_idx;
1014         tx_queue->q.port_id = dev->data->port_id;
1015         tx_queue->q.nb_desc = nb_desc;
1016
1017         tx_queue->q.stat_idx = -1;
1018         for (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {
1019                 if (priv->tx_stat_mapping[idx] == queue_idx)
1020                         tx_queue->q.stat_idx = idx;
1021         }
1022
1023         dev->data->tx_queues[queue_idx] = tx_queue;
1024
1025         return 0;
1026 }
1027
1028 static void
1029 mpipe_tx_queue_release(void *_txq)
1030 {
1031         rte_free(_txq);
1032 }
1033
1034 static int
1035 mpipe_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1036                      uint16_t nb_desc, unsigned int socket_id __rte_unused,
1037                      const struct rte_eth_rxconf *rx_conf __rte_unused,
1038                      struct rte_mempool *mp)
1039 {
1040         struct mpipe_rx_queue *rx_queue = dev->data->rx_queues[queue_idx];
1041         struct mpipe_dev_priv *priv = mpipe_priv(dev);
1042         uint16_t idx;
1043         int size, rc;
1044
1045         rc = mpipe_iqueue_size(nb_desc);
1046         if (rc < 0) {
1047                 RTE_LOG(ERR, PMD, "%s: Cannot allocate %d iqueue descs.\n",
1048                         mpipe_name(priv), (int)nb_desc);
1049                 return -ENOMEM;
1050         }
1051
1052         if (rc != nb_desc) {
1053                 RTE_LOG(WARNING, PMD, "%s: Extending RX descs from %d to %d.\n",
1054                         mpipe_name(priv), (int)nb_desc, rc);
1055                 nb_desc = rc;
1056         }
1057
1058         size = sizeof(*rx_queue);
1059         rx_queue = rte_realloc(rx_queue, size, RTE_CACHE_LINE_SIZE);
1060         if (!rx_queue) {
1061                 RTE_LOG(ERR, PMD, "%s: Failed to allocate RX queue.\n",
1062                         mpipe_name(priv));
1063                 return -ENOMEM;
1064         }
1065
1066         memset(&rx_queue->q, 0, sizeof(rx_queue->q));
1067         rx_queue->q.priv = priv;
1068         rx_queue->q.nb_desc = nb_desc;
1069         rx_queue->q.port_id = dev->data->port_id;
1070         rx_queue->q.queue_idx = queue_idx;
1071
1072         if (!priv->rx_mpool) {
1073                 int size = (rte_pktmbuf_data_room_size(mp) -
1074                             RTE_PKTMBUF_HEADROOM -
1075                             MPIPE_RX_IP_ALIGN);
1076
1077                 priv->rx_offset = (sizeof(struct rte_mbuf) +
1078                                    rte_pktmbuf_priv_size(mp) +
1079                                    RTE_PKTMBUF_HEADROOM +
1080                                    MPIPE_RX_IP_ALIGN);
1081                 if (size < 0) {
1082                         RTE_LOG(ERR, PMD, "%s: Bad buffer size %d.\n",
1083                                 mpipe_name(priv),
1084                                 rte_pktmbuf_data_room_size(mp));
1085                         return -ENOMEM;
1086                 }
1087
1088                 priv->rx_size_code = mpipe_buffer_size_index(size);
1089                 priv->rx_mpool = mp;
1090         }
1091
1092         if (priv->rx_mpool != mp) {
1093                 RTE_LOG(WARNING, PMD, "%s: Ignoring multiple buffer pools.\n",
1094                         mpipe_name(priv));
1095         }
1096
1097         rx_queue->q.stat_idx = -1;
1098         for (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {
1099                 if (priv->rx_stat_mapping[idx] == queue_idx)
1100                         rx_queue->q.stat_idx = idx;
1101         }
1102
1103         dev->data->rx_queues[queue_idx] = rx_queue;
1104
1105         return 0;
1106 }
1107
1108 static void
1109 mpipe_rx_queue_release(void *_rxq)
1110 {
1111         rte_free(_rxq);
1112 }
1113
1114 #define MPIPE_XGBE_ENA_HASH_MULTI       \
1115         (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_MULTI_SHIFT)
1116 #define MPIPE_XGBE_ENA_HASH_UNI         \
1117         (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_UNI_SHIFT)
1118 #define MPIPE_XGBE_COPY_ALL             \
1119         (1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__COPY_ALL_SHIFT)
1120 #define MPIPE_GBE_ENA_MULTI_HASH        \
1121         (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__MULTI_HASH_ENA_SHIFT)
1122 #define MPIPE_GBE_ENA_UNI_HASH          \
1123         (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__UNI_HASH_ENA_SHIFT)
1124 #define MPIPE_GBE_COPY_ALL              \
1125         (1UL << MPIPE_GBE_NETWORK_CONFIGURATION__COPY_ALL_SHIFT)
1126
1127 static void
1128 mpipe_promiscuous_enable(struct rte_eth_dev *dev)
1129 {
1130         struct mpipe_dev_priv *priv = mpipe_priv(dev);
1131         int64_t reg;
1132         int addr;
1133
1134         if (priv->is_xaui) {
1135                 addr = MPIPE_XAUI_RECEIVE_CONFIGURATION;
1136                 reg  = gxio_mpipe_link_mac_rd(&priv->link, addr);
1137                 reg &= ~MPIPE_XGBE_ENA_HASH_MULTI;
1138                 reg &= ~MPIPE_XGBE_ENA_HASH_UNI;
1139                 reg |=  MPIPE_XGBE_COPY_ALL;
1140                 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1141         } else {
1142                 addr = MPIPE_GBE_NETWORK_CONFIGURATION;
1143                 reg  = gxio_mpipe_link_mac_rd(&priv->link, addr);
1144                 reg &= ~MPIPE_GBE_ENA_MULTI_HASH;
1145                 reg &= ~MPIPE_GBE_ENA_UNI_HASH;
1146                 reg |=  MPIPE_GBE_COPY_ALL;
1147                 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1148         }
1149 }
1150
1151 static void
1152 mpipe_promiscuous_disable(struct rte_eth_dev *dev)
1153 {
1154         struct mpipe_dev_priv *priv = mpipe_priv(dev);
1155         int64_t reg;
1156         int addr;
1157
1158         if (priv->is_xaui) {
1159                 addr = MPIPE_XAUI_RECEIVE_CONFIGURATION;
1160                 reg  = gxio_mpipe_link_mac_rd(&priv->link, addr);
1161                 reg |=  MPIPE_XGBE_ENA_HASH_MULTI;
1162                 reg |=  MPIPE_XGBE_ENA_HASH_UNI;
1163                 reg &= ~MPIPE_XGBE_COPY_ALL;
1164                 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1165         } else {
1166                 addr = MPIPE_GBE_NETWORK_CONFIGURATION;
1167                 reg  = gxio_mpipe_link_mac_rd(&priv->link, addr);
1168                 reg |=  MPIPE_GBE_ENA_MULTI_HASH;
1169                 reg |=  MPIPE_GBE_ENA_UNI_HASH;
1170                 reg &= ~MPIPE_GBE_COPY_ALL;
1171                 gxio_mpipe_link_mac_wr(&priv->link, addr, reg);
1172         }
1173 }
1174
1175 static struct eth_dev_ops mpipe_dev_ops = {
1176         .dev_infos_get           = mpipe_infos_get,
1177         .dev_configure           = mpipe_configure,
1178         .dev_start               = mpipe_start,
1179         .dev_stop                = mpipe_stop,
1180         .dev_close               = mpipe_close,
1181         .stats_get               = mpipe_stats_get,
1182         .stats_reset             = mpipe_stats_reset,
1183         .queue_stats_mapping_set = mpipe_queue_stats_mapping_set,
1184         .tx_queue_setup          = mpipe_tx_queue_setup,
1185         .rx_queue_setup          = mpipe_rx_queue_setup,
1186         .tx_queue_release        = mpipe_tx_queue_release,
1187         .rx_queue_release        = mpipe_rx_queue_release,
1188         .link_update             = mpipe_link_update,
1189         .dev_set_link_up         = mpipe_set_link_up,
1190         .dev_set_link_down       = mpipe_set_link_down,
1191         .promiscuous_enable      = mpipe_promiscuous_enable,
1192         .promiscuous_disable     = mpipe_promiscuous_disable,
1193 };
1194
1195 static inline void
1196 mpipe_xmit_null(struct mpipe_dev_priv *priv, int64_t start, int64_t end)
1197 {
1198         gxio_mpipe_edesc_t null_desc = { { .bound = 1, .ns = 1 } };
1199         gxio_mpipe_equeue_t *equeue = &priv->equeue;
1200         int64_t slot;
1201
1202         for (slot = start; slot < end; slot++) {
1203                 gxio_mpipe_equeue_put_at(equeue, null_desc, slot);
1204         }
1205 }
1206
1207 static void
1208 mpipe_xmit_flush(struct mpipe_dev_priv *priv)
1209 {
1210         gxio_mpipe_equeue_t *equeue = &priv->equeue;
1211         int64_t slot;
1212
1213         /* Post a dummy descriptor and wait for its return. */
1214         slot = gxio_mpipe_equeue_reserve(equeue, 1);
1215         if (slot < 0) {
1216                 RTE_LOG(ERR, PMD, "%s: Failed to reserve stop slot.\n",
1217                         mpipe_name(priv));
1218                 return;
1219         }
1220
1221         mpipe_xmit_null(priv, slot, slot + 1);
1222
1223         while (!gxio_mpipe_equeue_is_complete(equeue, slot, 1)) {
1224                 rte_pause();
1225         }
1226
1227         for (slot = 0; slot < priv->equeue_size; slot++) {
1228                 if (priv->tx_comps[slot])
1229                         rte_pktmbuf_free_seg(priv->tx_comps[slot]);
1230         }
1231 }
1232
1233 static void
1234 mpipe_recv_flush(struct mpipe_dev_priv *priv)
1235 {
1236         uint8_t in_port = priv->port_id;
1237         struct mpipe_rx_queue *rx_queue;
1238         gxio_mpipe_iqueue_t *iqueue;
1239         gxio_mpipe_idesc_t idesc;
1240         struct rte_mbuf *mbuf;
1241         int retries = 0;
1242         unsigned queue;
1243
1244         do {
1245                 mpipe_recv_flush_stack(priv);
1246
1247                 /* Flush packets sitting in recv queues. */
1248                 for (queue = 0; queue < priv->nb_rx_queues; queue++) {
1249                         rx_queue = mpipe_rx_queue(priv, queue);
1250                         iqueue = &rx_queue->iqueue;
1251                         while (gxio_mpipe_iqueue_try_get(iqueue, &idesc) >= 0) {
1252                                 mbuf = mpipe_recv_mbuf(priv, &idesc, in_port);
1253                                 rte_pktmbuf_free(mbuf);
1254                                 priv->rx_buffers--;
1255                         }
1256                         rte_free(rx_queue->rx_ring_mem);
1257                 }
1258         } while (retries++ < 10 && priv->rx_buffers);
1259
1260         if (priv->rx_buffers) {
1261                 RTE_LOG(ERR, PMD, "%s: Leaked %d receive buffers.\n",
1262                         mpipe_name(priv), priv->rx_buffers);
1263         } else {
1264                 PMD_DEBUG_RX("%s: Returned all receive buffers.\n",
1265                              mpipe_name(priv));
1266         }
1267 }
1268
1269 static inline uint16_t
1270 mpipe_do_xmit(struct mpipe_tx_queue *tx_queue, struct rte_mbuf **tx_pkts,
1271               uint16_t nb_pkts)
1272 {
1273         struct mpipe_dev_priv *priv = tx_queue->q.priv;
1274         gxio_mpipe_equeue_t *equeue = &priv->equeue;
1275         unsigned nb_bytes = 0;
1276         unsigned nb_sent = 0;
1277         int nb_slots, i;
1278         uint8_t port_id;
1279
1280         PMD_DEBUG_TX("Trying to transmit %d packets on %s:%d.\n",
1281                      nb_pkts, mpipe_name(tx_queue->q.priv),
1282                      tx_queue->q.queue_idx);
1283
1284         /* Optimistic assumption that we need exactly one slot per packet. */
1285         nb_slots = RTE_MIN(nb_pkts, MPIPE_TX_DESCS / 2);
1286
1287         do {
1288                 struct rte_mbuf *mbuf = NULL, *pkt = NULL;
1289                 int64_t slot;
1290
1291                 /* Reserve eDMA ring slots. */
1292                 slot = gxio_mpipe_equeue_try_reserve_fast(equeue, nb_slots);
1293                 if (unlikely(slot < 0)) {
1294                         break;
1295                 }
1296
1297                 for (i = 0; i < nb_slots; i++) {
1298                         unsigned idx = (slot + i) & (priv->equeue_size - 1);
1299                         rte_prefetch0(priv->tx_comps[idx]);
1300                 }
1301
1302                 /* Fill up slots with descriptor and completion info. */
1303                 for (i = 0; i < nb_slots; i++) {
1304                         unsigned idx = (slot + i) & (priv->equeue_size - 1);
1305                         gxio_mpipe_edesc_t desc;
1306                         struct rte_mbuf *next;
1307
1308                         /* Starting on a new packet? */
1309                         if (likely(!mbuf)) {
1310                                 int room = nb_slots - i;
1311
1312                                 pkt = mbuf = tx_pkts[nb_sent];
1313
1314                                 /* Bail out if we run out of descs. */
1315                                 if (unlikely(pkt->nb_segs > room))
1316                                         break;
1317
1318                                 nb_sent++;
1319                         }
1320
1321                         /* We have a segment to send. */
1322                         next = mbuf->next;
1323
1324                         if (priv->tx_comps[idx])
1325                                 rte_pktmbuf_free_seg(priv->tx_comps[idx]);
1326
1327                         port_id = (mbuf->port < RTE_MAX_ETHPORTS) ?
1328                                                 mbuf->port : priv->port_id;
1329                         desc = (gxio_mpipe_edesc_t) { {
1330                                 .va        = rte_pktmbuf_mtod(mbuf, uintptr_t),
1331                                 .xfer_size = rte_pktmbuf_data_len(mbuf),
1332                                 .bound     = next ? 0 : 1,
1333                                 .stack_idx = mpipe_mbuf_stack_index(priv, mbuf),
1334                         } };
1335                         if (mpipe_local.mbuf_push_debt[port_id] > 0) {
1336                                 mpipe_local.mbuf_push_debt[port_id]--;
1337                                 desc.hwb = 1;
1338                                 priv->tx_comps[idx] = NULL;
1339                         } else
1340                                 priv->tx_comps[idx] = mbuf;
1341
1342                         nb_bytes += mbuf->data_len;
1343                         gxio_mpipe_equeue_put_at(equeue, desc, slot + i);
1344
1345                         PMD_DEBUG_TX("%s:%d: Sending packet %p, len %d\n",
1346                                      mpipe_name(priv),
1347                                      tx_queue->q.queue_idx,
1348                                      rte_pktmbuf_mtod(mbuf, void *),
1349                                      rte_pktmbuf_data_len(mbuf));
1350
1351                         mbuf = next;
1352                 }
1353
1354                 if (unlikely(nb_sent < nb_pkts)) {
1355
1356                         /* Fill remaining slots with null descriptors. */
1357                         mpipe_xmit_null(priv, slot + i, slot + nb_slots);
1358
1359                         /*
1360                          * Calculate exact number of descriptors needed for
1361                          * the next go around.
1362                          */
1363                         nb_slots = 0;
1364                         for (i = nb_sent; i < nb_pkts; i++) {
1365                                 nb_slots += tx_pkts[i]->nb_segs;
1366                         }
1367
1368                         nb_slots = RTE_MIN(nb_slots, MPIPE_TX_DESCS / 2);
1369                 }
1370         } while (nb_sent < nb_pkts);
1371
1372         tx_queue->q.stats.packets += nb_sent;
1373         tx_queue->q.stats.bytes   += nb_bytes;
1374
1375         return nb_sent;
1376 }
1377
1378 static inline uint16_t
1379 mpipe_do_recv(struct mpipe_rx_queue *rx_queue, struct rte_mbuf **rx_pkts,
1380               uint16_t nb_pkts)
1381 {
1382         struct mpipe_dev_priv *priv = rx_queue->q.priv;
1383         gxio_mpipe_iqueue_t *iqueue = &rx_queue->iqueue;
1384         gxio_mpipe_idesc_t *first_idesc, *idesc, *last_idesc;
1385         uint8_t in_port = rx_queue->q.port_id;
1386         const unsigned look_ahead = 8;
1387         int room = nb_pkts, rc = 0;
1388         unsigned nb_packets = 0;
1389         unsigned nb_dropped = 0;
1390         unsigned nb_nomem = 0;
1391         unsigned nb_bytes = 0;
1392         unsigned nb_descs, i;
1393
1394         while (room && !rc) {
1395                 if (rx_queue->avail_descs < room) {
1396                         rc = gxio_mpipe_iqueue_try_peek(iqueue,
1397                                                         &rx_queue->next_desc);
1398                         rx_queue->avail_descs = rc < 0 ? 0 : rc;
1399                 }
1400
1401                 if (unlikely(!rx_queue->avail_descs)) {
1402                         break;
1403                 }
1404
1405                 nb_descs = RTE_MIN(room, rx_queue->avail_descs);
1406
1407                 first_idesc = rx_queue->next_desc;
1408                 last_idesc  = first_idesc + nb_descs;
1409
1410                 rx_queue->next_desc   += nb_descs;
1411                 rx_queue->avail_descs -= nb_descs;
1412
1413                 for (i = 1; i < look_ahead; i++) {
1414                         rte_prefetch0(first_idesc + i);
1415                 }
1416
1417                 PMD_DEBUG_RX("%s:%d: Trying to receive %d packets\n",
1418                              mpipe_name(rx_queue->q.priv),
1419                              rx_queue->q.queue_idx,
1420                              nb_descs);
1421
1422                 for (idesc = first_idesc; idesc < last_idesc; idesc++) {
1423                         struct rte_mbuf *mbuf;
1424
1425                         PMD_DEBUG_RX("%s:%d: processing idesc %d/%d\n",
1426                                      mpipe_name(priv),
1427                                      rx_queue->q.queue_idx,
1428                                      nb_packets, nb_descs);
1429
1430                         rte_prefetch0(idesc + look_ahead);
1431
1432                         PMD_DEBUG_RX("%s:%d: idesc %p, %s%s%s%s%s%s%s%s%s%s"
1433                                      "size: %d, bkt: %d, chan: %d, ring: %d, sqn: %lu, va: %lu\n",
1434                                      mpipe_name(priv),
1435                                      rx_queue->q.queue_idx,
1436                                      idesc,
1437                                      idesc->me ? "me, " : "",
1438                                      idesc->tr ? "tr, " : "",
1439                                      idesc->ce ? "ce, " : "",
1440                                      idesc->ct ? "ct, " : "",
1441                                      idesc->cs ? "cs, " : "",
1442                                      idesc->nr ? "nr, " : "",
1443                                      idesc->sq ? "sq, " : "",
1444                                      idesc->ts ? "ts, " : "",
1445                                      idesc->ps ? "ps, " : "",
1446                                      idesc->be ? "be, " : "",
1447                                      idesc->l2_size,
1448                                      idesc->bucket_id,
1449                                      idesc->channel,
1450                                      idesc->notif_ring,
1451                                      (unsigned long)idesc->packet_sqn,
1452                                      (unsigned long)idesc->va);
1453
1454                         if (unlikely(gxio_mpipe_idesc_has_error(idesc))) {
1455                                 nb_dropped++;
1456                                 gxio_mpipe_iqueue_drop(iqueue, idesc);
1457                                 PMD_DEBUG_RX("%s:%d: Descriptor error\n",
1458                                              mpipe_name(rx_queue->q.priv),
1459                                              rx_queue->q.queue_idx);
1460                                 continue;
1461                         }
1462
1463                         if (mpipe_local.mbuf_push_debt[in_port] <
1464                                         MPIPE_BUF_DEBT_THRESHOLD)
1465                                 mpipe_local.mbuf_push_debt[in_port]++;
1466                         else {
1467                                 mbuf = __rte_mbuf_raw_alloc(priv->rx_mpool);
1468                                 if (unlikely(!mbuf)) {
1469                                         nb_nomem++;
1470                                         gxio_mpipe_iqueue_drop(iqueue, idesc);
1471                                         PMD_DEBUG_RX("%s:%d: alloc failure\n",
1472                                              mpipe_name(rx_queue->q.priv),
1473                                              rx_queue->q.queue_idx);
1474                                         continue;
1475                                 }
1476
1477                                 mpipe_recv_push(priv, mbuf);
1478                         }
1479
1480                         /* Get and setup the mbuf for the received packet. */
1481                         mbuf = mpipe_recv_mbuf(priv, idesc, in_port);
1482
1483                         /* Update results and statistics counters. */
1484                         rx_pkts[nb_packets] = mbuf;
1485                         nb_bytes += mbuf->pkt_len;
1486                         nb_packets++;
1487                 }
1488
1489                 /*
1490                  * We release the ring in bursts, but do not track and release
1491                  * buckets.  This therefore breaks dynamic flow affinity, but
1492                  * we always operate in static affinity mode, and so we're OK
1493                  * with this optimization.
1494                  */
1495                 gxio_mpipe_iqueue_advance(iqueue, nb_descs);
1496                 gxio_mpipe_credit(iqueue->context, iqueue->ring, -1, nb_descs);
1497
1498                 /*
1499                  * Go around once more if we haven't yet peeked the queue, and
1500                  * if we have more room to receive.
1501                  */
1502                 room = nb_pkts - nb_packets;
1503         }
1504
1505         rx_queue->q.stats.packets += nb_packets;
1506         rx_queue->q.stats.bytes   += nb_bytes;
1507         rx_queue->q.stats.errors  += nb_dropped;
1508         rx_queue->q.stats.nomem   += nb_nomem;
1509
1510         PMD_DEBUG_RX("%s:%d: RX: %d/%d pkts/bytes, %d/%d drops/nomem\n",
1511                      mpipe_name(rx_queue->q.priv), rx_queue->q.queue_idx,
1512                      nb_packets, nb_bytes, nb_dropped, nb_nomem);
1513
1514         return nb_packets;
1515 }
1516
1517 static uint16_t
1518 mpipe_recv_pkts(void *_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1519 {
1520         struct mpipe_rx_queue *rx_queue = _rxq;
1521         uint16_t result = 0;
1522
1523         if (rx_queue) {
1524                 mpipe_dp_enter(rx_queue->q.priv);
1525                 if (likely(rx_queue->q.link_status))
1526                         result = mpipe_do_recv(rx_queue, rx_pkts, nb_pkts);
1527                 mpipe_dp_exit(rx_queue->q.priv);
1528         }
1529
1530         return result;
1531 }
1532
1533 static uint16_t
1534 mpipe_xmit_pkts(void *_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1535 {
1536         struct mpipe_tx_queue *tx_queue = _txq;
1537         uint16_t result = 0;
1538
1539         if (tx_queue) {
1540                 mpipe_dp_enter(tx_queue->q.priv);
1541                 if (likely(tx_queue->q.link_status))
1542                         result = mpipe_do_xmit(tx_queue, tx_pkts, nb_pkts);
1543                 mpipe_dp_exit(tx_queue->q.priv);
1544         }
1545
1546         return result;
1547 }
1548
1549 static int
1550 mpipe_link_mac(const char *ifname, uint8_t *mac)
1551 {
1552         int rc, idx;
1553         char name[GXIO_MPIPE_LINK_NAME_LEN];
1554
1555         for (idx = 0, rc = 0; !rc; idx++) {
1556                 rc = gxio_mpipe_link_enumerate_mac(idx, name, mac);
1557                 if (!rc && !strncmp(name, ifname, GXIO_MPIPE_LINK_NAME_LEN))
1558                         return 0;
1559         }
1560         return -ENODEV;
1561 }
1562
1563 static int
1564 rte_pmd_mpipe_devinit(const char *ifname,
1565                       const char *params __rte_unused)
1566 {
1567         gxio_mpipe_context_t *context;
1568         struct rte_eth_dev *eth_dev;
1569         struct mpipe_dev_priv *priv;
1570         int instance, rc;
1571         uint8_t *mac;
1572
1573         /* Get the mPIPE instance that the device belongs to. */
1574         instance = gxio_mpipe_link_instance(ifname);
1575         context = mpipe_context(instance);
1576         if (!context) {
1577                 RTE_LOG(ERR, PMD, "%s: No device for link.\n", ifname);
1578                 return -ENODEV;
1579         }
1580
1581         priv = rte_zmalloc(NULL, sizeof(*priv), 0);
1582         if (!priv) {
1583                 RTE_LOG(ERR, PMD, "%s: Failed to allocate priv.\n", ifname);
1584                 return -ENOMEM;
1585         }
1586
1587         memset(&priv->tx_stat_mapping, 0xff, sizeof(priv->tx_stat_mapping));
1588         memset(&priv->rx_stat_mapping, 0xff, sizeof(priv->rx_stat_mapping));
1589         priv->context = context;
1590         priv->instance = instance;
1591         priv->is_xaui = (strncmp(ifname, "xgbe", 4) == 0);
1592         priv->channel = -1;
1593
1594         mac = priv->mac_addr.addr_bytes;
1595         rc = mpipe_link_mac(ifname, mac);
1596         if (rc < 0) {
1597                 RTE_LOG(ERR, PMD, "%s: Failed to enumerate link.\n", ifname);
1598                 rte_free(priv);
1599                 return -ENODEV;
1600         }
1601
1602         eth_dev = rte_eth_dev_allocate(ifname, RTE_ETH_DEV_VIRTUAL);
1603         if (!eth_dev) {
1604                 RTE_LOG(ERR, PMD, "%s: Failed to allocate device.\n", ifname);
1605                 rte_free(priv);
1606                 return -ENOMEM;
1607         }
1608
1609         RTE_LOG(INFO, PMD, "%s: Initialized mpipe device"
1610                 "(mac %02x:%02x:%02x:%02x:%02x:%02x).\n",
1611                 ifname, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
1612
1613         priv->eth_dev = eth_dev;
1614         priv->port_id = eth_dev->data->port_id;
1615         eth_dev->data->dev_private = priv;
1616         eth_dev->data->mac_addrs = &priv->mac_addr;
1617
1618         eth_dev->data->dev_flags = 0;
1619         eth_dev->data->kdrv = RTE_KDRV_NONE;
1620         eth_dev->driver = NULL;
1621         eth_dev->data->drv_name = drivername;
1622         eth_dev->data->numa_node = instance;
1623
1624         eth_dev->dev_ops      = &mpipe_dev_ops;
1625         eth_dev->rx_pkt_burst = &mpipe_recv_pkts;
1626         eth_dev->tx_pkt_burst = &mpipe_xmit_pkts;
1627
1628         rc = mpipe_link_init(priv);
1629         if (rc < 0) {
1630                 RTE_LOG(ERR, PMD, "%s: Failed to init link.\n",
1631                         mpipe_name(priv));
1632                 return rc;
1633         }
1634
1635         return 0;
1636 }
1637
1638 static struct rte_driver pmd_mpipe_xgbe_drv = {
1639         .name = "xgbe",
1640         .type = PMD_VDEV,
1641         .init = rte_pmd_mpipe_devinit,
1642 };
1643
1644 static struct rte_driver pmd_mpipe_gbe_drv = {
1645         .name = "gbe",
1646         .type = PMD_VDEV,
1647         .init = rte_pmd_mpipe_devinit,
1648 };
1649
1650 PMD_REGISTER_DRIVER(pmd_mpipe_xgbe_drv);
1651 PMD_REGISTER_DRIVER(pmd_mpipe_gbe_drv);
1652
1653 static void __attribute__((constructor, used))
1654 mpipe_init_contexts(void)
1655 {
1656         struct mpipe_context *context;
1657         int rc, instance;
1658
1659         for (instance = 0; instance < GXIO_MPIPE_INSTANCE_MAX; instance++) {
1660                 context = &mpipe_contexts[instance];
1661
1662                 rte_spinlock_init(&context->lock);
1663                 rc = gxio_mpipe_init(&context->context, instance);
1664                 if (rc < 0)
1665                         break;
1666         }
1667
1668         mpipe_instances = instance;
1669 }