4 * Copyright(c) 2017 Marvell International Ltd.
5 * Copyright(c) 2017 Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <rte_ethdev.h>
36 #include <rte_kvargs.h>
38 #include <rte_malloc.h>
39 #include <rte_bus_vdev.h>
41 /* Unluckily, container_of is defined by both DPDK and MUSDK,
42 * we'll declare only one version.
44 * Note that it is not used in this PMD anyway.
51 #include <linux/ethtool.h>
52 #include <linux/sockios.h>
54 #include <net/if_arp.h>
55 #include <sys/ioctl.h>
56 #include <sys/socket.h>
58 #include <sys/types.h>
60 #include "mrvl_ethdev.h"
63 /* bitmask with reserved hifs */
64 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
65 /* bitmask with reserved bpools */
66 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
67 /* bitmask with reserved kernel RSS tables */
68 #define MRVL_MUSDK_RSS_RESERVED 0x01
69 /* maximum number of available hifs */
70 #define MRVL_MUSDK_HIFS_MAX 9
73 #define MRVL_MUSDK_PREFETCH_SHIFT 2
75 /* TCAM has 25 entries reserved for uc/mc filter entries */
76 #define MRVL_MAC_ADDRS_MAX 25
77 #define MRVL_MATCH_LEN 16
78 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
79 /* Maximum allowable packet size */
80 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
82 #define MRVL_IFACE_NAME_ARG "iface"
83 #define MRVL_CFG_ARG "cfg"
85 #define MRVL_BURST_SIZE 64
87 #define MRVL_ARP_LENGTH 28
89 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
91 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
92 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
94 /* Memory size (in bytes) for MUSDK dma buffers */
95 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
97 static const char * const valid_args[] = {
103 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
104 static struct pp2_hif *hifs[RTE_MAX_LCORE];
105 static int used_bpools[PP2_NUM_PKT_PROC] = {
106 MRVL_MUSDK_BPOOLS_RESERVED,
107 MRVL_MUSDK_BPOOLS_RESERVED
110 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
111 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
112 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
115 * To use buffer harvesting based on loopback port shadow queue structure
116 * was introduced for buffers information bookkeeping.
118 * Before sending the packet, related buffer information (pp2_buff_inf) is
119 * stored in shadow queue. After packet is transmitted no longer used
120 * packet buffer is released back to it's original hardware pool,
121 * on condition it originated from interface.
122 * In case it was generated by application itself i.e: mbuf->port field is
123 * 0xff then its released to software mempool.
125 struct mrvl_shadow_txq {
126 int head; /* write index - used when sending buffers */
127 int tail; /* read index - used when releasing buffers */
128 u16 size; /* queue occupied size */
129 u16 num_to_release; /* number of buffers sent, that can be released */
130 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
134 struct mrvl_priv *priv;
135 struct rte_mempool *mp;
144 struct mrvl_priv *priv;
151 * Every tx queue should have dedicated shadow tx queue.
153 * Ports assigned by DPDK might not start at zero or be continuous so
154 * as a workaround define shadow queues for each possible port so that
155 * we eventually fit somewhere.
157 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_ETHPORTS][RTE_MAX_LCORE];
159 /** Number of ports configured. */
161 static int mrvl_lcore_first;
162 static int mrvl_lcore_last;
165 mrvl_get_bpool_size(int pp2_id, int pool_id)
170 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
171 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
177 mrvl_reserve_bit(int *bitmap, int max)
179 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
190 * Configure rss based on dpdk rss configuration.
193 * Pointer to private structure.
195 * Pointer to RSS configuration.
198 * 0 on success, negative error value otherwise.
201 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
203 if (rss_conf->rss_key)
204 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
206 if (rss_conf->rss_hf == 0) {
207 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
208 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
209 priv->ppio_params.inqs_params.hash_type =
210 PP2_PPIO_HASH_T_2_TUPLE;
211 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
212 priv->ppio_params.inqs_params.hash_type =
213 PP2_PPIO_HASH_T_5_TUPLE;
214 priv->rss_hf_tcp = 1;
215 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
216 priv->ppio_params.inqs_params.hash_type =
217 PP2_PPIO_HASH_T_5_TUPLE;
218 priv->rss_hf_tcp = 0;
227 * Ethernet device configuration.
229 * Prepare the driver for a given number of TX and RX queues and
233 * Pointer to Ethernet device structure.
236 * 0 on success, negative error value otherwise.
239 mrvl_dev_configure(struct rte_eth_dev *dev)
241 struct mrvl_priv *priv = dev->data->dev_private;
244 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
245 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
246 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
247 dev->data->dev_conf.rxmode.mq_mode);
251 if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
253 "L2 CRC stripping is always enabled in hw\n");
254 dev->data->dev_conf.rxmode.hw_strip_crc = 1;
257 if (dev->data->dev_conf.rxmode.hw_vlan_strip) {
258 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
262 if (dev->data->dev_conf.rxmode.split_hdr_size) {
263 RTE_LOG(INFO, PMD, "Split headers not supported\n");
267 if (dev->data->dev_conf.rxmode.enable_scatter) {
268 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
272 if (dev->data->dev_conf.rxmode.enable_lro) {
273 RTE_LOG(INFO, PMD, "LRO not supported\n");
277 if (dev->data->dev_conf.rxmode.jumbo_frame)
278 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
279 ETHER_HDR_LEN - ETHER_CRC_LEN;
281 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
282 dev->data->nb_rx_queues);
286 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
287 priv->ppio_params.maintain_stats = 1;
288 priv->nb_rx_queues = dev->data->nb_rx_queues;
290 if (dev->data->nb_rx_queues == 1 &&
291 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
292 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
293 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
298 return mrvl_configure_rss(priv,
299 &dev->data->dev_conf.rx_adv_conf.rss_conf);
303 * DPDK callback to change the MTU.
305 * Setting the MTU affects hardware MRU (packets larger than the MRU
309 * Pointer to Ethernet device structure.
314 * 0 on success, negative error value otherwise.
317 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
319 struct mrvl_priv *priv = dev->data->dev_private;
320 /* extra MV_MH_SIZE bytes are required for Marvell tag */
321 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
324 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
330 ret = pp2_ppio_set_mru(priv->ppio, mru);
334 return pp2_ppio_set_mtu(priv->ppio, mtu);
338 * DPDK callback to bring the link up.
341 * Pointer to Ethernet device structure.
344 * 0 on success, negative error value otherwise.
347 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
349 struct mrvl_priv *priv = dev->data->dev_private;
355 ret = pp2_ppio_enable(priv->ppio);
360 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
361 * as pp2_ppio_enable() changes port->t_mode from default 0 to
362 * PP2_TRAFFIC_INGRESS_EGRESS.
364 * Set mtu to default DPDK value here.
366 ret = mrvl_mtu_set(dev, dev->data->mtu);
368 pp2_ppio_disable(priv->ppio);
374 * DPDK callback to bring the link down.
377 * Pointer to Ethernet device structure.
380 * 0 on success, negative error value otherwise.
383 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
385 struct mrvl_priv *priv = dev->data->dev_private;
390 return pp2_ppio_disable(priv->ppio);
394 * DPDK callback to start the device.
397 * Pointer to Ethernet device structure.
400 * 0 on success, negative errno value on failure.
403 mrvl_dev_start(struct rte_eth_dev *dev)
405 struct mrvl_priv *priv = dev->data->dev_private;
406 char match[MRVL_MATCH_LEN];
409 snprintf(match, sizeof(match), "ppio-%d:%d",
410 priv->pp_id, priv->ppio_id);
411 priv->ppio_params.match = match;
414 * Calculate the maximum bpool size for refill feature to 1.5 of the
415 * configured size. In case the bpool size will exceed this value,
416 * superfluous buffers will be removed
418 priv->bpool_max_size = priv->bpool_init_size +
419 (priv->bpool_init_size >> 1);
421 * Calculate the minimum bpool size for refill feature as follows:
422 * 2 default burst sizes multiply by number of rx queues.
423 * If the bpool size will be below this value, new buffers will
424 * be added to the pool.
426 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
428 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
430 RTE_LOG(ERR, PMD, "Failed to init ppio\n");
435 * In case there are some some stale uc/mc mac addresses flush them
436 * here. It cannot be done during mrvl_dev_close() as port information
437 * is already gone at that point (due to pp2_ppio_deinit() in
440 if (!priv->uc_mc_flushed) {
441 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
444 "Failed to flush uc/mc filter list\n");
447 priv->uc_mc_flushed = 1;
450 if (!priv->vlan_flushed) {
451 ret = pp2_ppio_flush_vlan(priv->ppio);
453 RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
456 * once pp2_ppio_flush_vlan() is supported jump to out
460 priv->vlan_flushed = 1;
463 /* For default QoS config, don't start classifier. */
465 ret = mrvl_start_qos_mapping(priv);
467 RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n");
472 ret = mrvl_dev_set_link_up(dev);
474 RTE_LOG(ERR, PMD, "Failed to set link up\n");
480 RTE_LOG(ERR, PMD, "Failed to start device\n");
481 pp2_ppio_deinit(priv->ppio);
486 * Flush receive queues.
489 * Pointer to Ethernet device structure.
492 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
496 RTE_LOG(INFO, PMD, "Flushing rx queues\n");
497 for (i = 0; i < dev->data->nb_rx_queues; i++) {
501 struct mrvl_rxq *q = dev->data->rx_queues[i];
502 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
504 num = MRVL_PP2_RXD_MAX;
505 ret = pp2_ppio_recv(q->priv->ppio,
506 q->priv->rxq_map[q->queue_id].tc,
507 q->priv->rxq_map[q->queue_id].inq,
508 descs, (uint16_t *)&num);
509 } while (ret == 0 && num);
514 * Flush transmit shadow queues.
517 * Pointer to Ethernet device structure.
520 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
524 RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
525 for (i = 0; i < RTE_MAX_LCORE; i++) {
526 struct mrvl_shadow_txq *sq =
527 &shadow_txqs[dev->data->port_id][i];
529 while (sq->tail != sq->head) {
530 uint64_t addr = cookie_addr_high |
531 sq->ent[sq->tail].buff.cookie;
532 rte_pktmbuf_free((struct rte_mbuf *)addr);
533 sq->tail = (sq->tail + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
536 memset(sq, 0, sizeof(*sq));
541 * Flush hardware bpool (buffer-pool).
544 * Pointer to Ethernet device structure.
547 mrvl_flush_bpool(struct rte_eth_dev *dev)
549 struct mrvl_priv *priv = dev->data->dev_private;
553 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
555 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
560 struct pp2_buff_inf inf;
563 ret = pp2_bpool_get_buff(hifs[rte_lcore_id()], priv->bpool,
568 addr = cookie_addr_high | inf.cookie;
569 rte_pktmbuf_free((struct rte_mbuf *)addr);
574 * DPDK callback to stop the device.
577 * Pointer to Ethernet device structure.
580 mrvl_dev_stop(struct rte_eth_dev *dev)
582 struct mrvl_priv *priv = dev->data->dev_private;
584 mrvl_dev_set_link_down(dev);
585 mrvl_flush_rx_queues(dev);
586 mrvl_flush_tx_shadow_queues(dev);
588 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
589 pp2_ppio_deinit(priv->ppio);
594 * DPDK callback to close the device.
597 * Pointer to Ethernet device structure.
600 mrvl_dev_close(struct rte_eth_dev *dev)
602 struct mrvl_priv *priv = dev->data->dev_private;
605 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
606 struct pp2_ppio_tc_params *tc_params =
607 &priv->ppio_params.inqs_params.tcs_params[i];
609 if (tc_params->inqs_params) {
610 rte_free(tc_params->inqs_params);
611 tc_params->inqs_params = NULL;
615 mrvl_flush_bpool(dev);
619 * DPDK callback to retrieve physical link information.
622 * Pointer to Ethernet device structure.
623 * @param wait_to_complete
624 * Wait for request completion (ignored).
627 * 0 on success, negative error value otherwise.
630 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
634 * once MUSDK provides necessary API use it here
636 struct mrvl_priv *priv = dev->data->dev_private;
637 struct ethtool_cmd edata;
639 int ret, fd, link_up;
644 edata.cmd = ETHTOOL_GSET;
646 strcpy(req.ifr_name, dev->data->name);
647 req.ifr_data = (void *)&edata;
649 fd = socket(AF_INET, SOCK_DGRAM, 0);
653 ret = ioctl(fd, SIOCETHTOOL, &req);
661 switch (ethtool_cmd_speed(&edata)) {
663 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
666 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
669 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
672 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
675 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
678 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
679 ETH_LINK_HALF_DUPLEX;
680 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
682 pp2_ppio_get_link_state(priv->ppio, &link_up);
683 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
689 * DPDK callback to enable promiscuous mode.
692 * Pointer to Ethernet device structure.
695 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
697 struct mrvl_priv *priv = dev->data->dev_private;
703 ret = pp2_ppio_set_promisc(priv->ppio, 1);
705 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
709 * DPDK callback to enable allmulti mode.
712 * Pointer to Ethernet device structure.
715 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
717 struct mrvl_priv *priv = dev->data->dev_private;
723 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
725 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
729 * DPDK callback to disable promiscuous mode.
732 * Pointer to Ethernet device structure.
735 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
737 struct mrvl_priv *priv = dev->data->dev_private;
743 ret = pp2_ppio_set_promisc(priv->ppio, 0);
745 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
749 * DPDK callback to disable allmulticast mode.
752 * Pointer to Ethernet device structure.
755 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
757 struct mrvl_priv *priv = dev->data->dev_private;
763 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
765 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
769 * DPDK callback to remove a MAC address.
772 * Pointer to Ethernet device structure.
777 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
779 struct mrvl_priv *priv = dev->data->dev_private;
780 char buf[ETHER_ADDR_FMT_SIZE];
786 ret = pp2_ppio_remove_mac_addr(priv->ppio,
787 dev->data->mac_addrs[index].addr_bytes);
789 ether_format_addr(buf, sizeof(buf),
790 &dev->data->mac_addrs[index]);
791 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
796 * DPDK callback to add a MAC address.
799 * Pointer to Ethernet device structure.
801 * MAC address to register.
805 * VMDq pool index to associate address with (unused).
808 * 0 on success, negative error value otherwise.
811 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
812 uint32_t index, uint32_t vmdq __rte_unused)
814 struct mrvl_priv *priv = dev->data->dev_private;
815 char buf[ETHER_ADDR_FMT_SIZE];
819 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
826 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
827 * parameter uc_filter_max. Maximum number of mc addresses is then
828 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
831 * If more than uc_filter_max uc addresses were added to filter list
832 * then NIC will switch to promiscuous mode automatically.
834 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
835 * were added to filter list then NIC will switch to all-multicast mode
838 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
840 ether_format_addr(buf, sizeof(buf), mac_addr);
841 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
849 * DPDK callback to set the primary MAC address.
852 * Pointer to Ethernet device structure.
854 * MAC address to register.
857 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
859 struct mrvl_priv *priv = dev->data->dev_private;
865 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
867 char buf[ETHER_ADDR_FMT_SIZE];
868 ether_format_addr(buf, sizeof(buf), mac_addr);
869 RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf);
874 * DPDK callback to get device statistics.
877 * Pointer to Ethernet device structure.
879 * Stats structure output buffer.
882 * 0 on success, negative error value otherwise.
885 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
887 struct mrvl_priv *priv = dev->data->dev_private;
888 struct pp2_ppio_statistics ppio_stats;
889 uint64_t drop_mac = 0;
890 unsigned int i, idx, ret;
895 for (i = 0; i < dev->data->nb_rx_queues; i++) {
896 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
897 struct pp2_ppio_inq_statistics rx_stats;
903 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
905 "rx queue %d stats out of range (0 - %d)\n",
906 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
910 ret = pp2_ppio_inq_get_statistics(priv->ppio,
911 priv->rxq_map[idx].tc,
912 priv->rxq_map[idx].inq,
916 "Failed to update rx queue %d stats\n", idx);
920 stats->q_ibytes[idx] = rxq->bytes_recv;
921 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
922 stats->q_errors[idx] = rx_stats.drop_early +
923 rx_stats.drop_fullq +
926 stats->ibytes += rxq->bytes_recv;
927 drop_mac += rxq->drop_mac;
930 for (i = 0; i < dev->data->nb_tx_queues; i++) {
931 struct mrvl_txq *txq = dev->data->tx_queues[i];
932 struct pp2_ppio_outq_statistics tx_stats;
938 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
940 "tx queue %d stats out of range (0 - %d)\n",
941 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
944 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
948 "Failed to update tx queue %d stats\n", idx);
952 stats->q_opackets[idx] = tx_stats.deq_desc;
953 stats->q_obytes[idx] = txq->bytes_sent;
954 stats->obytes += txq->bytes_sent;
957 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
959 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
963 stats->ipackets += ppio_stats.rx_packets - drop_mac;
964 stats->opackets += ppio_stats.tx_packets;
965 stats->imissed += ppio_stats.rx_fullq_dropped +
966 ppio_stats.rx_bm_dropped +
967 ppio_stats.rx_early_dropped +
968 ppio_stats.rx_fifo_dropped +
969 ppio_stats.rx_cls_dropped;
970 stats->ierrors = drop_mac;
976 * DPDK callback to clear device statistics.
979 * Pointer to Ethernet device structure.
982 mrvl_stats_reset(struct rte_eth_dev *dev)
984 struct mrvl_priv *priv = dev->data->dev_private;
990 for (i = 0; i < dev->data->nb_rx_queues; i++) {
991 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
993 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
994 priv->rxq_map[i].inq, NULL, 1);
999 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1000 struct mrvl_txq *txq = dev->data->tx_queues[i];
1002 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1003 txq->bytes_sent = 0;
1006 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1010 * DPDK callback to get information about the device.
1013 * Pointer to Ethernet device structure (unused).
1015 * Info structure output buffer.
1018 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1019 struct rte_eth_dev_info *info)
1021 info->speed_capa = ETH_LINK_SPEED_10M |
1022 ETH_LINK_SPEED_100M |
1026 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1027 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1028 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1030 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1031 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1032 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1034 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1035 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1036 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1038 info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME |
1039 DEV_RX_OFFLOAD_VLAN_FILTER |
1040 DEV_RX_OFFLOAD_IPV4_CKSUM |
1041 DEV_RX_OFFLOAD_UDP_CKSUM |
1042 DEV_RX_OFFLOAD_TCP_CKSUM;
1044 info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
1045 DEV_TX_OFFLOAD_UDP_CKSUM |
1046 DEV_TX_OFFLOAD_TCP_CKSUM;
1048 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1049 ETH_RSS_NONFRAG_IPV4_TCP |
1050 ETH_RSS_NONFRAG_IPV4_UDP;
1052 /* By default packets are dropped if no descriptors are available */
1053 info->default_rxconf.rx_drop_en = 1;
1055 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1059 * Return supported packet types.
1062 * Pointer to Ethernet device structure (unused).
1065 * Const pointer to the table with supported packet types.
1067 static const uint32_t *
1068 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1070 static const uint32_t ptypes[] = {
1073 RTE_PTYPE_L3_IPV4_EXT,
1074 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1076 RTE_PTYPE_L3_IPV6_EXT,
1077 RTE_PTYPE_L2_ETHER_ARP,
1086 * DPDK callback to get information about specific receive queue.
1089 * Pointer to Ethernet device structure.
1090 * @param rx_queue_id
1091 * Receive queue index.
1093 * Receive queue information structure.
1095 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1096 struct rte_eth_rxq_info *qinfo)
1098 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1099 struct mrvl_priv *priv = dev->data->dev_private;
1100 int inq = priv->rxq_map[rx_queue_id].inq;
1101 int tc = priv->rxq_map[rx_queue_id].tc;
1102 struct pp2_ppio_tc_params *tc_params =
1103 &priv->ppio_params.inqs_params.tcs_params[tc];
1106 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1110 * DPDK callback to get information about specific transmit queue.
1113 * Pointer to Ethernet device structure.
1114 * @param tx_queue_id
1115 * Transmit queue index.
1117 * Transmit queue information structure.
1119 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1120 struct rte_eth_txq_info *qinfo)
1122 struct mrvl_priv *priv = dev->data->dev_private;
1125 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1129 * DPDK callback to Configure a VLAN filter.
1132 * Pointer to Ethernet device structure.
1134 * VLAN ID to filter.
1139 * 0 on success, negative error value otherwise.
1142 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1144 struct mrvl_priv *priv = dev->data->dev_private;
1149 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1150 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1154 * Release buffers to hardware bpool (buffer-pool)
1157 * Receive queue pointer.
1159 * Number of buffers to release to bpool.
1162 * 0 on success, negative error value otherwise.
1165 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1167 struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
1168 struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
1170 unsigned int core_id = rte_lcore_id();
1171 struct pp2_hif *hif = hifs[core_id];
1172 struct pp2_bpool *bpool = rxq->priv->bpool;
1174 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1178 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1180 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1182 for (i = 0; i < num; i++) {
1183 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1184 != cookie_addr_high) {
1186 "mbuf virtual addr high 0x%lx out of range\n",
1187 (uint64_t)mbufs[i] >> 32);
1191 entries[i].buff.addr =
1192 rte_mbuf_data_iova_default(mbufs[i]);
1193 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1194 entries[i].bpool = bpool;
1197 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1198 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1205 for (; i < num; i++)
1206 rte_pktmbuf_free(mbufs[i]);
1212 * DPDK callback to configure the receive queue.
1215 * Pointer to Ethernet device structure.
1219 * Number of descriptors to configure in queue.
1221 * NUMA socket on which memory must be allocated.
1223 * Thresholds parameters (unused_).
1225 * Memory pool for buffer allocations.
1228 * 0 on success, negative error value otherwise.
1231 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1232 unsigned int socket,
1233 const struct rte_eth_rxconf *conf __rte_unused,
1234 struct rte_mempool *mp)
1236 struct mrvl_priv *priv = dev->data->dev_private;
1237 struct mrvl_rxq *rxq;
1239 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1242 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1244 * Unknown TC mapping, mapping will not have a correct queue.
1246 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1247 idx, priv->ppio_id);
1251 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1252 MRVL_PKT_EFFEC_OFFS;
1253 if (min_size < max_rx_pkt_len) {
1255 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1256 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1257 MRVL_PKT_EFFEC_OFFS,
1262 if (dev->data->rx_queues[idx]) {
1263 rte_free(dev->data->rx_queues[idx]);
1264 dev->data->rx_queues[idx] = NULL;
1267 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1273 rxq->cksum_enabled = dev->data->dev_conf.rxmode.hw_ip_checksum;
1274 rxq->queue_id = idx;
1275 rxq->port_id = dev->data->port_id;
1276 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1278 tc = priv->rxq_map[rxq->queue_id].tc,
1279 inq = priv->rxq_map[rxq->queue_id].inq;
1280 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1283 ret = mrvl_fill_bpool(rxq, desc);
1289 priv->bpool_init_size += desc;
1291 dev->data->rx_queues[idx] = rxq;
1297 * DPDK callback to release the receive queue.
1300 * Generic receive queue pointer.
1303 mrvl_rx_queue_release(void *rxq)
1305 struct mrvl_rxq *q = rxq;
1306 struct pp2_ppio_tc_params *tc_params;
1307 int i, num, tc, inq;
1312 tc = q->priv->rxq_map[q->queue_id].tc;
1313 inq = q->priv->rxq_map[q->queue_id].inq;
1314 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1315 num = tc_params->inqs_params[inq].size;
1316 for (i = 0; i < num; i++) {
1317 struct pp2_buff_inf inf;
1320 pp2_bpool_get_buff(hifs[rte_lcore_id()], q->priv->bpool, &inf);
1321 addr = cookie_addr_high | inf.cookie;
1322 rte_pktmbuf_free((struct rte_mbuf *)addr);
1329 * DPDK callback to configure the transmit queue.
1332 * Pointer to Ethernet device structure.
1334 * Transmit queue index.
1336 * Number of descriptors to configure in the queue.
1338 * NUMA socket on which memory must be allocated.
1340 * Thresholds parameters (unused).
1343 * 0 on success, negative error value otherwise.
1346 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1347 unsigned int socket,
1348 const struct rte_eth_txconf *conf __rte_unused)
1350 struct mrvl_priv *priv = dev->data->dev_private;
1351 struct mrvl_txq *txq;
1353 if (dev->data->tx_queues[idx]) {
1354 rte_free(dev->data->tx_queues[idx]);
1355 dev->data->tx_queues[idx] = NULL;
1358 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1363 txq->queue_id = idx;
1364 txq->port_id = dev->data->port_id;
1365 dev->data->tx_queues[idx] = txq;
1367 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1368 priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1374 * DPDK callback to release the transmit queue.
1377 * Generic transmit queue pointer.
1380 mrvl_tx_queue_release(void *txq)
1382 struct mrvl_txq *q = txq;
1391 * Update RSS hash configuration
1394 * Pointer to Ethernet device structure.
1396 * Pointer to RSS configuration.
1399 * 0 on success, negative error value otherwise.
1402 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1403 struct rte_eth_rss_conf *rss_conf)
1405 struct mrvl_priv *priv = dev->data->dev_private;
1407 return mrvl_configure_rss(priv, rss_conf);
1411 * DPDK callback to get RSS hash configuration.
1414 * Pointer to Ethernet device structure.
1416 * Pointer to RSS configuration.
1422 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1423 struct rte_eth_rss_conf *rss_conf)
1425 struct mrvl_priv *priv = dev->data->dev_private;
1426 enum pp2_ppio_hash_type hash_type =
1427 priv->ppio_params.inqs_params.hash_type;
1429 rss_conf->rss_key = NULL;
1431 if (hash_type == PP2_PPIO_HASH_T_NONE)
1432 rss_conf->rss_hf = 0;
1433 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1434 rss_conf->rss_hf = ETH_RSS_IPV4;
1435 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1436 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1437 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1438 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1443 static const struct eth_dev_ops mrvl_ops = {
1444 .dev_configure = mrvl_dev_configure,
1445 .dev_start = mrvl_dev_start,
1446 .dev_stop = mrvl_dev_stop,
1447 .dev_set_link_up = mrvl_dev_set_link_up,
1448 .dev_set_link_down = mrvl_dev_set_link_down,
1449 .dev_close = mrvl_dev_close,
1450 .link_update = mrvl_link_update,
1451 .promiscuous_enable = mrvl_promiscuous_enable,
1452 .allmulticast_enable = mrvl_allmulticast_enable,
1453 .promiscuous_disable = mrvl_promiscuous_disable,
1454 .allmulticast_disable = mrvl_allmulticast_disable,
1455 .mac_addr_remove = mrvl_mac_addr_remove,
1456 .mac_addr_add = mrvl_mac_addr_add,
1457 .mac_addr_set = mrvl_mac_addr_set,
1458 .mtu_set = mrvl_mtu_set,
1459 .stats_get = mrvl_stats_get,
1460 .stats_reset = mrvl_stats_reset,
1461 .dev_infos_get = mrvl_dev_infos_get,
1462 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1463 .rxq_info_get = mrvl_rxq_info_get,
1464 .txq_info_get = mrvl_txq_info_get,
1465 .vlan_filter_set = mrvl_vlan_filter_set,
1466 .rx_queue_setup = mrvl_rx_queue_setup,
1467 .rx_queue_release = mrvl_rx_queue_release,
1468 .tx_queue_setup = mrvl_tx_queue_setup,
1469 .tx_queue_release = mrvl_tx_queue_release,
1470 .rss_hash_update = mrvl_rss_hash_update,
1471 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1475 * Return packet type information and l3/l4 offsets.
1478 * Pointer to the received packet descriptor.
1485 * Packet type information.
1487 static inline uint64_t
1488 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1489 uint8_t *l3_offset, uint8_t *l4_offset)
1491 enum pp2_inq_l3_type l3_type;
1492 enum pp2_inq_l4_type l4_type;
1493 uint64_t packet_type;
1495 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1496 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1498 packet_type = RTE_PTYPE_L2_ETHER;
1501 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1502 packet_type |= RTE_PTYPE_L3_IPV4;
1504 case PP2_INQ_L3_TYPE_IPV4_OK:
1505 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1507 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1508 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1510 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1511 packet_type |= RTE_PTYPE_L3_IPV6;
1513 case PP2_INQ_L3_TYPE_IPV6_EXT:
1514 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1516 case PP2_INQ_L3_TYPE_ARP:
1517 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1519 * In case of ARP l4_offset is set to wrong value.
1520 * Set it to proper one so that later on mbuf->l3_len can be
1521 * calculated subtracting l4_offset and l3_offset.
1523 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1526 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1531 case PP2_INQ_L4_TYPE_TCP:
1532 packet_type |= RTE_PTYPE_L4_TCP;
1534 case PP2_INQ_L4_TYPE_UDP:
1535 packet_type |= RTE_PTYPE_L4_UDP;
1538 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1546 * Get offload information from the received packet descriptor.
1549 * Pointer to the received packet descriptor.
1552 * Mbuf offload flags.
1554 static inline uint64_t
1555 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1558 enum pp2_inq_desc_status status;
1560 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1561 if (unlikely(status != PP2_DESC_ERR_OK))
1562 flags = PKT_RX_IP_CKSUM_BAD;
1564 flags = PKT_RX_IP_CKSUM_GOOD;
1566 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1567 if (unlikely(status != PP2_DESC_ERR_OK))
1568 flags |= PKT_RX_L4_CKSUM_BAD;
1570 flags |= PKT_RX_L4_CKSUM_GOOD;
1576 * DPDK callback for receive.
1579 * Generic pointer to the receive queue.
1581 * Array to store received packets.
1583 * Maximum number of packets in array.
1586 * Number of packets successfully received.
1589 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1591 struct mrvl_rxq *q = rxq;
1592 struct pp2_ppio_desc descs[nb_pkts];
1593 struct pp2_bpool *bpool;
1594 int i, ret, rx_done = 0;
1596 unsigned int core_id = rte_lcore_id();
1598 if (unlikely(!q->priv->ppio))
1601 bpool = q->priv->bpool;
1603 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1604 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1605 if (unlikely(ret < 0)) {
1606 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1609 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1611 for (i = 0; i < nb_pkts; i++) {
1612 struct rte_mbuf *mbuf;
1613 uint8_t l3_offset, l4_offset;
1614 enum pp2_inq_desc_status status;
1617 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1618 struct pp2_ppio_desc *pref_desc;
1621 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1622 pref_addr = cookie_addr_high |
1623 pp2_ppio_inq_desc_get_cookie(pref_desc);
1624 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1625 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1628 addr = cookie_addr_high |
1629 pp2_ppio_inq_desc_get_cookie(&descs[i]);
1630 mbuf = (struct rte_mbuf *)addr;
1631 rte_pktmbuf_reset(mbuf);
1633 /* drop packet in case of mac, overrun or resource error */
1634 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1635 if (unlikely(status != PP2_DESC_ERR_OK)) {
1636 struct pp2_buff_inf binf = {
1637 .addr = rte_mbuf_data_iova_default(mbuf),
1638 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1641 pp2_bpool_put_buff(hifs[core_id], bpool, &binf);
1642 mrvl_port_bpool_size
1643 [bpool->pp2_id][bpool->id][core_id]++;
1648 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1649 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1650 mbuf->data_len = mbuf->pkt_len;
1651 mbuf->port = q->port_id;
1653 mrvl_desc_to_packet_type_and_offset(&descs[i],
1656 mbuf->l2_len = l3_offset;
1657 mbuf->l3_len = l4_offset - l3_offset;
1659 if (likely(q->cksum_enabled))
1660 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
1662 rx_pkts[rx_done++] = mbuf;
1663 q->bytes_recv += mbuf->pkt_len;
1666 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1667 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1669 if (unlikely(num <= q->priv->bpool_min_size ||
1670 (!rx_done && num < q->priv->bpool_init_size))) {
1671 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1673 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1674 } else if (unlikely(num > q->priv->bpool_max_size)) {
1676 int pkt_to_remove = num - q->priv->bpool_init_size;
1677 struct rte_mbuf *mbuf;
1678 struct pp2_buff_inf buff;
1681 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1682 bpool->pp2_id, q->priv->ppio->port_id,
1683 bpool->id, pkt_to_remove, num,
1684 q->priv->bpool_init_size);
1686 for (i = 0; i < pkt_to_remove; i++) {
1687 pp2_bpool_get_buff(hifs[core_id], bpool, &buff);
1688 mbuf = (struct rte_mbuf *)
1689 (cookie_addr_high | buff.cookie);
1690 rte_pktmbuf_free(mbuf);
1692 mrvl_port_bpool_size
1693 [bpool->pp2_id][bpool->id][core_id] -=
1696 rte_spinlock_unlock(&q->priv->lock);
1703 * Prepare offload information.
1707 * @param packet_type
1708 * Packet type bitfield.
1710 * Pointer to the pp2_ouq_l3_type structure.
1712 * Pointer to the pp2_outq_l4_type structure.
1713 * @param gen_l3_cksum
1714 * Will be set to 1 in case l3 checksum is computed.
1716 * Will be set to 1 in case l4 checksum is computed.
1719 * 0 on success, negative error value otherwise.
1722 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
1723 enum pp2_outq_l3_type *l3_type,
1724 enum pp2_outq_l4_type *l4_type,
1729 * Based on ol_flags prepare information
1730 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
1733 if (ol_flags & PKT_TX_IPV4) {
1734 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
1735 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
1736 } else if (ol_flags & PKT_TX_IPV6) {
1737 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
1738 /* no checksum for ipv6 header */
1741 /* if something different then stop processing */
1745 ol_flags &= PKT_TX_L4_MASK;
1746 if ((packet_type & RTE_PTYPE_L4_TCP) &&
1747 ol_flags == PKT_TX_TCP_CKSUM) {
1748 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
1750 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
1751 ol_flags == PKT_TX_UDP_CKSUM) {
1752 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
1755 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
1756 /* no checksum for other type */
1764 * Release already sent buffers to bpool (buffer-pool).
1767 * Pointer to the port structure.
1769 * Pointer to the MUSDK hardware interface.
1771 * Pointer to the shadow queue.
1775 * Force releasing packets.
1778 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1779 struct mrvl_shadow_txq *sq, int qid, int force)
1781 struct buff_release_entry *entry;
1782 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1783 int i, core_id = rte_lcore_id();
1785 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1787 sq->num_to_release += nb_done;
1789 if (likely(!force &&
1790 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1793 nb_done = sq->num_to_release;
1794 sq->num_to_release = 0;
1796 for (i = 0; i < nb_done; i++) {
1797 entry = &sq->ent[sq->tail + num];
1798 if (unlikely(!entry->buff.addr)) {
1800 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1801 sq->tail, (u64)entry->buff.cookie,
1802 (u64)entry->buff.addr);
1807 if (unlikely(!entry->bpool)) {
1808 struct rte_mbuf *mbuf;
1810 mbuf = (struct rte_mbuf *)
1811 (cookie_addr_high | entry->buff.cookie);
1812 rte_pktmbuf_free(mbuf);
1817 mrvl_port_bpool_size
1818 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
1820 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
1825 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1827 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1833 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1834 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1840 * DPDK callback for transmit.
1843 * Generic pointer transmit queue.
1845 * Packets to transmit.
1847 * Number of packets in array.
1850 * Number of packets successfully transmitted.
1853 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1855 struct mrvl_txq *q = txq;
1856 struct mrvl_shadow_txq *sq = &shadow_txqs[q->port_id][rte_lcore_id()];
1857 struct pp2_hif *hif = hifs[rte_lcore_id()];
1858 struct pp2_ppio_desc descs[nb_pkts];
1859 int i, ret, bytes_sent = 0;
1860 uint16_t num, sq_free_size;
1863 if (unlikely(!q->priv->ppio))
1867 mrvl_free_sent_buffers(q->priv->ppio, hif, sq, q->queue_id, 0);
1869 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
1870 if (unlikely(nb_pkts > sq_free_size)) {
1872 "No room in shadow queue for %d packets! %d packets will be sent.\n",
1873 nb_pkts, sq_free_size);
1874 nb_pkts = sq_free_size;
1877 for (i = 0; i < nb_pkts; i++) {
1878 struct rte_mbuf *mbuf = tx_pkts[i];
1879 int gen_l3_cksum, gen_l4_cksum;
1880 enum pp2_outq_l3_type l3_type;
1881 enum pp2_outq_l4_type l4_type;
1883 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1884 struct rte_mbuf *pref_pkt_hdr;
1886 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
1887 rte_mbuf_prefetch_part1(pref_pkt_hdr);
1888 rte_mbuf_prefetch_part2(pref_pkt_hdr);
1891 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
1892 sq->ent[sq->head].buff.addr =
1893 rte_mbuf_data_iova_default(mbuf);
1894 sq->ent[sq->head].bpool =
1895 (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
1896 NULL : mrvl_port_to_bpool_lookup[mbuf->port];
1897 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
1900 pp2_ppio_outq_desc_reset(&descs[i]);
1901 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
1902 rte_pktmbuf_iova(mbuf));
1903 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
1904 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
1905 rte_pktmbuf_pkt_len(mbuf));
1907 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
1909 * in case unsupported ol_flags were passed
1910 * do not update descriptor offload information
1912 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
1913 &l3_type, &l4_type, &gen_l3_cksum,
1918 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
1920 mbuf->l2_len + mbuf->l3_len,
1921 gen_l3_cksum, gen_l4_cksum);
1925 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
1926 /* number of packets that were not sent */
1927 if (unlikely(num > nb_pkts)) {
1928 for (i = nb_pkts; i < num; i++) {
1929 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
1930 MRVL_PP2_TX_SHADOWQ_MASK;
1931 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
1933 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
1935 sq->size -= num - nb_pkts;
1938 q->bytes_sent += bytes_sent;
1944 * Initialize packet processor.
1947 * 0 on success, negative error value otherwise.
1952 struct pp2_init_params init_params;
1954 memset(&init_params, 0, sizeof(init_params));
1955 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
1956 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
1957 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
1959 return pp2_init(&init_params);
1963 * Deinitialize packet processor.
1966 * 0 on success, negative error value otherwise.
1969 mrvl_deinit_pp2(void)
1975 * Create private device structure.
1978 * Pointer to the port name passed in the initialization parameters.
1981 * Pointer to the newly allocated private device structure.
1983 static struct mrvl_priv *
1984 mrvl_priv_create(const char *dev_name)
1986 struct pp2_bpool_params bpool_params;
1987 char match[MRVL_MATCH_LEN];
1988 struct mrvl_priv *priv;
1991 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
1995 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
1996 &priv->pp_id, &priv->ppio_id);
2000 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2001 PP2_BPOOL_NUM_POOLS);
2004 priv->bpool_bit = bpool_bit;
2006 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2008 memset(&bpool_params, 0, sizeof(bpool_params));
2009 bpool_params.match = match;
2010 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2011 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2013 goto out_clear_bpool_bit;
2015 priv->ppio_params.type = PP2_PPIO_T_NIC;
2016 rte_spinlock_init(&priv->lock);
2019 out_clear_bpool_bit:
2020 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2027 * Create device representing Ethernet port.
2030 * Pointer to the port's name.
2033 * 0 on success, negative error value otherwise.
2036 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2038 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2039 struct rte_eth_dev *eth_dev;
2040 struct mrvl_priv *priv;
2043 eth_dev = rte_eth_dev_allocate(name);
2047 priv = mrvl_priv_create(name);
2053 eth_dev->data->mac_addrs =
2054 rte_zmalloc("mac_addrs",
2055 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2056 if (!eth_dev->data->mac_addrs) {
2057 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2062 memset(&req, 0, sizeof(req));
2063 strcpy(req.ifr_name, name);
2064 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2068 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2069 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2071 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2072 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2073 eth_dev->data->dev_private = priv;
2074 eth_dev->device = &vdev->device;
2075 eth_dev->dev_ops = &mrvl_ops;
2079 rte_free(eth_dev->data->mac_addrs);
2081 rte_eth_dev_release_port(eth_dev);
2089 * Cleanup previously created device representing Ethernet port.
2092 * Pointer to the port name.
2095 mrvl_eth_dev_destroy(const char *name)
2097 struct rte_eth_dev *eth_dev;
2098 struct mrvl_priv *priv;
2100 eth_dev = rte_eth_dev_allocated(name);
2104 priv = eth_dev->data->dev_private;
2105 pp2_bpool_deinit(priv->bpool);
2107 rte_free(eth_dev->data->mac_addrs);
2108 rte_eth_dev_release_port(eth_dev);
2112 * Callback used by rte_kvargs_process() during argument parsing.
2115 * Pointer to the parsed key (unused).
2117 * Pointer to the parsed value.
2119 * Pointer to the extra arguments which contains address of the
2120 * table of pointers to parsed interface names.
2126 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2129 const char **ifnames = extra_args;
2131 ifnames[mrvl_ports_nb++] = value;
2137 * Initialize per-lcore MUSDK hardware interfaces (hifs).
2140 * 0 on success, negative error value otherwise.
2143 mrvl_init_hifs(void)
2145 struct pp2_hif_params params;
2146 char match[MRVL_MATCH_LEN];
2149 RTE_LCORE_FOREACH(i) {
2150 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
2154 snprintf(match, sizeof(match), "hif-%d", ret);
2155 memset(¶ms, 0, sizeof(params));
2156 params.match = match;
2157 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
2158 ret = pp2_hif_init(¶ms, &hifs[i]);
2160 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", i);
2169 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2172 mrvl_deinit_hifs(void)
2176 RTE_LCORE_FOREACH(i) {
2178 pp2_hif_deinit(hifs[i]);
2182 static void mrvl_set_first_last_cores(int core_id)
2184 if (core_id < mrvl_lcore_first)
2185 mrvl_lcore_first = core_id;
2187 if (core_id > mrvl_lcore_last)
2188 mrvl_lcore_last = core_id;
2192 * DPDK callback to register the virtual device.
2195 * Pointer to the virtual device.
2198 * 0 on success, negative error value otherwise.
2201 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2203 struct rte_kvargs *kvlist;
2204 const char *ifnames[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
2206 uint32_t i, ifnum, cfgnum, core_id;
2209 params = rte_vdev_device_args(vdev);
2213 kvlist = rte_kvargs_parse(params, valid_args);
2217 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2218 if (ifnum > RTE_DIM(ifnames))
2219 goto out_free_kvlist;
2221 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2222 mrvl_get_ifnames, &ifnames);
2224 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2226 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2227 goto out_free_kvlist;
2228 } else if (cfgnum == 1) {
2229 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2230 mrvl_get_qoscfg, &mrvl_qos_cfg);
2234 * ret == -EEXIST is correct, it means DMA
2235 * has been already initialized (by another PMD).
2237 ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2240 goto out_free_kvlist;
2243 "DMA memory has been already initialized by a different driver.\n");
2246 ret = mrvl_init_pp2();
2248 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2249 goto out_deinit_dma;
2252 ret = mrvl_init_hifs();
2254 goto out_deinit_hifs;
2256 for (i = 0; i < ifnum; i++) {
2257 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames[i]);
2258 ret = mrvl_eth_dev_create(vdev, ifnames[i]);
2263 rte_kvargs_free(kvlist);
2265 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2267 mrvl_lcore_first = RTE_MAX_LCORE;
2268 mrvl_lcore_last = 0;
2270 RTE_LCORE_FOREACH(core_id) {
2271 mrvl_set_first_last_cores(core_id);
2277 mrvl_eth_dev_destroy(ifnames[i]);
2282 mv_sys_dma_mem_destroy();
2284 rte_kvargs_free(kvlist);
2290 * DPDK callback to remove virtual device.
2293 * Pointer to the removed virtual device.
2296 * 0 on success, negative error value otherwise.
2299 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2304 name = rte_vdev_device_name(vdev);
2308 RTE_LOG(INFO, PMD, "Removing %s\n", name);
2310 for (i = 0; i < rte_eth_dev_count(); i++) {
2311 char ifname[RTE_ETH_NAME_MAX_LEN];
2313 rte_eth_dev_get_name_by_port(i, ifname);
2314 mrvl_eth_dev_destroy(ifname);
2319 mv_sys_dma_mem_destroy();
2324 static struct rte_vdev_driver pmd_mrvl_drv = {
2325 .probe = rte_pmd_mrvl_probe,
2326 .remove = rte_pmd_mrvl_remove,
2329 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
2330 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);