4 * Copyright(c) 2017 Marvell International Ltd.
5 * Copyright(c) 2017 Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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15 * notice, this list of conditions and the following disclaimer in
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20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <rte_ethdev_driver.h>
36 #include <rte_kvargs.h>
38 #include <rte_malloc.h>
39 #include <rte_bus_vdev.h>
41 /* Unluckily, container_of is defined by both DPDK and MUSDK,
42 * we'll declare only one version.
44 * Note that it is not used in this PMD anyway.
51 #include <linux/ethtool.h>
52 #include <linux/sockios.h>
54 #include <net/if_arp.h>
55 #include <sys/ioctl.h>
56 #include <sys/socket.h>
58 #include <sys/types.h>
60 #include "mrvl_ethdev.h"
63 /* bitmask with reserved hifs */
64 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
65 /* bitmask with reserved bpools */
66 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
67 /* bitmask with reserved kernel RSS tables */
68 #define MRVL_MUSDK_RSS_RESERVED 0x01
69 /* maximum number of available hifs */
70 #define MRVL_MUSDK_HIFS_MAX 9
73 #define MRVL_MUSDK_PREFETCH_SHIFT 2
75 /* TCAM has 25 entries reserved for uc/mc filter entries */
76 #define MRVL_MAC_ADDRS_MAX 25
77 #define MRVL_MATCH_LEN 16
78 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
79 /* Maximum allowable packet size */
80 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
82 #define MRVL_IFACE_NAME_ARG "iface"
83 #define MRVL_CFG_ARG "cfg"
85 #define MRVL_BURST_SIZE 64
87 #define MRVL_ARP_LENGTH 28
89 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
91 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
92 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
94 /* Memory size (in bytes) for MUSDK dma buffers */
95 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
97 /** Port Rx offload capabilities */
98 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
99 DEV_RX_OFFLOAD_JUMBO_FRAME | \
100 DEV_RX_OFFLOAD_CRC_STRIP | \
101 DEV_RX_OFFLOAD_CHECKSUM)
103 /** Port Tx offloads capabilities */
104 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_UDP_CKSUM | \
106 DEV_TX_OFFLOAD_TCP_CKSUM)
108 static const char * const valid_args[] = {
114 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
115 static struct pp2_hif *hifs[RTE_MAX_LCORE];
116 static int used_bpools[PP2_NUM_PKT_PROC] = {
117 MRVL_MUSDK_BPOOLS_RESERVED,
118 MRVL_MUSDK_BPOOLS_RESERVED
121 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
122 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
123 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
125 struct mrvl_ifnames {
126 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
131 * To use buffer harvesting based on loopback port shadow queue structure
132 * was introduced for buffers information bookkeeping.
134 * Before sending the packet, related buffer information (pp2_buff_inf) is
135 * stored in shadow queue. After packet is transmitted no longer used
136 * packet buffer is released back to it's original hardware pool,
137 * on condition it originated from interface.
138 * In case it was generated by application itself i.e: mbuf->port field is
139 * 0xff then its released to software mempool.
141 struct mrvl_shadow_txq {
142 int head; /* write index - used when sending buffers */
143 int tail; /* read index - used when releasing buffers */
144 u16 size; /* queue occupied size */
145 u16 num_to_release; /* number of buffers sent, that can be released */
146 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
150 struct mrvl_priv *priv;
151 struct rte_mempool *mp;
160 struct mrvl_priv *priv;
164 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
167 static int mrvl_lcore_first;
168 static int mrvl_lcore_last;
169 static int mrvl_dev_num;
171 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
172 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
173 struct pp2_hif *hif, unsigned int core_id,
174 struct mrvl_shadow_txq *sq, int qid, int force);
177 mrvl_get_bpool_size(int pp2_id, int pool_id)
182 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
183 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
189 mrvl_reserve_bit(int *bitmap, int max)
191 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
202 mrvl_init_hif(int core_id)
204 struct pp2_hif_params params;
205 char match[MRVL_MATCH_LEN];
208 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
210 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
214 snprintf(match, sizeof(match), "hif-%d", ret);
215 memset(¶ms, 0, sizeof(params));
216 params.match = match;
217 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
218 ret = pp2_hif_init(¶ms, &hifs[core_id]);
220 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
227 static inline struct pp2_hif*
228 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
232 if (likely(hifs[core_id] != NULL))
233 return hifs[core_id];
235 rte_spinlock_lock(&priv->lock);
237 ret = mrvl_init_hif(core_id);
239 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
243 if (core_id < mrvl_lcore_first)
244 mrvl_lcore_first = core_id;
246 if (core_id > mrvl_lcore_last)
247 mrvl_lcore_last = core_id;
249 rte_spinlock_unlock(&priv->lock);
251 return hifs[core_id];
255 * Configure rss based on dpdk rss configuration.
258 * Pointer to private structure.
260 * Pointer to RSS configuration.
263 * 0 on success, negative error value otherwise.
266 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
268 if (rss_conf->rss_key)
269 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
271 if (rss_conf->rss_hf == 0) {
272 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
273 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
274 priv->ppio_params.inqs_params.hash_type =
275 PP2_PPIO_HASH_T_2_TUPLE;
276 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
277 priv->ppio_params.inqs_params.hash_type =
278 PP2_PPIO_HASH_T_5_TUPLE;
279 priv->rss_hf_tcp = 1;
280 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
281 priv->ppio_params.inqs_params.hash_type =
282 PP2_PPIO_HASH_T_5_TUPLE;
283 priv->rss_hf_tcp = 0;
292 * Ethernet device configuration.
294 * Prepare the driver for a given number of TX and RX queues and
298 * Pointer to Ethernet device structure.
301 * 0 on success, negative error value otherwise.
304 mrvl_dev_configure(struct rte_eth_dev *dev)
306 struct mrvl_priv *priv = dev->data->dev_private;
309 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
310 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
311 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
312 dev->data->dev_conf.rxmode.mq_mode);
316 if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
318 "L2 CRC stripping is always enabled in hw\n");
319 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
322 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
323 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
327 if (dev->data->dev_conf.rxmode.split_hdr_size) {
328 RTE_LOG(INFO, PMD, "Split headers not supported\n");
332 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) {
333 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
337 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
338 RTE_LOG(INFO, PMD, "LRO not supported\n");
342 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
343 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
344 ETHER_HDR_LEN - ETHER_CRC_LEN;
346 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
347 dev->data->nb_rx_queues);
351 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
352 priv->ppio_params.maintain_stats = 1;
353 priv->nb_rx_queues = dev->data->nb_rx_queues;
355 if (dev->data->nb_rx_queues == 1 &&
356 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
357 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
358 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
363 return mrvl_configure_rss(priv,
364 &dev->data->dev_conf.rx_adv_conf.rss_conf);
368 * DPDK callback to change the MTU.
370 * Setting the MTU affects hardware MRU (packets larger than the MRU
374 * Pointer to Ethernet device structure.
379 * 0 on success, negative error value otherwise.
382 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
384 struct mrvl_priv *priv = dev->data->dev_private;
385 /* extra MV_MH_SIZE bytes are required for Marvell tag */
386 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
389 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
395 ret = pp2_ppio_set_mru(priv->ppio, mru);
399 return pp2_ppio_set_mtu(priv->ppio, mtu);
403 * DPDK callback to bring the link up.
406 * Pointer to Ethernet device structure.
409 * 0 on success, negative error value otherwise.
412 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
414 struct mrvl_priv *priv = dev->data->dev_private;
420 ret = pp2_ppio_enable(priv->ppio);
425 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
426 * as pp2_ppio_enable() changes port->t_mode from default 0 to
427 * PP2_TRAFFIC_INGRESS_EGRESS.
429 * Set mtu to default DPDK value here.
431 ret = mrvl_mtu_set(dev, dev->data->mtu);
433 pp2_ppio_disable(priv->ppio);
439 * DPDK callback to bring the link down.
442 * Pointer to Ethernet device structure.
445 * 0 on success, negative error value otherwise.
448 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
450 struct mrvl_priv *priv = dev->data->dev_private;
455 return pp2_ppio_disable(priv->ppio);
459 * DPDK callback to start the device.
462 * Pointer to Ethernet device structure.
465 * 0 on success, negative errno value on failure.
468 mrvl_dev_start(struct rte_eth_dev *dev)
470 struct mrvl_priv *priv = dev->data->dev_private;
471 char match[MRVL_MATCH_LEN];
472 int ret = 0, def_init_size;
474 snprintf(match, sizeof(match), "ppio-%d:%d",
475 priv->pp_id, priv->ppio_id);
476 priv->ppio_params.match = match;
479 * Calculate the minimum bpool size for refill feature as follows:
480 * 2 default burst sizes multiply by number of rx queues.
481 * If the bpool size will be below this value, new buffers will
482 * be added to the pool.
484 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
486 /* In case initial bpool size configured in queues setup is
487 * smaller than minimum size add more buffers
489 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
490 if (priv->bpool_init_size < def_init_size) {
491 int buffs_to_add = def_init_size - priv->bpool_init_size;
493 priv->bpool_init_size += buffs_to_add;
494 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
496 RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
500 * Calculate the maximum bpool size for refill feature as follows:
501 * maximum number of descriptors in rx queue multiply by number
502 * of rx queues plus minimum bpool size.
503 * In case the bpool size will exceed this value, superfluous buffers
506 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
507 priv->bpool_min_size;
509 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
511 RTE_LOG(ERR, PMD, "Failed to init ppio\n");
516 * In case there are some some stale uc/mc mac addresses flush them
517 * here. It cannot be done during mrvl_dev_close() as port information
518 * is already gone at that point (due to pp2_ppio_deinit() in
521 if (!priv->uc_mc_flushed) {
522 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
525 "Failed to flush uc/mc filter list\n");
528 priv->uc_mc_flushed = 1;
531 if (!priv->vlan_flushed) {
532 ret = pp2_ppio_flush_vlan(priv->ppio);
534 RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
537 * once pp2_ppio_flush_vlan() is supported jump to out
541 priv->vlan_flushed = 1;
544 /* For default QoS config, don't start classifier. */
546 ret = mrvl_start_qos_mapping(priv);
548 RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n");
553 ret = mrvl_dev_set_link_up(dev);
555 RTE_LOG(ERR, PMD, "Failed to set link up\n");
561 RTE_LOG(ERR, PMD, "Failed to start device\n");
562 pp2_ppio_deinit(priv->ppio);
567 * Flush receive queues.
570 * Pointer to Ethernet device structure.
573 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
577 RTE_LOG(INFO, PMD, "Flushing rx queues\n");
578 for (i = 0; i < dev->data->nb_rx_queues; i++) {
582 struct mrvl_rxq *q = dev->data->rx_queues[i];
583 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
585 num = MRVL_PP2_RXD_MAX;
586 ret = pp2_ppio_recv(q->priv->ppio,
587 q->priv->rxq_map[q->queue_id].tc,
588 q->priv->rxq_map[q->queue_id].inq,
589 descs, (uint16_t *)&num);
590 } while (ret == 0 && num);
595 * Flush transmit shadow queues.
598 * Pointer to Ethernet device structure.
601 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
604 struct mrvl_txq *txq;
606 RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
607 for (i = 0; i < dev->data->nb_tx_queues; i++) {
608 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
610 for (j = 0; j < RTE_MAX_LCORE; j++) {
611 struct mrvl_shadow_txq *sq;
616 sq = &txq->shadow_txqs[j];
617 mrvl_free_sent_buffers(txq->priv->ppio,
618 hifs[j], j, sq, txq->queue_id, 1);
619 while (sq->tail != sq->head) {
620 uint64_t addr = cookie_addr_high |
621 sq->ent[sq->tail].buff.cookie;
623 (struct rte_mbuf *)addr);
624 sq->tail = (sq->tail + 1) &
625 MRVL_PP2_TX_SHADOWQ_MASK;
627 memset(sq, 0, sizeof(*sq));
633 * Flush hardware bpool (buffer-pool).
636 * Pointer to Ethernet device structure.
639 mrvl_flush_bpool(struct rte_eth_dev *dev)
641 struct mrvl_priv *priv = dev->data->dev_private;
645 unsigned int core_id = rte_lcore_id();
647 if (core_id == LCORE_ID_ANY)
650 hif = mrvl_get_hif(priv, core_id);
652 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
654 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
659 struct pp2_buff_inf inf;
662 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
666 addr = cookie_addr_high | inf.cookie;
667 rte_pktmbuf_free((struct rte_mbuf *)addr);
672 * DPDK callback to stop the device.
675 * Pointer to Ethernet device structure.
678 mrvl_dev_stop(struct rte_eth_dev *dev)
680 struct mrvl_priv *priv = dev->data->dev_private;
682 mrvl_dev_set_link_down(dev);
683 mrvl_flush_rx_queues(dev);
684 mrvl_flush_tx_shadow_queues(dev);
686 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
687 priv->qos_tbl = NULL;
689 pp2_ppio_deinit(priv->ppio);
694 * DPDK callback to close the device.
697 * Pointer to Ethernet device structure.
700 mrvl_dev_close(struct rte_eth_dev *dev)
702 struct mrvl_priv *priv = dev->data->dev_private;
705 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
706 struct pp2_ppio_tc_params *tc_params =
707 &priv->ppio_params.inqs_params.tcs_params[i];
709 if (tc_params->inqs_params) {
710 rte_free(tc_params->inqs_params);
711 tc_params->inqs_params = NULL;
715 mrvl_flush_bpool(dev);
719 * DPDK callback to retrieve physical link information.
722 * Pointer to Ethernet device structure.
723 * @param wait_to_complete
724 * Wait for request completion (ignored).
727 * 0 on success, negative error value otherwise.
730 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
734 * once MUSDK provides necessary API use it here
736 struct mrvl_priv *priv = dev->data->dev_private;
737 struct ethtool_cmd edata;
739 int ret, fd, link_up;
744 edata.cmd = ETHTOOL_GSET;
746 strcpy(req.ifr_name, dev->data->name);
747 req.ifr_data = (void *)&edata;
749 fd = socket(AF_INET, SOCK_DGRAM, 0);
753 ret = ioctl(fd, SIOCETHTOOL, &req);
761 switch (ethtool_cmd_speed(&edata)) {
763 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
766 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
769 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
772 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
775 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
778 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
779 ETH_LINK_HALF_DUPLEX;
780 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
782 pp2_ppio_get_link_state(priv->ppio, &link_up);
783 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
789 * DPDK callback to enable promiscuous mode.
792 * Pointer to Ethernet device structure.
795 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
797 struct mrvl_priv *priv = dev->data->dev_private;
803 ret = pp2_ppio_set_promisc(priv->ppio, 1);
805 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
809 * DPDK callback to enable allmulti mode.
812 * Pointer to Ethernet device structure.
815 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
817 struct mrvl_priv *priv = dev->data->dev_private;
823 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
825 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
829 * DPDK callback to disable promiscuous mode.
832 * Pointer to Ethernet device structure.
835 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
837 struct mrvl_priv *priv = dev->data->dev_private;
843 ret = pp2_ppio_set_promisc(priv->ppio, 0);
845 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
849 * DPDK callback to disable allmulticast mode.
852 * Pointer to Ethernet device structure.
855 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
857 struct mrvl_priv *priv = dev->data->dev_private;
863 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
865 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
869 * DPDK callback to remove a MAC address.
872 * Pointer to Ethernet device structure.
877 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
879 struct mrvl_priv *priv = dev->data->dev_private;
880 char buf[ETHER_ADDR_FMT_SIZE];
886 ret = pp2_ppio_remove_mac_addr(priv->ppio,
887 dev->data->mac_addrs[index].addr_bytes);
889 ether_format_addr(buf, sizeof(buf),
890 &dev->data->mac_addrs[index]);
891 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
896 * DPDK callback to add a MAC address.
899 * Pointer to Ethernet device structure.
901 * MAC address to register.
905 * VMDq pool index to associate address with (unused).
908 * 0 on success, negative error value otherwise.
911 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
912 uint32_t index, uint32_t vmdq __rte_unused)
914 struct mrvl_priv *priv = dev->data->dev_private;
915 char buf[ETHER_ADDR_FMT_SIZE];
919 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
926 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
927 * parameter uc_filter_max. Maximum number of mc addresses is then
928 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
931 * If more than uc_filter_max uc addresses were added to filter list
932 * then NIC will switch to promiscuous mode automatically.
934 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
935 * were added to filter list then NIC will switch to all-multicast mode
938 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
940 ether_format_addr(buf, sizeof(buf), mac_addr);
941 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
949 * DPDK callback to set the primary MAC address.
952 * Pointer to Ethernet device structure.
954 * MAC address to register.
957 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
959 struct mrvl_priv *priv = dev->data->dev_private;
965 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
967 char buf[ETHER_ADDR_FMT_SIZE];
968 ether_format_addr(buf, sizeof(buf), mac_addr);
969 RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf);
974 * DPDK callback to get device statistics.
977 * Pointer to Ethernet device structure.
979 * Stats structure output buffer.
982 * 0 on success, negative error value otherwise.
985 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
987 struct mrvl_priv *priv = dev->data->dev_private;
988 struct pp2_ppio_statistics ppio_stats;
989 uint64_t drop_mac = 0;
990 unsigned int i, idx, ret;
995 for (i = 0; i < dev->data->nb_rx_queues; i++) {
996 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
997 struct pp2_ppio_inq_statistics rx_stats;
1002 idx = rxq->queue_id;
1003 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1005 "rx queue %d stats out of range (0 - %d)\n",
1006 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1010 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1011 priv->rxq_map[idx].tc,
1012 priv->rxq_map[idx].inq,
1014 if (unlikely(ret)) {
1016 "Failed to update rx queue %d stats\n", idx);
1020 stats->q_ibytes[idx] = rxq->bytes_recv;
1021 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1022 stats->q_errors[idx] = rx_stats.drop_early +
1023 rx_stats.drop_fullq +
1026 stats->ibytes += rxq->bytes_recv;
1027 drop_mac += rxq->drop_mac;
1030 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1031 struct mrvl_txq *txq = dev->data->tx_queues[i];
1032 struct pp2_ppio_outq_statistics tx_stats;
1037 idx = txq->queue_id;
1038 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1040 "tx queue %d stats out of range (0 - %d)\n",
1041 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1044 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1046 if (unlikely(ret)) {
1048 "Failed to update tx queue %d stats\n", idx);
1052 stats->q_opackets[idx] = tx_stats.deq_desc;
1053 stats->q_obytes[idx] = txq->bytes_sent;
1054 stats->obytes += txq->bytes_sent;
1057 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1058 if (unlikely(ret)) {
1059 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
1063 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1064 stats->opackets += ppio_stats.tx_packets;
1065 stats->imissed += ppio_stats.rx_fullq_dropped +
1066 ppio_stats.rx_bm_dropped +
1067 ppio_stats.rx_early_dropped +
1068 ppio_stats.rx_fifo_dropped +
1069 ppio_stats.rx_cls_dropped;
1070 stats->ierrors = drop_mac;
1076 * DPDK callback to clear device statistics.
1079 * Pointer to Ethernet device structure.
1082 mrvl_stats_reset(struct rte_eth_dev *dev)
1084 struct mrvl_priv *priv = dev->data->dev_private;
1090 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1091 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1093 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1094 priv->rxq_map[i].inq, NULL, 1);
1095 rxq->bytes_recv = 0;
1099 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1100 struct mrvl_txq *txq = dev->data->tx_queues[i];
1102 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1103 txq->bytes_sent = 0;
1106 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1110 * DPDK callback to get information about the device.
1113 * Pointer to Ethernet device structure (unused).
1115 * Info structure output buffer.
1118 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1119 struct rte_eth_dev_info *info)
1121 info->speed_capa = ETH_LINK_SPEED_10M |
1122 ETH_LINK_SPEED_100M |
1126 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1127 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1128 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1130 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1131 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1132 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1134 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1135 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1136 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1138 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1139 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1141 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1142 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1144 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1145 ETH_RSS_NONFRAG_IPV4_TCP |
1146 ETH_RSS_NONFRAG_IPV4_UDP;
1148 /* By default packets are dropped if no descriptors are available */
1149 info->default_rxconf.rx_drop_en = 1;
1150 info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
1152 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1156 * Return supported packet types.
1159 * Pointer to Ethernet device structure (unused).
1162 * Const pointer to the table with supported packet types.
1164 static const uint32_t *
1165 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1167 static const uint32_t ptypes[] = {
1170 RTE_PTYPE_L3_IPV4_EXT,
1171 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1173 RTE_PTYPE_L3_IPV6_EXT,
1174 RTE_PTYPE_L2_ETHER_ARP,
1183 * DPDK callback to get information about specific receive queue.
1186 * Pointer to Ethernet device structure.
1187 * @param rx_queue_id
1188 * Receive queue index.
1190 * Receive queue information structure.
1192 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1193 struct rte_eth_rxq_info *qinfo)
1195 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1196 struct mrvl_priv *priv = dev->data->dev_private;
1197 int inq = priv->rxq_map[rx_queue_id].inq;
1198 int tc = priv->rxq_map[rx_queue_id].tc;
1199 struct pp2_ppio_tc_params *tc_params =
1200 &priv->ppio_params.inqs_params.tcs_params[tc];
1203 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1207 * DPDK callback to get information about specific transmit queue.
1210 * Pointer to Ethernet device structure.
1211 * @param tx_queue_id
1212 * Transmit queue index.
1214 * Transmit queue information structure.
1216 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1217 struct rte_eth_txq_info *qinfo)
1219 struct mrvl_priv *priv = dev->data->dev_private;
1222 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1226 * DPDK callback to Configure a VLAN filter.
1229 * Pointer to Ethernet device structure.
1231 * VLAN ID to filter.
1236 * 0 on success, negative error value otherwise.
1239 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1241 struct mrvl_priv *priv = dev->data->dev_private;
1246 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1247 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1251 * Release buffers to hardware bpool (buffer-pool)
1254 * Receive queue pointer.
1256 * Number of buffers to release to bpool.
1259 * 0 on success, negative error value otherwise.
1262 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1264 struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
1265 struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
1267 unsigned int core_id;
1268 struct pp2_hif *hif;
1269 struct pp2_bpool *bpool;
1271 core_id = rte_lcore_id();
1272 if (core_id == LCORE_ID_ANY)
1275 hif = mrvl_get_hif(rxq->priv, core_id);
1279 bpool = rxq->priv->bpool;
1281 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1285 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1287 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1289 for (i = 0; i < num; i++) {
1290 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1291 != cookie_addr_high) {
1293 "mbuf virtual addr high 0x%lx out of range\n",
1294 (uint64_t)mbufs[i] >> 32);
1298 entries[i].buff.addr =
1299 rte_mbuf_data_iova_default(mbufs[i]);
1300 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1301 entries[i].bpool = bpool;
1304 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1305 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1312 for (; i < num; i++)
1313 rte_pktmbuf_free(mbufs[i]);
1319 * Check whether requested rx queue offloads match port offloads.
1322 * dev Pointer to the device.
1324 * requested Bitmap of the requested offloads.
1327 * 1 if requested offloads are okay, 0 otherwise.
1330 mrvl_rx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
1332 uint64_t mandatory = dev->data->dev_conf.rxmode.offloads;
1333 uint64_t supported = MRVL_RX_OFFLOADS;
1334 uint64_t unsupported = requested & ~supported;
1335 uint64_t missing = mandatory & ~requested;
1338 RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. "
1339 "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
1340 requested, supported);
1345 RTE_LOG(ERR, PMD, "Some Rx offloads are missing. "
1346 "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
1347 requested, missing);
1355 * DPDK callback to configure the receive queue.
1358 * Pointer to Ethernet device structure.
1362 * Number of descriptors to configure in queue.
1364 * NUMA socket on which memory must be allocated.
1366 * Thresholds parameters.
1368 * Memory pool for buffer allocations.
1371 * 0 on success, negative error value otherwise.
1374 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1375 unsigned int socket,
1376 const struct rte_eth_rxconf *conf,
1377 struct rte_mempool *mp)
1379 struct mrvl_priv *priv = dev->data->dev_private;
1380 struct mrvl_rxq *rxq;
1382 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1385 if (!mrvl_rx_queue_offloads_okay(dev, conf->offloads))
1388 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1390 * Unknown TC mapping, mapping will not have a correct queue.
1392 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1393 idx, priv->ppio_id);
1397 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1398 MRVL_PKT_EFFEC_OFFS;
1399 if (min_size < max_rx_pkt_len) {
1401 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1402 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1403 MRVL_PKT_EFFEC_OFFS,
1408 if (dev->data->rx_queues[idx]) {
1409 rte_free(dev->data->rx_queues[idx]);
1410 dev->data->rx_queues[idx] = NULL;
1413 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1419 rxq->cksum_enabled =
1420 dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1421 rxq->queue_id = idx;
1422 rxq->port_id = dev->data->port_id;
1423 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1425 tc = priv->rxq_map[rxq->queue_id].tc,
1426 inq = priv->rxq_map[rxq->queue_id].inq;
1427 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1430 ret = mrvl_fill_bpool(rxq, desc);
1436 priv->bpool_init_size += desc;
1438 dev->data->rx_queues[idx] = rxq;
1444 * DPDK callback to release the receive queue.
1447 * Generic receive queue pointer.
1450 mrvl_rx_queue_release(void *rxq)
1452 struct mrvl_rxq *q = rxq;
1453 struct pp2_ppio_tc_params *tc_params;
1454 int i, num, tc, inq;
1455 struct pp2_hif *hif;
1456 unsigned int core_id = rte_lcore_id();
1458 if (core_id == LCORE_ID_ANY)
1461 hif = mrvl_get_hif(q->priv, core_id);
1466 tc = q->priv->rxq_map[q->queue_id].tc;
1467 inq = q->priv->rxq_map[q->queue_id].inq;
1468 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1469 num = tc_params->inqs_params[inq].size;
1470 for (i = 0; i < num; i++) {
1471 struct pp2_buff_inf inf;
1474 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1475 addr = cookie_addr_high | inf.cookie;
1476 rte_pktmbuf_free((struct rte_mbuf *)addr);
1483 * Check whether requested tx queue offloads match port offloads.
1486 * dev Pointer to the device.
1488 * requested Bitmap of the requested offloads.
1491 * 1 if requested offloads are okay, 0 otherwise.
1494 mrvl_tx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
1496 uint64_t mandatory = dev->data->dev_conf.txmode.offloads;
1497 uint64_t supported = MRVL_TX_OFFLOADS;
1498 uint64_t unsupported = requested & ~supported;
1499 uint64_t missing = mandatory & ~requested;
1502 RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. "
1503 "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
1504 requested, supported);
1509 RTE_LOG(ERR, PMD, "Some Rx offloads are missing. "
1510 "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
1511 requested, missing);
1519 * DPDK callback to configure the transmit queue.
1522 * Pointer to Ethernet device structure.
1524 * Transmit queue index.
1526 * Number of descriptors to configure in the queue.
1528 * NUMA socket on which memory must be allocated.
1530 * Thresholds parameters.
1533 * 0 on success, negative error value otherwise.
1536 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1537 unsigned int socket,
1538 const struct rte_eth_txconf *conf)
1540 struct mrvl_priv *priv = dev->data->dev_private;
1541 struct mrvl_txq *txq;
1543 if (!mrvl_tx_queue_offloads_okay(dev, conf->offloads))
1546 if (dev->data->tx_queues[idx]) {
1547 rte_free(dev->data->tx_queues[idx]);
1548 dev->data->tx_queues[idx] = NULL;
1551 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1556 txq->queue_id = idx;
1557 txq->port_id = dev->data->port_id;
1558 dev->data->tx_queues[idx] = txq;
1560 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1561 priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1567 * DPDK callback to release the transmit queue.
1570 * Generic transmit queue pointer.
1573 mrvl_tx_queue_release(void *txq)
1575 struct mrvl_txq *q = txq;
1584 * Update RSS hash configuration
1587 * Pointer to Ethernet device structure.
1589 * Pointer to RSS configuration.
1592 * 0 on success, negative error value otherwise.
1595 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1596 struct rte_eth_rss_conf *rss_conf)
1598 struct mrvl_priv *priv = dev->data->dev_private;
1600 return mrvl_configure_rss(priv, rss_conf);
1604 * DPDK callback to get RSS hash configuration.
1607 * Pointer to Ethernet device structure.
1609 * Pointer to RSS configuration.
1615 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1616 struct rte_eth_rss_conf *rss_conf)
1618 struct mrvl_priv *priv = dev->data->dev_private;
1619 enum pp2_ppio_hash_type hash_type =
1620 priv->ppio_params.inqs_params.hash_type;
1622 rss_conf->rss_key = NULL;
1624 if (hash_type == PP2_PPIO_HASH_T_NONE)
1625 rss_conf->rss_hf = 0;
1626 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1627 rss_conf->rss_hf = ETH_RSS_IPV4;
1628 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1629 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1630 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1631 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1636 static const struct eth_dev_ops mrvl_ops = {
1637 .dev_configure = mrvl_dev_configure,
1638 .dev_start = mrvl_dev_start,
1639 .dev_stop = mrvl_dev_stop,
1640 .dev_set_link_up = mrvl_dev_set_link_up,
1641 .dev_set_link_down = mrvl_dev_set_link_down,
1642 .dev_close = mrvl_dev_close,
1643 .link_update = mrvl_link_update,
1644 .promiscuous_enable = mrvl_promiscuous_enable,
1645 .allmulticast_enable = mrvl_allmulticast_enable,
1646 .promiscuous_disable = mrvl_promiscuous_disable,
1647 .allmulticast_disable = mrvl_allmulticast_disable,
1648 .mac_addr_remove = mrvl_mac_addr_remove,
1649 .mac_addr_add = mrvl_mac_addr_add,
1650 .mac_addr_set = mrvl_mac_addr_set,
1651 .mtu_set = mrvl_mtu_set,
1652 .stats_get = mrvl_stats_get,
1653 .stats_reset = mrvl_stats_reset,
1654 .dev_infos_get = mrvl_dev_infos_get,
1655 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1656 .rxq_info_get = mrvl_rxq_info_get,
1657 .txq_info_get = mrvl_txq_info_get,
1658 .vlan_filter_set = mrvl_vlan_filter_set,
1659 .rx_queue_setup = mrvl_rx_queue_setup,
1660 .rx_queue_release = mrvl_rx_queue_release,
1661 .tx_queue_setup = mrvl_tx_queue_setup,
1662 .tx_queue_release = mrvl_tx_queue_release,
1663 .rss_hash_update = mrvl_rss_hash_update,
1664 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1668 * Return packet type information and l3/l4 offsets.
1671 * Pointer to the received packet descriptor.
1678 * Packet type information.
1680 static inline uint64_t
1681 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1682 uint8_t *l3_offset, uint8_t *l4_offset)
1684 enum pp2_inq_l3_type l3_type;
1685 enum pp2_inq_l4_type l4_type;
1686 uint64_t packet_type;
1688 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1689 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1691 packet_type = RTE_PTYPE_L2_ETHER;
1694 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1695 packet_type |= RTE_PTYPE_L3_IPV4;
1697 case PP2_INQ_L3_TYPE_IPV4_OK:
1698 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1700 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1701 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1703 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1704 packet_type |= RTE_PTYPE_L3_IPV6;
1706 case PP2_INQ_L3_TYPE_IPV6_EXT:
1707 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1709 case PP2_INQ_L3_TYPE_ARP:
1710 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1712 * In case of ARP l4_offset is set to wrong value.
1713 * Set it to proper one so that later on mbuf->l3_len can be
1714 * calculated subtracting l4_offset and l3_offset.
1716 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1719 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1724 case PP2_INQ_L4_TYPE_TCP:
1725 packet_type |= RTE_PTYPE_L4_TCP;
1727 case PP2_INQ_L4_TYPE_UDP:
1728 packet_type |= RTE_PTYPE_L4_UDP;
1731 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1739 * Get offload information from the received packet descriptor.
1742 * Pointer to the received packet descriptor.
1745 * Mbuf offload flags.
1747 static inline uint64_t
1748 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1751 enum pp2_inq_desc_status status;
1753 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1754 if (unlikely(status != PP2_DESC_ERR_OK))
1755 flags = PKT_RX_IP_CKSUM_BAD;
1757 flags = PKT_RX_IP_CKSUM_GOOD;
1759 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1760 if (unlikely(status != PP2_DESC_ERR_OK))
1761 flags |= PKT_RX_L4_CKSUM_BAD;
1763 flags |= PKT_RX_L4_CKSUM_GOOD;
1769 * DPDK callback for receive.
1772 * Generic pointer to the receive queue.
1774 * Array to store received packets.
1776 * Maximum number of packets in array.
1779 * Number of packets successfully received.
1782 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1784 struct mrvl_rxq *q = rxq;
1785 struct pp2_ppio_desc descs[nb_pkts];
1786 struct pp2_bpool *bpool;
1787 int i, ret, rx_done = 0;
1789 struct pp2_hif *hif;
1790 unsigned int core_id = rte_lcore_id();
1792 hif = mrvl_get_hif(q->priv, core_id);
1794 if (unlikely(!q->priv->ppio || !hif))
1797 bpool = q->priv->bpool;
1799 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1800 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1801 if (unlikely(ret < 0)) {
1802 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1805 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1807 for (i = 0; i < nb_pkts; i++) {
1808 struct rte_mbuf *mbuf;
1809 uint8_t l3_offset, l4_offset;
1810 enum pp2_inq_desc_status status;
1813 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1814 struct pp2_ppio_desc *pref_desc;
1817 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1818 pref_addr = cookie_addr_high |
1819 pp2_ppio_inq_desc_get_cookie(pref_desc);
1820 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1821 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1824 addr = cookie_addr_high |
1825 pp2_ppio_inq_desc_get_cookie(&descs[i]);
1826 mbuf = (struct rte_mbuf *)addr;
1827 rte_pktmbuf_reset(mbuf);
1829 /* drop packet in case of mac, overrun or resource error */
1830 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1831 if (unlikely(status != PP2_DESC_ERR_OK)) {
1832 struct pp2_buff_inf binf = {
1833 .addr = rte_mbuf_data_iova_default(mbuf),
1834 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1837 pp2_bpool_put_buff(hif, bpool, &binf);
1838 mrvl_port_bpool_size
1839 [bpool->pp2_id][bpool->id][core_id]++;
1844 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1845 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1846 mbuf->data_len = mbuf->pkt_len;
1847 mbuf->port = q->port_id;
1849 mrvl_desc_to_packet_type_and_offset(&descs[i],
1852 mbuf->l2_len = l3_offset;
1853 mbuf->l3_len = l4_offset - l3_offset;
1855 if (likely(q->cksum_enabled))
1856 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
1858 rx_pkts[rx_done++] = mbuf;
1859 q->bytes_recv += mbuf->pkt_len;
1862 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1863 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1865 if (unlikely(num <= q->priv->bpool_min_size ||
1866 (!rx_done && num < q->priv->bpool_init_size))) {
1867 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1869 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1870 } else if (unlikely(num > q->priv->bpool_max_size)) {
1872 int pkt_to_remove = num - q->priv->bpool_init_size;
1873 struct rte_mbuf *mbuf;
1874 struct pp2_buff_inf buff;
1877 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1878 bpool->pp2_id, q->priv->ppio->port_id,
1879 bpool->id, pkt_to_remove, num,
1880 q->priv->bpool_init_size);
1882 for (i = 0; i < pkt_to_remove; i++) {
1883 ret = pp2_bpool_get_buff(hif, bpool, &buff);
1886 mbuf = (struct rte_mbuf *)
1887 (cookie_addr_high | buff.cookie);
1888 rte_pktmbuf_free(mbuf);
1890 mrvl_port_bpool_size
1891 [bpool->pp2_id][bpool->id][core_id] -= i;
1893 rte_spinlock_unlock(&q->priv->lock);
1900 * Prepare offload information.
1904 * @param packet_type
1905 * Packet type bitfield.
1907 * Pointer to the pp2_ouq_l3_type structure.
1909 * Pointer to the pp2_outq_l4_type structure.
1910 * @param gen_l3_cksum
1911 * Will be set to 1 in case l3 checksum is computed.
1913 * Will be set to 1 in case l4 checksum is computed.
1916 * 0 on success, negative error value otherwise.
1919 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
1920 enum pp2_outq_l3_type *l3_type,
1921 enum pp2_outq_l4_type *l4_type,
1926 * Based on ol_flags prepare information
1927 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
1930 if (ol_flags & PKT_TX_IPV4) {
1931 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
1932 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
1933 } else if (ol_flags & PKT_TX_IPV6) {
1934 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
1935 /* no checksum for ipv6 header */
1938 /* if something different then stop processing */
1942 ol_flags &= PKT_TX_L4_MASK;
1943 if ((packet_type & RTE_PTYPE_L4_TCP) &&
1944 ol_flags == PKT_TX_TCP_CKSUM) {
1945 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
1947 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
1948 ol_flags == PKT_TX_UDP_CKSUM) {
1949 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
1952 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
1953 /* no checksum for other type */
1961 * Release already sent buffers to bpool (buffer-pool).
1964 * Pointer to the port structure.
1966 * Pointer to the MUSDK hardware interface.
1968 * Pointer to the shadow queue.
1972 * Force releasing packets.
1975 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1976 unsigned int core_id, struct mrvl_shadow_txq *sq,
1979 struct buff_release_entry *entry;
1980 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1983 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1985 sq->num_to_release += nb_done;
1987 if (likely(!force &&
1988 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1991 nb_done = sq->num_to_release;
1992 sq->num_to_release = 0;
1994 for (i = 0; i < nb_done; i++) {
1995 entry = &sq->ent[sq->tail + num];
1996 if (unlikely(!entry->buff.addr)) {
1998 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1999 sq->tail, (u64)entry->buff.cookie,
2000 (u64)entry->buff.addr);
2005 if (unlikely(!entry->bpool)) {
2006 struct rte_mbuf *mbuf;
2008 mbuf = (struct rte_mbuf *)
2009 (cookie_addr_high | entry->buff.cookie);
2010 rte_pktmbuf_free(mbuf);
2015 mrvl_port_bpool_size
2016 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2018 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2023 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2025 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2032 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2033 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2039 * DPDK callback for transmit.
2042 * Generic pointer transmit queue.
2044 * Packets to transmit.
2046 * Number of packets in array.
2049 * Number of packets successfully transmitted.
2052 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2054 struct mrvl_txq *q = txq;
2055 struct mrvl_shadow_txq *sq;
2056 struct pp2_hif *hif;
2057 struct pp2_ppio_desc descs[nb_pkts];
2058 unsigned int core_id = rte_lcore_id();
2059 int i, ret, bytes_sent = 0;
2060 uint16_t num, sq_free_size;
2063 hif = mrvl_get_hif(q->priv, core_id);
2064 sq = &q->shadow_txqs[core_id];
2066 if (unlikely(!q->priv->ppio || !hif))
2070 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2071 sq, q->queue_id, 0);
2073 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2074 if (unlikely(nb_pkts > sq_free_size)) {
2076 "No room in shadow queue for %d packets! %d packets will be sent.\n",
2077 nb_pkts, sq_free_size);
2078 nb_pkts = sq_free_size;
2081 for (i = 0; i < nb_pkts; i++) {
2082 struct rte_mbuf *mbuf = tx_pkts[i];
2083 int gen_l3_cksum, gen_l4_cksum;
2084 enum pp2_outq_l3_type l3_type;
2085 enum pp2_outq_l4_type l4_type;
2087 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2088 struct rte_mbuf *pref_pkt_hdr;
2090 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2091 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2092 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2095 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2096 sq->ent[sq->head].buff.addr =
2097 rte_mbuf_data_iova_default(mbuf);
2098 sq->ent[sq->head].bpool =
2099 (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
2100 NULL : mrvl_port_to_bpool_lookup[mbuf->port];
2101 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2104 pp2_ppio_outq_desc_reset(&descs[i]);
2105 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2106 rte_pktmbuf_iova(mbuf));
2107 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2108 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2109 rte_pktmbuf_pkt_len(mbuf));
2111 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2113 * in case unsupported ol_flags were passed
2114 * do not update descriptor offload information
2116 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2117 &l3_type, &l4_type, &gen_l3_cksum,
2122 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2124 mbuf->l2_len + mbuf->l3_len,
2125 gen_l3_cksum, gen_l4_cksum);
2129 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2130 /* number of packets that were not sent */
2131 if (unlikely(num > nb_pkts)) {
2132 for (i = nb_pkts; i < num; i++) {
2133 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2134 MRVL_PP2_TX_SHADOWQ_MASK;
2135 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2137 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2139 sq->size -= num - nb_pkts;
2142 q->bytes_sent += bytes_sent;
2148 * Initialize packet processor.
2151 * 0 on success, negative error value otherwise.
2156 struct pp2_init_params init_params;
2158 memset(&init_params, 0, sizeof(init_params));
2159 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2160 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2161 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2163 return pp2_init(&init_params);
2167 * Deinitialize packet processor.
2170 * 0 on success, negative error value otherwise.
2173 mrvl_deinit_pp2(void)
2179 * Create private device structure.
2182 * Pointer to the port name passed in the initialization parameters.
2185 * Pointer to the newly allocated private device structure.
2187 static struct mrvl_priv *
2188 mrvl_priv_create(const char *dev_name)
2190 struct pp2_bpool_params bpool_params;
2191 char match[MRVL_MATCH_LEN];
2192 struct mrvl_priv *priv;
2195 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2199 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2200 &priv->pp_id, &priv->ppio_id);
2204 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2205 PP2_BPOOL_NUM_POOLS);
2208 priv->bpool_bit = bpool_bit;
2210 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2212 memset(&bpool_params, 0, sizeof(bpool_params));
2213 bpool_params.match = match;
2214 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2215 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2217 goto out_clear_bpool_bit;
2219 priv->ppio_params.type = PP2_PPIO_T_NIC;
2220 rte_spinlock_init(&priv->lock);
2223 out_clear_bpool_bit:
2224 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2231 * Create device representing Ethernet port.
2234 * Pointer to the port's name.
2237 * 0 on success, negative error value otherwise.
2240 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2242 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2243 struct rte_eth_dev *eth_dev;
2244 struct mrvl_priv *priv;
2247 eth_dev = rte_eth_dev_allocate(name);
2251 priv = mrvl_priv_create(name);
2257 eth_dev->data->mac_addrs =
2258 rte_zmalloc("mac_addrs",
2259 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2260 if (!eth_dev->data->mac_addrs) {
2261 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2266 memset(&req, 0, sizeof(req));
2267 strcpy(req.ifr_name, name);
2268 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2272 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2273 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2275 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2276 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2277 eth_dev->data->kdrv = RTE_KDRV_NONE;
2278 eth_dev->data->dev_private = priv;
2279 eth_dev->device = &vdev->device;
2280 eth_dev->dev_ops = &mrvl_ops;
2284 rte_free(eth_dev->data->mac_addrs);
2286 rte_eth_dev_release_port(eth_dev);
2294 * Cleanup previously created device representing Ethernet port.
2297 * Pointer to the port name.
2300 mrvl_eth_dev_destroy(const char *name)
2302 struct rte_eth_dev *eth_dev;
2303 struct mrvl_priv *priv;
2305 eth_dev = rte_eth_dev_allocated(name);
2309 priv = eth_dev->data->dev_private;
2310 pp2_bpool_deinit(priv->bpool);
2311 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2313 rte_free(eth_dev->data->mac_addrs);
2314 rte_eth_dev_release_port(eth_dev);
2318 * Callback used by rte_kvargs_process() during argument parsing.
2321 * Pointer to the parsed key (unused).
2323 * Pointer to the parsed value.
2325 * Pointer to the extra arguments which contains address of the
2326 * table of pointers to parsed interface names.
2332 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2335 struct mrvl_ifnames *ifnames = extra_args;
2337 ifnames->names[ifnames->idx++] = value;
2343 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2346 mrvl_deinit_hifs(void)
2350 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2352 pp2_hif_deinit(hifs[i]);
2354 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2355 memset(hifs, 0, sizeof(hifs));
2359 * DPDK callback to register the virtual device.
2362 * Pointer to the virtual device.
2365 * 0 on success, negative error value otherwise.
2368 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2370 struct rte_kvargs *kvlist;
2371 struct mrvl_ifnames ifnames;
2373 uint32_t i, ifnum, cfgnum;
2376 params = rte_vdev_device_args(vdev);
2380 kvlist = rte_kvargs_parse(params, valid_args);
2384 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2385 if (ifnum > RTE_DIM(ifnames.names))
2386 goto out_free_kvlist;
2389 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2390 mrvl_get_ifnames, &ifnames);
2394 * The below system initialization should be done only once,
2395 * on the first provided configuration file
2397 if (!mrvl_qos_cfg) {
2398 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2399 RTE_LOG(INFO, PMD, "Parsing config file!\n");
2401 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2402 goto out_free_kvlist;
2403 } else if (cfgnum == 1) {
2404 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2405 mrvl_get_qoscfg, &mrvl_qos_cfg);
2412 RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n");
2414 * ret == -EEXIST is correct, it means DMA
2415 * has been already initialized (by another PMD).
2417 ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2420 goto out_free_kvlist;
2423 "DMA memory has been already initialized by a different driver.\n");
2426 ret = mrvl_init_pp2();
2428 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2429 goto out_deinit_dma;
2432 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2434 mrvl_lcore_first = RTE_MAX_LCORE;
2435 mrvl_lcore_last = 0;
2438 for (i = 0; i < ifnum; i++) {
2439 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]);
2440 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2444 mrvl_dev_num += ifnum;
2446 rte_kvargs_free(kvlist);
2451 mrvl_eth_dev_destroy(ifnames.names[i]);
2453 if (mrvl_dev_num == 0)
2456 if (mrvl_dev_num == 0)
2457 mv_sys_dma_mem_destroy();
2459 rte_kvargs_free(kvlist);
2465 * DPDK callback to remove virtual device.
2468 * Pointer to the removed virtual device.
2471 * 0 on success, negative error value otherwise.
2474 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2479 name = rte_vdev_device_name(vdev);
2483 RTE_LOG(INFO, PMD, "Removing %s\n", name);
2485 for (i = 0; i < rte_eth_dev_count(); i++) {
2486 char ifname[RTE_ETH_NAME_MAX_LEN];
2488 rte_eth_dev_get_name_by_port(i, ifname);
2489 mrvl_eth_dev_destroy(ifname);
2493 if (mrvl_dev_num == 0) {
2494 RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n");
2497 mv_sys_dma_mem_destroy();
2503 static struct rte_vdev_driver pmd_mrvl_drv = {
2504 .probe = rte_pmd_mrvl_probe,
2505 .remove = rte_pmd_mrvl_remove,
2508 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
2509 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);