4 * Copyright(c) 2017 Marvell International Ltd.
5 * Copyright(c) 2017 Semihalf.
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9 * modification, are permitted provided that the following conditions
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <rte_ethdev.h>
36 #include <rte_kvargs.h>
38 #include <rte_malloc.h>
39 #include <rte_bus_vdev.h>
41 /* Unluckily, container_of is defined by both DPDK and MUSDK,
42 * we'll declare only one version.
44 * Note that it is not used in this PMD anyway.
51 #include <linux/ethtool.h>
52 #include <linux/sockios.h>
54 #include <net/if_arp.h>
55 #include <sys/ioctl.h>
56 #include <sys/socket.h>
58 #include <sys/types.h>
60 #include "mrvl_ethdev.h"
63 /* bitmask with reserved hifs */
64 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
65 /* bitmask with reserved bpools */
66 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
67 /* bitmask with reserved kernel RSS tables */
68 #define MRVL_MUSDK_RSS_RESERVED 0x01
69 /* maximum number of available hifs */
70 #define MRVL_MUSDK_HIFS_MAX 9
73 #define MRVL_MUSDK_PREFETCH_SHIFT 2
75 /* TCAM has 25 entries reserved for uc/mc filter entries */
76 #define MRVL_MAC_ADDRS_MAX 25
77 #define MRVL_MATCH_LEN 16
78 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
79 /* Maximum allowable packet size */
80 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
82 #define MRVL_IFACE_NAME_ARG "iface"
83 #define MRVL_CFG_ARG "cfg"
85 #define MRVL_BURST_SIZE 64
87 #define MRVL_ARP_LENGTH 28
89 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
91 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
92 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
94 /* Memory size (in bytes) for MUSDK dma buffers */
95 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
97 static const char * const valid_args[] = {
103 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
104 static struct pp2_hif *hifs[RTE_MAX_LCORE];
105 static int used_bpools[PP2_NUM_PKT_PROC] = {
106 MRVL_MUSDK_BPOOLS_RESERVED,
107 MRVL_MUSDK_BPOOLS_RESERVED
110 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
111 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
112 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
114 struct mrvl_ifnames {
115 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
120 * To use buffer harvesting based on loopback port shadow queue structure
121 * was introduced for buffers information bookkeeping.
123 * Before sending the packet, related buffer information (pp2_buff_inf) is
124 * stored in shadow queue. After packet is transmitted no longer used
125 * packet buffer is released back to it's original hardware pool,
126 * on condition it originated from interface.
127 * In case it was generated by application itself i.e: mbuf->port field is
128 * 0xff then its released to software mempool.
130 struct mrvl_shadow_txq {
131 int head; /* write index - used when sending buffers */
132 int tail; /* read index - used when releasing buffers */
133 u16 size; /* queue occupied size */
134 u16 num_to_release; /* number of buffers sent, that can be released */
135 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
139 struct mrvl_priv *priv;
140 struct rte_mempool *mp;
149 struct mrvl_priv *priv;
153 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
156 static int mrvl_lcore_first;
157 static int mrvl_lcore_last;
158 static int mrvl_dev_num;
160 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
161 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
162 struct pp2_hif *hif, unsigned int core_id,
163 struct mrvl_shadow_txq *sq, int qid, int force);
166 mrvl_get_bpool_size(int pp2_id, int pool_id)
171 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
172 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
178 mrvl_reserve_bit(int *bitmap, int max)
180 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
191 mrvl_init_hif(int core_id)
193 struct pp2_hif_params params;
194 char match[MRVL_MATCH_LEN];
197 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
199 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
203 snprintf(match, sizeof(match), "hif-%d", ret);
204 memset(¶ms, 0, sizeof(params));
205 params.match = match;
206 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
207 ret = pp2_hif_init(¶ms, &hifs[core_id]);
209 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
216 static inline struct pp2_hif*
217 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
221 if (likely(hifs[core_id] != NULL))
222 return hifs[core_id];
224 rte_spinlock_lock(&priv->lock);
226 ret = mrvl_init_hif(core_id);
228 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
232 if (core_id < mrvl_lcore_first)
233 mrvl_lcore_first = core_id;
235 if (core_id > mrvl_lcore_last)
236 mrvl_lcore_last = core_id;
238 rte_spinlock_unlock(&priv->lock);
240 return hifs[core_id];
244 * Configure rss based on dpdk rss configuration.
247 * Pointer to private structure.
249 * Pointer to RSS configuration.
252 * 0 on success, negative error value otherwise.
255 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
257 if (rss_conf->rss_key)
258 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
260 if (rss_conf->rss_hf == 0) {
261 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
262 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
263 priv->ppio_params.inqs_params.hash_type =
264 PP2_PPIO_HASH_T_2_TUPLE;
265 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
266 priv->ppio_params.inqs_params.hash_type =
267 PP2_PPIO_HASH_T_5_TUPLE;
268 priv->rss_hf_tcp = 1;
269 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
270 priv->ppio_params.inqs_params.hash_type =
271 PP2_PPIO_HASH_T_5_TUPLE;
272 priv->rss_hf_tcp = 0;
281 * Ethernet device configuration.
283 * Prepare the driver for a given number of TX and RX queues and
287 * Pointer to Ethernet device structure.
290 * 0 on success, negative error value otherwise.
293 mrvl_dev_configure(struct rte_eth_dev *dev)
295 struct mrvl_priv *priv = dev->data->dev_private;
298 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
299 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
300 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
301 dev->data->dev_conf.rxmode.mq_mode);
305 if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
307 "L2 CRC stripping is always enabled in hw\n");
308 dev->data->dev_conf.rxmode.hw_strip_crc = 1;
311 if (dev->data->dev_conf.rxmode.hw_vlan_strip) {
312 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
316 if (dev->data->dev_conf.rxmode.split_hdr_size) {
317 RTE_LOG(INFO, PMD, "Split headers not supported\n");
321 if (dev->data->dev_conf.rxmode.enable_scatter) {
322 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
326 if (dev->data->dev_conf.rxmode.enable_lro) {
327 RTE_LOG(INFO, PMD, "LRO not supported\n");
331 if (dev->data->dev_conf.rxmode.jumbo_frame)
332 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
333 ETHER_HDR_LEN - ETHER_CRC_LEN;
335 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
336 dev->data->nb_rx_queues);
340 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
341 priv->ppio_params.maintain_stats = 1;
342 priv->nb_rx_queues = dev->data->nb_rx_queues;
344 if (dev->data->nb_rx_queues == 1 &&
345 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
346 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
347 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
352 return mrvl_configure_rss(priv,
353 &dev->data->dev_conf.rx_adv_conf.rss_conf);
357 * DPDK callback to change the MTU.
359 * Setting the MTU affects hardware MRU (packets larger than the MRU
363 * Pointer to Ethernet device structure.
368 * 0 on success, negative error value otherwise.
371 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
373 struct mrvl_priv *priv = dev->data->dev_private;
374 /* extra MV_MH_SIZE bytes are required for Marvell tag */
375 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
378 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
384 ret = pp2_ppio_set_mru(priv->ppio, mru);
388 return pp2_ppio_set_mtu(priv->ppio, mtu);
392 * DPDK callback to bring the link up.
395 * Pointer to Ethernet device structure.
398 * 0 on success, negative error value otherwise.
401 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
403 struct mrvl_priv *priv = dev->data->dev_private;
409 ret = pp2_ppio_enable(priv->ppio);
414 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
415 * as pp2_ppio_enable() changes port->t_mode from default 0 to
416 * PP2_TRAFFIC_INGRESS_EGRESS.
418 * Set mtu to default DPDK value here.
420 ret = mrvl_mtu_set(dev, dev->data->mtu);
422 pp2_ppio_disable(priv->ppio);
428 * DPDK callback to bring the link down.
431 * Pointer to Ethernet device structure.
434 * 0 on success, negative error value otherwise.
437 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
439 struct mrvl_priv *priv = dev->data->dev_private;
444 return pp2_ppio_disable(priv->ppio);
448 * DPDK callback to start the device.
451 * Pointer to Ethernet device structure.
454 * 0 on success, negative errno value on failure.
457 mrvl_dev_start(struct rte_eth_dev *dev)
459 struct mrvl_priv *priv = dev->data->dev_private;
460 char match[MRVL_MATCH_LEN];
461 int ret = 0, def_init_size;
463 snprintf(match, sizeof(match), "ppio-%d:%d",
464 priv->pp_id, priv->ppio_id);
465 priv->ppio_params.match = match;
468 * Calculate the minimum bpool size for refill feature as follows:
469 * 2 default burst sizes multiply by number of rx queues.
470 * If the bpool size will be below this value, new buffers will
471 * be added to the pool.
473 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
475 /* In case initial bpool size configured in queues setup is
476 * smaller than minimum size add more buffers
478 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
479 if (priv->bpool_init_size < def_init_size) {
480 int buffs_to_add = def_init_size - priv->bpool_init_size;
482 priv->bpool_init_size += buffs_to_add;
483 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
485 RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
489 * Calculate the maximum bpool size for refill feature as follows:
490 * maximum number of descriptors in rx queue multiply by number
491 * of rx queues plus minimum bpool size.
492 * In case the bpool size will exceed this value, superfluous buffers
495 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
496 priv->bpool_min_size;
498 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
500 RTE_LOG(ERR, PMD, "Failed to init ppio\n");
505 * In case there are some some stale uc/mc mac addresses flush them
506 * here. It cannot be done during mrvl_dev_close() as port information
507 * is already gone at that point (due to pp2_ppio_deinit() in
510 if (!priv->uc_mc_flushed) {
511 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
514 "Failed to flush uc/mc filter list\n");
517 priv->uc_mc_flushed = 1;
520 if (!priv->vlan_flushed) {
521 ret = pp2_ppio_flush_vlan(priv->ppio);
523 RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
526 * once pp2_ppio_flush_vlan() is supported jump to out
530 priv->vlan_flushed = 1;
533 /* For default QoS config, don't start classifier. */
535 ret = mrvl_start_qos_mapping(priv);
537 RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n");
542 ret = mrvl_dev_set_link_up(dev);
544 RTE_LOG(ERR, PMD, "Failed to set link up\n");
550 RTE_LOG(ERR, PMD, "Failed to start device\n");
551 pp2_ppio_deinit(priv->ppio);
556 * Flush receive queues.
559 * Pointer to Ethernet device structure.
562 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
566 RTE_LOG(INFO, PMD, "Flushing rx queues\n");
567 for (i = 0; i < dev->data->nb_rx_queues; i++) {
571 struct mrvl_rxq *q = dev->data->rx_queues[i];
572 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
574 num = MRVL_PP2_RXD_MAX;
575 ret = pp2_ppio_recv(q->priv->ppio,
576 q->priv->rxq_map[q->queue_id].tc,
577 q->priv->rxq_map[q->queue_id].inq,
578 descs, (uint16_t *)&num);
579 } while (ret == 0 && num);
584 * Flush transmit shadow queues.
587 * Pointer to Ethernet device structure.
590 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
593 struct mrvl_txq *txq;
595 RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
596 for (i = 0; i < dev->data->nb_tx_queues; i++) {
597 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
599 for (j = 0; j < RTE_MAX_LCORE; j++) {
600 struct mrvl_shadow_txq *sq;
605 sq = &txq->shadow_txqs[j];
606 mrvl_free_sent_buffers(txq->priv->ppio,
607 hifs[j], j, sq, txq->queue_id, 1);
608 while (sq->tail != sq->head) {
609 uint64_t addr = cookie_addr_high |
610 sq->ent[sq->tail].buff.cookie;
612 (struct rte_mbuf *)addr);
613 sq->tail = (sq->tail + 1) &
614 MRVL_PP2_TX_SHADOWQ_MASK;
616 memset(sq, 0, sizeof(*sq));
622 * Flush hardware bpool (buffer-pool).
625 * Pointer to Ethernet device structure.
628 mrvl_flush_bpool(struct rte_eth_dev *dev)
630 struct mrvl_priv *priv = dev->data->dev_private;
634 unsigned int core_id = rte_lcore_id();
636 if (core_id == LCORE_ID_ANY)
639 hif = mrvl_get_hif(priv, core_id);
641 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
643 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
648 struct pp2_buff_inf inf;
651 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
655 addr = cookie_addr_high | inf.cookie;
656 rte_pktmbuf_free((struct rte_mbuf *)addr);
661 * DPDK callback to stop the device.
664 * Pointer to Ethernet device structure.
667 mrvl_dev_stop(struct rte_eth_dev *dev)
669 struct mrvl_priv *priv = dev->data->dev_private;
671 mrvl_dev_set_link_down(dev);
672 mrvl_flush_rx_queues(dev);
673 mrvl_flush_tx_shadow_queues(dev);
675 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
676 priv->qos_tbl = NULL;
678 pp2_ppio_deinit(priv->ppio);
683 * DPDK callback to close the device.
686 * Pointer to Ethernet device structure.
689 mrvl_dev_close(struct rte_eth_dev *dev)
691 struct mrvl_priv *priv = dev->data->dev_private;
694 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
695 struct pp2_ppio_tc_params *tc_params =
696 &priv->ppio_params.inqs_params.tcs_params[i];
698 if (tc_params->inqs_params) {
699 rte_free(tc_params->inqs_params);
700 tc_params->inqs_params = NULL;
704 mrvl_flush_bpool(dev);
708 * DPDK callback to retrieve physical link information.
711 * Pointer to Ethernet device structure.
712 * @param wait_to_complete
713 * Wait for request completion (ignored).
716 * 0 on success, negative error value otherwise.
719 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
723 * once MUSDK provides necessary API use it here
725 struct mrvl_priv *priv = dev->data->dev_private;
726 struct ethtool_cmd edata;
728 int ret, fd, link_up;
733 edata.cmd = ETHTOOL_GSET;
735 strcpy(req.ifr_name, dev->data->name);
736 req.ifr_data = (void *)&edata;
738 fd = socket(AF_INET, SOCK_DGRAM, 0);
742 ret = ioctl(fd, SIOCETHTOOL, &req);
750 switch (ethtool_cmd_speed(&edata)) {
752 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
755 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
758 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
761 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
764 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
767 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
768 ETH_LINK_HALF_DUPLEX;
769 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
771 pp2_ppio_get_link_state(priv->ppio, &link_up);
772 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
778 * DPDK callback to enable promiscuous mode.
781 * Pointer to Ethernet device structure.
784 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
786 struct mrvl_priv *priv = dev->data->dev_private;
792 ret = pp2_ppio_set_promisc(priv->ppio, 1);
794 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
798 * DPDK callback to enable allmulti mode.
801 * Pointer to Ethernet device structure.
804 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
806 struct mrvl_priv *priv = dev->data->dev_private;
812 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
814 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
818 * DPDK callback to disable promiscuous mode.
821 * Pointer to Ethernet device structure.
824 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
826 struct mrvl_priv *priv = dev->data->dev_private;
832 ret = pp2_ppio_set_promisc(priv->ppio, 0);
834 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
838 * DPDK callback to disable allmulticast mode.
841 * Pointer to Ethernet device structure.
844 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
846 struct mrvl_priv *priv = dev->data->dev_private;
852 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
854 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
858 * DPDK callback to remove a MAC address.
861 * Pointer to Ethernet device structure.
866 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
868 struct mrvl_priv *priv = dev->data->dev_private;
869 char buf[ETHER_ADDR_FMT_SIZE];
875 ret = pp2_ppio_remove_mac_addr(priv->ppio,
876 dev->data->mac_addrs[index].addr_bytes);
878 ether_format_addr(buf, sizeof(buf),
879 &dev->data->mac_addrs[index]);
880 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
885 * DPDK callback to add a MAC address.
888 * Pointer to Ethernet device structure.
890 * MAC address to register.
894 * VMDq pool index to associate address with (unused).
897 * 0 on success, negative error value otherwise.
900 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
901 uint32_t index, uint32_t vmdq __rte_unused)
903 struct mrvl_priv *priv = dev->data->dev_private;
904 char buf[ETHER_ADDR_FMT_SIZE];
908 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
915 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
916 * parameter uc_filter_max. Maximum number of mc addresses is then
917 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
920 * If more than uc_filter_max uc addresses were added to filter list
921 * then NIC will switch to promiscuous mode automatically.
923 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
924 * were added to filter list then NIC will switch to all-multicast mode
927 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
929 ether_format_addr(buf, sizeof(buf), mac_addr);
930 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
938 * DPDK callback to set the primary MAC address.
941 * Pointer to Ethernet device structure.
943 * MAC address to register.
946 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
948 struct mrvl_priv *priv = dev->data->dev_private;
954 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
956 char buf[ETHER_ADDR_FMT_SIZE];
957 ether_format_addr(buf, sizeof(buf), mac_addr);
958 RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf);
963 * DPDK callback to get device statistics.
966 * Pointer to Ethernet device structure.
968 * Stats structure output buffer.
971 * 0 on success, negative error value otherwise.
974 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
976 struct mrvl_priv *priv = dev->data->dev_private;
977 struct pp2_ppio_statistics ppio_stats;
978 uint64_t drop_mac = 0;
979 unsigned int i, idx, ret;
984 for (i = 0; i < dev->data->nb_rx_queues; i++) {
985 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
986 struct pp2_ppio_inq_statistics rx_stats;
992 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
994 "rx queue %d stats out of range (0 - %d)\n",
995 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
999 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1000 priv->rxq_map[idx].tc,
1001 priv->rxq_map[idx].inq,
1003 if (unlikely(ret)) {
1005 "Failed to update rx queue %d stats\n", idx);
1009 stats->q_ibytes[idx] = rxq->bytes_recv;
1010 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1011 stats->q_errors[idx] = rx_stats.drop_early +
1012 rx_stats.drop_fullq +
1015 stats->ibytes += rxq->bytes_recv;
1016 drop_mac += rxq->drop_mac;
1019 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1020 struct mrvl_txq *txq = dev->data->tx_queues[i];
1021 struct pp2_ppio_outq_statistics tx_stats;
1026 idx = txq->queue_id;
1027 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1029 "tx queue %d stats out of range (0 - %d)\n",
1030 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1033 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1035 if (unlikely(ret)) {
1037 "Failed to update tx queue %d stats\n", idx);
1041 stats->q_opackets[idx] = tx_stats.deq_desc;
1042 stats->q_obytes[idx] = txq->bytes_sent;
1043 stats->obytes += txq->bytes_sent;
1046 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1047 if (unlikely(ret)) {
1048 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
1052 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1053 stats->opackets += ppio_stats.tx_packets;
1054 stats->imissed += ppio_stats.rx_fullq_dropped +
1055 ppio_stats.rx_bm_dropped +
1056 ppio_stats.rx_early_dropped +
1057 ppio_stats.rx_fifo_dropped +
1058 ppio_stats.rx_cls_dropped;
1059 stats->ierrors = drop_mac;
1065 * DPDK callback to clear device statistics.
1068 * Pointer to Ethernet device structure.
1071 mrvl_stats_reset(struct rte_eth_dev *dev)
1073 struct mrvl_priv *priv = dev->data->dev_private;
1079 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1080 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1082 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1083 priv->rxq_map[i].inq, NULL, 1);
1084 rxq->bytes_recv = 0;
1088 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1089 struct mrvl_txq *txq = dev->data->tx_queues[i];
1091 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1092 txq->bytes_sent = 0;
1095 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1099 * DPDK callback to get information about the device.
1102 * Pointer to Ethernet device structure (unused).
1104 * Info structure output buffer.
1107 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1108 struct rte_eth_dev_info *info)
1110 info->speed_capa = ETH_LINK_SPEED_10M |
1111 ETH_LINK_SPEED_100M |
1115 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1116 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1117 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1119 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1120 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1121 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1123 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1124 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1125 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1127 info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME |
1128 DEV_RX_OFFLOAD_VLAN_FILTER |
1129 DEV_RX_OFFLOAD_IPV4_CKSUM |
1130 DEV_RX_OFFLOAD_UDP_CKSUM |
1131 DEV_RX_OFFLOAD_TCP_CKSUM;
1133 info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
1134 DEV_TX_OFFLOAD_UDP_CKSUM |
1135 DEV_TX_OFFLOAD_TCP_CKSUM;
1137 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1138 ETH_RSS_NONFRAG_IPV4_TCP |
1139 ETH_RSS_NONFRAG_IPV4_UDP;
1141 /* By default packets are dropped if no descriptors are available */
1142 info->default_rxconf.rx_drop_en = 1;
1144 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1148 * Return supported packet types.
1151 * Pointer to Ethernet device structure (unused).
1154 * Const pointer to the table with supported packet types.
1156 static const uint32_t *
1157 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1159 static const uint32_t ptypes[] = {
1162 RTE_PTYPE_L3_IPV4_EXT,
1163 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1165 RTE_PTYPE_L3_IPV6_EXT,
1166 RTE_PTYPE_L2_ETHER_ARP,
1175 * DPDK callback to get information about specific receive queue.
1178 * Pointer to Ethernet device structure.
1179 * @param rx_queue_id
1180 * Receive queue index.
1182 * Receive queue information structure.
1184 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1185 struct rte_eth_rxq_info *qinfo)
1187 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1188 struct mrvl_priv *priv = dev->data->dev_private;
1189 int inq = priv->rxq_map[rx_queue_id].inq;
1190 int tc = priv->rxq_map[rx_queue_id].tc;
1191 struct pp2_ppio_tc_params *tc_params =
1192 &priv->ppio_params.inqs_params.tcs_params[tc];
1195 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1199 * DPDK callback to get information about specific transmit queue.
1202 * Pointer to Ethernet device structure.
1203 * @param tx_queue_id
1204 * Transmit queue index.
1206 * Transmit queue information structure.
1208 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1209 struct rte_eth_txq_info *qinfo)
1211 struct mrvl_priv *priv = dev->data->dev_private;
1214 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1218 * DPDK callback to Configure a VLAN filter.
1221 * Pointer to Ethernet device structure.
1223 * VLAN ID to filter.
1228 * 0 on success, negative error value otherwise.
1231 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1233 struct mrvl_priv *priv = dev->data->dev_private;
1238 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1239 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1243 * Release buffers to hardware bpool (buffer-pool)
1246 * Receive queue pointer.
1248 * Number of buffers to release to bpool.
1251 * 0 on success, negative error value otherwise.
1254 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1256 struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
1257 struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
1259 unsigned int core_id;
1260 struct pp2_hif *hif;
1261 struct pp2_bpool *bpool;
1263 core_id = rte_lcore_id();
1264 if (core_id == LCORE_ID_ANY)
1267 hif = mrvl_get_hif(rxq->priv, core_id);
1271 bpool = rxq->priv->bpool;
1273 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1277 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1279 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1281 for (i = 0; i < num; i++) {
1282 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1283 != cookie_addr_high) {
1285 "mbuf virtual addr high 0x%lx out of range\n",
1286 (uint64_t)mbufs[i] >> 32);
1290 entries[i].buff.addr =
1291 rte_mbuf_data_iova_default(mbufs[i]);
1292 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1293 entries[i].bpool = bpool;
1296 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1297 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1304 for (; i < num; i++)
1305 rte_pktmbuf_free(mbufs[i]);
1311 * DPDK callback to configure the receive queue.
1314 * Pointer to Ethernet device structure.
1318 * Number of descriptors to configure in queue.
1320 * NUMA socket on which memory must be allocated.
1322 * Thresholds parameters (unused_).
1324 * Memory pool for buffer allocations.
1327 * 0 on success, negative error value otherwise.
1330 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1331 unsigned int socket,
1332 const struct rte_eth_rxconf *conf __rte_unused,
1333 struct rte_mempool *mp)
1335 struct mrvl_priv *priv = dev->data->dev_private;
1336 struct mrvl_rxq *rxq;
1338 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1341 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1343 * Unknown TC mapping, mapping will not have a correct queue.
1345 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1346 idx, priv->ppio_id);
1350 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1351 MRVL_PKT_EFFEC_OFFS;
1352 if (min_size < max_rx_pkt_len) {
1354 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1355 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1356 MRVL_PKT_EFFEC_OFFS,
1361 if (dev->data->rx_queues[idx]) {
1362 rte_free(dev->data->rx_queues[idx]);
1363 dev->data->rx_queues[idx] = NULL;
1366 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1372 rxq->cksum_enabled = dev->data->dev_conf.rxmode.hw_ip_checksum;
1373 rxq->queue_id = idx;
1374 rxq->port_id = dev->data->port_id;
1375 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1377 tc = priv->rxq_map[rxq->queue_id].tc,
1378 inq = priv->rxq_map[rxq->queue_id].inq;
1379 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1382 ret = mrvl_fill_bpool(rxq, desc);
1388 priv->bpool_init_size += desc;
1390 dev->data->rx_queues[idx] = rxq;
1396 * DPDK callback to release the receive queue.
1399 * Generic receive queue pointer.
1402 mrvl_rx_queue_release(void *rxq)
1404 struct mrvl_rxq *q = rxq;
1405 struct pp2_ppio_tc_params *tc_params;
1406 int i, num, tc, inq;
1407 struct pp2_hif *hif;
1408 unsigned int core_id = rte_lcore_id();
1410 if (core_id == LCORE_ID_ANY)
1413 hif = mrvl_get_hif(q->priv, core_id);
1418 tc = q->priv->rxq_map[q->queue_id].tc;
1419 inq = q->priv->rxq_map[q->queue_id].inq;
1420 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1421 num = tc_params->inqs_params[inq].size;
1422 for (i = 0; i < num; i++) {
1423 struct pp2_buff_inf inf;
1426 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1427 addr = cookie_addr_high | inf.cookie;
1428 rte_pktmbuf_free((struct rte_mbuf *)addr);
1435 * DPDK callback to configure the transmit queue.
1438 * Pointer to Ethernet device structure.
1440 * Transmit queue index.
1442 * Number of descriptors to configure in the queue.
1444 * NUMA socket on which memory must be allocated.
1446 * Thresholds parameters (unused).
1449 * 0 on success, negative error value otherwise.
1452 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1453 unsigned int socket,
1454 const struct rte_eth_txconf *conf __rte_unused)
1456 struct mrvl_priv *priv = dev->data->dev_private;
1457 struct mrvl_txq *txq;
1459 if (dev->data->tx_queues[idx]) {
1460 rte_free(dev->data->tx_queues[idx]);
1461 dev->data->tx_queues[idx] = NULL;
1464 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1469 txq->queue_id = idx;
1470 txq->port_id = dev->data->port_id;
1471 dev->data->tx_queues[idx] = txq;
1473 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1474 priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1480 * DPDK callback to release the transmit queue.
1483 * Generic transmit queue pointer.
1486 mrvl_tx_queue_release(void *txq)
1488 struct mrvl_txq *q = txq;
1497 * Update RSS hash configuration
1500 * Pointer to Ethernet device structure.
1502 * Pointer to RSS configuration.
1505 * 0 on success, negative error value otherwise.
1508 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1509 struct rte_eth_rss_conf *rss_conf)
1511 struct mrvl_priv *priv = dev->data->dev_private;
1513 return mrvl_configure_rss(priv, rss_conf);
1517 * DPDK callback to get RSS hash configuration.
1520 * Pointer to Ethernet device structure.
1522 * Pointer to RSS configuration.
1528 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1529 struct rte_eth_rss_conf *rss_conf)
1531 struct mrvl_priv *priv = dev->data->dev_private;
1532 enum pp2_ppio_hash_type hash_type =
1533 priv->ppio_params.inqs_params.hash_type;
1535 rss_conf->rss_key = NULL;
1537 if (hash_type == PP2_PPIO_HASH_T_NONE)
1538 rss_conf->rss_hf = 0;
1539 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1540 rss_conf->rss_hf = ETH_RSS_IPV4;
1541 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1542 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1543 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1544 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1549 static const struct eth_dev_ops mrvl_ops = {
1550 .dev_configure = mrvl_dev_configure,
1551 .dev_start = mrvl_dev_start,
1552 .dev_stop = mrvl_dev_stop,
1553 .dev_set_link_up = mrvl_dev_set_link_up,
1554 .dev_set_link_down = mrvl_dev_set_link_down,
1555 .dev_close = mrvl_dev_close,
1556 .link_update = mrvl_link_update,
1557 .promiscuous_enable = mrvl_promiscuous_enable,
1558 .allmulticast_enable = mrvl_allmulticast_enable,
1559 .promiscuous_disable = mrvl_promiscuous_disable,
1560 .allmulticast_disable = mrvl_allmulticast_disable,
1561 .mac_addr_remove = mrvl_mac_addr_remove,
1562 .mac_addr_add = mrvl_mac_addr_add,
1563 .mac_addr_set = mrvl_mac_addr_set,
1564 .mtu_set = mrvl_mtu_set,
1565 .stats_get = mrvl_stats_get,
1566 .stats_reset = mrvl_stats_reset,
1567 .dev_infos_get = mrvl_dev_infos_get,
1568 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1569 .rxq_info_get = mrvl_rxq_info_get,
1570 .txq_info_get = mrvl_txq_info_get,
1571 .vlan_filter_set = mrvl_vlan_filter_set,
1572 .rx_queue_setup = mrvl_rx_queue_setup,
1573 .rx_queue_release = mrvl_rx_queue_release,
1574 .tx_queue_setup = mrvl_tx_queue_setup,
1575 .tx_queue_release = mrvl_tx_queue_release,
1576 .rss_hash_update = mrvl_rss_hash_update,
1577 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1581 * Return packet type information and l3/l4 offsets.
1584 * Pointer to the received packet descriptor.
1591 * Packet type information.
1593 static inline uint64_t
1594 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1595 uint8_t *l3_offset, uint8_t *l4_offset)
1597 enum pp2_inq_l3_type l3_type;
1598 enum pp2_inq_l4_type l4_type;
1599 uint64_t packet_type;
1601 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1602 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1604 packet_type = RTE_PTYPE_L2_ETHER;
1607 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1608 packet_type |= RTE_PTYPE_L3_IPV4;
1610 case PP2_INQ_L3_TYPE_IPV4_OK:
1611 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1613 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1614 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1616 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1617 packet_type |= RTE_PTYPE_L3_IPV6;
1619 case PP2_INQ_L3_TYPE_IPV6_EXT:
1620 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1622 case PP2_INQ_L3_TYPE_ARP:
1623 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1625 * In case of ARP l4_offset is set to wrong value.
1626 * Set it to proper one so that later on mbuf->l3_len can be
1627 * calculated subtracting l4_offset and l3_offset.
1629 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1632 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1637 case PP2_INQ_L4_TYPE_TCP:
1638 packet_type |= RTE_PTYPE_L4_TCP;
1640 case PP2_INQ_L4_TYPE_UDP:
1641 packet_type |= RTE_PTYPE_L4_UDP;
1644 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1652 * Get offload information from the received packet descriptor.
1655 * Pointer to the received packet descriptor.
1658 * Mbuf offload flags.
1660 static inline uint64_t
1661 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1664 enum pp2_inq_desc_status status;
1666 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1667 if (unlikely(status != PP2_DESC_ERR_OK))
1668 flags = PKT_RX_IP_CKSUM_BAD;
1670 flags = PKT_RX_IP_CKSUM_GOOD;
1672 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1673 if (unlikely(status != PP2_DESC_ERR_OK))
1674 flags |= PKT_RX_L4_CKSUM_BAD;
1676 flags |= PKT_RX_L4_CKSUM_GOOD;
1682 * DPDK callback for receive.
1685 * Generic pointer to the receive queue.
1687 * Array to store received packets.
1689 * Maximum number of packets in array.
1692 * Number of packets successfully received.
1695 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1697 struct mrvl_rxq *q = rxq;
1698 struct pp2_ppio_desc descs[nb_pkts];
1699 struct pp2_bpool *bpool;
1700 int i, ret, rx_done = 0;
1702 struct pp2_hif *hif;
1703 unsigned int core_id = rte_lcore_id();
1705 hif = mrvl_get_hif(q->priv, core_id);
1707 if (unlikely(!q->priv->ppio || !hif))
1710 bpool = q->priv->bpool;
1712 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1713 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1714 if (unlikely(ret < 0)) {
1715 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1718 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1720 for (i = 0; i < nb_pkts; i++) {
1721 struct rte_mbuf *mbuf;
1722 uint8_t l3_offset, l4_offset;
1723 enum pp2_inq_desc_status status;
1726 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1727 struct pp2_ppio_desc *pref_desc;
1730 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1731 pref_addr = cookie_addr_high |
1732 pp2_ppio_inq_desc_get_cookie(pref_desc);
1733 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1734 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1737 addr = cookie_addr_high |
1738 pp2_ppio_inq_desc_get_cookie(&descs[i]);
1739 mbuf = (struct rte_mbuf *)addr;
1740 rte_pktmbuf_reset(mbuf);
1742 /* drop packet in case of mac, overrun or resource error */
1743 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1744 if (unlikely(status != PP2_DESC_ERR_OK)) {
1745 struct pp2_buff_inf binf = {
1746 .addr = rte_mbuf_data_iova_default(mbuf),
1747 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1750 pp2_bpool_put_buff(hif, bpool, &binf);
1751 mrvl_port_bpool_size
1752 [bpool->pp2_id][bpool->id][core_id]++;
1757 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1758 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1759 mbuf->data_len = mbuf->pkt_len;
1760 mbuf->port = q->port_id;
1762 mrvl_desc_to_packet_type_and_offset(&descs[i],
1765 mbuf->l2_len = l3_offset;
1766 mbuf->l3_len = l4_offset - l3_offset;
1768 if (likely(q->cksum_enabled))
1769 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
1771 rx_pkts[rx_done++] = mbuf;
1772 q->bytes_recv += mbuf->pkt_len;
1775 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1776 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1778 if (unlikely(num <= q->priv->bpool_min_size ||
1779 (!rx_done && num < q->priv->bpool_init_size))) {
1780 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1782 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1783 } else if (unlikely(num > q->priv->bpool_max_size)) {
1785 int pkt_to_remove = num - q->priv->bpool_init_size;
1786 struct rte_mbuf *mbuf;
1787 struct pp2_buff_inf buff;
1790 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1791 bpool->pp2_id, q->priv->ppio->port_id,
1792 bpool->id, pkt_to_remove, num,
1793 q->priv->bpool_init_size);
1795 for (i = 0; i < pkt_to_remove; i++) {
1796 ret = pp2_bpool_get_buff(hif, bpool, &buff);
1799 mbuf = (struct rte_mbuf *)
1800 (cookie_addr_high | buff.cookie);
1801 rte_pktmbuf_free(mbuf);
1803 mrvl_port_bpool_size
1804 [bpool->pp2_id][bpool->id][core_id] -= i;
1806 rte_spinlock_unlock(&q->priv->lock);
1813 * Prepare offload information.
1817 * @param packet_type
1818 * Packet type bitfield.
1820 * Pointer to the pp2_ouq_l3_type structure.
1822 * Pointer to the pp2_outq_l4_type structure.
1823 * @param gen_l3_cksum
1824 * Will be set to 1 in case l3 checksum is computed.
1826 * Will be set to 1 in case l4 checksum is computed.
1829 * 0 on success, negative error value otherwise.
1832 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
1833 enum pp2_outq_l3_type *l3_type,
1834 enum pp2_outq_l4_type *l4_type,
1839 * Based on ol_flags prepare information
1840 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
1843 if (ol_flags & PKT_TX_IPV4) {
1844 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
1845 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
1846 } else if (ol_flags & PKT_TX_IPV6) {
1847 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
1848 /* no checksum for ipv6 header */
1851 /* if something different then stop processing */
1855 ol_flags &= PKT_TX_L4_MASK;
1856 if ((packet_type & RTE_PTYPE_L4_TCP) &&
1857 ol_flags == PKT_TX_TCP_CKSUM) {
1858 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
1860 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
1861 ol_flags == PKT_TX_UDP_CKSUM) {
1862 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
1865 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
1866 /* no checksum for other type */
1874 * Release already sent buffers to bpool (buffer-pool).
1877 * Pointer to the port structure.
1879 * Pointer to the MUSDK hardware interface.
1881 * Pointer to the shadow queue.
1885 * Force releasing packets.
1888 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1889 unsigned int core_id, struct mrvl_shadow_txq *sq,
1892 struct buff_release_entry *entry;
1893 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1896 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1898 sq->num_to_release += nb_done;
1900 if (likely(!force &&
1901 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1904 nb_done = sq->num_to_release;
1905 sq->num_to_release = 0;
1907 for (i = 0; i < nb_done; i++) {
1908 entry = &sq->ent[sq->tail + num];
1909 if (unlikely(!entry->buff.addr)) {
1911 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1912 sq->tail, (u64)entry->buff.cookie,
1913 (u64)entry->buff.addr);
1918 if (unlikely(!entry->bpool)) {
1919 struct rte_mbuf *mbuf;
1921 mbuf = (struct rte_mbuf *)
1922 (cookie_addr_high | entry->buff.cookie);
1923 rte_pktmbuf_free(mbuf);
1928 mrvl_port_bpool_size
1929 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
1931 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
1936 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1938 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1945 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1946 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1952 * DPDK callback for transmit.
1955 * Generic pointer transmit queue.
1957 * Packets to transmit.
1959 * Number of packets in array.
1962 * Number of packets successfully transmitted.
1965 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1967 struct mrvl_txq *q = txq;
1968 struct mrvl_shadow_txq *sq;
1969 struct pp2_hif *hif;
1970 struct pp2_ppio_desc descs[nb_pkts];
1971 unsigned int core_id = rte_lcore_id();
1972 int i, ret, bytes_sent = 0;
1973 uint16_t num, sq_free_size;
1976 hif = mrvl_get_hif(q->priv, core_id);
1977 sq = &q->shadow_txqs[core_id];
1979 if (unlikely(!q->priv->ppio || !hif))
1983 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
1984 sq, q->queue_id, 0);
1986 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
1987 if (unlikely(nb_pkts > sq_free_size)) {
1989 "No room in shadow queue for %d packets! %d packets will be sent.\n",
1990 nb_pkts, sq_free_size);
1991 nb_pkts = sq_free_size;
1994 for (i = 0; i < nb_pkts; i++) {
1995 struct rte_mbuf *mbuf = tx_pkts[i];
1996 int gen_l3_cksum, gen_l4_cksum;
1997 enum pp2_outq_l3_type l3_type;
1998 enum pp2_outq_l4_type l4_type;
2000 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2001 struct rte_mbuf *pref_pkt_hdr;
2003 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2004 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2005 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2008 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2009 sq->ent[sq->head].buff.addr =
2010 rte_mbuf_data_iova_default(mbuf);
2011 sq->ent[sq->head].bpool =
2012 (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
2013 NULL : mrvl_port_to_bpool_lookup[mbuf->port];
2014 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2017 pp2_ppio_outq_desc_reset(&descs[i]);
2018 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2019 rte_pktmbuf_iova(mbuf));
2020 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2021 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2022 rte_pktmbuf_pkt_len(mbuf));
2024 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2026 * in case unsupported ol_flags were passed
2027 * do not update descriptor offload information
2029 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2030 &l3_type, &l4_type, &gen_l3_cksum,
2035 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2037 mbuf->l2_len + mbuf->l3_len,
2038 gen_l3_cksum, gen_l4_cksum);
2042 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2043 /* number of packets that were not sent */
2044 if (unlikely(num > nb_pkts)) {
2045 for (i = nb_pkts; i < num; i++) {
2046 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2047 MRVL_PP2_TX_SHADOWQ_MASK;
2048 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2050 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2052 sq->size -= num - nb_pkts;
2055 q->bytes_sent += bytes_sent;
2061 * Initialize packet processor.
2064 * 0 on success, negative error value otherwise.
2069 struct pp2_init_params init_params;
2071 memset(&init_params, 0, sizeof(init_params));
2072 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2073 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2074 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2076 return pp2_init(&init_params);
2080 * Deinitialize packet processor.
2083 * 0 on success, negative error value otherwise.
2086 mrvl_deinit_pp2(void)
2092 * Create private device structure.
2095 * Pointer to the port name passed in the initialization parameters.
2098 * Pointer to the newly allocated private device structure.
2100 static struct mrvl_priv *
2101 mrvl_priv_create(const char *dev_name)
2103 struct pp2_bpool_params bpool_params;
2104 char match[MRVL_MATCH_LEN];
2105 struct mrvl_priv *priv;
2108 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2112 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2113 &priv->pp_id, &priv->ppio_id);
2117 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2118 PP2_BPOOL_NUM_POOLS);
2121 priv->bpool_bit = bpool_bit;
2123 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2125 memset(&bpool_params, 0, sizeof(bpool_params));
2126 bpool_params.match = match;
2127 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2128 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2130 goto out_clear_bpool_bit;
2132 priv->ppio_params.type = PP2_PPIO_T_NIC;
2133 rte_spinlock_init(&priv->lock);
2136 out_clear_bpool_bit:
2137 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2144 * Create device representing Ethernet port.
2147 * Pointer to the port's name.
2150 * 0 on success, negative error value otherwise.
2153 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2155 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2156 struct rte_eth_dev *eth_dev;
2157 struct mrvl_priv *priv;
2160 eth_dev = rte_eth_dev_allocate(name);
2164 priv = mrvl_priv_create(name);
2170 eth_dev->data->mac_addrs =
2171 rte_zmalloc("mac_addrs",
2172 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2173 if (!eth_dev->data->mac_addrs) {
2174 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2179 memset(&req, 0, sizeof(req));
2180 strcpy(req.ifr_name, name);
2181 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2185 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2186 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2188 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2189 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2190 eth_dev->data->kdrv = RTE_KDRV_NONE;
2191 eth_dev->data->dev_private = priv;
2192 eth_dev->device = &vdev->device;
2193 eth_dev->dev_ops = &mrvl_ops;
2197 rte_free(eth_dev->data->mac_addrs);
2199 rte_eth_dev_release_port(eth_dev);
2207 * Cleanup previously created device representing Ethernet port.
2210 * Pointer to the port name.
2213 mrvl_eth_dev_destroy(const char *name)
2215 struct rte_eth_dev *eth_dev;
2216 struct mrvl_priv *priv;
2218 eth_dev = rte_eth_dev_allocated(name);
2222 priv = eth_dev->data->dev_private;
2223 pp2_bpool_deinit(priv->bpool);
2224 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2226 rte_free(eth_dev->data->mac_addrs);
2227 rte_eth_dev_release_port(eth_dev);
2231 * Callback used by rte_kvargs_process() during argument parsing.
2234 * Pointer to the parsed key (unused).
2236 * Pointer to the parsed value.
2238 * Pointer to the extra arguments which contains address of the
2239 * table of pointers to parsed interface names.
2245 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2248 struct mrvl_ifnames *ifnames = extra_args;
2250 ifnames->names[ifnames->idx++] = value;
2256 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2259 mrvl_deinit_hifs(void)
2263 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2265 pp2_hif_deinit(hifs[i]);
2267 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2268 memset(hifs, 0, sizeof(hifs));
2272 * DPDK callback to register the virtual device.
2275 * Pointer to the virtual device.
2278 * 0 on success, negative error value otherwise.
2281 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2283 struct rte_kvargs *kvlist;
2284 struct mrvl_ifnames ifnames;
2286 uint32_t i, ifnum, cfgnum;
2289 params = rte_vdev_device_args(vdev);
2293 kvlist = rte_kvargs_parse(params, valid_args);
2297 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2298 if (ifnum > RTE_DIM(ifnames.names))
2299 goto out_free_kvlist;
2302 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2303 mrvl_get_ifnames, &ifnames);
2307 * The below system initialization should be done only once,
2308 * on the first provided configuration file
2310 if (!mrvl_qos_cfg) {
2311 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2312 RTE_LOG(INFO, PMD, "Parsing config file!\n");
2314 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2315 goto out_free_kvlist;
2316 } else if (cfgnum == 1) {
2317 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2318 mrvl_get_qoscfg, &mrvl_qos_cfg);
2325 RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n");
2327 * ret == -EEXIST is correct, it means DMA
2328 * has been already initialized (by another PMD).
2330 ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2333 goto out_free_kvlist;
2336 "DMA memory has been already initialized by a different driver.\n");
2339 ret = mrvl_init_pp2();
2341 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2342 goto out_deinit_dma;
2345 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2347 mrvl_lcore_first = RTE_MAX_LCORE;
2348 mrvl_lcore_last = 0;
2351 for (i = 0; i < ifnum; i++) {
2352 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]);
2353 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2357 mrvl_dev_num += ifnum;
2359 rte_kvargs_free(kvlist);
2364 mrvl_eth_dev_destroy(ifnames.names[i]);
2366 if (mrvl_dev_num == 0)
2369 if (mrvl_dev_num == 0)
2370 mv_sys_dma_mem_destroy();
2372 rte_kvargs_free(kvlist);
2378 * DPDK callback to remove virtual device.
2381 * Pointer to the removed virtual device.
2384 * 0 on success, negative error value otherwise.
2387 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2392 name = rte_vdev_device_name(vdev);
2396 RTE_LOG(INFO, PMD, "Removing %s\n", name);
2398 for (i = 0; i < rte_eth_dev_count(); i++) {
2399 char ifname[RTE_ETH_NAME_MAX_LEN];
2401 rte_eth_dev_get_name_by_port(i, ifname);
2402 mrvl_eth_dev_destroy(ifname);
2406 if (mrvl_dev_num == 0) {
2407 RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n");
2410 mv_sys_dma_mem_destroy();
2416 static struct rte_vdev_driver pmd_mrvl_drv = {
2417 .probe = rte_pmd_mrvl_probe,
2418 .remove = rte_pmd_mrvl_remove,
2421 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
2422 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);