drivers/net/mrvl/mrvl_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2017 Semihalf. All rights reserved.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Semihalf nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <rte_ethdev.h>
  34 #include <rte_kvargs.h>
  35 #include <rte_log.h>
  36 #include <rte_malloc.h>
  37 #include <rte_vdev.h>
  38
  39 /* Unluckily, container_of is defined by both DPDK and MUSDK,
  40  * we'll declare only one version.
  41  *
  42  * Note that it is not used in this PMD anyway.
  43  */
  44 #ifdef container_of
  45 #undef container_of
  46 #endif
  47
  48 #include <drivers/mv_pp2.h>
  49 #include <drivers/mv_pp2_bpool.h>
  50 #include <drivers/mv_pp2_hif.h>
  51
  52 #include <fcntl.h>
  53 #include <linux/ethtool.h>
  54 #include <linux/sockios.h>
  55 #include <net/if.h>
  56 #include <net/if_arp.h>
  57 #include <sys/ioctl.h>
  58 #include <sys/socket.h>
  59 #include <sys/stat.h>
  60 #include <sys/types.h>
  61
  62 #include "mrvl_ethdev.h"
  63 #include "mrvl_qos.h"
  64
  65 /* bitmask with reserved hifs */
  66 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
  67 /* bitmask with reserved bpools */
  68 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
  69 /* bitmask with reserved kernel RSS tables */
  70 #define MRVL_MUSDK_RSS_RESERVED 0x01
  71 /* maximum number of available hifs */
  72 #define MRVL_MUSDK_HIFS_MAX 9
  73
  74 /* prefetch shift */
  75 #define MRVL_MUSDK_PREFETCH_SHIFT 2
  76
  77 /* TCAM has 25 entries reserved for uc/mc filter entries */
  78 #define MRVL_MAC_ADDRS_MAX 25
  79 #define MRVL_MATCH_LEN 16
  80 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
  81 /* Maximum allowable packet size */
  82 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
  83
  84 #define MRVL_IFACE_NAME_ARG "iface"
  85 #define MRVL_CFG_ARG "cfg"
  86
  87 #define MRVL_BURST_SIZE 64
  88
  89 #define MRVL_ARP_LENGTH 28
  90
  91 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
  92
  93 #define MRVL_COOKIE_HIGH_ADDR_SHIFT     (sizeof(pp2_cookie_t) * 8)
  94 #define MRVL_COOKIE_HIGH_ADDR_MASK      (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
  95
  96 static const char * const valid_args[] = {
  97         MRVL_IFACE_NAME_ARG,
  98         MRVL_CFG_ARG,
  99         NULL
 100 };
 101
 102 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
 103 static struct pp2_hif *hifs[RTE_MAX_LCORE];
 104 static int used_bpools[PP2_NUM_PKT_PROC] = {
 105         MRVL_MUSDK_BPOOLS_RESERVED,
 106         MRVL_MUSDK_BPOOLS_RESERVED
 107 };
 108
 109 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
 110 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
 111 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
 112
 113 /*
 114  * To use buffer harvesting based on loopback port shadow queue structure
 115  * was introduced for buffers information bookkeeping.
 116  *
 117  * Before sending the packet, related buffer information (pp2_buff_inf) is
 118  * stored in shadow queue. After packet is transmitted no longer used
 119  * packet buffer is released back to it's original hardware pool,
 120  * on condition it originated from interface.
 121  * In case it  was generated by application itself i.e: mbuf->port field is
 122  * 0xff then its released to software mempool.
 123  */
 124 struct mrvl_shadow_txq {
 125         int head;           /* write index - used when sending buffers */
 126         int tail;           /* read index - used when releasing buffers */
 127         u16 size;           /* queue occupied size */
 128         u16 num_to_release; /* number of buffers sent, that can be released */
 129         struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
 130 };
 131
 132 struct mrvl_rxq {
 133         struct mrvl_priv *priv;
 134         struct rte_mempool *mp;
 135         int queue_id;
 136         int port_id;
 137         int cksum_enabled;
 138 };
 139
 140 struct mrvl_txq {
 141         struct mrvl_priv *priv;
 142         int queue_id;
 143         int port_id;
 144 };
 145
 146 /*
 147  * Every tx queue should have dedicated shadow tx queue.
 148  *
 149  * Ports assigned by DPDK might not start at zero or be continuous so
 150  * as a workaround define shadow queues for each possible port so that
 151  * we eventually fit somewhere.
 152  */
 153 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_ETHPORTS][RTE_MAX_LCORE];
 154
 155 /** Number of ports configured. */
 156 int mrvl_ports_nb;
 157 static int mrvl_lcore_first;
 158 static int mrvl_lcore_last;
 159
 160 static inline int
 161 mrvl_get_bpool_size(int pp2_id, int pool_id)
 162 {
 163         int i;
 164         int size = 0;
 165
 166         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
 167                 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
 168
 169         return size;
 170 }
 171
 172 static inline int
 173 mrvl_reserve_bit(int *bitmap, int max)
 174 {
 175         int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
 176
 177         if (n >= max)
 178                 return -1;
 179
 180         *bitmap |= 1 << n;
 181
 182         return n;
 183 }
 184
 185 /**
 186  * Configure rss based on dpdk rss configuration.
 187  *
 188  * @param priv
 189  *   Pointer to private structure.
 190  * @param rss_conf
 191  *   Pointer to RSS configuration.
 192  *
 193  * @return
 194  *   0 on success, negative error value otherwise.
 195  */
 196 static int
 197 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
 198 {
 199         if (rss_conf->rss_key)
 200                 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
 201
 202         if (rss_conf->rss_hf == 0) {
 203                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 204         } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
 205                 priv->ppio_params.inqs_params.hash_type =
 206                         PP2_PPIO_HASH_T_2_TUPLE;
 207         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
 208                 priv->ppio_params.inqs_params.hash_type =
 209                         PP2_PPIO_HASH_T_5_TUPLE;
 210                 priv->rss_hf_tcp = 1;
 211         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
 212                 priv->ppio_params.inqs_params.hash_type =
 213                         PP2_PPIO_HASH_T_5_TUPLE;
 214                 priv->rss_hf_tcp = 0;
 215         } else {
 216                 return -EINVAL;
 217         }
 218
 219         return 0;
 220 }
 221
 222 /**
 223  * Ethernet device configuration.
 224  *
 225  * Prepare the driver for a given number of TX and RX queues and
 226  * configure RSS.
 227  *
 228  * @param dev
 229  *   Pointer to Ethernet device structure.
 230  *
 231  * @return
 232  *   0 on success, negative error value otherwise.
 233  */
 234 static int
 235 mrvl_dev_configure(struct rte_eth_dev *dev)
 236 {
 237         struct mrvl_priv *priv = dev->data->dev_private;
 238         int ret;
 239
 240         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
 241             dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
 242                 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
 243                         dev->data->dev_conf.rxmode.mq_mode);
 244                 return -EINVAL;
 245         }
 246
 247         if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
 248                 RTE_LOG(INFO, PMD,
 249                         "L2 CRC stripping is always enabled in hw\n");
 250                 dev->data->dev_conf.rxmode.hw_strip_crc = 1;
 251         }
 252
 253         if (dev->data->dev_conf.rxmode.hw_vlan_strip) {
 254                 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
 255                 return -EINVAL;
 256         }
 257
 258         if (dev->data->dev_conf.rxmode.split_hdr_size) {
 259                 RTE_LOG(INFO, PMD, "Split headers not supported\n");
 260                 return -EINVAL;
 261         }
 262
 263         if (dev->data->dev_conf.rxmode.enable_scatter) {
 264                 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
 265                 return -EINVAL;
 266         }
 267
 268         if (dev->data->dev_conf.rxmode.enable_lro) {
 269                 RTE_LOG(INFO, PMD, "LRO not supported\n");
 270                 return -EINVAL;
 271         }
 272
 273         if (dev->data->dev_conf.rxmode.jumbo_frame)
 274                 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
 275                                  ETHER_HDR_LEN - ETHER_CRC_LEN;
 276
 277         ret = mrvl_configure_rxqs(priv, dev->data->port_id,
 278                                   dev->data->nb_rx_queues);
 279         if (ret < 0)
 280                 return ret;
 281
 282         priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
 283         priv->nb_rx_queues = dev->data->nb_rx_queues;
 284
 285         if (dev->data->nb_rx_queues == 1 &&
 286             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 287                 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
 288                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 289
 290                 return 0;
 291         }
 292
 293         return mrvl_configure_rss(priv,
 294                                   &dev->data->dev_conf.rx_adv_conf.rss_conf);
 295 }
 296
 297 /**
 298  * DPDK callback to change the MTU.
 299  *
 300  * Setting the MTU affects hardware MRU (packets larger than the MRU
 301  * will be dropped).
 302  *
 303  * @param dev
 304  *   Pointer to Ethernet device structure.
 305  * @param mtu
 306  *   New MTU.
 307  *
 308  * @return
 309  *   0 on success, negative error value otherwise.
 310  */
 311 static int
 312 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 313 {
 314         struct mrvl_priv *priv = dev->data->dev_private;
 315         /* extra MV_MH_SIZE bytes are required for Marvell tag */
 316         uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
 317         int ret;
 318
 319         if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
 320                 return -EINVAL;
 321
 322         ret = pp2_ppio_set_mru(priv->ppio, mru);
 323         if (ret)
 324                 return ret;
 325
 326         return pp2_ppio_set_mtu(priv->ppio, mtu);
 327 }
 328
 329 /**
 330  * DPDK callback to bring the link up.
 331  *
 332  * @param dev
 333  *   Pointer to Ethernet device structure.
 334  *
 335  * @return
 336  *   0 on success, negative error value otherwise.
 337  */
 338 static int
 339 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
 340 {
 341         struct mrvl_priv *priv = dev->data->dev_private;
 342         int ret;
 343
 344         ret = pp2_ppio_enable(priv->ppio);
 345         if (ret)
 346                 return ret;
 347
 348         /*
 349          * mtu/mru can be updated if pp2_ppio_enable() was called at least once
 350          * as pp2_ppio_enable() changes port->t_mode from default 0 to
 351          * PP2_TRAFFIC_INGRESS_EGRESS.
 352          *
 353          * Set mtu to default DPDK value here.
 354          */
 355         ret = mrvl_mtu_set(dev, dev->data->mtu);
 356         if (ret)
 357                 pp2_ppio_disable(priv->ppio);
 358
 359         dev->data->dev_link.link_status = ETH_LINK_UP;
 360
 361         return ret;
 362 }
 363
 364 /**
 365  * DPDK callback to bring the link down.
 366  *
 367  * @param dev
 368  *   Pointer to Ethernet device structure.
 369  *
 370  * @return
 371  *   0 on success, negative error value otherwise.
 372  */
 373 static int
 374 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
 375 {
 376         struct mrvl_priv *priv = dev->data->dev_private;
 377         int ret;
 378
 379         ret = pp2_ppio_disable(priv->ppio);
 380         if (ret)
 381                 return ret;
 382
 383         dev->data->dev_link.link_status = ETH_LINK_DOWN;
 384
 385         return ret;
 386 }
 387
 388 /**
 389  * DPDK callback to start the device.
 390  *
 391  * @param dev
 392  *   Pointer to Ethernet device structure.
 393  *
 394  * @return
 395  *   0 on success, negative errno value on failure.
 396  */
 397 static int
 398 mrvl_dev_start(struct rte_eth_dev *dev)
 399 {
 400         struct mrvl_priv *priv = dev->data->dev_private;
 401         char match[MRVL_MATCH_LEN];
 402         int ret;
 403
 404         snprintf(match, sizeof(match), "ppio-%d:%d",
 405                  priv->pp_id, priv->ppio_id);
 406         priv->ppio_params.match = match;
 407
 408         /*
 409          * Calculate the maximum bpool size for refill feature to 1.5 of the
 410          * configured size. In case the bpool size will exceed this value,
 411          * superfluous buffers will be removed
 412          */
 413         priv->bpool_max_size = priv->bpool_init_size +
 414                               (priv->bpool_init_size >> 1);
 415         /*
 416          * Calculate the minimum bpool size for refill feature as follows:
 417          * 2 default burst sizes multiply by number of rx queues.
 418          * If the bpool size will be below this value, new buffers will
 419          * be added to the pool.
 420          */
 421         priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
 422
 423         ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
 424         if (ret)
 425                 return ret;
 426
 427         /*
 428          * In case there are some some stale uc/mc mac addresses flush them
 429          * here. It cannot be done during mrvl_dev_close() as port information
 430          * is already gone at that point (due to pp2_ppio_deinit() in
 431          * mrvl_dev_stop()).
 432          */
 433         if (!priv->uc_mc_flushed) {
 434                 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
 435                 if (ret) {
 436                         RTE_LOG(ERR, PMD,
 437                                 "Failed to flush uc/mc filter list\n");
 438                         goto out;
 439                 }
 440                 priv->uc_mc_flushed = 1;
 441         }
 442
 443         if (!priv->vlan_flushed) {
 444                 ret = pp2_ppio_flush_vlan(priv->ppio);
 445                 if (ret) {
 446                         RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
 447                         /*
 448                          * TODO
 449                          * once pp2_ppio_flush_vlan() is supported jump to out
 450                          * goto out;
 451                          */
 452                 }
 453                 priv->vlan_flushed = 1;
 454         }
 455
 456         /* For default QoS config, don't start classifier. */
 457         if (mrvl_qos_cfg) {
 458                 ret = mrvl_start_qos_mapping(priv);
 459                 if (ret) {
 460                         pp2_ppio_deinit(priv->ppio);
 461                         return ret;
 462                 }
 463         }
 464
 465         ret = mrvl_dev_set_link_up(dev);
 466         if (ret)
 467                 goto out;
 468
 469         return 0;
 470 out:
 471         pp2_ppio_deinit(priv->ppio);
 472         return ret;
 473 }
 474
 475 /**
 476  * Flush receive queues.
 477  *
 478  * @param dev
 479  *   Pointer to Ethernet device structure.
 480  */
 481 static void
 482 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
 483 {
 484         int i;
 485
 486         RTE_LOG(INFO, PMD, "Flushing rx queues\n");
 487         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 488                 int ret, num;
 489
 490                 do {
 491                         struct mrvl_rxq *q = dev->data->rx_queues[i];
 492                         struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
 493
 494                         num = MRVL_PP2_RXD_MAX;
 495                         ret = pp2_ppio_recv(q->priv->ppio,
 496                                             q->priv->rxq_map[q->queue_id].tc,
 497                                             q->priv->rxq_map[q->queue_id].inq,
 498                                             descs, (uint16_t *)&num);
 499                 } while (ret == 0 && num);
 500         }
 501 }
 502
 503 /**
 504  * Flush transmit shadow queues.
 505  *
 506  * @param dev
 507  *   Pointer to Ethernet device structure.
 508  */
 509 static void
 510 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
 511 {
 512         int i;
 513
 514         RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
 515         for (i = 0; i < RTE_MAX_LCORE; i++) {
 516                 struct mrvl_shadow_txq *sq =
 517                         &shadow_txqs[dev->data->port_id][i];
 518
 519                 while (sq->tail != sq->head) {
 520                         uint64_t addr = cookie_addr_high |
 521                                         sq->ent[sq->tail].buff.cookie;
 522                         rte_pktmbuf_free((struct rte_mbuf *)addr);
 523                         sq->tail = (sq->tail + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
 524                 }
 525
 526                 memset(sq, 0, sizeof(*sq));
 527         }
 528 }
 529
 530 /**
 531  * Flush hardware bpool (buffer-pool).
 532  *
 533  * @param dev
 534  *   Pointer to Ethernet device structure.
 535  */
 536 static void
 537 mrvl_flush_bpool(struct rte_eth_dev *dev)
 538 {
 539         struct mrvl_priv *priv = dev->data->dev_private;
 540         uint32_t num;
 541         int ret;
 542
 543         ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
 544         if (ret) {
 545                 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
 546                 return;
 547         }
 548
 549         while (num--) {
 550                 struct pp2_buff_inf inf;
 551                 uint64_t addr;
 552
 553                 ret = pp2_bpool_get_buff(hifs[rte_lcore_id()], priv->bpool,
 554                                          &inf);
 555                 if (ret)
 556                         break;
 557
 558                 addr = cookie_addr_high | inf.cookie;
 559                 rte_pktmbuf_free((struct rte_mbuf *)addr);
 560         }
 561 }
 562
 563 /**
 564  * DPDK callback to stop the device.
 565  *
 566  * @param dev
 567  *   Pointer to Ethernet device structure.
 568  */
 569 static void
 570 mrvl_dev_stop(struct rte_eth_dev *dev)
 571 {
 572         struct mrvl_priv *priv = dev->data->dev_private;
 573
 574         mrvl_dev_set_link_down(dev);
 575         mrvl_flush_rx_queues(dev);
 576         mrvl_flush_tx_shadow_queues(dev);
 577         if (priv->qos_tbl)
 578                 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
 579         pp2_ppio_deinit(priv->ppio);
 580         priv->ppio = NULL;
 581 }
 582
 583 /**
 584  * DPDK callback to close the device.
 585  *
 586  * @param dev
 587  *   Pointer to Ethernet device structure.
 588  */
 589 static void
 590 mrvl_dev_close(struct rte_eth_dev *dev)
 591 {
 592         struct mrvl_priv *priv = dev->data->dev_private;
 593         size_t i;
 594
 595         for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
 596                 struct pp2_ppio_tc_params *tc_params =
 597                         &priv->ppio_params.inqs_params.tcs_params[i];
 598
 599                 if (tc_params->inqs_params) {
 600                         rte_free(tc_params->inqs_params);
 601                         tc_params->inqs_params = NULL;
 602                 }
 603         }
 604
 605         mrvl_flush_bpool(dev);
 606 }
 607
 608 /**
 609  * DPDK callback to retrieve physical link information.
 610  *
 611  * @param dev
 612  *   Pointer to Ethernet device structure.
 613  * @param wait_to_complete
 614  *   Wait for request completion (ignored).
 615  *
 616  * @return
 617  *   0 on success, negative error value otherwise.
 618  */
 619 static int
 620 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
 621 {
 622         /*
 623          * TODO
 624          * once MUSDK provides necessary API use it here
 625          */
 626         struct ethtool_cmd edata;
 627         struct ifreq req;
 628         int ret, fd;
 629
 630         edata.cmd = ETHTOOL_GSET;
 631
 632         strcpy(req.ifr_name, dev->data->name);
 633         req.ifr_data = (void *)&edata;
 634
 635         fd = socket(AF_INET, SOCK_DGRAM, 0);
 636         if (fd == -1)
 637                 return -EFAULT;
 638
 639         ret = ioctl(fd, SIOCETHTOOL, &req);
 640         if (ret == -1) {
 641                 close(fd);
 642                 return -EFAULT;
 643         }
 644
 645         close(fd);
 646
 647         switch (ethtool_cmd_speed(&edata)) {
 648         case SPEED_10:
 649                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
 650                 break;
 651         case SPEED_100:
 652                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
 653                 break;
 654         case SPEED_1000:
 655                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
 656                 break;
 657         case SPEED_10000:
 658                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
 659                 break;
 660         default:
 661                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
 662         }
 663
 664         dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
 665                                                          ETH_LINK_HALF_DUPLEX;
 666         dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
 667                                                            ETH_LINK_FIXED;
 668
 669         return 0;
 670 }
 671
 672 /**
 673  * DPDK callback to enable promiscuous mode.
 674  *
 675  * @param dev
 676  *   Pointer to Ethernet device structure.
 677  */
 678 static void
 679 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
 680 {
 681         struct mrvl_priv *priv = dev->data->dev_private;
 682         int ret;
 683
 684         ret = pp2_ppio_set_uc_promisc(priv->ppio, 1);
 685         if (ret)
 686                 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
 687 }
 688
 689 /**
 690  * DPDK callback to enable allmulti mode.
 691  *
 692  * @param dev
 693  *   Pointer to Ethernet device structure.
 694  */
 695 static void
 696 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
 697 {
 698         struct mrvl_priv *priv = dev->data->dev_private;
 699         int ret;
 700
 701         ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
 702         if (ret)
 703                 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
 704 }
 705
 706 /**
 707  * DPDK callback to disable promiscuous mode.
 708  *
 709  * @param dev
 710  *   Pointer to Ethernet device structure.
 711  */
 712 static void
 713 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
 714 {
 715         struct mrvl_priv *priv = dev->data->dev_private;
 716         int ret;
 717
 718         ret = pp2_ppio_set_uc_promisc(priv->ppio, 0);
 719         if (ret)
 720                 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
 721 }
 722
 723 /**
 724  * DPDK callback to disable allmulticast mode.
 725  *
 726  * @param dev
 727  *   Pointer to Ethernet device structure.
 728  */
 729 static void
 730 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
 731 {
 732         struct mrvl_priv *priv = dev->data->dev_private;
 733         int ret;
 734
 735         ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
 736         if (ret)
 737                 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
 738 }
 739
 740 /**
 741  * DPDK callback to remove a MAC address.
 742  *
 743  * @param dev
 744  *   Pointer to Ethernet device structure.
 745  * @param index
 746  *   MAC address index.
 747  */
 748 static void
 749 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 750 {
 751         struct mrvl_priv *priv = dev->data->dev_private;
 752         char buf[ETHER_ADDR_FMT_SIZE];
 753         int ret;
 754
 755         ret = pp2_ppio_remove_mac_addr(priv->ppio,
 756                                        dev->data->mac_addrs[index].addr_bytes);
 757         if (ret) {
 758                 ether_format_addr(buf, sizeof(buf),
 759                                   &dev->data->mac_addrs[index]);
 760                 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
 761         }
 762 }
 763
 764 /**
 765  * DPDK callback to add a MAC address.
 766  *
 767  * @param dev
 768  *   Pointer to Ethernet device structure.
 769  * @param mac_addr
 770  *   MAC address to register.
 771  * @param index
 772  *   MAC address index.
 773  * @param vmdq
 774  *   VMDq pool index to associate address with (unused).
 775  *
 776  * @return
 777  *   0 on success, negative error value otherwise.
 778  */
 779 static int
 780 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 781                   uint32_t index, uint32_t vmdq __rte_unused)
 782 {
 783         struct mrvl_priv *priv = dev->data->dev_private;
 784         char buf[ETHER_ADDR_FMT_SIZE];
 785         int ret;
 786
 787         if (index == 0)
 788                 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
 789                 return -1;
 790
 791         /*
 792          * Maximum number of uc addresses can be tuned via kernel module mvpp2x
 793          * parameter uc_filter_max. Maximum number of mc addresses is then
 794          * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
 795          * 21 respectively.
 796          *
 797          * If more than uc_filter_max uc addresses were added to filter list
 798          * then NIC will switch to promiscuous mode automatically.
 799          *
 800          * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
 801          * were added to filter list then NIC will switch to all-multicast mode
 802          * automatically.
 803          */
 804         ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
 805         if (ret) {
 806                 ether_format_addr(buf, sizeof(buf), mac_addr);
 807                 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
 808                 return -1;
 809         }
 810
 811         return 0;
 812 }
 813
 814 /**
 815  * DPDK callback to set the primary MAC address.
 816  *
 817  * @param dev
 818  *   Pointer to Ethernet device structure.
 819  * @param mac_addr
 820  *   MAC address to register.
 821  */
 822 static void
 823 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 824 {
 825         struct mrvl_priv *priv = dev->data->dev_private;
 826
 827         pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
 828         /*
 829          * TODO
 830          * Port stops sending packets if pp2_ppio_set_mac_addr()
 831          * was called after pp2_ppio_enable(). As a quick fix issue
 832          * enable port once again.
 833          */
 834         pp2_ppio_enable(priv->ppio);
 835 }
 836
 837 /**
 838  * DPDK callback to get information about the device.
 839  *
 840  * @param dev
 841  *   Pointer to Ethernet device structure (unused).
 842  * @param info
 843  *   Info structure output buffer.
 844  */
 845 static void
 846 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
 847                    struct rte_eth_dev_info *info)
 848 {
 849         info->speed_capa = ETH_LINK_SPEED_10M |
 850                            ETH_LINK_SPEED_100M |
 851                            ETH_LINK_SPEED_1G |
 852                            ETH_LINK_SPEED_10G;
 853
 854         info->max_rx_queues = MRVL_PP2_RXQ_MAX;
 855         info->max_tx_queues = MRVL_PP2_TXQ_MAX;
 856         info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
 857
 858         info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
 859         info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
 860         info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
 861
 862         info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
 863         info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
 864         info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
 865
 866         info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME |
 867                                 DEV_RX_OFFLOAD_VLAN_FILTER |
 868                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 869                                 DEV_RX_OFFLOAD_UDP_CKSUM |
 870                                 DEV_RX_OFFLOAD_TCP_CKSUM;
 871
 872         info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
 873                                 DEV_TX_OFFLOAD_UDP_CKSUM |
 874                                 DEV_TX_OFFLOAD_TCP_CKSUM;
 875
 876         info->flow_type_rss_offloads = ETH_RSS_IPV4 |
 877                                        ETH_RSS_NONFRAG_IPV4_TCP |
 878                                        ETH_RSS_NONFRAG_IPV4_UDP;
 879
 880         /* By default packets are dropped if no descriptors are available */
 881         info->default_rxconf.rx_drop_en = 1;
 882
 883         info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
 884 }
 885
 886 /**
 887  * Return supported packet types.
 888  *
 889  * @param dev
 890  *   Pointer to Ethernet device structure (unused).
 891  *
 892  * @return
 893  *   Const pointer to the table with supported packet types.
 894  */
 895 static const uint32_t *
 896 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
 897 {
 898         static const uint32_t ptypes[] = {
 899                 RTE_PTYPE_L2_ETHER,
 900                 RTE_PTYPE_L3_IPV4,
 901                 RTE_PTYPE_L3_IPV4_EXT,
 902                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 903                 RTE_PTYPE_L3_IPV6,
 904                 RTE_PTYPE_L3_IPV6_EXT,
 905                 RTE_PTYPE_L2_ETHER_ARP,
 906                 RTE_PTYPE_L4_TCP,
 907                 RTE_PTYPE_L4_UDP
 908         };
 909
 910         return ptypes;
 911 }
 912
 913 /**
 914  * DPDK callback to get information about specific receive queue.
 915  *
 916  * @param dev
 917  *   Pointer to Ethernet device structure.
 918  * @param rx_queue_id
 919  *   Receive queue index.
 920  * @param qinfo
 921  *   Receive queue information structure.
 922  */
 923 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
 924                               struct rte_eth_rxq_info *qinfo)
 925 {
 926         struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
 927         struct mrvl_priv *priv = dev->data->dev_private;
 928         int inq = priv->rxq_map[rx_queue_id].inq;
 929         int tc = priv->rxq_map[rx_queue_id].tc;
 930         struct pp2_ppio_tc_params *tc_params =
 931                 &priv->ppio_params.inqs_params.tcs_params[tc];
 932
 933         qinfo->mp = q->mp;
 934         qinfo->nb_desc = tc_params->inqs_params[inq].size;
 935 }
 936
 937 /**
 938  * DPDK callback to get information about specific transmit queue.
 939  *
 940  * @param dev
 941  *   Pointer to Ethernet device structure.
 942  * @param tx_queue_id
 943  *   Transmit queue index.
 944  * @param qinfo
 945  *   Transmit queue information structure.
 946  */
 947 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
 948                               struct rte_eth_txq_info *qinfo)
 949 {
 950         struct mrvl_priv *priv = dev->data->dev_private;
 951
 952         qinfo->nb_desc =
 953                 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
 954 }
 955
 956 /**
 957  * DPDK callback to Configure a VLAN filter.
 958  *
 959  * @param dev
 960  *   Pointer to Ethernet device structure.
 961  * @param vlan_id
 962  *   VLAN ID to filter.
 963  * @param on
 964  *   Toggle filter.
 965  *
 966  * @return
 967  *   0 on success, negative error value otherwise.
 968  */
 969 static int
 970 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 971 {
 972         struct mrvl_priv *priv = dev->data->dev_private;
 973
 974         return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
 975                     pp2_ppio_remove_vlan(priv->ppio, vlan_id);
 976 }
 977
 978 /**
 979  * Release buffers to hardware bpool (buffer-pool)
 980  *
 981  * @param rxq
 982  *   Receive queue pointer.
 983  * @param num
 984  *   Number of buffers to release to bpool.
 985  *
 986  * @return
 987  *   0 on success, negative error value otherwise.
 988  */
 989 static int
 990 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
 991 {
 992         struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
 993         struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
 994         int i, ret;
 995         unsigned int core_id = rte_lcore_id();
 996         struct pp2_hif *hif = hifs[core_id];
 997         struct pp2_bpool *bpool = rxq->priv->bpool;
 998
 999         ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1000         if (ret)
1001                 return ret;
1002
1003         if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1004                 cookie_addr_high =
1005                         (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1006
1007         for (i = 0; i < num; i++) {
1008                 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1009                         != cookie_addr_high) {
1010                         RTE_LOG(ERR, PMD,
1011                                 "mbuf virtual addr high 0x%lx out of range\n",
1012                                 (uint64_t)mbufs[i] >> 32);
1013                         goto out;
1014                 }
1015
1016                 entries[i].buff.addr =
1017                         rte_mbuf_data_dma_addr_default(mbufs[i]);
1018                 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1019                 entries[i].bpool = bpool;
1020         }
1021
1022         pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1023         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1024
1025         if (i != num)
1026                 goto out;
1027
1028         return 0;
1029 out:
1030         for (; i < num; i++)
1031                 rte_pktmbuf_free(mbufs[i]);
1032
1033         return -1;
1034 }
1035
1036 /**
1037  * DPDK callback to configure the receive queue.
1038  *
1039  * @param dev
1040  *   Pointer to Ethernet device structure.
1041  * @param idx
1042  *   RX queue index.
1043  * @param desc
1044  *   Number of descriptors to configure in queue.
1045  * @param socket
1046  *   NUMA socket on which memory must be allocated.
1047  * @param conf
1048  *   Thresholds parameters (unused_).
1049  * @param mp
1050  *   Memory pool for buffer allocations.
1051  *
1052  * @return
1053  *   0 on success, negative error value otherwise.
1054  */
1055 static int
1056 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1057                     unsigned int socket,
1058                     const struct rte_eth_rxconf *conf __rte_unused,
1059                     struct rte_mempool *mp)
1060 {
1061         struct mrvl_priv *priv = dev->data->dev_private;
1062         struct mrvl_rxq *rxq;
1063         uint32_t min_size,
1064                  max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1065         int ret, tc, inq;
1066
1067         if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1068                 /*
1069                  * Unknown TC mapping, mapping will not have a correct queue.
1070                  */
1071                 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1072                         idx, priv->ppio_id);
1073                 return -EFAULT;
1074         }
1075
1076         min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1077                    MRVL_PKT_EFFEC_OFFS;
1078         if (min_size < max_rx_pkt_len) {
1079                 RTE_LOG(ERR, PMD,
1080                         "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1081                         max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1082                         MRVL_PKT_EFFEC_OFFS,
1083                         max_rx_pkt_len);
1084                 return -EINVAL;
1085         }
1086
1087         if (dev->data->rx_queues[idx]) {
1088                 rte_free(dev->data->rx_queues[idx]);
1089                 dev->data->rx_queues[idx] = NULL;
1090         }
1091
1092         rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1093         if (!rxq)
1094                 return -ENOMEM;
1095
1096         rxq->priv = priv;
1097         rxq->mp = mp;
1098         rxq->cksum_enabled = dev->data->dev_conf.rxmode.hw_ip_checksum;
1099         rxq->queue_id = idx;
1100         rxq->port_id = dev->data->port_id;
1101         mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1102
1103         tc = priv->rxq_map[rxq->queue_id].tc,
1104         inq = priv->rxq_map[rxq->queue_id].inq;
1105         priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1106                 desc;
1107
1108         ret = mrvl_fill_bpool(rxq, desc);
1109         if (ret) {
1110                 rte_free(rxq);
1111                 return ret;
1112         }
1113
1114         priv->bpool_init_size += desc;
1115
1116         dev->data->rx_queues[idx] = rxq;
1117
1118         return 0;
1119 }
1120
1121 /**
1122  * DPDK callback to release the receive queue.
1123  *
1124  * @param rxq
1125  *   Generic receive queue pointer.
1126  */
1127 static void
1128 mrvl_rx_queue_release(void *rxq)
1129 {
1130         struct mrvl_rxq *q = rxq;
1131         struct pp2_ppio_tc_params *tc_params;
1132         int i, num, tc, inq;
1133
1134         if (!q)
1135                 return;
1136
1137         tc = q->priv->rxq_map[q->queue_id].tc;
1138         inq = q->priv->rxq_map[q->queue_id].inq;
1139         tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1140         num = tc_params->inqs_params[inq].size;
1141         for (i = 0; i < num; i++) {
1142                 struct pp2_buff_inf inf;
1143                 uint64_t addr;
1144
1145                 pp2_bpool_get_buff(hifs[rte_lcore_id()], q->priv->bpool, &inf);
1146                 addr = cookie_addr_high | inf.cookie;
1147                 rte_pktmbuf_free((struct rte_mbuf *)addr);
1148         }
1149
1150         rte_free(q);
1151 }
1152
1153 /**
1154  * DPDK callback to configure the transmit queue.
1155  *
1156  * @param dev
1157  *   Pointer to Ethernet device structure.
1158  * @param idx
1159  *   Transmit queue index.
1160  * @param desc
1161  *   Number of descriptors to configure in the queue.
1162  * @param socket
1163  *   NUMA socket on which memory must be allocated.
1164  * @param conf
1165  *   Thresholds parameters (unused).
1166  *
1167  * @return
1168  *   0 on success, negative error value otherwise.
1169  */
1170 static int
1171 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1172                     unsigned int socket,
1173                     const struct rte_eth_txconf *conf __rte_unused)
1174 {
1175         struct mrvl_priv *priv = dev->data->dev_private;
1176         struct mrvl_txq *txq;
1177
1178         if (dev->data->tx_queues[idx]) {
1179                 rte_free(dev->data->tx_queues[idx]);
1180                 dev->data->tx_queues[idx] = NULL;
1181         }
1182
1183         txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1184         if (!txq)
1185                 return -ENOMEM;
1186
1187         txq->priv = priv;
1188         txq->queue_id = idx;
1189         txq->port_id = dev->data->port_id;
1190         dev->data->tx_queues[idx] = txq;
1191
1192         priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1193         priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1194
1195         return 0;
1196 }
1197
1198 /**
1199  * DPDK callback to release the transmit queue.
1200  *
1201  * @param txq
1202  *   Generic transmit queue pointer.
1203  */
1204 static void
1205 mrvl_tx_queue_release(void *txq)
1206 {
1207         struct mrvl_txq *q = txq;
1208
1209         if (!q)
1210                 return;
1211
1212         rte_free(q);
1213 }
1214
1215 /**
1216  * Update RSS hash configuration
1217  *
1218  * @param dev
1219  *   Pointer to Ethernet device structure.
1220  * @param rss_conf
1221  *   Pointer to RSS configuration.
1222  *
1223  * @return
1224  *   0 on success, negative error value otherwise.
1225  */
1226 static int
1227 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1228                      struct rte_eth_rss_conf *rss_conf)
1229 {
1230         struct mrvl_priv *priv = dev->data->dev_private;
1231
1232         return mrvl_configure_rss(priv, rss_conf);
1233 }
1234
1235 /**
1236  * DPDK callback to get RSS hash configuration.
1237  *
1238  * @param dev
1239  *   Pointer to Ethernet device structure.
1240  * @rss_conf
1241  *   Pointer to RSS configuration.
1242  *
1243  * @return
1244  *   Always 0.
1245  */
1246 static int
1247 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1248                        struct rte_eth_rss_conf *rss_conf)
1249 {
1250         struct mrvl_priv *priv = dev->data->dev_private;
1251         enum pp2_ppio_hash_type hash_type =
1252                 priv->ppio_params.inqs_params.hash_type;
1253
1254         rss_conf->rss_key = NULL;
1255
1256         if (hash_type == PP2_PPIO_HASH_T_NONE)
1257                 rss_conf->rss_hf = 0;
1258         else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1259                 rss_conf->rss_hf = ETH_RSS_IPV4;
1260         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1261                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1262         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1263                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1264
1265         return 0;
1266 }
1267
1268 static const struct eth_dev_ops mrvl_ops = {
1269         .dev_configure = mrvl_dev_configure,
1270         .dev_start = mrvl_dev_start,
1271         .dev_stop = mrvl_dev_stop,
1272         .dev_set_link_up = mrvl_dev_set_link_up,
1273         .dev_set_link_down = mrvl_dev_set_link_down,
1274         .dev_close = mrvl_dev_close,
1275         .link_update = mrvl_link_update,
1276         .promiscuous_enable = mrvl_promiscuous_enable,
1277         .allmulticast_enable = mrvl_allmulticast_enable,
1278         .promiscuous_disable = mrvl_promiscuous_disable,
1279         .allmulticast_disable = mrvl_allmulticast_disable,
1280         .mac_addr_remove = mrvl_mac_addr_remove,
1281         .mac_addr_add = mrvl_mac_addr_add,
1282         .mac_addr_set = mrvl_mac_addr_set,
1283         .mtu_set = mrvl_mtu_set,
1284         .dev_infos_get = mrvl_dev_infos_get,
1285         .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1286         .rxq_info_get = mrvl_rxq_info_get,
1287         .txq_info_get = mrvl_txq_info_get,
1288         .vlan_filter_set = mrvl_vlan_filter_set,
1289         .rx_queue_setup = mrvl_rx_queue_setup,
1290         .rx_queue_release = mrvl_rx_queue_release,
1291         .tx_queue_setup = mrvl_tx_queue_setup,
1292         .tx_queue_release = mrvl_tx_queue_release,
1293         .rss_hash_update = mrvl_rss_hash_update,
1294         .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1295 };
1296
1297 /**
1298  * Return packet type information and l3/l4 offsets.
1299  *
1300  * @param desc
1301  *   Pointer to the received packet descriptor.
1302  * @param l3_offset
1303  *   l3 packet offset.
1304  * @param l4_offset
1305  *   l4 packet offset.
1306  *
1307  * @return
1308  *   Packet type information.
1309  */
1310 static inline uint64_t
1311 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1312                                     uint8_t *l3_offset, uint8_t *l4_offset)
1313 {
1314         enum pp2_inq_l3_type l3_type;
1315         enum pp2_inq_l4_type l4_type;
1316         uint64_t packet_type;
1317
1318         pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1319         pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1320
1321         packet_type = RTE_PTYPE_L2_ETHER;
1322
1323         switch (l3_type) {
1324         case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1325                 packet_type |= RTE_PTYPE_L3_IPV4;
1326                 break;
1327         case PP2_INQ_L3_TYPE_IPV4_OK:
1328                 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1329                 break;
1330         case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1331                 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1332                 break;
1333         case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1334                 packet_type |= RTE_PTYPE_L3_IPV6;
1335                 break;
1336         case PP2_INQ_L3_TYPE_IPV6_EXT:
1337                 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1338                 break;
1339         case PP2_INQ_L3_TYPE_ARP:
1340                 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1341                 /*
1342                  * In case of ARP l4_offset is set to wrong value.
1343                  * Set it to proper one so that later on mbuf->l3_len can be
1344                  * calculated subtracting l4_offset and l3_offset.
1345                  */
1346                 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1347                 break;
1348         default:
1349                 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1350                 break;
1351         }
1352
1353         switch (l4_type) {
1354         case PP2_INQ_L4_TYPE_TCP:
1355                 packet_type |= RTE_PTYPE_L4_TCP;
1356                 break;
1357         case PP2_INQ_L4_TYPE_UDP:
1358                 packet_type |= RTE_PTYPE_L4_UDP;
1359                 break;
1360         default:
1361                 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1362                 break;
1363         }
1364
1365         return packet_type;
1366 }
1367
1368 /**
1369  * Get offload information from the received packet descriptor.
1370  *
1371  * @param desc
1372  *   Pointer to the received packet descriptor.
1373  *
1374  * @return
1375  *   Mbuf offload flags.
1376  */
1377 static inline uint64_t
1378 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1379 {
1380         uint64_t flags;
1381         enum pp2_inq_desc_status status;
1382
1383         status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1384         if (unlikely(status != PP2_DESC_ERR_OK))
1385                 flags = PKT_RX_IP_CKSUM_BAD;
1386         else
1387                 flags = PKT_RX_IP_CKSUM_GOOD;
1388
1389         status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1390         if (unlikely(status != PP2_DESC_ERR_OK))
1391                 flags |= PKT_RX_L4_CKSUM_BAD;
1392         else
1393                 flags |= PKT_RX_L4_CKSUM_GOOD;
1394
1395         return flags;
1396 }
1397
1398 /**
1399  * DPDK callback for receive.
1400  *
1401  * @param rxq
1402  *   Generic pointer to the receive queue.
1403  * @param rx_pkts
1404  *   Array to store received packets.
1405  * @param nb_pkts
1406  *   Maximum number of packets in array.
1407  *
1408  * @return
1409  *   Number of packets successfully received.
1410  */
1411 static uint16_t
1412 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1413 {
1414         struct mrvl_rxq *q = rxq;
1415         struct pp2_ppio_desc descs[nb_pkts];
1416         struct pp2_bpool *bpool;
1417         int i, ret, rx_done = 0;
1418         int num;
1419         unsigned int core_id = rte_lcore_id();
1420
1421         if (unlikely(!q->priv->ppio))
1422                 return 0;
1423
1424         bpool = q->priv->bpool;
1425
1426         ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1427                             q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1428         if (unlikely(ret < 0)) {
1429                 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1430                 return 0;
1431         }
1432         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1433
1434         for (i = 0; i < nb_pkts; i++) {
1435                 struct rte_mbuf *mbuf;
1436                 uint8_t l3_offset, l4_offset;
1437                 enum pp2_inq_desc_status status;
1438                 uint64_t addr;
1439
1440                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1441                         struct pp2_ppio_desc *pref_desc;
1442                         u64 pref_addr;
1443
1444                         pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1445                         pref_addr = cookie_addr_high |
1446                                     pp2_ppio_inq_desc_get_cookie(pref_desc);
1447                         rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1448                         rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1449                 }
1450
1451                 addr = cookie_addr_high |
1452                        pp2_ppio_inq_desc_get_cookie(&descs[i]);
1453                 mbuf = (struct rte_mbuf *)addr;
1454                 rte_pktmbuf_reset(mbuf);
1455
1456                 /* drop packet in case of mac, overrun or resource error */
1457                 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1458                 if (unlikely(status != PP2_DESC_ERR_OK)) {
1459                         struct pp2_buff_inf binf = {
1460                                 .addr = rte_mbuf_data_dma_addr_default(mbuf),
1461                                 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1462                         };
1463
1464                         pp2_bpool_put_buff(hifs[core_id], bpool, &binf);
1465                         mrvl_port_bpool_size
1466                                 [bpool->pp2_id][bpool->id][core_id]++;
1467                         continue;
1468                 }
1469
1470                 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1471                 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1472                 mbuf->data_len = mbuf->pkt_len;
1473                 mbuf->port = q->port_id;
1474                 mbuf->packet_type =
1475                         mrvl_desc_to_packet_type_and_offset(&descs[i],
1476                                                             &l3_offset,
1477                                                             &l4_offset);
1478                 mbuf->l2_len = l3_offset;
1479                 mbuf->l3_len = l4_offset - l3_offset;
1480
1481                 if (likely(q->cksum_enabled))
1482                         mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
1483
1484                 rx_pkts[rx_done++] = mbuf;
1485         }
1486
1487         if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1488                 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1489
1490                 if (unlikely(num <= q->priv->bpool_min_size ||
1491                              (!rx_done && num < q->priv->bpool_init_size))) {
1492                         ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1493                         if (ret)
1494                                 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1495                 } else if (unlikely(num > q->priv->bpool_max_size)) {
1496                         int i;
1497                         int pkt_to_remove = num - q->priv->bpool_init_size;
1498                         struct rte_mbuf *mbuf;
1499                         struct pp2_buff_inf buff;
1500
1501                         RTE_LOG(DEBUG, PMD,
1502                                 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1503                                 bpool->pp2_id, q->priv->ppio->port_id,
1504                                 bpool->id, pkt_to_remove, num,
1505                                 q->priv->bpool_init_size);
1506
1507                         for (i = 0; i < pkt_to_remove; i++) {
1508                                 pp2_bpool_get_buff(hifs[core_id], bpool, &buff);
1509                                 mbuf = (struct rte_mbuf *)
1510                                         (cookie_addr_high | buff.cookie);
1511                                 rte_pktmbuf_free(mbuf);
1512                         }
1513                         mrvl_port_bpool_size
1514                                 [bpool->pp2_id][bpool->id][core_id] -=
1515                                                                 pkt_to_remove;
1516                 }
1517                 rte_spinlock_unlock(&q->priv->lock);
1518         }
1519
1520         return rx_done;
1521 }
1522
1523 /**
1524  * Prepare offload information.
1525  *
1526  * @param ol_flags
1527  *   Offload flags.
1528  * @param packet_type
1529  *   Packet type bitfield.
1530  * @param l3_type
1531  *   Pointer to the pp2_ouq_l3_type structure.
1532  * @param l4_type
1533  *   Pointer to the pp2_outq_l4_type structure.
1534  * @param gen_l3_cksum
1535  *   Will be set to 1 in case l3 checksum is computed.
1536  * @param l4_cksum
1537  *   Will be set to 1 in case l4 checksum is computed.
1538  *
1539  * @return
1540  *   0 on success, negative error value otherwise.
1541  */
1542 static inline int
1543 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
1544                         enum pp2_outq_l3_type *l3_type,
1545                         enum pp2_outq_l4_type *l4_type,
1546                         int *gen_l3_cksum,
1547                         int *gen_l4_cksum)
1548 {
1549         /*
1550          * Based on ol_flags prepare information
1551          * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
1552          * for offloading.
1553          */
1554         if (ol_flags & PKT_TX_IPV4) {
1555                 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
1556                 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
1557         } else if (ol_flags & PKT_TX_IPV6) {
1558                 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
1559                 /* no checksum for ipv6 header */
1560                 *gen_l3_cksum = 0;
1561         } else {
1562                 /* if something different then stop processing */
1563                 return -1;
1564         }
1565
1566         ol_flags &= PKT_TX_L4_MASK;
1567         if ((packet_type & RTE_PTYPE_L4_TCP) &&
1568             ol_flags == PKT_TX_TCP_CKSUM) {
1569                 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
1570                 *gen_l4_cksum = 1;
1571         } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
1572                    ol_flags == PKT_TX_UDP_CKSUM) {
1573                 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
1574                 *gen_l4_cksum = 1;
1575         } else {
1576                 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
1577                 /* no checksum for other type */
1578                 *gen_l4_cksum = 0;
1579         }
1580
1581         return 0;
1582 }
1583
1584 /**
1585  * Release already sent buffers to bpool (buffer-pool).
1586  *
1587  * @param ppio
1588  *   Pointer to the port structure.
1589  * @param hif
1590  *   Pointer to the MUSDK hardware interface.
1591  * @param sq
1592  *   Pointer to the shadow queue.
1593  * @param qid
1594  *   Queue id number.
1595  * @param force
1596  *   Force releasing packets.
1597  */
1598 static inline void
1599 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1600                        struct mrvl_shadow_txq *sq, int qid, int force)
1601 {
1602         struct buff_release_entry *entry;
1603         uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1604         int i, core_id = rte_lcore_id();
1605
1606         pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1607
1608         sq->num_to_release += nb_done;
1609
1610         if (likely(!force &&
1611                    sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1612                 return;
1613
1614         nb_done = sq->num_to_release;
1615         sq->num_to_release = 0;
1616
1617         for (i = 0; i < nb_done; i++) {
1618                 entry = &sq->ent[sq->tail + num];
1619                 if (unlikely(!entry->buff.addr)) {
1620                         RTE_LOG(ERR, PMD,
1621                                 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1622                                 sq->tail, (u64)entry->buff.cookie,
1623                                 (u64)entry->buff.addr);
1624                         skip_bufs = 1;
1625                         goto skip;
1626                 }
1627
1628                 if (unlikely(!entry->bpool)) {
1629                         struct rte_mbuf *mbuf;
1630
1631                         mbuf = (struct rte_mbuf *)
1632                                (cookie_addr_high | entry->buff.cookie);
1633                         rte_pktmbuf_free(mbuf);
1634                         skip_bufs = 1;
1635                         goto skip;
1636                 }
1637
1638                 mrvl_port_bpool_size
1639                         [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
1640                 num++;
1641                 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
1642                         goto skip;
1643                 continue;
1644 skip:
1645                 if (likely(num))
1646                         pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1647                 num += skip_bufs;
1648                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1649                 sq->size -= num;
1650                 num = 0;
1651         }
1652
1653         if (likely(num)) {
1654                 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1655                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1656                 sq->size -= num;
1657         }
1658 }
1659
1660 /**
1661  * DPDK callback for transmit.
1662  *
1663  * @param txq
1664  *   Generic pointer transmit queue.
1665  * @param tx_pkts
1666  *   Packets to transmit.
1667  * @param nb_pkts
1668  *   Number of packets in array.
1669  *
1670  * @return
1671  *   Number of packets successfully transmitted.
1672  */
1673 static uint16_t
1674 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1675 {
1676         struct mrvl_txq *q = txq;
1677         struct mrvl_shadow_txq *sq = &shadow_txqs[q->port_id][rte_lcore_id()];
1678         struct pp2_hif *hif = hifs[rte_lcore_id()];
1679         struct pp2_ppio_desc descs[nb_pkts];
1680         int i, ret;
1681         uint16_t num, sq_free_size;
1682
1683         if (unlikely(!q->priv->ppio))
1684                 return 0;
1685
1686         if (sq->size)
1687                 mrvl_free_sent_buffers(q->priv->ppio, hif, sq, q->queue_id, 0);
1688
1689         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
1690         if (unlikely(nb_pkts > sq_free_size)) {
1691                 RTE_LOG(DEBUG, PMD,
1692                         "No room in shadow queue for %d packets! %d packets will be sent.\n",
1693                         nb_pkts, sq_free_size);
1694                 nb_pkts = sq_free_size;
1695         }
1696
1697         for (i = 0; i < nb_pkts; i++) {
1698                 struct rte_mbuf *mbuf = tx_pkts[i];
1699                 int gen_l3_cksum, gen_l4_cksum;
1700                 enum pp2_outq_l3_type l3_type;
1701                 enum pp2_outq_l4_type l4_type;
1702
1703                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1704                         struct rte_mbuf *pref_pkt_hdr;
1705
1706                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
1707                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
1708                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
1709                 }
1710
1711                 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
1712                 sq->ent[sq->head].buff.addr =
1713                         rte_mbuf_data_dma_addr_default(mbuf);
1714                 sq->ent[sq->head].bpool =
1715                         (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
1716                          NULL : mrvl_port_to_bpool_lookup[mbuf->port];
1717                 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
1718                 sq->size++;
1719
1720                 pp2_ppio_outq_desc_reset(&descs[i]);
1721                 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
1722                                                  rte_pktmbuf_mtophys(mbuf));
1723                 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
1724                 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
1725                                                rte_pktmbuf_pkt_len(mbuf));
1726
1727                 /*
1728                  * in case unsupported ol_flags were passed
1729                  * do not update descriptor offload information
1730                  */
1731                 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
1732                                               &l3_type, &l4_type, &gen_l3_cksum,
1733                                               &gen_l4_cksum);
1734                 if (unlikely(ret))
1735                         continue;
1736
1737                 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
1738                                                   mbuf->l2_len,
1739                                                   mbuf->l2_len + mbuf->l3_len,
1740                                                   gen_l3_cksum, gen_l4_cksum);
1741         }
1742
1743         num = nb_pkts;
1744         pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
1745         /* number of packets that were not sent */
1746         if (unlikely(num > nb_pkts)) {
1747                 for (i = nb_pkts; i < num; i++) {
1748                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
1749                                 MRVL_PP2_TX_SHADOWQ_MASK;
1750                 }
1751                 sq->size -= num - nb_pkts;
1752         }
1753
1754         return nb_pkts;
1755 }
1756
1757 /**
1758  * Initialize packet processor.
1759  *
1760  * @return
1761  *   0 on success, negative error value otherwise.
1762  */
1763 static int
1764 mrvl_init_pp2(void)
1765 {
1766         struct pp2_init_params init_params;
1767
1768         memset(&init_params, 0, sizeof(init_params));
1769         init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
1770         init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
1771         init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
1772
1773         return pp2_init(&init_params);
1774 }
1775
1776 /**
1777  * Deinitialize packet processor.
1778  *
1779  * @return
1780  *   0 on success, negative error value otherwise.
1781  */
1782 static void
1783 mrvl_deinit_pp2(void)
1784 {
1785         pp2_deinit();
1786 }
1787
1788 /**
1789  * Create private device structure.
1790  *
1791  * @param dev_name
1792  *   Pointer to the port name passed in the initialization parameters.
1793  *
1794  * @return
1795  *   Pointer to the newly allocated private device structure.
1796  */
1797 static struct mrvl_priv *
1798 mrvl_priv_create(const char *dev_name)
1799 {
1800         struct pp2_bpool_params bpool_params;
1801         char match[MRVL_MATCH_LEN];
1802         struct mrvl_priv *priv;
1803         int ret, bpool_bit;
1804
1805         priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
1806         if (!priv)
1807                 return NULL;
1808
1809         ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
1810                                        &priv->pp_id, &priv->ppio_id);
1811         if (ret)
1812                 goto out_free_priv;
1813
1814         bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
1815                                      PP2_BPOOL_NUM_POOLS);
1816         if (bpool_bit < 0)
1817                 goto out_free_priv;
1818         priv->bpool_bit = bpool_bit;
1819
1820         snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
1821                  priv->bpool_bit);
1822         memset(&bpool_params, 0, sizeof(bpool_params));
1823         bpool_params.match = match;
1824         bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
1825         ret = pp2_bpool_init(&bpool_params, &priv->bpool);
1826         if (ret)
1827                 goto out_clear_bpool_bit;
1828
1829         priv->ppio_params.type = PP2_PPIO_T_NIC;
1830         rte_spinlock_init(&priv->lock);
1831
1832         return priv;
1833 out_clear_bpool_bit:
1834         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
1835 out_free_priv:
1836         rte_free(priv);
1837         return NULL;
1838 }
1839
1840 /**
1841  * Create device representing Ethernet port.
1842  *
1843  * @param name
1844  *   Pointer to the port's name.
1845  *
1846  * @return
1847  *   0 on success, negative error value otherwise.
1848  */
1849 static int
1850 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
1851 {
1852         int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
1853         struct rte_eth_dev *eth_dev;
1854         struct mrvl_priv *priv;
1855         struct ifreq req;
1856
1857         eth_dev = rte_eth_dev_allocate(name);
1858         if (!eth_dev)
1859                 return -ENOMEM;
1860
1861         priv = mrvl_priv_create(name);
1862         if (!priv) {
1863                 ret = -ENOMEM;
1864                 goto out_free_dev;
1865         }
1866
1867         eth_dev->data->mac_addrs =
1868                 rte_zmalloc("mac_addrs",
1869                             ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
1870         if (!eth_dev->data->mac_addrs) {
1871                 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
1872                 ret = -ENOMEM;
1873                 goto out_free_priv;
1874         }
1875
1876         memset(&req, 0, sizeof(req));
1877         strcpy(req.ifr_name, name);
1878         ret = ioctl(fd, SIOCGIFHWADDR, &req);
1879         if (ret)
1880                 goto out_free_mac;
1881
1882         memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
1883                req.ifr_addr.sa_data, ETHER_ADDR_LEN);
1884
1885         eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
1886         eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
1887         eth_dev->data->dev_private = priv;
1888         eth_dev->device = &vdev->device;
1889         eth_dev->dev_ops = &mrvl_ops;
1890
1891         return 0;
1892 out_free_mac:
1893         rte_free(eth_dev->data->mac_addrs);
1894 out_free_dev:
1895         rte_eth_dev_release_port(eth_dev);
1896 out_free_priv:
1897         rte_free(priv);
1898
1899         return ret;
1900 }
1901
1902 /**
1903  * Cleanup previously created device representing Ethernet port.
1904  *
1905  * @param name
1906  *   Pointer to the port name.
1907  */
1908 static void
1909 mrvl_eth_dev_destroy(const char *name)
1910 {
1911         struct rte_eth_dev *eth_dev;
1912         struct mrvl_priv *priv;
1913
1914         eth_dev = rte_eth_dev_allocated(name);
1915         if (!eth_dev)
1916                 return;
1917
1918         priv = eth_dev->data->dev_private;
1919         pp2_bpool_deinit(priv->bpool);
1920         rte_free(priv);
1921         rte_free(eth_dev->data->mac_addrs);
1922         rte_eth_dev_release_port(eth_dev);
1923 }
1924
1925 /**
1926  * Callback used by rte_kvargs_process() during argument parsing.
1927  *
1928  * @param key
1929  *   Pointer to the parsed key (unused).
1930  * @param value
1931  *   Pointer to the parsed value.
1932  * @param extra_args
1933  *   Pointer to the extra arguments which contains address of the
1934  *   table of pointers to parsed interface names.
1935  *
1936  * @return
1937  *   Always 0.
1938  */
1939 static int
1940 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
1941                  void *extra_args)
1942 {
1943         const char **ifnames = extra_args;
1944
1945         ifnames[mrvl_ports_nb++] = value;
1946
1947         return 0;
1948 }
1949
1950 /**
1951  * Initialize per-lcore MUSDK hardware interfaces (hifs).
1952  *
1953  * @return
1954  *   0 on success, negative error value otherwise.
1955  */
1956 static int
1957 mrvl_init_hifs(void)
1958 {
1959         struct pp2_hif_params params;
1960         char match[MRVL_MATCH_LEN];
1961         int i, ret;
1962
1963         RTE_LCORE_FOREACH(i) {
1964                 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
1965                 if (ret < 0)
1966                         return ret;
1967
1968                 snprintf(match, sizeof(match), "hif-%d", ret);
1969                 memset(&params, 0, sizeof(params));
1970                 params.match = match;
1971                 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
1972                 ret = pp2_hif_init(&params, &hifs[i]);
1973                 if (ret) {
1974                         RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", i);
1975                         return ret;
1976                 }
1977         }
1978
1979         return 0;
1980 }
1981
1982 /**
1983  * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
1984  */
1985 static void
1986 mrvl_deinit_hifs(void)
1987 {
1988         int i;
1989
1990         RTE_LCORE_FOREACH(i) {
1991                 if (hifs[i])
1992                         pp2_hif_deinit(hifs[i]);
1993         }
1994 }
1995
1996 static void mrvl_set_first_last_cores(int core_id)
1997 {
1998         if (core_id < mrvl_lcore_first)
1999                 mrvl_lcore_first = core_id;
2000
2001         if (core_id > mrvl_lcore_last)
2002                 mrvl_lcore_last = core_id;
2003 }
2004
2005 /**
2006  * DPDK callback to register the virtual device.
2007  *
2008  * @param vdev
2009  *   Pointer to the virtual device.
2010  *
2011  * @return
2012  *   0 on success, negative error value otherwise.
2013  */
2014 static int
2015 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2016 {
2017         struct rte_kvargs *kvlist;
2018         const char *ifnames[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
2019         int ret = -EINVAL;
2020         uint32_t i, ifnum, cfgnum, core_id;
2021         const char *params;
2022
2023         params = rte_vdev_device_args(vdev);
2024         if (!params)
2025                 return -EINVAL;
2026
2027         kvlist = rte_kvargs_parse(params, valid_args);
2028         if (!kvlist)
2029                 return -EINVAL;
2030
2031         ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2032         if (ifnum > RTE_DIM(ifnames))
2033                 goto out_free_kvlist;
2034
2035         rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2036                            mrvl_get_ifnames, &ifnames);
2037
2038         cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2039         if (cfgnum > 1) {
2040                 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2041                 goto out_free_kvlist;
2042         } else if (cfgnum == 1) {
2043                 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2044                                    mrvl_get_qoscfg, &mrvl_qos_cfg);
2045         }
2046
2047         /*
2048          * ret == -EEXIST is correct, it means DMA
2049          * has been already initialized (by another PMD).
2050          */
2051         ret = mv_sys_dma_mem_init(RTE_MRVL_MUSDK_DMA_MEMSIZE);
2052         if (ret < 0 && ret != -EEXIST)
2053                 goto out_free_kvlist;
2054
2055         ret = mrvl_init_pp2();
2056         if (ret) {
2057                 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2058                 goto out_deinit_dma;
2059         }
2060
2061         ret = mrvl_init_hifs();
2062         if (ret)
2063                 goto out_deinit_hifs;
2064
2065         for (i = 0; i < ifnum; i++) {
2066                 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames[i]);
2067                 ret = mrvl_eth_dev_create(vdev, ifnames[i]);
2068                 if (ret)
2069                         goto out_cleanup;
2070         }
2071
2072         rte_kvargs_free(kvlist);
2073
2074         memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2075
2076         mrvl_lcore_first = RTE_MAX_LCORE;
2077         mrvl_lcore_last = 0;
2078
2079         RTE_LCORE_FOREACH(core_id) {
2080                 mrvl_set_first_last_cores(core_id);
2081         }
2082
2083         return 0;
2084 out_cleanup:
2085         for (; i > 0; i--)
2086                 mrvl_eth_dev_destroy(ifnames[i]);
2087 out_deinit_hifs:
2088         mrvl_deinit_hifs();
2089         mrvl_deinit_pp2();
2090 out_deinit_dma:
2091         mv_sys_dma_mem_destroy();
2092 out_free_kvlist:
2093         rte_kvargs_free(kvlist);
2094
2095         return ret;
2096 }
2097
2098 /**
2099  * DPDK callback to remove virtual device.
2100  *
2101  * @param vdev
2102  *   Pointer to the removed virtual device.
2103  *
2104  * @return
2105  *   0 on success, negative error value otherwise.
2106  */
2107 static int
2108 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2109 {
2110         int i;
2111         const char *name;
2112
2113         name = rte_vdev_device_name(vdev);
2114         if (!name)
2115                 return -EINVAL;
2116
2117         RTE_LOG(INFO, PMD, "Removing %s\n", name);
2118
2119         for (i = 0; i < rte_eth_dev_count(); i++) {
2120                 char ifname[RTE_ETH_NAME_MAX_LEN];
2121
2122                 rte_eth_dev_get_name_by_port(i, ifname);
2123                 mrvl_eth_dev_destroy(ifname);
2124         }
2125
2126         mrvl_deinit_hifs();
2127         mrvl_deinit_pp2();
2128         mv_sys_dma_mem_destroy();
2129
2130         return 0;
2131 }
2132
2133 static struct rte_vdev_driver pmd_mrvl_drv = {
2134         .probe = rte_pmd_mrvl_probe,
2135         .remove = rte_pmd_mrvl_remove,
2136 };
2137
2138 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
2139 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);