4 * Copyright(c) 2017 Marvell International Ltd.
5 * Copyright(c) 2017 Semihalf.
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9 * modification, are permitted provided that the following conditions
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35 #include <rte_ethdev.h>
36 #include <rte_kvargs.h>
38 #include <rte_malloc.h>
39 #include <rte_bus_vdev.h>
41 /* Unluckily, container_of is defined by both DPDK and MUSDK,
42 * we'll declare only one version.
44 * Note that it is not used in this PMD anyway.
51 #include <linux/ethtool.h>
52 #include <linux/sockios.h>
54 #include <net/if_arp.h>
55 #include <sys/ioctl.h>
56 #include <sys/socket.h>
58 #include <sys/types.h>
60 #include "mrvl_ethdev.h"
63 /* bitmask with reserved hifs */
64 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
65 /* bitmask with reserved bpools */
66 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
67 /* bitmask with reserved kernel RSS tables */
68 #define MRVL_MUSDK_RSS_RESERVED 0x01
69 /* maximum number of available hifs */
70 #define MRVL_MUSDK_HIFS_MAX 9
73 #define MRVL_MUSDK_PREFETCH_SHIFT 2
75 /* TCAM has 25 entries reserved for uc/mc filter entries */
76 #define MRVL_MAC_ADDRS_MAX 25
77 #define MRVL_MATCH_LEN 16
78 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
79 /* Maximum allowable packet size */
80 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
82 #define MRVL_IFACE_NAME_ARG "iface"
83 #define MRVL_CFG_ARG "cfg"
85 #define MRVL_BURST_SIZE 64
87 #define MRVL_ARP_LENGTH 28
89 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
91 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
92 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
94 /* Memory size (in bytes) for MUSDK dma buffers */
95 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
97 static const char * const valid_args[] = {
103 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
104 static struct pp2_hif *hifs[RTE_MAX_LCORE];
105 static int used_bpools[PP2_NUM_PKT_PROC] = {
106 MRVL_MUSDK_BPOOLS_RESERVED,
107 MRVL_MUSDK_BPOOLS_RESERVED
110 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
111 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
112 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
114 struct mrvl_ifnames {
115 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
120 * To use buffer harvesting based on loopback port shadow queue structure
121 * was introduced for buffers information bookkeeping.
123 * Before sending the packet, related buffer information (pp2_buff_inf) is
124 * stored in shadow queue. After packet is transmitted no longer used
125 * packet buffer is released back to it's original hardware pool,
126 * on condition it originated from interface.
127 * In case it was generated by application itself i.e: mbuf->port field is
128 * 0xff then its released to software mempool.
130 struct mrvl_shadow_txq {
131 int head; /* write index - used when sending buffers */
132 int tail; /* read index - used when releasing buffers */
133 u16 size; /* queue occupied size */
134 u16 num_to_release; /* number of buffers sent, that can be released */
135 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
139 struct mrvl_priv *priv;
140 struct rte_mempool *mp;
149 struct mrvl_priv *priv;
156 * Every tx queue should have dedicated shadow tx queue.
158 * Ports assigned by DPDK might not start at zero or be continuous so
159 * as a workaround define shadow queues for each possible port so that
160 * we eventually fit somewhere.
162 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_ETHPORTS][RTE_MAX_LCORE];
164 static int mrvl_lcore_first;
165 static int mrvl_lcore_last;
166 static int mrvl_dev_num;
168 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
171 mrvl_get_bpool_size(int pp2_id, int pool_id)
176 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
177 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
183 mrvl_reserve_bit(int *bitmap, int max)
185 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
196 mrvl_init_hif(int core_id)
198 struct pp2_hif_params params;
199 char match[MRVL_MATCH_LEN];
202 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
204 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
208 snprintf(match, sizeof(match), "hif-%d", ret);
209 memset(¶ms, 0, sizeof(params));
210 params.match = match;
211 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
212 ret = pp2_hif_init(¶ms, &hifs[core_id]);
214 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
221 static inline struct pp2_hif*
222 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
226 if (likely(hifs[core_id] != NULL))
227 return hifs[core_id];
229 rte_spinlock_lock(&priv->lock);
231 ret = mrvl_init_hif(core_id);
233 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
237 if (core_id < mrvl_lcore_first)
238 mrvl_lcore_first = core_id;
240 if (core_id > mrvl_lcore_last)
241 mrvl_lcore_last = core_id;
243 rte_spinlock_unlock(&priv->lock);
245 return hifs[core_id];
249 * Configure rss based on dpdk rss configuration.
252 * Pointer to private structure.
254 * Pointer to RSS configuration.
257 * 0 on success, negative error value otherwise.
260 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
262 if (rss_conf->rss_key)
263 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
265 if (rss_conf->rss_hf == 0) {
266 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
267 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
268 priv->ppio_params.inqs_params.hash_type =
269 PP2_PPIO_HASH_T_2_TUPLE;
270 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
271 priv->ppio_params.inqs_params.hash_type =
272 PP2_PPIO_HASH_T_5_TUPLE;
273 priv->rss_hf_tcp = 1;
274 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
275 priv->ppio_params.inqs_params.hash_type =
276 PP2_PPIO_HASH_T_5_TUPLE;
277 priv->rss_hf_tcp = 0;
286 * Ethernet device configuration.
288 * Prepare the driver for a given number of TX and RX queues and
292 * Pointer to Ethernet device structure.
295 * 0 on success, negative error value otherwise.
298 mrvl_dev_configure(struct rte_eth_dev *dev)
300 struct mrvl_priv *priv = dev->data->dev_private;
303 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
304 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
305 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
306 dev->data->dev_conf.rxmode.mq_mode);
310 if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
312 "L2 CRC stripping is always enabled in hw\n");
313 dev->data->dev_conf.rxmode.hw_strip_crc = 1;
316 if (dev->data->dev_conf.rxmode.hw_vlan_strip) {
317 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
321 if (dev->data->dev_conf.rxmode.split_hdr_size) {
322 RTE_LOG(INFO, PMD, "Split headers not supported\n");
326 if (dev->data->dev_conf.rxmode.enable_scatter) {
327 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
331 if (dev->data->dev_conf.rxmode.enable_lro) {
332 RTE_LOG(INFO, PMD, "LRO not supported\n");
336 if (dev->data->dev_conf.rxmode.jumbo_frame)
337 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
338 ETHER_HDR_LEN - ETHER_CRC_LEN;
340 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
341 dev->data->nb_rx_queues);
345 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
346 priv->ppio_params.maintain_stats = 1;
347 priv->nb_rx_queues = dev->data->nb_rx_queues;
349 if (dev->data->nb_rx_queues == 1 &&
350 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
351 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
352 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
357 return mrvl_configure_rss(priv,
358 &dev->data->dev_conf.rx_adv_conf.rss_conf);
362 * DPDK callback to change the MTU.
364 * Setting the MTU affects hardware MRU (packets larger than the MRU
368 * Pointer to Ethernet device structure.
373 * 0 on success, negative error value otherwise.
376 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
378 struct mrvl_priv *priv = dev->data->dev_private;
379 /* extra MV_MH_SIZE bytes are required for Marvell tag */
380 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
383 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
389 ret = pp2_ppio_set_mru(priv->ppio, mru);
393 return pp2_ppio_set_mtu(priv->ppio, mtu);
397 * DPDK callback to bring the link up.
400 * Pointer to Ethernet device structure.
403 * 0 on success, negative error value otherwise.
406 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
408 struct mrvl_priv *priv = dev->data->dev_private;
414 ret = pp2_ppio_enable(priv->ppio);
419 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
420 * as pp2_ppio_enable() changes port->t_mode from default 0 to
421 * PP2_TRAFFIC_INGRESS_EGRESS.
423 * Set mtu to default DPDK value here.
425 ret = mrvl_mtu_set(dev, dev->data->mtu);
427 pp2_ppio_disable(priv->ppio);
433 * DPDK callback to bring the link down.
436 * Pointer to Ethernet device structure.
439 * 0 on success, negative error value otherwise.
442 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
444 struct mrvl_priv *priv = dev->data->dev_private;
449 return pp2_ppio_disable(priv->ppio);
453 * DPDK callback to start the device.
456 * Pointer to Ethernet device structure.
459 * 0 on success, negative errno value on failure.
462 mrvl_dev_start(struct rte_eth_dev *dev)
464 struct mrvl_priv *priv = dev->data->dev_private;
465 char match[MRVL_MATCH_LEN];
466 int ret = 0, def_init_size;
468 snprintf(match, sizeof(match), "ppio-%d:%d",
469 priv->pp_id, priv->ppio_id);
470 priv->ppio_params.match = match;
473 * Calculate the minimum bpool size for refill feature as follows:
474 * 2 default burst sizes multiply by number of rx queues.
475 * If the bpool size will be below this value, new buffers will
476 * be added to the pool.
478 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
480 /* In case initial bpool size configured in queues setup is
481 * smaller than minimum size add more buffers
483 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
484 if (priv->bpool_init_size < def_init_size) {
485 int buffs_to_add = def_init_size - priv->bpool_init_size;
487 priv->bpool_init_size += buffs_to_add;
488 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
490 RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
494 * Calculate the maximum bpool size for refill feature as follows:
495 * maximum number of descriptors in rx queue multiply by number
496 * of rx queues plus minimum bpool size.
497 * In case the bpool size will exceed this value, superfluous buffers
500 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
501 priv->bpool_min_size;
503 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
505 RTE_LOG(ERR, PMD, "Failed to init ppio\n");
510 * In case there are some some stale uc/mc mac addresses flush them
511 * here. It cannot be done during mrvl_dev_close() as port information
512 * is already gone at that point (due to pp2_ppio_deinit() in
515 if (!priv->uc_mc_flushed) {
516 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
519 "Failed to flush uc/mc filter list\n");
522 priv->uc_mc_flushed = 1;
525 if (!priv->vlan_flushed) {
526 ret = pp2_ppio_flush_vlan(priv->ppio);
528 RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
531 * once pp2_ppio_flush_vlan() is supported jump to out
535 priv->vlan_flushed = 1;
538 /* For default QoS config, don't start classifier. */
540 ret = mrvl_start_qos_mapping(priv);
542 RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n");
547 ret = mrvl_dev_set_link_up(dev);
549 RTE_LOG(ERR, PMD, "Failed to set link up\n");
555 RTE_LOG(ERR, PMD, "Failed to start device\n");
556 pp2_ppio_deinit(priv->ppio);
561 * Flush receive queues.
564 * Pointer to Ethernet device structure.
567 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
571 RTE_LOG(INFO, PMD, "Flushing rx queues\n");
572 for (i = 0; i < dev->data->nb_rx_queues; i++) {
576 struct mrvl_rxq *q = dev->data->rx_queues[i];
577 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
579 num = MRVL_PP2_RXD_MAX;
580 ret = pp2_ppio_recv(q->priv->ppio,
581 q->priv->rxq_map[q->queue_id].tc,
582 q->priv->rxq_map[q->queue_id].inq,
583 descs, (uint16_t *)&num);
584 } while (ret == 0 && num);
589 * Flush transmit shadow queues.
592 * Pointer to Ethernet device structure.
595 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
599 RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
600 for (i = 0; i < RTE_MAX_LCORE; i++) {
601 struct mrvl_shadow_txq *sq =
602 &shadow_txqs[dev->data->port_id][i];
604 while (sq->tail != sq->head) {
605 uint64_t addr = cookie_addr_high |
606 sq->ent[sq->tail].buff.cookie;
607 rte_pktmbuf_free((struct rte_mbuf *)addr);
608 sq->tail = (sq->tail + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
611 memset(sq, 0, sizeof(*sq));
616 * Flush hardware bpool (buffer-pool).
619 * Pointer to Ethernet device structure.
622 mrvl_flush_bpool(struct rte_eth_dev *dev)
624 struct mrvl_priv *priv = dev->data->dev_private;
628 unsigned int core_id = rte_lcore_id();
630 if (core_id == LCORE_ID_ANY)
633 hif = mrvl_get_hif(priv, core_id);
635 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
637 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
642 struct pp2_buff_inf inf;
645 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
649 addr = cookie_addr_high | inf.cookie;
650 rte_pktmbuf_free((struct rte_mbuf *)addr);
655 * DPDK callback to stop the device.
658 * Pointer to Ethernet device structure.
661 mrvl_dev_stop(struct rte_eth_dev *dev)
663 struct mrvl_priv *priv = dev->data->dev_private;
665 mrvl_dev_set_link_down(dev);
666 mrvl_flush_rx_queues(dev);
667 mrvl_flush_tx_shadow_queues(dev);
669 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
670 priv->qos_tbl = NULL;
672 pp2_ppio_deinit(priv->ppio);
677 * DPDK callback to close the device.
680 * Pointer to Ethernet device structure.
683 mrvl_dev_close(struct rte_eth_dev *dev)
685 struct mrvl_priv *priv = dev->data->dev_private;
688 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
689 struct pp2_ppio_tc_params *tc_params =
690 &priv->ppio_params.inqs_params.tcs_params[i];
692 if (tc_params->inqs_params) {
693 rte_free(tc_params->inqs_params);
694 tc_params->inqs_params = NULL;
698 mrvl_flush_bpool(dev);
702 * DPDK callback to retrieve physical link information.
705 * Pointer to Ethernet device structure.
706 * @param wait_to_complete
707 * Wait for request completion (ignored).
710 * 0 on success, negative error value otherwise.
713 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
717 * once MUSDK provides necessary API use it here
719 struct mrvl_priv *priv = dev->data->dev_private;
720 struct ethtool_cmd edata;
722 int ret, fd, link_up;
727 edata.cmd = ETHTOOL_GSET;
729 strcpy(req.ifr_name, dev->data->name);
730 req.ifr_data = (void *)&edata;
732 fd = socket(AF_INET, SOCK_DGRAM, 0);
736 ret = ioctl(fd, SIOCETHTOOL, &req);
744 switch (ethtool_cmd_speed(&edata)) {
746 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
749 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
752 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
755 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
758 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
761 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
762 ETH_LINK_HALF_DUPLEX;
763 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
765 pp2_ppio_get_link_state(priv->ppio, &link_up);
766 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
772 * DPDK callback to enable promiscuous mode.
775 * Pointer to Ethernet device structure.
778 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
780 struct mrvl_priv *priv = dev->data->dev_private;
786 ret = pp2_ppio_set_promisc(priv->ppio, 1);
788 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
792 * DPDK callback to enable allmulti mode.
795 * Pointer to Ethernet device structure.
798 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
800 struct mrvl_priv *priv = dev->data->dev_private;
806 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
808 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
812 * DPDK callback to disable promiscuous mode.
815 * Pointer to Ethernet device structure.
818 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
820 struct mrvl_priv *priv = dev->data->dev_private;
826 ret = pp2_ppio_set_promisc(priv->ppio, 0);
828 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
832 * DPDK callback to disable allmulticast mode.
835 * Pointer to Ethernet device structure.
838 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
840 struct mrvl_priv *priv = dev->data->dev_private;
846 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
848 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
852 * DPDK callback to remove a MAC address.
855 * Pointer to Ethernet device structure.
860 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
862 struct mrvl_priv *priv = dev->data->dev_private;
863 char buf[ETHER_ADDR_FMT_SIZE];
869 ret = pp2_ppio_remove_mac_addr(priv->ppio,
870 dev->data->mac_addrs[index].addr_bytes);
872 ether_format_addr(buf, sizeof(buf),
873 &dev->data->mac_addrs[index]);
874 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
879 * DPDK callback to add a MAC address.
882 * Pointer to Ethernet device structure.
884 * MAC address to register.
888 * VMDq pool index to associate address with (unused).
891 * 0 on success, negative error value otherwise.
894 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
895 uint32_t index, uint32_t vmdq __rte_unused)
897 struct mrvl_priv *priv = dev->data->dev_private;
898 char buf[ETHER_ADDR_FMT_SIZE];
902 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
909 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
910 * parameter uc_filter_max. Maximum number of mc addresses is then
911 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
914 * If more than uc_filter_max uc addresses were added to filter list
915 * then NIC will switch to promiscuous mode automatically.
917 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
918 * were added to filter list then NIC will switch to all-multicast mode
921 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
923 ether_format_addr(buf, sizeof(buf), mac_addr);
924 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
932 * DPDK callback to set the primary MAC address.
935 * Pointer to Ethernet device structure.
937 * MAC address to register.
940 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
942 struct mrvl_priv *priv = dev->data->dev_private;
948 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
950 char buf[ETHER_ADDR_FMT_SIZE];
951 ether_format_addr(buf, sizeof(buf), mac_addr);
952 RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf);
957 * DPDK callback to get device statistics.
960 * Pointer to Ethernet device structure.
962 * Stats structure output buffer.
965 * 0 on success, negative error value otherwise.
968 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
970 struct mrvl_priv *priv = dev->data->dev_private;
971 struct pp2_ppio_statistics ppio_stats;
972 uint64_t drop_mac = 0;
973 unsigned int i, idx, ret;
978 for (i = 0; i < dev->data->nb_rx_queues; i++) {
979 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
980 struct pp2_ppio_inq_statistics rx_stats;
986 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
988 "rx queue %d stats out of range (0 - %d)\n",
989 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
993 ret = pp2_ppio_inq_get_statistics(priv->ppio,
994 priv->rxq_map[idx].tc,
995 priv->rxq_map[idx].inq,
999 "Failed to update rx queue %d stats\n", idx);
1003 stats->q_ibytes[idx] = rxq->bytes_recv;
1004 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1005 stats->q_errors[idx] = rx_stats.drop_early +
1006 rx_stats.drop_fullq +
1009 stats->ibytes += rxq->bytes_recv;
1010 drop_mac += rxq->drop_mac;
1013 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1014 struct mrvl_txq *txq = dev->data->tx_queues[i];
1015 struct pp2_ppio_outq_statistics tx_stats;
1020 idx = txq->queue_id;
1021 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1023 "tx queue %d stats out of range (0 - %d)\n",
1024 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1027 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1029 if (unlikely(ret)) {
1031 "Failed to update tx queue %d stats\n", idx);
1035 stats->q_opackets[idx] = tx_stats.deq_desc;
1036 stats->q_obytes[idx] = txq->bytes_sent;
1037 stats->obytes += txq->bytes_sent;
1040 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1041 if (unlikely(ret)) {
1042 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
1046 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1047 stats->opackets += ppio_stats.tx_packets;
1048 stats->imissed += ppio_stats.rx_fullq_dropped +
1049 ppio_stats.rx_bm_dropped +
1050 ppio_stats.rx_early_dropped +
1051 ppio_stats.rx_fifo_dropped +
1052 ppio_stats.rx_cls_dropped;
1053 stats->ierrors = drop_mac;
1059 * DPDK callback to clear device statistics.
1062 * Pointer to Ethernet device structure.
1065 mrvl_stats_reset(struct rte_eth_dev *dev)
1067 struct mrvl_priv *priv = dev->data->dev_private;
1073 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1074 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1076 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1077 priv->rxq_map[i].inq, NULL, 1);
1078 rxq->bytes_recv = 0;
1082 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1083 struct mrvl_txq *txq = dev->data->tx_queues[i];
1085 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1086 txq->bytes_sent = 0;
1089 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1093 * DPDK callback to get information about the device.
1096 * Pointer to Ethernet device structure (unused).
1098 * Info structure output buffer.
1101 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1102 struct rte_eth_dev_info *info)
1104 info->speed_capa = ETH_LINK_SPEED_10M |
1105 ETH_LINK_SPEED_100M |
1109 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1110 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1111 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1113 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1114 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1115 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1117 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1118 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1119 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1121 info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME |
1122 DEV_RX_OFFLOAD_VLAN_FILTER |
1123 DEV_RX_OFFLOAD_IPV4_CKSUM |
1124 DEV_RX_OFFLOAD_UDP_CKSUM |
1125 DEV_RX_OFFLOAD_TCP_CKSUM;
1127 info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
1128 DEV_TX_OFFLOAD_UDP_CKSUM |
1129 DEV_TX_OFFLOAD_TCP_CKSUM;
1131 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1132 ETH_RSS_NONFRAG_IPV4_TCP |
1133 ETH_RSS_NONFRAG_IPV4_UDP;
1135 /* By default packets are dropped if no descriptors are available */
1136 info->default_rxconf.rx_drop_en = 1;
1138 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1142 * Return supported packet types.
1145 * Pointer to Ethernet device structure (unused).
1148 * Const pointer to the table with supported packet types.
1150 static const uint32_t *
1151 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1153 static const uint32_t ptypes[] = {
1156 RTE_PTYPE_L3_IPV4_EXT,
1157 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1159 RTE_PTYPE_L3_IPV6_EXT,
1160 RTE_PTYPE_L2_ETHER_ARP,
1169 * DPDK callback to get information about specific receive queue.
1172 * Pointer to Ethernet device structure.
1173 * @param rx_queue_id
1174 * Receive queue index.
1176 * Receive queue information structure.
1178 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1179 struct rte_eth_rxq_info *qinfo)
1181 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1182 struct mrvl_priv *priv = dev->data->dev_private;
1183 int inq = priv->rxq_map[rx_queue_id].inq;
1184 int tc = priv->rxq_map[rx_queue_id].tc;
1185 struct pp2_ppio_tc_params *tc_params =
1186 &priv->ppio_params.inqs_params.tcs_params[tc];
1189 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1193 * DPDK callback to get information about specific transmit queue.
1196 * Pointer to Ethernet device structure.
1197 * @param tx_queue_id
1198 * Transmit queue index.
1200 * Transmit queue information structure.
1202 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1203 struct rte_eth_txq_info *qinfo)
1205 struct mrvl_priv *priv = dev->data->dev_private;
1208 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1212 * DPDK callback to Configure a VLAN filter.
1215 * Pointer to Ethernet device structure.
1217 * VLAN ID to filter.
1222 * 0 on success, negative error value otherwise.
1225 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1227 struct mrvl_priv *priv = dev->data->dev_private;
1232 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1233 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1237 * Release buffers to hardware bpool (buffer-pool)
1240 * Receive queue pointer.
1242 * Number of buffers to release to bpool.
1245 * 0 on success, negative error value otherwise.
1248 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1250 struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
1251 struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
1253 unsigned int core_id;
1254 struct pp2_hif *hif;
1255 struct pp2_bpool *bpool;
1257 core_id = rte_lcore_id();
1258 if (core_id == LCORE_ID_ANY)
1261 hif = mrvl_get_hif(rxq->priv, core_id);
1265 bpool = rxq->priv->bpool;
1267 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1271 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1273 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1275 for (i = 0; i < num; i++) {
1276 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1277 != cookie_addr_high) {
1279 "mbuf virtual addr high 0x%lx out of range\n",
1280 (uint64_t)mbufs[i] >> 32);
1284 entries[i].buff.addr =
1285 rte_mbuf_data_iova_default(mbufs[i]);
1286 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1287 entries[i].bpool = bpool;
1290 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1291 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1298 for (; i < num; i++)
1299 rte_pktmbuf_free(mbufs[i]);
1305 * DPDK callback to configure the receive queue.
1308 * Pointer to Ethernet device structure.
1312 * Number of descriptors to configure in queue.
1314 * NUMA socket on which memory must be allocated.
1316 * Thresholds parameters (unused_).
1318 * Memory pool for buffer allocations.
1321 * 0 on success, negative error value otherwise.
1324 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1325 unsigned int socket,
1326 const struct rte_eth_rxconf *conf __rte_unused,
1327 struct rte_mempool *mp)
1329 struct mrvl_priv *priv = dev->data->dev_private;
1330 struct mrvl_rxq *rxq;
1332 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1335 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1337 * Unknown TC mapping, mapping will not have a correct queue.
1339 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1340 idx, priv->ppio_id);
1344 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1345 MRVL_PKT_EFFEC_OFFS;
1346 if (min_size < max_rx_pkt_len) {
1348 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1349 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1350 MRVL_PKT_EFFEC_OFFS,
1355 if (dev->data->rx_queues[idx]) {
1356 rte_free(dev->data->rx_queues[idx]);
1357 dev->data->rx_queues[idx] = NULL;
1360 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1366 rxq->cksum_enabled = dev->data->dev_conf.rxmode.hw_ip_checksum;
1367 rxq->queue_id = idx;
1368 rxq->port_id = dev->data->port_id;
1369 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1371 tc = priv->rxq_map[rxq->queue_id].tc,
1372 inq = priv->rxq_map[rxq->queue_id].inq;
1373 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1376 ret = mrvl_fill_bpool(rxq, desc);
1382 priv->bpool_init_size += desc;
1384 dev->data->rx_queues[idx] = rxq;
1390 * DPDK callback to release the receive queue.
1393 * Generic receive queue pointer.
1396 mrvl_rx_queue_release(void *rxq)
1398 struct mrvl_rxq *q = rxq;
1399 struct pp2_ppio_tc_params *tc_params;
1400 int i, num, tc, inq;
1401 struct pp2_hif *hif;
1402 unsigned int core_id = rte_lcore_id();
1404 if (core_id == LCORE_ID_ANY)
1407 hif = mrvl_get_hif(q->priv, core_id);
1412 tc = q->priv->rxq_map[q->queue_id].tc;
1413 inq = q->priv->rxq_map[q->queue_id].inq;
1414 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1415 num = tc_params->inqs_params[inq].size;
1416 for (i = 0; i < num; i++) {
1417 struct pp2_buff_inf inf;
1420 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1421 addr = cookie_addr_high | inf.cookie;
1422 rte_pktmbuf_free((struct rte_mbuf *)addr);
1429 * DPDK callback to configure the transmit queue.
1432 * Pointer to Ethernet device structure.
1434 * Transmit queue index.
1436 * Number of descriptors to configure in the queue.
1438 * NUMA socket on which memory must be allocated.
1440 * Thresholds parameters (unused).
1443 * 0 on success, negative error value otherwise.
1446 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1447 unsigned int socket,
1448 const struct rte_eth_txconf *conf __rte_unused)
1450 struct mrvl_priv *priv = dev->data->dev_private;
1451 struct mrvl_txq *txq;
1453 if (dev->data->tx_queues[idx]) {
1454 rte_free(dev->data->tx_queues[idx]);
1455 dev->data->tx_queues[idx] = NULL;
1458 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1463 txq->queue_id = idx;
1464 txq->port_id = dev->data->port_id;
1465 dev->data->tx_queues[idx] = txq;
1467 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1468 priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1474 * DPDK callback to release the transmit queue.
1477 * Generic transmit queue pointer.
1480 mrvl_tx_queue_release(void *txq)
1482 struct mrvl_txq *q = txq;
1491 * Update RSS hash configuration
1494 * Pointer to Ethernet device structure.
1496 * Pointer to RSS configuration.
1499 * 0 on success, negative error value otherwise.
1502 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1503 struct rte_eth_rss_conf *rss_conf)
1505 struct mrvl_priv *priv = dev->data->dev_private;
1507 return mrvl_configure_rss(priv, rss_conf);
1511 * DPDK callback to get RSS hash configuration.
1514 * Pointer to Ethernet device structure.
1516 * Pointer to RSS configuration.
1522 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1523 struct rte_eth_rss_conf *rss_conf)
1525 struct mrvl_priv *priv = dev->data->dev_private;
1526 enum pp2_ppio_hash_type hash_type =
1527 priv->ppio_params.inqs_params.hash_type;
1529 rss_conf->rss_key = NULL;
1531 if (hash_type == PP2_PPIO_HASH_T_NONE)
1532 rss_conf->rss_hf = 0;
1533 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1534 rss_conf->rss_hf = ETH_RSS_IPV4;
1535 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1536 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1537 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1538 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1543 static const struct eth_dev_ops mrvl_ops = {
1544 .dev_configure = mrvl_dev_configure,
1545 .dev_start = mrvl_dev_start,
1546 .dev_stop = mrvl_dev_stop,
1547 .dev_set_link_up = mrvl_dev_set_link_up,
1548 .dev_set_link_down = mrvl_dev_set_link_down,
1549 .dev_close = mrvl_dev_close,
1550 .link_update = mrvl_link_update,
1551 .promiscuous_enable = mrvl_promiscuous_enable,
1552 .allmulticast_enable = mrvl_allmulticast_enable,
1553 .promiscuous_disable = mrvl_promiscuous_disable,
1554 .allmulticast_disable = mrvl_allmulticast_disable,
1555 .mac_addr_remove = mrvl_mac_addr_remove,
1556 .mac_addr_add = mrvl_mac_addr_add,
1557 .mac_addr_set = mrvl_mac_addr_set,
1558 .mtu_set = mrvl_mtu_set,
1559 .stats_get = mrvl_stats_get,
1560 .stats_reset = mrvl_stats_reset,
1561 .dev_infos_get = mrvl_dev_infos_get,
1562 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1563 .rxq_info_get = mrvl_rxq_info_get,
1564 .txq_info_get = mrvl_txq_info_get,
1565 .vlan_filter_set = mrvl_vlan_filter_set,
1566 .rx_queue_setup = mrvl_rx_queue_setup,
1567 .rx_queue_release = mrvl_rx_queue_release,
1568 .tx_queue_setup = mrvl_tx_queue_setup,
1569 .tx_queue_release = mrvl_tx_queue_release,
1570 .rss_hash_update = mrvl_rss_hash_update,
1571 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1575 * Return packet type information and l3/l4 offsets.
1578 * Pointer to the received packet descriptor.
1585 * Packet type information.
1587 static inline uint64_t
1588 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1589 uint8_t *l3_offset, uint8_t *l4_offset)
1591 enum pp2_inq_l3_type l3_type;
1592 enum pp2_inq_l4_type l4_type;
1593 uint64_t packet_type;
1595 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1596 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1598 packet_type = RTE_PTYPE_L2_ETHER;
1601 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1602 packet_type |= RTE_PTYPE_L3_IPV4;
1604 case PP2_INQ_L3_TYPE_IPV4_OK:
1605 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1607 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1608 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1610 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1611 packet_type |= RTE_PTYPE_L3_IPV6;
1613 case PP2_INQ_L3_TYPE_IPV6_EXT:
1614 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1616 case PP2_INQ_L3_TYPE_ARP:
1617 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1619 * In case of ARP l4_offset is set to wrong value.
1620 * Set it to proper one so that later on mbuf->l3_len can be
1621 * calculated subtracting l4_offset and l3_offset.
1623 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1626 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1631 case PP2_INQ_L4_TYPE_TCP:
1632 packet_type |= RTE_PTYPE_L4_TCP;
1634 case PP2_INQ_L4_TYPE_UDP:
1635 packet_type |= RTE_PTYPE_L4_UDP;
1638 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1646 * Get offload information from the received packet descriptor.
1649 * Pointer to the received packet descriptor.
1652 * Mbuf offload flags.
1654 static inline uint64_t
1655 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1658 enum pp2_inq_desc_status status;
1660 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1661 if (unlikely(status != PP2_DESC_ERR_OK))
1662 flags = PKT_RX_IP_CKSUM_BAD;
1664 flags = PKT_RX_IP_CKSUM_GOOD;
1666 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1667 if (unlikely(status != PP2_DESC_ERR_OK))
1668 flags |= PKT_RX_L4_CKSUM_BAD;
1670 flags |= PKT_RX_L4_CKSUM_GOOD;
1676 * DPDK callback for receive.
1679 * Generic pointer to the receive queue.
1681 * Array to store received packets.
1683 * Maximum number of packets in array.
1686 * Number of packets successfully received.
1689 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1691 struct mrvl_rxq *q = rxq;
1692 struct pp2_ppio_desc descs[nb_pkts];
1693 struct pp2_bpool *bpool;
1694 int i, ret, rx_done = 0;
1696 struct pp2_hif *hif;
1697 unsigned int core_id = rte_lcore_id();
1699 hif = mrvl_get_hif(q->priv, core_id);
1701 if (unlikely(!q->priv->ppio || !hif))
1704 bpool = q->priv->bpool;
1706 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1707 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1708 if (unlikely(ret < 0)) {
1709 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1712 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1714 for (i = 0; i < nb_pkts; i++) {
1715 struct rte_mbuf *mbuf;
1716 uint8_t l3_offset, l4_offset;
1717 enum pp2_inq_desc_status status;
1720 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1721 struct pp2_ppio_desc *pref_desc;
1724 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1725 pref_addr = cookie_addr_high |
1726 pp2_ppio_inq_desc_get_cookie(pref_desc);
1727 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1728 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1731 addr = cookie_addr_high |
1732 pp2_ppio_inq_desc_get_cookie(&descs[i]);
1733 mbuf = (struct rte_mbuf *)addr;
1734 rte_pktmbuf_reset(mbuf);
1736 /* drop packet in case of mac, overrun or resource error */
1737 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1738 if (unlikely(status != PP2_DESC_ERR_OK)) {
1739 struct pp2_buff_inf binf = {
1740 .addr = rte_mbuf_data_iova_default(mbuf),
1741 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1744 pp2_bpool_put_buff(hif, bpool, &binf);
1745 mrvl_port_bpool_size
1746 [bpool->pp2_id][bpool->id][core_id]++;
1751 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1752 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1753 mbuf->data_len = mbuf->pkt_len;
1754 mbuf->port = q->port_id;
1756 mrvl_desc_to_packet_type_and_offset(&descs[i],
1759 mbuf->l2_len = l3_offset;
1760 mbuf->l3_len = l4_offset - l3_offset;
1762 if (likely(q->cksum_enabled))
1763 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
1765 rx_pkts[rx_done++] = mbuf;
1766 q->bytes_recv += mbuf->pkt_len;
1769 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1770 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1772 if (unlikely(num <= q->priv->bpool_min_size ||
1773 (!rx_done && num < q->priv->bpool_init_size))) {
1774 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1776 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1777 } else if (unlikely(num > q->priv->bpool_max_size)) {
1779 int pkt_to_remove = num - q->priv->bpool_init_size;
1780 struct rte_mbuf *mbuf;
1781 struct pp2_buff_inf buff;
1784 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1785 bpool->pp2_id, q->priv->ppio->port_id,
1786 bpool->id, pkt_to_remove, num,
1787 q->priv->bpool_init_size);
1789 for (i = 0; i < pkt_to_remove; i++) {
1790 ret = pp2_bpool_get_buff(hif, bpool, &buff);
1793 mbuf = (struct rte_mbuf *)
1794 (cookie_addr_high | buff.cookie);
1795 rte_pktmbuf_free(mbuf);
1797 mrvl_port_bpool_size
1798 [bpool->pp2_id][bpool->id][core_id] -= i;
1800 rte_spinlock_unlock(&q->priv->lock);
1807 * Prepare offload information.
1811 * @param packet_type
1812 * Packet type bitfield.
1814 * Pointer to the pp2_ouq_l3_type structure.
1816 * Pointer to the pp2_outq_l4_type structure.
1817 * @param gen_l3_cksum
1818 * Will be set to 1 in case l3 checksum is computed.
1820 * Will be set to 1 in case l4 checksum is computed.
1823 * 0 on success, negative error value otherwise.
1826 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
1827 enum pp2_outq_l3_type *l3_type,
1828 enum pp2_outq_l4_type *l4_type,
1833 * Based on ol_flags prepare information
1834 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
1837 if (ol_flags & PKT_TX_IPV4) {
1838 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
1839 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
1840 } else if (ol_flags & PKT_TX_IPV6) {
1841 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
1842 /* no checksum for ipv6 header */
1845 /* if something different then stop processing */
1849 ol_flags &= PKT_TX_L4_MASK;
1850 if ((packet_type & RTE_PTYPE_L4_TCP) &&
1851 ol_flags == PKT_TX_TCP_CKSUM) {
1852 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
1854 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
1855 ol_flags == PKT_TX_UDP_CKSUM) {
1856 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
1859 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
1860 /* no checksum for other type */
1868 * Release already sent buffers to bpool (buffer-pool).
1871 * Pointer to the port structure.
1873 * Pointer to the MUSDK hardware interface.
1875 * Pointer to the shadow queue.
1879 * Force releasing packets.
1882 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1883 unsigned int core_id, struct mrvl_shadow_txq *sq,
1886 struct buff_release_entry *entry;
1887 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1890 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1892 sq->num_to_release += nb_done;
1894 if (likely(!force &&
1895 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1898 nb_done = sq->num_to_release;
1899 sq->num_to_release = 0;
1901 for (i = 0; i < nb_done; i++) {
1902 entry = &sq->ent[sq->tail + num];
1903 if (unlikely(!entry->buff.addr)) {
1905 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1906 sq->tail, (u64)entry->buff.cookie,
1907 (u64)entry->buff.addr);
1912 if (unlikely(!entry->bpool)) {
1913 struct rte_mbuf *mbuf;
1915 mbuf = (struct rte_mbuf *)
1916 (cookie_addr_high | entry->buff.cookie);
1917 rte_pktmbuf_free(mbuf);
1922 mrvl_port_bpool_size
1923 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
1925 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
1930 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1932 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1939 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1940 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1946 * DPDK callback for transmit.
1949 * Generic pointer transmit queue.
1951 * Packets to transmit.
1953 * Number of packets in array.
1956 * Number of packets successfully transmitted.
1959 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1961 struct mrvl_txq *q = txq;
1962 struct mrvl_shadow_txq *sq = &shadow_txqs[q->port_id][rte_lcore_id()];
1963 struct pp2_hif *hif;
1964 struct pp2_ppio_desc descs[nb_pkts];
1965 unsigned int core_id = rte_lcore_id();
1966 int i, ret, bytes_sent = 0;
1967 uint16_t num, sq_free_size;
1970 hif = mrvl_get_hif(q->priv, core_id);
1972 if (unlikely(!q->priv->ppio || !hif))
1976 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
1977 sq, q->queue_id, 0);
1979 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
1980 if (unlikely(nb_pkts > sq_free_size)) {
1982 "No room in shadow queue for %d packets! %d packets will be sent.\n",
1983 nb_pkts, sq_free_size);
1984 nb_pkts = sq_free_size;
1987 for (i = 0; i < nb_pkts; i++) {
1988 struct rte_mbuf *mbuf = tx_pkts[i];
1989 int gen_l3_cksum, gen_l4_cksum;
1990 enum pp2_outq_l3_type l3_type;
1991 enum pp2_outq_l4_type l4_type;
1993 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1994 struct rte_mbuf *pref_pkt_hdr;
1996 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
1997 rte_mbuf_prefetch_part1(pref_pkt_hdr);
1998 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2001 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2002 sq->ent[sq->head].buff.addr =
2003 rte_mbuf_data_iova_default(mbuf);
2004 sq->ent[sq->head].bpool =
2005 (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
2006 NULL : mrvl_port_to_bpool_lookup[mbuf->port];
2007 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2010 pp2_ppio_outq_desc_reset(&descs[i]);
2011 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2012 rte_pktmbuf_iova(mbuf));
2013 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2014 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2015 rte_pktmbuf_pkt_len(mbuf));
2017 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2019 * in case unsupported ol_flags were passed
2020 * do not update descriptor offload information
2022 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2023 &l3_type, &l4_type, &gen_l3_cksum,
2028 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2030 mbuf->l2_len + mbuf->l3_len,
2031 gen_l3_cksum, gen_l4_cksum);
2035 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2036 /* number of packets that were not sent */
2037 if (unlikely(num > nb_pkts)) {
2038 for (i = nb_pkts; i < num; i++) {
2039 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2040 MRVL_PP2_TX_SHADOWQ_MASK;
2041 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2043 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2045 sq->size -= num - nb_pkts;
2048 q->bytes_sent += bytes_sent;
2054 * Initialize packet processor.
2057 * 0 on success, negative error value otherwise.
2062 struct pp2_init_params init_params;
2064 memset(&init_params, 0, sizeof(init_params));
2065 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2066 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2067 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2069 return pp2_init(&init_params);
2073 * Deinitialize packet processor.
2076 * 0 on success, negative error value otherwise.
2079 mrvl_deinit_pp2(void)
2085 * Create private device structure.
2088 * Pointer to the port name passed in the initialization parameters.
2091 * Pointer to the newly allocated private device structure.
2093 static struct mrvl_priv *
2094 mrvl_priv_create(const char *dev_name)
2096 struct pp2_bpool_params bpool_params;
2097 char match[MRVL_MATCH_LEN];
2098 struct mrvl_priv *priv;
2101 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2105 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2106 &priv->pp_id, &priv->ppio_id);
2110 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2111 PP2_BPOOL_NUM_POOLS);
2114 priv->bpool_bit = bpool_bit;
2116 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2118 memset(&bpool_params, 0, sizeof(bpool_params));
2119 bpool_params.match = match;
2120 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2121 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2123 goto out_clear_bpool_bit;
2125 priv->ppio_params.type = PP2_PPIO_T_NIC;
2126 rte_spinlock_init(&priv->lock);
2129 out_clear_bpool_bit:
2130 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2137 * Create device representing Ethernet port.
2140 * Pointer to the port's name.
2143 * 0 on success, negative error value otherwise.
2146 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2148 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2149 struct rte_eth_dev *eth_dev;
2150 struct mrvl_priv *priv;
2153 eth_dev = rte_eth_dev_allocate(name);
2157 priv = mrvl_priv_create(name);
2163 eth_dev->data->mac_addrs =
2164 rte_zmalloc("mac_addrs",
2165 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2166 if (!eth_dev->data->mac_addrs) {
2167 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2172 memset(&req, 0, sizeof(req));
2173 strcpy(req.ifr_name, name);
2174 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2178 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2179 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2181 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2182 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2183 eth_dev->data->kdrv = RTE_KDRV_NONE;
2184 eth_dev->data->dev_private = priv;
2185 eth_dev->device = &vdev->device;
2186 eth_dev->dev_ops = &mrvl_ops;
2190 rte_free(eth_dev->data->mac_addrs);
2192 rte_eth_dev_release_port(eth_dev);
2200 * Cleanup previously created device representing Ethernet port.
2203 * Pointer to the port name.
2206 mrvl_eth_dev_destroy(const char *name)
2208 struct rte_eth_dev *eth_dev;
2209 struct mrvl_priv *priv;
2211 eth_dev = rte_eth_dev_allocated(name);
2215 priv = eth_dev->data->dev_private;
2216 pp2_bpool_deinit(priv->bpool);
2217 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2219 rte_free(eth_dev->data->mac_addrs);
2220 rte_eth_dev_release_port(eth_dev);
2224 * Callback used by rte_kvargs_process() during argument parsing.
2227 * Pointer to the parsed key (unused).
2229 * Pointer to the parsed value.
2231 * Pointer to the extra arguments which contains address of the
2232 * table of pointers to parsed interface names.
2238 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2241 struct mrvl_ifnames *ifnames = extra_args;
2243 ifnames->names[ifnames->idx++] = value;
2249 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2252 mrvl_deinit_hifs(void)
2256 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2258 pp2_hif_deinit(hifs[i]);
2260 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2261 memset(hifs, 0, sizeof(hifs));
2265 * DPDK callback to register the virtual device.
2268 * Pointer to the virtual device.
2271 * 0 on success, negative error value otherwise.
2274 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2276 struct rte_kvargs *kvlist;
2277 struct mrvl_ifnames ifnames;
2279 uint32_t i, ifnum, cfgnum;
2282 params = rte_vdev_device_args(vdev);
2286 kvlist = rte_kvargs_parse(params, valid_args);
2290 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2291 if (ifnum > RTE_DIM(ifnames.names))
2292 goto out_free_kvlist;
2295 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2296 mrvl_get_ifnames, &ifnames);
2300 * The below system initialization should be done only once,
2301 * on the first provided configuration file
2303 if (!mrvl_qos_cfg) {
2304 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2305 RTE_LOG(INFO, PMD, "Parsing config file!\n");
2307 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2308 goto out_free_kvlist;
2309 } else if (cfgnum == 1) {
2310 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2311 mrvl_get_qoscfg, &mrvl_qos_cfg);
2318 RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n");
2320 * ret == -EEXIST is correct, it means DMA
2321 * has been already initialized (by another PMD).
2323 ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2326 goto out_free_kvlist;
2329 "DMA memory has been already initialized by a different driver.\n");
2332 ret = mrvl_init_pp2();
2334 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2335 goto out_deinit_dma;
2338 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2340 mrvl_lcore_first = RTE_MAX_LCORE;
2341 mrvl_lcore_last = 0;
2344 for (i = 0; i < ifnum; i++) {
2345 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]);
2346 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2350 mrvl_dev_num += ifnum;
2352 rte_kvargs_free(kvlist);
2357 mrvl_eth_dev_destroy(ifnames.names[i]);
2359 if (mrvl_dev_num == 0)
2362 if (mrvl_dev_num == 0)
2363 mv_sys_dma_mem_destroy();
2365 rte_kvargs_free(kvlist);
2371 * DPDK callback to remove virtual device.
2374 * Pointer to the removed virtual device.
2377 * 0 on success, negative error value otherwise.
2380 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2385 name = rte_vdev_device_name(vdev);
2389 RTE_LOG(INFO, PMD, "Removing %s\n", name);
2391 for (i = 0; i < rte_eth_dev_count(); i++) {
2392 char ifname[RTE_ETH_NAME_MAX_LEN];
2394 rte_eth_dev_get_name_by_port(i, ifname);
2395 mrvl_eth_dev_destroy(ifname);
2399 if (mrvl_dev_num == 0) {
2400 RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n");
2403 mv_sys_dma_mem_destroy();
2409 static struct rte_vdev_driver pmd_mrvl_drv = {
2410 .probe = rte_pmd_mrvl_probe,
2411 .remove = rte_pmd_mrvl_remove,
2414 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
2415 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);