4 * Copyright(c) 2017 Marvell International Ltd.
5 * Copyright(c) 2017 Semihalf.
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35 #ifndef _MRVL_ETHDEV_H_
36 #define _MRVL_ETHDEV_H_
38 #include <rte_spinlock.h>
39 #include <drivers/mv_pp2_cls.h>
40 #include <drivers/mv_pp2_ppio.h>
42 /** Maximum number of rx queues per port */
43 #define MRVL_PP2_RXQ_MAX 32
45 /** Maximum number of tx queues per port */
46 #define MRVL_PP2_TXQ_MAX 8
48 /** Minimum number of descriptors in tx queue */
49 #define MRVL_PP2_TXD_MIN 16
51 /** Maximum number of descriptors in tx queue */
52 #define MRVL_PP2_TXD_MAX 2048
54 /** Tx queue descriptors alignment */
55 #define MRVL_PP2_TXD_ALIGN 16
57 /** Minimum number of descriptors in rx queue */
58 #define MRVL_PP2_RXD_MIN 16
60 /** Maximum number of descriptors in rx queue */
61 #define MRVL_PP2_RXD_MAX 2048
63 /** Rx queue descriptors alignment */
64 #define MRVL_PP2_RXD_ALIGN 16
66 /** Maximum number of descriptors in tx aggregated queue */
67 #define MRVL_PP2_AGGR_TXQD_MAX 2048
69 /** Maximum number of Traffic Classes. */
70 #define MRVL_PP2_TC_MAX 8
72 /** Packet offset inside RX buffer. */
73 #define MRVL_PKT_OFFS 64
75 /** Maximum number of descriptors in shadow queue. Must be power of 2 */
76 #define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX
78 /** Shadow queue size mask (since shadow queue size is power of 2) */
79 #define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1)
81 /** Minimum number of sent buffers to release from shadow queue to BM */
82 #define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64
85 /* Hot fields, used in fast path. */
86 struct pp2_bpool *bpool; /**< BPool pointer */
87 struct pp2_ppio *ppio; /**< Port handler pointer */
88 rte_spinlock_t lock; /**< Spinlock for checking bpool status */
89 uint16_t bpool_max_size; /**< BPool maximum size */
90 uint16_t bpool_min_size; /**< BPool minimum size */
91 uint16_t bpool_init_size; /**< Configured BPool size */
93 /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
95 uint8_t tc; /**< Traffic Class */
96 uint8_t inq; /**< Relative in-queue number */
97 } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
99 /* Configuration data, used sporadically. */
104 uint8_t uc_mc_flushed;
105 uint8_t vlan_flushed;
107 struct pp2_ppio_params ppio_params;
108 struct pp2_cls_qos_tbl_params qos_tbl_params;
109 struct pp2_cls_tbl *qos_tbl;
110 uint16_t nb_rx_queues;
113 /** Number of ports configured. */
114 extern int mrvl_ports_nb;
116 #endif /* _MRVL_ETHDEV_H_ */