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33 #ifndef _MRVL_ETHDEV_H_
34 #define _MRVL_ETHDEV_H_
36 #include <rte_spinlock.h>
37 #include <drivers/mv_pp2_cls.h>
38 #include <drivers/mv_pp2_ppio.h>
40 /** Maximum number of rx queues per port */
41 #define MRVL_PP2_RXQ_MAX 32
43 /** Maximum number of tx queues per port */
44 #define MRVL_PP2_TXQ_MAX 8
46 /** Minimum number of descriptors in tx queue */
47 #define MRVL_PP2_TXD_MIN 16
49 /** Maximum number of descriptors in tx queue */
50 #define MRVL_PP2_TXD_MAX 2048
52 /** Tx queue descriptors alignment */
53 #define MRVL_PP2_TXD_ALIGN 16
55 /** Minimum number of descriptors in rx queue */
56 #define MRVL_PP2_RXD_MIN 16
58 /** Maximum number of descriptors in rx queue */
59 #define MRVL_PP2_RXD_MAX 2048
61 /** Rx queue descriptors alignment */
62 #define MRVL_PP2_RXD_ALIGN 16
64 /** Maximum number of descriptors in tx aggregated queue */
65 #define MRVL_PP2_AGGR_TXQD_MAX 2048
67 /** Maximum number of Traffic Classes. */
68 #define MRVL_PP2_TC_MAX 8
70 /** Packet offset inside RX buffer. */
71 #define MRVL_PKT_OFFS 64
73 /** Maximum number of descriptors in shadow queue. Must be power of 2 */
74 #define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX
76 /** Shadow queue size mask (since shadow queue size is power of 2) */
77 #define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1)
79 /** Minimum number of sent buffers to release from shadow queue to BM */
80 #define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64
83 /* Hot fields, used in fast path. */
84 struct pp2_bpool *bpool; /**< BPool pointer */
85 struct pp2_ppio *ppio; /**< Port handler pointer */
86 rte_spinlock_t lock; /**< Spinlock for checking bpool status */
87 uint16_t bpool_max_size; /**< BPool maximum size */
88 uint16_t bpool_min_size; /**< BPool minimum size */
89 uint16_t bpool_init_size; /**< Configured BPool size */
91 /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
93 uint8_t tc; /**< Traffic Class */
94 uint8_t inq; /**< Relative in-queue number */
95 } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
97 /* Configuration data, used sporadically. */
102 uint8_t uc_mc_flushed;
103 uint8_t vlan_flushed;
105 struct pp2_ppio_params ppio_params;
106 struct pp2_cls_qos_tbl_params qos_tbl_params;
107 struct pp2_cls_tbl *qos_tbl;
108 uint16_t nb_rx_queues;
111 /** Number of ports configured. */
112 extern int mrvl_ports_nb;
114 #endif /* _MRVL_ETHDEV_H_ */