1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #ifndef _MRVL_ETHDEV_H_
8 #define _MRVL_ETHDEV_H_
10 #include <rte_spinlock.h>
12 #include <env/mv_autogen_comp_flags.h>
13 #include <drivers/mv_pp2.h>
14 #include <drivers/mv_pp2_bpool.h>
15 #include <drivers/mv_pp2_cls.h>
16 #include <drivers/mv_pp2_hif.h>
17 #include <drivers/mv_pp2_ppio.h>
19 /** Maximum number of rx queues per port */
20 #define MRVL_PP2_RXQ_MAX 32
22 /** Maximum number of tx queues per port */
23 #define MRVL_PP2_TXQ_MAX 8
25 /** Minimum number of descriptors in tx queue */
26 #define MRVL_PP2_TXD_MIN 16
28 /** Maximum number of descriptors in tx queue */
29 #define MRVL_PP2_TXD_MAX 2048
31 /** Tx queue descriptors alignment */
32 #define MRVL_PP2_TXD_ALIGN 16
34 /** Minimum number of descriptors in rx queue */
35 #define MRVL_PP2_RXD_MIN 16
37 /** Maximum number of descriptors in rx queue */
38 #define MRVL_PP2_RXD_MAX 2048
40 /** Rx queue descriptors alignment */
41 #define MRVL_PP2_RXD_ALIGN 16
43 /** Maximum number of descriptors in tx aggregated queue */
44 #define MRVL_PP2_AGGR_TXQD_MAX 2048
46 /** Maximum number of Traffic Classes. */
47 #define MRVL_PP2_TC_MAX 8
49 /** Packet offset inside RX buffer. */
50 #define MRVL_PKT_OFFS 64
52 /** Maximum number of descriptors in shadow queue. Must be power of 2 */
53 #define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX
55 /** Shadow queue size mask (since shadow queue size is power of 2) */
56 #define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1)
58 /** Minimum number of sent buffers to release from shadow queue to BM */
59 #define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64
62 /* Hot fields, used in fast path. */
63 struct pp2_bpool *bpool; /**< BPool pointer */
64 struct pp2_ppio *ppio; /**< Port handler pointer */
65 rte_spinlock_t lock; /**< Spinlock for checking bpool status */
66 uint16_t bpool_max_size; /**< BPool maximum size */
67 uint16_t bpool_min_size; /**< BPool minimum size */
68 uint16_t bpool_init_size; /**< Configured BPool size */
70 /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
72 uint8_t tc; /**< Traffic Class */
73 uint8_t inq; /**< Relative in-queue number */
74 } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
76 /* Configuration data, used sporadically. */
81 uint8_t uc_mc_flushed;
84 struct pp2_ppio_params ppio_params;
85 struct pp2_cls_qos_tbl_params qos_tbl_params;
86 struct pp2_cls_tbl *qos_tbl;
87 uint16_t nb_rx_queues;
90 #endif /* _MRVL_ETHDEV_H_ */