4 * Copyright(c) 2017 Marvell International Ltd.
5 * Copyright(c) 2017 Semihalf.
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20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35 #ifndef _MRVL_ETHDEV_H_
36 #define _MRVL_ETHDEV_H_
38 #include <rte_spinlock.h>
40 #include <env/mv_autogen_comp_flags.h>
41 #include <drivers/mv_pp2.h>
42 #include <drivers/mv_pp2_bpool.h>
43 #include <drivers/mv_pp2_cls.h>
44 #include <drivers/mv_pp2_hif.h>
45 #include <drivers/mv_pp2_ppio.h>
47 /** Maximum number of rx queues per port */
48 #define MRVL_PP2_RXQ_MAX 32
50 /** Maximum number of tx queues per port */
51 #define MRVL_PP2_TXQ_MAX 8
53 /** Minimum number of descriptors in tx queue */
54 #define MRVL_PP2_TXD_MIN 16
56 /** Maximum number of descriptors in tx queue */
57 #define MRVL_PP2_TXD_MAX 2048
59 /** Tx queue descriptors alignment */
60 #define MRVL_PP2_TXD_ALIGN 16
62 /** Minimum number of descriptors in rx queue */
63 #define MRVL_PP2_RXD_MIN 16
65 /** Maximum number of descriptors in rx queue */
66 #define MRVL_PP2_RXD_MAX 2048
68 /** Rx queue descriptors alignment */
69 #define MRVL_PP2_RXD_ALIGN 16
71 /** Maximum number of descriptors in tx aggregated queue */
72 #define MRVL_PP2_AGGR_TXQD_MAX 2048
74 /** Maximum number of Traffic Classes. */
75 #define MRVL_PP2_TC_MAX 8
77 /** Packet offset inside RX buffer. */
78 #define MRVL_PKT_OFFS 64
80 /** Maximum number of descriptors in shadow queue. Must be power of 2 */
81 #define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX
83 /** Shadow queue size mask (since shadow queue size is power of 2) */
84 #define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1)
86 /** Minimum number of sent buffers to release from shadow queue to BM */
87 #define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64
90 /* Hot fields, used in fast path. */
91 struct pp2_bpool *bpool; /**< BPool pointer */
92 struct pp2_ppio *ppio; /**< Port handler pointer */
93 rte_spinlock_t lock; /**< Spinlock for checking bpool status */
94 uint16_t bpool_max_size; /**< BPool maximum size */
95 uint16_t bpool_min_size; /**< BPool minimum size */
96 uint16_t bpool_init_size; /**< Configured BPool size */
98 /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
100 uint8_t tc; /**< Traffic Class */
101 uint8_t inq; /**< Relative in-queue number */
102 } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
104 /* Configuration data, used sporadically. */
109 uint8_t uc_mc_flushed;
110 uint8_t vlan_flushed;
112 struct pp2_ppio_params ppio_params;
113 struct pp2_cls_qos_tbl_params qos_tbl_params;
114 struct pp2_cls_tbl *qos_tbl;
115 uint16_t nb_rx_queues;
118 #endif /* _MRVL_ETHDEV_H_ */