1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_ethdev_driver.h>
8 #include <rte_kvargs.h>
10 #include <rte_malloc.h>
11 #include <rte_bus_vdev.h>
13 /* Unluckily, container_of is defined by both DPDK and MUSDK,
14 * we'll declare only one version.
16 * Note that it is not used in this PMD anyway.
23 #include <linux/ethtool.h>
24 #include <linux/sockios.h>
26 #include <net/if_arp.h>
27 #include <sys/ioctl.h>
28 #include <sys/socket.h>
30 #include <sys/types.h>
32 #include "mrvl_ethdev.h"
35 /* bitmask with reserved hifs */
36 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
37 /* bitmask with reserved bpools */
38 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
39 /* bitmask with reserved kernel RSS tables */
40 #define MRVL_MUSDK_RSS_RESERVED 0x01
41 /* maximum number of available hifs */
42 #define MRVL_MUSDK_HIFS_MAX 9
45 #define MRVL_MUSDK_PREFETCH_SHIFT 2
47 /* TCAM has 25 entries reserved for uc/mc filter entries */
48 #define MRVL_MAC_ADDRS_MAX 25
49 #define MRVL_MATCH_LEN 16
50 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
51 /* Maximum allowable packet size */
52 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
54 #define MRVL_IFACE_NAME_ARG "iface"
55 #define MRVL_CFG_ARG "cfg"
57 #define MRVL_BURST_SIZE 64
59 #define MRVL_ARP_LENGTH 28
61 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
63 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
64 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
66 /* Memory size (in bytes) for MUSDK dma buffers */
67 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
69 /** Port Rx offload capabilities */
70 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
71 DEV_RX_OFFLOAD_JUMBO_FRAME | \
72 DEV_RX_OFFLOAD_CRC_STRIP | \
73 DEV_RX_OFFLOAD_CHECKSUM)
75 /** Port Tx offloads capabilities */
76 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
77 DEV_TX_OFFLOAD_UDP_CKSUM | \
78 DEV_TX_OFFLOAD_TCP_CKSUM)
80 static const char * const valid_args[] = {
86 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
87 static struct pp2_hif *hifs[RTE_MAX_LCORE];
88 static int used_bpools[PP2_NUM_PKT_PROC] = {
89 MRVL_MUSDK_BPOOLS_RESERVED,
90 MRVL_MUSDK_BPOOLS_RESERVED
93 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
94 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
95 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
98 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
103 * To use buffer harvesting based on loopback port shadow queue structure
104 * was introduced for buffers information bookkeeping.
106 * Before sending the packet, related buffer information (pp2_buff_inf) is
107 * stored in shadow queue. After packet is transmitted no longer used
108 * packet buffer is released back to it's original hardware pool,
109 * on condition it originated from interface.
110 * In case it was generated by application itself i.e: mbuf->port field is
111 * 0xff then its released to software mempool.
113 struct mrvl_shadow_txq {
114 int head; /* write index - used when sending buffers */
115 int tail; /* read index - used when releasing buffers */
116 u16 size; /* queue occupied size */
117 u16 num_to_release; /* number of buffers sent, that can be released */
118 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
122 struct mrvl_priv *priv;
123 struct rte_mempool *mp;
132 struct mrvl_priv *priv;
136 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
137 int tx_deferred_start;
140 static int mrvl_lcore_first;
141 static int mrvl_lcore_last;
142 static int mrvl_dev_num;
144 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
145 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
146 struct pp2_hif *hif, unsigned int core_id,
147 struct mrvl_shadow_txq *sq, int qid, int force);
149 #define MRVL_XSTATS_TBL_ENTRY(name) { \
150 #name, offsetof(struct pp2_ppio_statistics, name), \
151 sizeof(((struct pp2_ppio_statistics *)0)->name) \
154 /* Table with xstats data */
159 } mrvl_xstats_tbl[] = {
160 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
161 MRVL_XSTATS_TBL_ENTRY(rx_packets),
162 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
163 MRVL_XSTATS_TBL_ENTRY(rx_errors),
164 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
165 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
166 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
167 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
168 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
169 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
170 MRVL_XSTATS_TBL_ENTRY(tx_packets),
171 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
172 MRVL_XSTATS_TBL_ENTRY(tx_errors)
176 mrvl_get_bpool_size(int pp2_id, int pool_id)
181 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
182 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
188 mrvl_reserve_bit(int *bitmap, int max)
190 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
201 mrvl_init_hif(int core_id)
203 struct pp2_hif_params params;
204 char match[MRVL_MATCH_LEN];
207 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
209 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
213 snprintf(match, sizeof(match), "hif-%d", ret);
214 memset(¶ms, 0, sizeof(params));
215 params.match = match;
216 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
217 ret = pp2_hif_init(¶ms, &hifs[core_id]);
219 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
226 static inline struct pp2_hif*
227 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
231 if (likely(hifs[core_id] != NULL))
232 return hifs[core_id];
234 rte_spinlock_lock(&priv->lock);
236 ret = mrvl_init_hif(core_id);
238 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
242 if (core_id < mrvl_lcore_first)
243 mrvl_lcore_first = core_id;
245 if (core_id > mrvl_lcore_last)
246 mrvl_lcore_last = core_id;
248 rte_spinlock_unlock(&priv->lock);
250 return hifs[core_id];
254 * Configure rss based on dpdk rss configuration.
257 * Pointer to private structure.
259 * Pointer to RSS configuration.
262 * 0 on success, negative error value otherwise.
265 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
267 if (rss_conf->rss_key)
268 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
270 if (rss_conf->rss_hf == 0) {
271 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
272 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
273 priv->ppio_params.inqs_params.hash_type =
274 PP2_PPIO_HASH_T_2_TUPLE;
275 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
276 priv->ppio_params.inqs_params.hash_type =
277 PP2_PPIO_HASH_T_5_TUPLE;
278 priv->rss_hf_tcp = 1;
279 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
280 priv->ppio_params.inqs_params.hash_type =
281 PP2_PPIO_HASH_T_5_TUPLE;
282 priv->rss_hf_tcp = 0;
291 * Ethernet device configuration.
293 * Prepare the driver for a given number of TX and RX queues and
297 * Pointer to Ethernet device structure.
300 * 0 on success, negative error value otherwise.
303 mrvl_dev_configure(struct rte_eth_dev *dev)
305 struct mrvl_priv *priv = dev->data->dev_private;
308 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
309 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
310 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
311 dev->data->dev_conf.rxmode.mq_mode);
315 if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
317 "L2 CRC stripping is always enabled in hw\n");
318 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
321 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
322 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
326 if (dev->data->dev_conf.rxmode.split_hdr_size) {
327 RTE_LOG(INFO, PMD, "Split headers not supported\n");
331 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) {
332 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
336 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
337 RTE_LOG(INFO, PMD, "LRO not supported\n");
341 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
342 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
343 ETHER_HDR_LEN - ETHER_CRC_LEN;
345 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
346 dev->data->nb_rx_queues);
350 ret = mrvl_configure_txqs(priv, dev->data->port_id,
351 dev->data->nb_tx_queues);
355 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
356 priv->ppio_params.maintain_stats = 1;
357 priv->nb_rx_queues = dev->data->nb_rx_queues;
359 if (dev->data->nb_rx_queues == 1 &&
360 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
361 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
362 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
367 return mrvl_configure_rss(priv,
368 &dev->data->dev_conf.rx_adv_conf.rss_conf);
372 * DPDK callback to change the MTU.
374 * Setting the MTU affects hardware MRU (packets larger than the MRU
378 * Pointer to Ethernet device structure.
383 * 0 on success, negative error value otherwise.
386 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
388 struct mrvl_priv *priv = dev->data->dev_private;
389 /* extra MV_MH_SIZE bytes are required for Marvell tag */
390 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
393 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
399 ret = pp2_ppio_set_mru(priv->ppio, mru);
403 return pp2_ppio_set_mtu(priv->ppio, mtu);
407 * DPDK callback to bring the link up.
410 * Pointer to Ethernet device structure.
413 * 0 on success, negative error value otherwise.
416 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
418 struct mrvl_priv *priv = dev->data->dev_private;
424 ret = pp2_ppio_enable(priv->ppio);
429 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
430 * as pp2_ppio_enable() changes port->t_mode from default 0 to
431 * PP2_TRAFFIC_INGRESS_EGRESS.
433 * Set mtu to default DPDK value here.
435 ret = mrvl_mtu_set(dev, dev->data->mtu);
437 pp2_ppio_disable(priv->ppio);
443 * DPDK callback to bring the link down.
446 * Pointer to Ethernet device structure.
449 * 0 on success, negative error value otherwise.
452 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
454 struct mrvl_priv *priv = dev->data->dev_private;
459 return pp2_ppio_disable(priv->ppio);
463 * DPDK callback to start tx queue.
466 * Pointer to Ethernet device structure.
468 * Transmit queue index.
471 * 0 on success, negative error value otherwise.
474 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
476 struct mrvl_priv *priv = dev->data->dev_private;
482 /* passing 1 enables given tx queue */
483 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
485 RTE_LOG(ERR, PMD, "Failed to start txq %d\n", queue_id);
489 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
495 * DPDK callback to stop tx queue.
498 * Pointer to Ethernet device structure.
500 * Transmit queue index.
503 * 0 on success, negative error value otherwise.
506 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
508 struct mrvl_priv *priv = dev->data->dev_private;
514 /* passing 0 disables given tx queue */
515 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
517 RTE_LOG(ERR, PMD, "Failed to stop txq %d\n", queue_id);
521 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
527 * DPDK callback to start the device.
530 * Pointer to Ethernet device structure.
533 * 0 on success, negative errno value on failure.
536 mrvl_dev_start(struct rte_eth_dev *dev)
538 struct mrvl_priv *priv = dev->data->dev_private;
539 char match[MRVL_MATCH_LEN];
540 int ret = 0, i, def_init_size;
542 snprintf(match, sizeof(match), "ppio-%d:%d",
543 priv->pp_id, priv->ppio_id);
544 priv->ppio_params.match = match;
547 * Calculate the minimum bpool size for refill feature as follows:
548 * 2 default burst sizes multiply by number of rx queues.
549 * If the bpool size will be below this value, new buffers will
550 * be added to the pool.
552 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
554 /* In case initial bpool size configured in queues setup is
555 * smaller than minimum size add more buffers
557 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
558 if (priv->bpool_init_size < def_init_size) {
559 int buffs_to_add = def_init_size - priv->bpool_init_size;
561 priv->bpool_init_size += buffs_to_add;
562 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
564 RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
568 * Calculate the maximum bpool size for refill feature as follows:
569 * maximum number of descriptors in rx queue multiply by number
570 * of rx queues plus minimum bpool size.
571 * In case the bpool size will exceed this value, superfluous buffers
574 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
575 priv->bpool_min_size;
577 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
579 RTE_LOG(ERR, PMD, "Failed to init ppio\n");
584 * In case there are some some stale uc/mc mac addresses flush them
585 * here. It cannot be done during mrvl_dev_close() as port information
586 * is already gone at that point (due to pp2_ppio_deinit() in
589 if (!priv->uc_mc_flushed) {
590 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
593 "Failed to flush uc/mc filter list\n");
596 priv->uc_mc_flushed = 1;
599 if (!priv->vlan_flushed) {
600 ret = pp2_ppio_flush_vlan(priv->ppio);
602 RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
605 * once pp2_ppio_flush_vlan() is supported jump to out
609 priv->vlan_flushed = 1;
612 /* For default QoS config, don't start classifier. */
614 ret = mrvl_start_qos_mapping(priv);
616 RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n");
621 ret = mrvl_dev_set_link_up(dev);
623 RTE_LOG(ERR, PMD, "Failed to set link up\n");
627 /* start tx queues */
628 for (i = 0; i < dev->data->nb_tx_queues; i++) {
629 struct mrvl_txq *txq = dev->data->tx_queues[i];
631 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
633 if (!txq->tx_deferred_start)
637 * All txqs are started by default. Stop them
638 * so that tx_deferred_start works as expected.
640 ret = mrvl_tx_queue_stop(dev, i);
647 RTE_LOG(ERR, PMD, "Failed to start device\n");
648 pp2_ppio_deinit(priv->ppio);
653 * Flush receive queues.
656 * Pointer to Ethernet device structure.
659 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
663 RTE_LOG(INFO, PMD, "Flushing rx queues\n");
664 for (i = 0; i < dev->data->nb_rx_queues; i++) {
668 struct mrvl_rxq *q = dev->data->rx_queues[i];
669 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
671 num = MRVL_PP2_RXD_MAX;
672 ret = pp2_ppio_recv(q->priv->ppio,
673 q->priv->rxq_map[q->queue_id].tc,
674 q->priv->rxq_map[q->queue_id].inq,
675 descs, (uint16_t *)&num);
676 } while (ret == 0 && num);
681 * Flush transmit shadow queues.
684 * Pointer to Ethernet device structure.
687 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
690 struct mrvl_txq *txq;
692 RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
693 for (i = 0; i < dev->data->nb_tx_queues; i++) {
694 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
696 for (j = 0; j < RTE_MAX_LCORE; j++) {
697 struct mrvl_shadow_txq *sq;
702 sq = &txq->shadow_txqs[j];
703 mrvl_free_sent_buffers(txq->priv->ppio,
704 hifs[j], j, sq, txq->queue_id, 1);
705 while (sq->tail != sq->head) {
706 uint64_t addr = cookie_addr_high |
707 sq->ent[sq->tail].buff.cookie;
709 (struct rte_mbuf *)addr);
710 sq->tail = (sq->tail + 1) &
711 MRVL_PP2_TX_SHADOWQ_MASK;
713 memset(sq, 0, sizeof(*sq));
719 * Flush hardware bpool (buffer-pool).
722 * Pointer to Ethernet device structure.
725 mrvl_flush_bpool(struct rte_eth_dev *dev)
727 struct mrvl_priv *priv = dev->data->dev_private;
731 unsigned int core_id = rte_lcore_id();
733 if (core_id == LCORE_ID_ANY)
736 hif = mrvl_get_hif(priv, core_id);
738 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
740 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
745 struct pp2_buff_inf inf;
748 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
752 addr = cookie_addr_high | inf.cookie;
753 rte_pktmbuf_free((struct rte_mbuf *)addr);
758 * DPDK callback to stop the device.
761 * Pointer to Ethernet device structure.
764 mrvl_dev_stop(struct rte_eth_dev *dev)
766 struct mrvl_priv *priv = dev->data->dev_private;
768 mrvl_dev_set_link_down(dev);
769 mrvl_flush_rx_queues(dev);
770 mrvl_flush_tx_shadow_queues(dev);
772 pp2_cls_tbl_deinit(priv->cls_tbl);
773 priv->cls_tbl = NULL;
776 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
777 priv->qos_tbl = NULL;
780 pp2_ppio_deinit(priv->ppio);
783 /* policer must be released after ppio deinitialization */
785 pp2_cls_plcr_deinit(priv->policer);
786 priv->policer = NULL;
791 * DPDK callback to close the device.
794 * Pointer to Ethernet device structure.
797 mrvl_dev_close(struct rte_eth_dev *dev)
799 struct mrvl_priv *priv = dev->data->dev_private;
802 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
803 struct pp2_ppio_tc_params *tc_params =
804 &priv->ppio_params.inqs_params.tcs_params[i];
806 if (tc_params->inqs_params) {
807 rte_free(tc_params->inqs_params);
808 tc_params->inqs_params = NULL;
812 mrvl_flush_bpool(dev);
816 * DPDK callback to retrieve physical link information.
819 * Pointer to Ethernet device structure.
820 * @param wait_to_complete
821 * Wait for request completion (ignored).
824 * 0 on success, negative error value otherwise.
827 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
831 * once MUSDK provides necessary API use it here
833 struct mrvl_priv *priv = dev->data->dev_private;
834 struct ethtool_cmd edata;
836 int ret, fd, link_up;
841 edata.cmd = ETHTOOL_GSET;
843 strcpy(req.ifr_name, dev->data->name);
844 req.ifr_data = (void *)&edata;
846 fd = socket(AF_INET, SOCK_DGRAM, 0);
850 ret = ioctl(fd, SIOCETHTOOL, &req);
858 switch (ethtool_cmd_speed(&edata)) {
860 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
863 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
866 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
869 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
872 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
875 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
876 ETH_LINK_HALF_DUPLEX;
877 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
879 pp2_ppio_get_link_state(priv->ppio, &link_up);
880 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
886 * DPDK callback to enable promiscuous mode.
889 * Pointer to Ethernet device structure.
892 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
894 struct mrvl_priv *priv = dev->data->dev_private;
903 ret = pp2_ppio_set_promisc(priv->ppio, 1);
905 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
909 * DPDK callback to enable allmulti mode.
912 * Pointer to Ethernet device structure.
915 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
917 struct mrvl_priv *priv = dev->data->dev_private;
926 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
928 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
932 * DPDK callback to disable promiscuous mode.
935 * Pointer to Ethernet device structure.
938 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
940 struct mrvl_priv *priv = dev->data->dev_private;
946 ret = pp2_ppio_set_promisc(priv->ppio, 0);
948 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
952 * DPDK callback to disable allmulticast mode.
955 * Pointer to Ethernet device structure.
958 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
960 struct mrvl_priv *priv = dev->data->dev_private;
966 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
968 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
972 * DPDK callback to remove a MAC address.
975 * Pointer to Ethernet device structure.
980 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
982 struct mrvl_priv *priv = dev->data->dev_private;
983 char buf[ETHER_ADDR_FMT_SIZE];
992 ret = pp2_ppio_remove_mac_addr(priv->ppio,
993 dev->data->mac_addrs[index].addr_bytes);
995 ether_format_addr(buf, sizeof(buf),
996 &dev->data->mac_addrs[index]);
997 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
1002 * DPDK callback to add a MAC address.
1005 * Pointer to Ethernet device structure.
1007 * MAC address to register.
1009 * MAC address index.
1011 * VMDq pool index to associate address with (unused).
1014 * 0 on success, negative error value otherwise.
1017 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1018 uint32_t index, uint32_t vmdq __rte_unused)
1020 struct mrvl_priv *priv = dev->data->dev_private;
1021 char buf[ETHER_ADDR_FMT_SIZE];
1028 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1035 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1036 * parameter uc_filter_max. Maximum number of mc addresses is then
1037 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1040 * If more than uc_filter_max uc addresses were added to filter list
1041 * then NIC will switch to promiscuous mode automatically.
1043 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1044 * were added to filter list then NIC will switch to all-multicast mode
1047 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1049 ether_format_addr(buf, sizeof(buf), mac_addr);
1050 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
1058 * DPDK callback to set the primary MAC address.
1061 * Pointer to Ethernet device structure.
1063 * MAC address to register.
1066 * 0 on success, negative error value otherwise.
1069 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1071 struct mrvl_priv *priv = dev->data->dev_private;
1080 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1082 char buf[ETHER_ADDR_FMT_SIZE];
1083 ether_format_addr(buf, sizeof(buf), mac_addr);
1084 RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf);
1091 * DPDK callback to get device statistics.
1094 * Pointer to Ethernet device structure.
1096 * Stats structure output buffer.
1099 * 0 on success, negative error value otherwise.
1102 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1104 struct mrvl_priv *priv = dev->data->dev_private;
1105 struct pp2_ppio_statistics ppio_stats;
1106 uint64_t drop_mac = 0;
1107 unsigned int i, idx, ret;
1112 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1113 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1114 struct pp2_ppio_inq_statistics rx_stats;
1119 idx = rxq->queue_id;
1120 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1122 "rx queue %d stats out of range (0 - %d)\n",
1123 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1127 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1128 priv->rxq_map[idx].tc,
1129 priv->rxq_map[idx].inq,
1131 if (unlikely(ret)) {
1133 "Failed to update rx queue %d stats\n", idx);
1137 stats->q_ibytes[idx] = rxq->bytes_recv;
1138 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1139 stats->q_errors[idx] = rx_stats.drop_early +
1140 rx_stats.drop_fullq +
1143 stats->ibytes += rxq->bytes_recv;
1144 drop_mac += rxq->drop_mac;
1147 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1148 struct mrvl_txq *txq = dev->data->tx_queues[i];
1149 struct pp2_ppio_outq_statistics tx_stats;
1154 idx = txq->queue_id;
1155 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1157 "tx queue %d stats out of range (0 - %d)\n",
1158 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1161 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1163 if (unlikely(ret)) {
1165 "Failed to update tx queue %d stats\n", idx);
1169 stats->q_opackets[idx] = tx_stats.deq_desc;
1170 stats->q_obytes[idx] = txq->bytes_sent;
1171 stats->obytes += txq->bytes_sent;
1174 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1175 if (unlikely(ret)) {
1176 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
1180 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1181 stats->opackets += ppio_stats.tx_packets;
1182 stats->imissed += ppio_stats.rx_fullq_dropped +
1183 ppio_stats.rx_bm_dropped +
1184 ppio_stats.rx_early_dropped +
1185 ppio_stats.rx_fifo_dropped +
1186 ppio_stats.rx_cls_dropped;
1187 stats->ierrors = drop_mac;
1193 * DPDK callback to clear device statistics.
1196 * Pointer to Ethernet device structure.
1199 mrvl_stats_reset(struct rte_eth_dev *dev)
1201 struct mrvl_priv *priv = dev->data->dev_private;
1207 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1208 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1210 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1211 priv->rxq_map[i].inq, NULL, 1);
1212 rxq->bytes_recv = 0;
1216 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1217 struct mrvl_txq *txq = dev->data->tx_queues[i];
1219 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1220 txq->bytes_sent = 0;
1223 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1227 * DPDK callback to get extended statistics.
1230 * Pointer to Ethernet device structure.
1232 * Pointer to xstats table.
1234 * Number of entries in xstats table.
1236 * Negative value on error, number of read xstats otherwise.
1239 mrvl_xstats_get(struct rte_eth_dev *dev,
1240 struct rte_eth_xstat *stats, unsigned int n)
1242 struct mrvl_priv *priv = dev->data->dev_private;
1243 struct pp2_ppio_statistics ppio_stats;
1249 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1250 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1253 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1254 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1255 mrvl_xstats_tbl[i].offset);
1256 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1257 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1258 mrvl_xstats_tbl[i].offset);
1263 stats[i].value = val;
1270 * DPDK callback to reset extended statistics.
1273 * Pointer to Ethernet device structure.
1276 mrvl_xstats_reset(struct rte_eth_dev *dev)
1278 mrvl_stats_reset(dev);
1282 * DPDK callback to get extended statistics names.
1284 * @param dev (unused)
1285 * Pointer to Ethernet device structure.
1286 * @param xstats_names
1287 * Pointer to xstats names table.
1289 * Size of the xstats names table.
1291 * Number of read names.
1294 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1295 struct rte_eth_xstat_name *xstats_names,
1301 return RTE_DIM(mrvl_xstats_tbl);
1303 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1304 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s",
1305 mrvl_xstats_tbl[i].name);
1311 * DPDK callback to get information about the device.
1314 * Pointer to Ethernet device structure (unused).
1316 * Info structure output buffer.
1319 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1320 struct rte_eth_dev_info *info)
1322 info->speed_capa = ETH_LINK_SPEED_10M |
1323 ETH_LINK_SPEED_100M |
1327 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1328 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1329 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1331 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1332 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1333 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1335 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1336 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1337 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1339 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1340 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1342 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1343 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1345 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1346 ETH_RSS_NONFRAG_IPV4_TCP |
1347 ETH_RSS_NONFRAG_IPV4_UDP;
1349 /* By default packets are dropped if no descriptors are available */
1350 info->default_rxconf.rx_drop_en = 1;
1351 info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
1353 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1357 * Return supported packet types.
1360 * Pointer to Ethernet device structure (unused).
1363 * Const pointer to the table with supported packet types.
1365 static const uint32_t *
1366 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1368 static const uint32_t ptypes[] = {
1371 RTE_PTYPE_L3_IPV4_EXT,
1372 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1374 RTE_PTYPE_L3_IPV6_EXT,
1375 RTE_PTYPE_L2_ETHER_ARP,
1384 * DPDK callback to get information about specific receive queue.
1387 * Pointer to Ethernet device structure.
1388 * @param rx_queue_id
1389 * Receive queue index.
1391 * Receive queue information structure.
1393 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1394 struct rte_eth_rxq_info *qinfo)
1396 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1397 struct mrvl_priv *priv = dev->data->dev_private;
1398 int inq = priv->rxq_map[rx_queue_id].inq;
1399 int tc = priv->rxq_map[rx_queue_id].tc;
1400 struct pp2_ppio_tc_params *tc_params =
1401 &priv->ppio_params.inqs_params.tcs_params[tc];
1404 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1408 * DPDK callback to get information about specific transmit queue.
1411 * Pointer to Ethernet device structure.
1412 * @param tx_queue_id
1413 * Transmit queue index.
1415 * Transmit queue information structure.
1417 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1418 struct rte_eth_txq_info *qinfo)
1420 struct mrvl_priv *priv = dev->data->dev_private;
1421 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1424 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1425 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1429 * DPDK callback to Configure a VLAN filter.
1432 * Pointer to Ethernet device structure.
1434 * VLAN ID to filter.
1439 * 0 on success, negative error value otherwise.
1442 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1444 struct mrvl_priv *priv = dev->data->dev_private;
1452 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1453 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1457 * Release buffers to hardware bpool (buffer-pool)
1460 * Receive queue pointer.
1462 * Number of buffers to release to bpool.
1465 * 0 on success, negative error value otherwise.
1468 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1470 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1471 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1473 unsigned int core_id;
1474 struct pp2_hif *hif;
1475 struct pp2_bpool *bpool;
1477 core_id = rte_lcore_id();
1478 if (core_id == LCORE_ID_ANY)
1481 hif = mrvl_get_hif(rxq->priv, core_id);
1485 bpool = rxq->priv->bpool;
1487 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1491 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1493 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1495 for (i = 0; i < num; i++) {
1496 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1497 != cookie_addr_high) {
1499 "mbuf virtual addr high 0x%lx out of range\n",
1500 (uint64_t)mbufs[i] >> 32);
1504 entries[i].buff.addr =
1505 rte_mbuf_data_iova_default(mbufs[i]);
1506 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1507 entries[i].bpool = bpool;
1510 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1511 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1518 for (; i < num; i++)
1519 rte_pktmbuf_free(mbufs[i]);
1525 * Check whether requested rx queue offloads match port offloads.
1528 * dev Pointer to the device.
1530 * requested Bitmap of the requested offloads.
1533 * 1 if requested offloads are okay, 0 otherwise.
1536 mrvl_rx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
1538 uint64_t mandatory = dev->data->dev_conf.rxmode.offloads;
1539 uint64_t supported = MRVL_RX_OFFLOADS;
1540 uint64_t unsupported = requested & ~supported;
1541 uint64_t missing = mandatory & ~requested;
1544 RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. "
1545 "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
1546 requested, supported);
1551 RTE_LOG(ERR, PMD, "Some Rx offloads are missing. "
1552 "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
1553 requested, missing);
1561 * DPDK callback to configure the receive queue.
1564 * Pointer to Ethernet device structure.
1568 * Number of descriptors to configure in queue.
1570 * NUMA socket on which memory must be allocated.
1572 * Thresholds parameters.
1574 * Memory pool for buffer allocations.
1577 * 0 on success, negative error value otherwise.
1580 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1581 unsigned int socket,
1582 const struct rte_eth_rxconf *conf,
1583 struct rte_mempool *mp)
1585 struct mrvl_priv *priv = dev->data->dev_private;
1586 struct mrvl_rxq *rxq;
1588 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1591 if (!mrvl_rx_queue_offloads_okay(dev, conf->offloads))
1594 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1596 * Unknown TC mapping, mapping will not have a correct queue.
1598 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1599 idx, priv->ppio_id);
1603 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1604 MRVL_PKT_EFFEC_OFFS;
1605 if (min_size < max_rx_pkt_len) {
1607 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1608 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1609 MRVL_PKT_EFFEC_OFFS,
1614 if (dev->data->rx_queues[idx]) {
1615 rte_free(dev->data->rx_queues[idx]);
1616 dev->data->rx_queues[idx] = NULL;
1619 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1625 rxq->cksum_enabled =
1626 dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1627 rxq->queue_id = idx;
1628 rxq->port_id = dev->data->port_id;
1629 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1631 tc = priv->rxq_map[rxq->queue_id].tc,
1632 inq = priv->rxq_map[rxq->queue_id].inq;
1633 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1636 ret = mrvl_fill_bpool(rxq, desc);
1642 priv->bpool_init_size += desc;
1644 dev->data->rx_queues[idx] = rxq;
1650 * DPDK callback to release the receive queue.
1653 * Generic receive queue pointer.
1656 mrvl_rx_queue_release(void *rxq)
1658 struct mrvl_rxq *q = rxq;
1659 struct pp2_ppio_tc_params *tc_params;
1660 int i, num, tc, inq;
1661 struct pp2_hif *hif;
1662 unsigned int core_id = rte_lcore_id();
1664 if (core_id == LCORE_ID_ANY)
1667 hif = mrvl_get_hif(q->priv, core_id);
1672 tc = q->priv->rxq_map[q->queue_id].tc;
1673 inq = q->priv->rxq_map[q->queue_id].inq;
1674 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1675 num = tc_params->inqs_params[inq].size;
1676 for (i = 0; i < num; i++) {
1677 struct pp2_buff_inf inf;
1680 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1681 addr = cookie_addr_high | inf.cookie;
1682 rte_pktmbuf_free((struct rte_mbuf *)addr);
1689 * Check whether requested tx queue offloads match port offloads.
1692 * dev Pointer to the device.
1694 * requested Bitmap of the requested offloads.
1697 * 1 if requested offloads are okay, 0 otherwise.
1700 mrvl_tx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
1702 uint64_t mandatory = dev->data->dev_conf.txmode.offloads;
1703 uint64_t supported = MRVL_TX_OFFLOADS;
1704 uint64_t unsupported = requested & ~supported;
1705 uint64_t missing = mandatory & ~requested;
1708 RTE_LOG(ERR, PMD, "Some Tx offloads are not supported. "
1709 "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
1710 requested, supported);
1715 RTE_LOG(ERR, PMD, "Some Tx offloads are missing. "
1716 "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
1717 requested, missing);
1725 * DPDK callback to configure the transmit queue.
1728 * Pointer to Ethernet device structure.
1730 * Transmit queue index.
1732 * Number of descriptors to configure in the queue.
1734 * NUMA socket on which memory must be allocated.
1736 * Tx queue configuration parameters.
1739 * 0 on success, negative error value otherwise.
1742 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1743 unsigned int socket,
1744 const struct rte_eth_txconf *conf)
1746 struct mrvl_priv *priv = dev->data->dev_private;
1747 struct mrvl_txq *txq;
1749 if (!mrvl_tx_queue_offloads_okay(dev, conf->offloads))
1752 if (dev->data->tx_queues[idx]) {
1753 rte_free(dev->data->tx_queues[idx]);
1754 dev->data->tx_queues[idx] = NULL;
1757 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1762 txq->queue_id = idx;
1763 txq->port_id = dev->data->port_id;
1764 txq->tx_deferred_start = conf->tx_deferred_start;
1765 dev->data->tx_queues[idx] = txq;
1767 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1773 * DPDK callback to release the transmit queue.
1776 * Generic transmit queue pointer.
1779 mrvl_tx_queue_release(void *txq)
1781 struct mrvl_txq *q = txq;
1790 * DPDK callback to get flow control configuration.
1793 * Pointer to Ethernet device structure.
1795 * Pointer to the flow control configuration.
1798 * 0 on success, negative error value otherwise.
1801 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1803 struct mrvl_priv *priv = dev->data->dev_private;
1809 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1811 RTE_LOG(ERR, PMD, "Failed to read rx pause state\n");
1815 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1821 * DPDK callback to set flow control configuration.
1824 * Pointer to Ethernet device structure.
1826 * Pointer to the flow control configuration.
1829 * 0 on success, negative error value otherwise.
1832 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1834 struct mrvl_priv *priv = dev->data->dev_private;
1839 if (fc_conf->high_water ||
1840 fc_conf->low_water ||
1841 fc_conf->pause_time ||
1842 fc_conf->mac_ctrl_frame_fwd ||
1844 RTE_LOG(ERR, PMD, "Flowctrl parameter is not supported\n");
1849 if (fc_conf->mode == RTE_FC_NONE ||
1850 fc_conf->mode == RTE_FC_RX_PAUSE) {
1853 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1854 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1857 "Failed to change flowctrl on RX side\n");
1866 * Update RSS hash configuration
1869 * Pointer to Ethernet device structure.
1871 * Pointer to RSS configuration.
1874 * 0 on success, negative error value otherwise.
1877 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1878 struct rte_eth_rss_conf *rss_conf)
1880 struct mrvl_priv *priv = dev->data->dev_private;
1885 return mrvl_configure_rss(priv, rss_conf);
1889 * DPDK callback to get RSS hash configuration.
1892 * Pointer to Ethernet device structure.
1894 * Pointer to RSS configuration.
1900 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1901 struct rte_eth_rss_conf *rss_conf)
1903 struct mrvl_priv *priv = dev->data->dev_private;
1904 enum pp2_ppio_hash_type hash_type =
1905 priv->ppio_params.inqs_params.hash_type;
1907 rss_conf->rss_key = NULL;
1909 if (hash_type == PP2_PPIO_HASH_T_NONE)
1910 rss_conf->rss_hf = 0;
1911 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1912 rss_conf->rss_hf = ETH_RSS_IPV4;
1913 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1914 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1915 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1916 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1922 * DPDK callback to get rte_flow callbacks.
1925 * Pointer to the device structure.
1929 * Flow filter operation.
1931 * Pointer to pass the flow ops.
1934 * 0 on success, negative error value otherwise.
1937 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1938 enum rte_filter_type filter_type,
1939 enum rte_filter_op filter_op, void *arg)
1941 switch (filter_type) {
1942 case RTE_ETH_FILTER_GENERIC:
1943 if (filter_op != RTE_ETH_FILTER_GET)
1945 *(const void **)arg = &mrvl_flow_ops;
1948 RTE_LOG(WARNING, PMD, "Filter type (%d) not supported",
1954 static const struct eth_dev_ops mrvl_ops = {
1955 .dev_configure = mrvl_dev_configure,
1956 .dev_start = mrvl_dev_start,
1957 .dev_stop = mrvl_dev_stop,
1958 .dev_set_link_up = mrvl_dev_set_link_up,
1959 .dev_set_link_down = mrvl_dev_set_link_down,
1960 .dev_close = mrvl_dev_close,
1961 .link_update = mrvl_link_update,
1962 .promiscuous_enable = mrvl_promiscuous_enable,
1963 .allmulticast_enable = mrvl_allmulticast_enable,
1964 .promiscuous_disable = mrvl_promiscuous_disable,
1965 .allmulticast_disable = mrvl_allmulticast_disable,
1966 .mac_addr_remove = mrvl_mac_addr_remove,
1967 .mac_addr_add = mrvl_mac_addr_add,
1968 .mac_addr_set = mrvl_mac_addr_set,
1969 .mtu_set = mrvl_mtu_set,
1970 .stats_get = mrvl_stats_get,
1971 .stats_reset = mrvl_stats_reset,
1972 .xstats_get = mrvl_xstats_get,
1973 .xstats_reset = mrvl_xstats_reset,
1974 .xstats_get_names = mrvl_xstats_get_names,
1975 .dev_infos_get = mrvl_dev_infos_get,
1976 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1977 .rxq_info_get = mrvl_rxq_info_get,
1978 .txq_info_get = mrvl_txq_info_get,
1979 .vlan_filter_set = mrvl_vlan_filter_set,
1980 .tx_queue_start = mrvl_tx_queue_start,
1981 .tx_queue_stop = mrvl_tx_queue_stop,
1982 .rx_queue_setup = mrvl_rx_queue_setup,
1983 .rx_queue_release = mrvl_rx_queue_release,
1984 .tx_queue_setup = mrvl_tx_queue_setup,
1985 .tx_queue_release = mrvl_tx_queue_release,
1986 .flow_ctrl_get = mrvl_flow_ctrl_get,
1987 .flow_ctrl_set = mrvl_flow_ctrl_set,
1988 .rss_hash_update = mrvl_rss_hash_update,
1989 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1990 .filter_ctrl = mrvl_eth_filter_ctrl,
1994 * Return packet type information and l3/l4 offsets.
1997 * Pointer to the received packet descriptor.
2004 * Packet type information.
2006 static inline uint64_t
2007 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2008 uint8_t *l3_offset, uint8_t *l4_offset)
2010 enum pp2_inq_l3_type l3_type;
2011 enum pp2_inq_l4_type l4_type;
2012 uint64_t packet_type;
2014 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2015 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2017 packet_type = RTE_PTYPE_L2_ETHER;
2020 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2021 packet_type |= RTE_PTYPE_L3_IPV4;
2023 case PP2_INQ_L3_TYPE_IPV4_OK:
2024 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2026 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2027 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2029 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2030 packet_type |= RTE_PTYPE_L3_IPV6;
2032 case PP2_INQ_L3_TYPE_IPV6_EXT:
2033 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2035 case PP2_INQ_L3_TYPE_ARP:
2036 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2038 * In case of ARP l4_offset is set to wrong value.
2039 * Set it to proper one so that later on mbuf->l3_len can be
2040 * calculated subtracting l4_offset and l3_offset.
2042 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2045 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
2050 case PP2_INQ_L4_TYPE_TCP:
2051 packet_type |= RTE_PTYPE_L4_TCP;
2053 case PP2_INQ_L4_TYPE_UDP:
2054 packet_type |= RTE_PTYPE_L4_UDP;
2057 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
2065 * Get offload information from the received packet descriptor.
2068 * Pointer to the received packet descriptor.
2071 * Mbuf offload flags.
2073 static inline uint64_t
2074 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
2077 enum pp2_inq_desc_status status;
2079 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2080 if (unlikely(status != PP2_DESC_ERR_OK))
2081 flags = PKT_RX_IP_CKSUM_BAD;
2083 flags = PKT_RX_IP_CKSUM_GOOD;
2085 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2086 if (unlikely(status != PP2_DESC_ERR_OK))
2087 flags |= PKT_RX_L4_CKSUM_BAD;
2089 flags |= PKT_RX_L4_CKSUM_GOOD;
2095 * DPDK callback for receive.
2098 * Generic pointer to the receive queue.
2100 * Array to store received packets.
2102 * Maximum number of packets in array.
2105 * Number of packets successfully received.
2108 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2110 struct mrvl_rxq *q = rxq;
2111 struct pp2_ppio_desc descs[nb_pkts];
2112 struct pp2_bpool *bpool;
2113 int i, ret, rx_done = 0;
2115 struct pp2_hif *hif;
2116 unsigned int core_id = rte_lcore_id();
2118 hif = mrvl_get_hif(q->priv, core_id);
2120 if (unlikely(!q->priv->ppio || !hif))
2123 bpool = q->priv->bpool;
2125 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2126 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2127 if (unlikely(ret < 0)) {
2128 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
2131 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2133 for (i = 0; i < nb_pkts; i++) {
2134 struct rte_mbuf *mbuf;
2135 uint8_t l3_offset, l4_offset;
2136 enum pp2_inq_desc_status status;
2139 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2140 struct pp2_ppio_desc *pref_desc;
2143 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2144 pref_addr = cookie_addr_high |
2145 pp2_ppio_inq_desc_get_cookie(pref_desc);
2146 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2147 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2150 addr = cookie_addr_high |
2151 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2152 mbuf = (struct rte_mbuf *)addr;
2153 rte_pktmbuf_reset(mbuf);
2155 /* drop packet in case of mac, overrun or resource error */
2156 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2157 if (unlikely(status != PP2_DESC_ERR_OK)) {
2158 struct pp2_buff_inf binf = {
2159 .addr = rte_mbuf_data_iova_default(mbuf),
2160 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
2163 pp2_bpool_put_buff(hif, bpool, &binf);
2164 mrvl_port_bpool_size
2165 [bpool->pp2_id][bpool->id][core_id]++;
2170 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2171 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2172 mbuf->data_len = mbuf->pkt_len;
2173 mbuf->port = q->port_id;
2175 mrvl_desc_to_packet_type_and_offset(&descs[i],
2178 mbuf->l2_len = l3_offset;
2179 mbuf->l3_len = l4_offset - l3_offset;
2181 if (likely(q->cksum_enabled))
2182 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2184 rx_pkts[rx_done++] = mbuf;
2185 q->bytes_recv += mbuf->pkt_len;
2188 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2189 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2191 if (unlikely(num <= q->priv->bpool_min_size ||
2192 (!rx_done && num < q->priv->bpool_init_size))) {
2193 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2195 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
2196 } else if (unlikely(num > q->priv->bpool_max_size)) {
2198 int pkt_to_remove = num - q->priv->bpool_init_size;
2199 struct rte_mbuf *mbuf;
2200 struct pp2_buff_inf buff;
2203 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
2204 bpool->pp2_id, q->priv->ppio->port_id,
2205 bpool->id, pkt_to_remove, num,
2206 q->priv->bpool_init_size);
2208 for (i = 0; i < pkt_to_remove; i++) {
2209 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2212 mbuf = (struct rte_mbuf *)
2213 (cookie_addr_high | buff.cookie);
2214 rte_pktmbuf_free(mbuf);
2216 mrvl_port_bpool_size
2217 [bpool->pp2_id][bpool->id][core_id] -= i;
2219 rte_spinlock_unlock(&q->priv->lock);
2226 * Prepare offload information.
2230 * @param packet_type
2231 * Packet type bitfield.
2233 * Pointer to the pp2_ouq_l3_type structure.
2235 * Pointer to the pp2_outq_l4_type structure.
2236 * @param gen_l3_cksum
2237 * Will be set to 1 in case l3 checksum is computed.
2239 * Will be set to 1 in case l4 checksum is computed.
2242 * 0 on success, negative error value otherwise.
2245 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2246 enum pp2_outq_l3_type *l3_type,
2247 enum pp2_outq_l4_type *l4_type,
2252 * Based on ol_flags prepare information
2253 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2256 if (ol_flags & PKT_TX_IPV4) {
2257 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2258 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2259 } else if (ol_flags & PKT_TX_IPV6) {
2260 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2261 /* no checksum for ipv6 header */
2264 /* if something different then stop processing */
2268 ol_flags &= PKT_TX_L4_MASK;
2269 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2270 ol_flags == PKT_TX_TCP_CKSUM) {
2271 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2273 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2274 ol_flags == PKT_TX_UDP_CKSUM) {
2275 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2278 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2279 /* no checksum for other type */
2287 * Release already sent buffers to bpool (buffer-pool).
2290 * Pointer to the port structure.
2292 * Pointer to the MUSDK hardware interface.
2294 * Pointer to the shadow queue.
2298 * Force releasing packets.
2301 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2302 unsigned int core_id, struct mrvl_shadow_txq *sq,
2305 struct buff_release_entry *entry;
2306 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2309 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2311 sq->num_to_release += nb_done;
2313 if (likely(!force &&
2314 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2317 nb_done = sq->num_to_release;
2318 sq->num_to_release = 0;
2320 for (i = 0; i < nb_done; i++) {
2321 entry = &sq->ent[sq->tail + num];
2322 if (unlikely(!entry->buff.addr)) {
2324 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
2325 sq->tail, (u64)entry->buff.cookie,
2326 (u64)entry->buff.addr);
2331 if (unlikely(!entry->bpool)) {
2332 struct rte_mbuf *mbuf;
2334 mbuf = (struct rte_mbuf *)
2335 (cookie_addr_high | entry->buff.cookie);
2336 rte_pktmbuf_free(mbuf);
2341 mrvl_port_bpool_size
2342 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2344 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2349 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2351 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2358 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2359 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2365 * DPDK callback for transmit.
2368 * Generic pointer transmit queue.
2370 * Packets to transmit.
2372 * Number of packets in array.
2375 * Number of packets successfully transmitted.
2378 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2380 struct mrvl_txq *q = txq;
2381 struct mrvl_shadow_txq *sq;
2382 struct pp2_hif *hif;
2383 struct pp2_ppio_desc descs[nb_pkts];
2384 unsigned int core_id = rte_lcore_id();
2385 int i, ret, bytes_sent = 0;
2386 uint16_t num, sq_free_size;
2389 hif = mrvl_get_hif(q->priv, core_id);
2390 sq = &q->shadow_txqs[core_id];
2392 if (unlikely(!q->priv->ppio || !hif))
2396 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2397 sq, q->queue_id, 0);
2399 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2400 if (unlikely(nb_pkts > sq_free_size)) {
2402 "No room in shadow queue for %d packets! %d packets will be sent.\n",
2403 nb_pkts, sq_free_size);
2404 nb_pkts = sq_free_size;
2407 for (i = 0; i < nb_pkts; i++) {
2408 struct rte_mbuf *mbuf = tx_pkts[i];
2409 int gen_l3_cksum, gen_l4_cksum;
2410 enum pp2_outq_l3_type l3_type;
2411 enum pp2_outq_l4_type l4_type;
2413 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2414 struct rte_mbuf *pref_pkt_hdr;
2416 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2417 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2418 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2421 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2422 sq->ent[sq->head].buff.addr =
2423 rte_mbuf_data_iova_default(mbuf);
2424 sq->ent[sq->head].bpool =
2425 (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
2426 mbuf->refcnt > 1)) ? NULL :
2427 mrvl_port_to_bpool_lookup[mbuf->port];
2428 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2431 pp2_ppio_outq_desc_reset(&descs[i]);
2432 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2433 rte_pktmbuf_iova(mbuf));
2434 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2435 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2436 rte_pktmbuf_pkt_len(mbuf));
2438 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2440 * in case unsupported ol_flags were passed
2441 * do not update descriptor offload information
2443 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2444 &l3_type, &l4_type, &gen_l3_cksum,
2449 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2451 mbuf->l2_len + mbuf->l3_len,
2452 gen_l3_cksum, gen_l4_cksum);
2456 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2457 /* number of packets that were not sent */
2458 if (unlikely(num > nb_pkts)) {
2459 for (i = nb_pkts; i < num; i++) {
2460 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2461 MRVL_PP2_TX_SHADOWQ_MASK;
2462 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2464 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2466 sq->size -= num - nb_pkts;
2469 q->bytes_sent += bytes_sent;
2475 * Initialize packet processor.
2478 * 0 on success, negative error value otherwise.
2483 struct pp2_init_params init_params;
2485 memset(&init_params, 0, sizeof(init_params));
2486 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2487 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2488 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2490 return pp2_init(&init_params);
2494 * Deinitialize packet processor.
2497 * 0 on success, negative error value otherwise.
2500 mrvl_deinit_pp2(void)
2506 * Create private device structure.
2509 * Pointer to the port name passed in the initialization parameters.
2512 * Pointer to the newly allocated private device structure.
2514 static struct mrvl_priv *
2515 mrvl_priv_create(const char *dev_name)
2517 struct pp2_bpool_params bpool_params;
2518 char match[MRVL_MATCH_LEN];
2519 struct mrvl_priv *priv;
2522 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2526 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2527 &priv->pp_id, &priv->ppio_id);
2531 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2532 PP2_BPOOL_NUM_POOLS);
2535 priv->bpool_bit = bpool_bit;
2537 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2539 memset(&bpool_params, 0, sizeof(bpool_params));
2540 bpool_params.match = match;
2541 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2542 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2544 goto out_clear_bpool_bit;
2546 priv->ppio_params.type = PP2_PPIO_T_NIC;
2547 rte_spinlock_init(&priv->lock);
2550 out_clear_bpool_bit:
2551 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2558 * Create device representing Ethernet port.
2561 * Pointer to the port's name.
2564 * 0 on success, negative error value otherwise.
2567 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2569 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2570 struct rte_eth_dev *eth_dev;
2571 struct mrvl_priv *priv;
2574 eth_dev = rte_eth_dev_allocate(name);
2578 priv = mrvl_priv_create(name);
2584 eth_dev->data->mac_addrs =
2585 rte_zmalloc("mac_addrs",
2586 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2587 if (!eth_dev->data->mac_addrs) {
2588 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2593 memset(&req, 0, sizeof(req));
2594 strcpy(req.ifr_name, name);
2595 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2599 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2600 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2602 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2603 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2604 eth_dev->data->kdrv = RTE_KDRV_NONE;
2605 eth_dev->data->dev_private = priv;
2606 eth_dev->device = &vdev->device;
2607 eth_dev->dev_ops = &mrvl_ops;
2611 rte_free(eth_dev->data->mac_addrs);
2613 rte_eth_dev_release_port(eth_dev);
2621 * Cleanup previously created device representing Ethernet port.
2624 * Pointer to the port name.
2627 mrvl_eth_dev_destroy(const char *name)
2629 struct rte_eth_dev *eth_dev;
2630 struct mrvl_priv *priv;
2632 eth_dev = rte_eth_dev_allocated(name);
2636 priv = eth_dev->data->dev_private;
2637 pp2_bpool_deinit(priv->bpool);
2638 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2640 rte_free(eth_dev->data->mac_addrs);
2641 rte_eth_dev_release_port(eth_dev);
2645 * Callback used by rte_kvargs_process() during argument parsing.
2648 * Pointer to the parsed key (unused).
2650 * Pointer to the parsed value.
2652 * Pointer to the extra arguments which contains address of the
2653 * table of pointers to parsed interface names.
2659 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2662 struct mrvl_ifnames *ifnames = extra_args;
2664 ifnames->names[ifnames->idx++] = value;
2670 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2673 mrvl_deinit_hifs(void)
2677 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2679 pp2_hif_deinit(hifs[i]);
2681 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2682 memset(hifs, 0, sizeof(hifs));
2686 * DPDK callback to register the virtual device.
2689 * Pointer to the virtual device.
2692 * 0 on success, negative error value otherwise.
2695 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2697 struct rte_kvargs *kvlist;
2698 struct mrvl_ifnames ifnames;
2700 uint32_t i, ifnum, cfgnum;
2703 params = rte_vdev_device_args(vdev);
2707 kvlist = rte_kvargs_parse(params, valid_args);
2711 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2712 if (ifnum > RTE_DIM(ifnames.names))
2713 goto out_free_kvlist;
2716 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2717 mrvl_get_ifnames, &ifnames);
2721 * The below system initialization should be done only once,
2722 * on the first provided configuration file
2724 if (!mrvl_qos_cfg) {
2725 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2726 RTE_LOG(INFO, PMD, "Parsing config file!\n");
2728 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2729 goto out_free_kvlist;
2730 } else if (cfgnum == 1) {
2731 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2732 mrvl_get_qoscfg, &mrvl_qos_cfg);
2739 RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n");
2741 * ret == -EEXIST is correct, it means DMA
2742 * has been already initialized (by another PMD).
2744 ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2747 goto out_free_kvlist;
2750 "DMA memory has been already initialized by a different driver.\n");
2753 ret = mrvl_init_pp2();
2755 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2756 goto out_deinit_dma;
2759 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2760 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2762 mrvl_lcore_first = RTE_MAX_LCORE;
2763 mrvl_lcore_last = 0;
2766 for (i = 0; i < ifnum; i++) {
2767 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]);
2768 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2772 mrvl_dev_num += ifnum;
2774 rte_kvargs_free(kvlist);
2779 mrvl_eth_dev_destroy(ifnames.names[i]);
2781 if (mrvl_dev_num == 0)
2784 if (mrvl_dev_num == 0)
2785 mv_sys_dma_mem_destroy();
2787 rte_kvargs_free(kvlist);
2793 * DPDK callback to remove virtual device.
2796 * Pointer to the removed virtual device.
2799 * 0 on success, negative error value otherwise.
2802 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2807 name = rte_vdev_device_name(vdev);
2811 RTE_LOG(INFO, PMD, "Removing %s\n", name);
2813 RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */
2814 char ifname[RTE_ETH_NAME_MAX_LEN];
2816 rte_eth_dev_get_name_by_port(i, ifname);
2817 mrvl_eth_dev_destroy(ifname);
2821 if (mrvl_dev_num == 0) {
2822 RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n");
2825 mv_sys_dma_mem_destroy();
2831 static struct rte_vdev_driver pmd_mrvl_drv = {
2832 .probe = rte_pmd_mrvl_probe,
2833 .remove = rte_pmd_mrvl_remove,
2836 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
2837 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);