1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_ethdev_driver.h>
8 #include <rte_kvargs.h>
10 #include <rte_malloc.h>
11 #include <rte_bus_vdev.h>
14 #include <linux/ethtool.h>
15 #include <linux/sockios.h>
17 #include <net/if_arp.h>
18 #include <sys/ioctl.h>
19 #include <sys/socket.h>
21 #include <sys/types.h>
23 #include <rte_mvep_common.h>
24 #include "mrvl_ethdev.h"
26 #include "mrvl_flow.h"
30 /* bitmask with reserved hifs */
31 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
32 /* bitmask with reserved bpools */
33 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
34 /* bitmask with reserved kernel RSS tables */
35 #define MRVL_MUSDK_RSS_RESERVED 0x01
36 /* maximum number of available hifs */
37 #define MRVL_MUSDK_HIFS_MAX 9
40 #define MRVL_MUSDK_PREFETCH_SHIFT 2
42 /* TCAM has 25 entries reserved for uc/mc filter entries */
43 #define MRVL_MAC_ADDRS_MAX 25
44 #define MRVL_MATCH_LEN 16
45 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
46 /* Maximum allowable packet size */
47 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
49 #define MRVL_IFACE_NAME_ARG "iface"
50 #define MRVL_CFG_ARG "cfg"
52 #define MRVL_BURST_SIZE 64
54 #define MRVL_ARP_LENGTH 28
56 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
57 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
59 /** Port Rx offload capabilities */
60 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
61 DEV_RX_OFFLOAD_JUMBO_FRAME | \
62 DEV_RX_OFFLOAD_CHECKSUM)
64 /** Port Tx offloads capabilities */
65 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
66 DEV_TX_OFFLOAD_UDP_CKSUM | \
67 DEV_TX_OFFLOAD_TCP_CKSUM | \
68 DEV_TX_OFFLOAD_MULTI_SEGS)
70 static const char * const valid_args[] = {
76 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
77 static struct pp2_hif *hifs[RTE_MAX_LCORE];
78 static int used_bpools[PP2_NUM_PKT_PROC] = {
79 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
82 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
83 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
84 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
89 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
94 * To use buffer harvesting based on loopback port shadow queue structure
95 * was introduced for buffers information bookkeeping.
97 * Before sending the packet, related buffer information (pp2_buff_inf) is
98 * stored in shadow queue. After packet is transmitted no longer used
99 * packet buffer is released back to it's original hardware pool,
100 * on condition it originated from interface.
101 * In case it was generated by application itself i.e: mbuf->port field is
102 * 0xff then its released to software mempool.
104 struct mrvl_shadow_txq {
105 int head; /* write index - used when sending buffers */
106 int tail; /* read index - used when releasing buffers */
107 u16 size; /* queue occupied size */
108 u16 num_to_release; /* number of descriptors sent, that can be
111 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
115 struct mrvl_priv *priv;
116 struct rte_mempool *mp;
125 struct mrvl_priv *priv;
129 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
130 int tx_deferred_start;
133 static int mrvl_lcore_first;
134 static int mrvl_lcore_last;
135 static int mrvl_dev_num;
137 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
138 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
139 struct pp2_hif *hif, unsigned int core_id,
140 struct mrvl_shadow_txq *sq, int qid, int force);
142 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
144 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
148 #define MRVL_XSTATS_TBL_ENTRY(name) { \
149 #name, offsetof(struct pp2_ppio_statistics, name), \
150 sizeof(((struct pp2_ppio_statistics *)0)->name) \
153 /* Table with xstats data */
158 } mrvl_xstats_tbl[] = {
159 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
160 MRVL_XSTATS_TBL_ENTRY(rx_packets),
161 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
162 MRVL_XSTATS_TBL_ENTRY(rx_errors),
163 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
164 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
165 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
166 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
167 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
168 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
169 MRVL_XSTATS_TBL_ENTRY(tx_packets),
170 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
171 MRVL_XSTATS_TBL_ENTRY(tx_errors)
175 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf)
177 sq->ent[sq->head].buff.cookie = (uint64_t)buf;
178 sq->ent[sq->head].buff.addr = buf ?
179 rte_mbuf_data_iova_default(buf) : 0;
181 sq->ent[sq->head].bpool =
182 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS ||
183 buf->refcnt > 1)) ? NULL :
184 mrvl_port_to_bpool_lookup[buf->port];
186 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
191 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf)
193 pp2_ppio_outq_desc_reset(desc);
194 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf));
195 pp2_ppio_outq_desc_set_pkt_offset(desc, 0);
196 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf));
200 mrvl_get_bpool_size(int pp2_id, int pool_id)
205 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
206 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
212 mrvl_reserve_bit(int *bitmap, int max)
214 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
225 mrvl_init_hif(int core_id)
227 struct pp2_hif_params params;
228 char match[MRVL_MATCH_LEN];
231 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
233 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
237 snprintf(match, sizeof(match), "hif-%d", ret);
238 memset(¶ms, 0, sizeof(params));
239 params.match = match;
240 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
241 ret = pp2_hif_init(¶ms, &hifs[core_id]);
243 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
250 static inline struct pp2_hif*
251 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
255 if (likely(hifs[core_id] != NULL))
256 return hifs[core_id];
258 rte_spinlock_lock(&priv->lock);
260 ret = mrvl_init_hif(core_id);
262 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
266 if (core_id < mrvl_lcore_first)
267 mrvl_lcore_first = core_id;
269 if (core_id > mrvl_lcore_last)
270 mrvl_lcore_last = core_id;
272 rte_spinlock_unlock(&priv->lock);
274 return hifs[core_id];
278 * Set tx burst function according to offload flag
281 * Pointer to Ethernet device structure.
284 mrvl_set_tx_function(struct rte_eth_dev *dev)
286 struct mrvl_priv *priv = dev->data->dev_private;
288 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
289 if (priv->multiseg) {
290 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n");
291 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst;
293 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n");
294 dev->tx_pkt_burst = mrvl_tx_pkt_burst;
299 * Configure rss based on dpdk rss configuration.
302 * Pointer to private structure.
304 * Pointer to RSS configuration.
307 * 0 on success, negative error value otherwise.
310 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
312 if (rss_conf->rss_key)
313 MRVL_LOG(WARNING, "Changing hash key is not supported");
315 if (rss_conf->rss_hf == 0) {
316 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
317 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
318 priv->ppio_params.inqs_params.hash_type =
319 PP2_PPIO_HASH_T_2_TUPLE;
320 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
321 priv->ppio_params.inqs_params.hash_type =
322 PP2_PPIO_HASH_T_5_TUPLE;
323 priv->rss_hf_tcp = 1;
324 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
325 priv->ppio_params.inqs_params.hash_type =
326 PP2_PPIO_HASH_T_5_TUPLE;
327 priv->rss_hf_tcp = 0;
336 * Ethernet device configuration.
338 * Prepare the driver for a given number of TX and RX queues and
342 * Pointer to Ethernet device structure.
345 * 0 on success, negative error value otherwise.
348 mrvl_dev_configure(struct rte_eth_dev *dev)
350 struct mrvl_priv *priv = dev->data->dev_private;
354 MRVL_LOG(INFO, "Device reconfiguration is not supported");
358 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
359 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
360 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
361 dev->data->dev_conf.rxmode.mq_mode);
365 if (dev->data->dev_conf.rxmode.split_hdr_size) {
366 MRVL_LOG(INFO, "Split headers not supported");
370 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
371 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
372 MRVL_PP2_ETH_HDRS_LEN;
374 if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
377 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
378 dev->data->nb_rx_queues);
382 ret = mrvl_configure_txqs(priv, dev->data->port_id,
383 dev->data->nb_tx_queues);
387 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
388 priv->ppio_params.maintain_stats = 1;
389 priv->nb_rx_queues = dev->data->nb_rx_queues;
391 ret = mrvl_tm_init(dev);
395 if (dev->data->nb_rx_queues == 1 &&
396 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
397 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
398 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
403 return mrvl_configure_rss(priv,
404 &dev->data->dev_conf.rx_adv_conf.rss_conf);
408 * DPDK callback to change the MTU.
410 * Setting the MTU affects hardware MRU (packets larger than the MRU
414 * Pointer to Ethernet device structure.
419 * 0 on success, negative error value otherwise.
422 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
424 struct mrvl_priv *priv = dev->data->dev_private;
426 uint16_t mbuf_data_size = 0; /* SW buffer size */
429 mru = MRVL_PP2_MTU_TO_MRU(mtu);
431 * min_rx_buf_size is equal to mbuf data size
432 * if pmd didn't set it differently
434 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
436 * - setting mru greater than the mbuf size resulting in
437 * hw and sw buffer size mismatch
438 * - setting mtu that requires the support of scattered packets
439 * when this feature has not been enabled/supported so far
440 * (TODO check scattered_rx flag here once scattered RX is supported).
442 if (mru + MRVL_PKT_OFFS > mbuf_data_size) {
443 mru = mbuf_data_size - MRVL_PKT_OFFS;
444 mtu = MRVL_PP2_MRU_TO_MTU(mru);
445 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted "
446 "by current mbuf size: %u. Set MTU to %u, MRU to %u",
447 mbuf_data_size, mtu, mru);
450 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) {
451 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru);
455 dev->data->mtu = mtu;
456 dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE;
461 ret = pp2_ppio_set_mru(priv->ppio, mru);
463 MRVL_LOG(ERR, "Failed to change MRU");
467 ret = pp2_ppio_set_mtu(priv->ppio, mtu);
469 MRVL_LOG(ERR, "Failed to change MTU");
477 * DPDK callback to bring the link up.
480 * Pointer to Ethernet device structure.
483 * 0 on success, negative error value otherwise.
486 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
488 struct mrvl_priv *priv = dev->data->dev_private;
494 ret = pp2_ppio_enable(priv->ppio);
499 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
500 * as pp2_ppio_enable() changes port->t_mode from default 0 to
501 * PP2_TRAFFIC_INGRESS_EGRESS.
503 * Set mtu to default DPDK value here.
505 ret = mrvl_mtu_set(dev, dev->data->mtu);
507 pp2_ppio_disable(priv->ppio);
513 * DPDK callback to bring the link down.
516 * Pointer to Ethernet device structure.
519 * 0 on success, negative error value otherwise.
522 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
524 struct mrvl_priv *priv = dev->data->dev_private;
529 return pp2_ppio_disable(priv->ppio);
533 * DPDK callback to start tx queue.
536 * Pointer to Ethernet device structure.
538 * Transmit queue index.
541 * 0 on success, negative error value otherwise.
544 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
546 struct mrvl_priv *priv = dev->data->dev_private;
552 /* passing 1 enables given tx queue */
553 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
555 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
559 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
565 * DPDK callback to stop tx queue.
568 * Pointer to Ethernet device structure.
570 * Transmit queue index.
573 * 0 on success, negative error value otherwise.
576 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
578 struct mrvl_priv *priv = dev->data->dev_private;
584 /* passing 0 disables given tx queue */
585 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
587 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
591 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
597 * DPDK callback to start the device.
600 * Pointer to Ethernet device structure.
603 * 0 on success, negative errno value on failure.
606 mrvl_dev_start(struct rte_eth_dev *dev)
608 struct mrvl_priv *priv = dev->data->dev_private;
609 char match[MRVL_MATCH_LEN];
610 int ret = 0, i, def_init_size;
613 return mrvl_dev_set_link_up(dev);
615 snprintf(match, sizeof(match), "ppio-%d:%d",
616 priv->pp_id, priv->ppio_id);
617 priv->ppio_params.match = match;
620 * Calculate the minimum bpool size for refill feature as follows:
621 * 2 default burst sizes multiply by number of rx queues.
622 * If the bpool size will be below this value, new buffers will
623 * be added to the pool.
625 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
627 /* In case initial bpool size configured in queues setup is
628 * smaller than minimum size add more buffers
630 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
631 if (priv->bpool_init_size < def_init_size) {
632 int buffs_to_add = def_init_size - priv->bpool_init_size;
634 priv->bpool_init_size += buffs_to_add;
635 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
637 MRVL_LOG(ERR, "Failed to add buffers to bpool");
641 * Calculate the maximum bpool size for refill feature as follows:
642 * maximum number of descriptors in rx queue multiply by number
643 * of rx queues plus minimum bpool size.
644 * In case the bpool size will exceed this value, superfluous buffers
647 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
648 priv->bpool_min_size;
650 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
652 MRVL_LOG(ERR, "Failed to init ppio");
657 * In case there are some some stale uc/mc mac addresses flush them
658 * here. It cannot be done during mrvl_dev_close() as port information
659 * is already gone at that point (due to pp2_ppio_deinit() in
662 if (!priv->uc_mc_flushed) {
663 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
666 "Failed to flush uc/mc filter list");
669 priv->uc_mc_flushed = 1;
672 if (!priv->vlan_flushed) {
673 ret = pp2_ppio_flush_vlan(priv->ppio);
675 MRVL_LOG(ERR, "Failed to flush vlan list");
678 * once pp2_ppio_flush_vlan() is supported jump to out
682 priv->vlan_flushed = 1;
684 ret = mrvl_mtu_set(dev, dev->data->mtu);
686 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu);
688 /* For default QoS config, don't start classifier. */
690 mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) {
691 ret = mrvl_start_qos_mapping(priv);
693 MRVL_LOG(ERR, "Failed to setup QoS mapping");
698 ret = mrvl_dev_set_link_up(dev);
700 MRVL_LOG(ERR, "Failed to set link up");
704 /* start tx queues */
705 for (i = 0; i < dev->data->nb_tx_queues; i++) {
706 struct mrvl_txq *txq = dev->data->tx_queues[i];
708 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
710 if (!txq->tx_deferred_start)
714 * All txqs are started by default. Stop them
715 * so that tx_deferred_start works as expected.
717 ret = mrvl_tx_queue_stop(dev, i);
724 mrvl_set_tx_function(dev);
728 MRVL_LOG(ERR, "Failed to start device");
729 pp2_ppio_deinit(priv->ppio);
734 * Flush receive queues.
737 * Pointer to Ethernet device structure.
740 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
744 MRVL_LOG(INFO, "Flushing rx queues");
745 for (i = 0; i < dev->data->nb_rx_queues; i++) {
749 struct mrvl_rxq *q = dev->data->rx_queues[i];
750 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
752 num = MRVL_PP2_RXD_MAX;
753 ret = pp2_ppio_recv(q->priv->ppio,
754 q->priv->rxq_map[q->queue_id].tc,
755 q->priv->rxq_map[q->queue_id].inq,
756 descs, (uint16_t *)&num);
757 } while (ret == 0 && num);
762 * Flush transmit shadow queues.
765 * Pointer to Ethernet device structure.
768 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
771 struct mrvl_txq *txq;
773 MRVL_LOG(INFO, "Flushing tx shadow queues");
774 for (i = 0; i < dev->data->nb_tx_queues; i++) {
775 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
777 for (j = 0; j < RTE_MAX_LCORE; j++) {
778 struct mrvl_shadow_txq *sq;
783 sq = &txq->shadow_txqs[j];
784 mrvl_free_sent_buffers(txq->priv->ppio,
785 hifs[j], j, sq, txq->queue_id, 1);
786 while (sq->tail != sq->head) {
787 uint64_t addr = cookie_addr_high |
788 sq->ent[sq->tail].buff.cookie;
790 (struct rte_mbuf *)addr);
791 sq->tail = (sq->tail + 1) &
792 MRVL_PP2_TX_SHADOWQ_MASK;
794 memset(sq, 0, sizeof(*sq));
800 * Flush hardware bpool (buffer-pool).
803 * Pointer to Ethernet device structure.
806 mrvl_flush_bpool(struct rte_eth_dev *dev)
808 struct mrvl_priv *priv = dev->data->dev_private;
812 unsigned int core_id = rte_lcore_id();
814 if (core_id == LCORE_ID_ANY)
817 hif = mrvl_get_hif(priv, core_id);
819 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
821 MRVL_LOG(ERR, "Failed to get bpool buffers number");
826 struct pp2_buff_inf inf;
829 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
833 addr = cookie_addr_high | inf.cookie;
834 rte_pktmbuf_free((struct rte_mbuf *)addr);
839 * DPDK callback to stop the device.
842 * Pointer to Ethernet device structure.
845 mrvl_dev_stop(struct rte_eth_dev *dev)
847 mrvl_dev_set_link_down(dev);
851 * DPDK callback to close the device.
854 * Pointer to Ethernet device structure.
857 mrvl_dev_close(struct rte_eth_dev *dev)
859 struct mrvl_priv *priv = dev->data->dev_private;
862 mrvl_flush_rx_queues(dev);
863 mrvl_flush_tx_shadow_queues(dev);
864 mrvl_flow_deinit(dev);
865 mrvl_mtr_deinit(dev);
867 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
868 struct pp2_ppio_tc_params *tc_params =
869 &priv->ppio_params.inqs_params.tcs_params[i];
871 if (tc_params->inqs_params) {
872 rte_free(tc_params->inqs_params);
873 tc_params->inqs_params = NULL;
878 pp2_cls_tbl_deinit(priv->cls_tbl);
879 priv->cls_tbl = NULL;
883 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
884 priv->qos_tbl = NULL;
887 mrvl_flush_bpool(dev);
891 pp2_ppio_deinit(priv->ppio);
895 /* policer must be released after ppio deinitialization */
896 if (priv->default_policer) {
897 pp2_cls_plcr_deinit(priv->default_policer);
898 priv->default_policer = NULL;
903 * DPDK callback to retrieve physical link information.
906 * Pointer to Ethernet device structure.
907 * @param wait_to_complete
908 * Wait for request completion (ignored).
911 * 0 on success, negative error value otherwise.
914 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
918 * once MUSDK provides necessary API use it here
920 struct mrvl_priv *priv = dev->data->dev_private;
921 struct ethtool_cmd edata;
923 int ret, fd, link_up;
928 edata.cmd = ETHTOOL_GSET;
930 strcpy(req.ifr_name, dev->data->name);
931 req.ifr_data = (void *)&edata;
933 fd = socket(AF_INET, SOCK_DGRAM, 0);
937 ret = ioctl(fd, SIOCETHTOOL, &req);
945 switch (ethtool_cmd_speed(&edata)) {
947 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
950 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
953 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
956 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
959 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
962 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
963 ETH_LINK_HALF_DUPLEX;
964 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
966 pp2_ppio_get_link_state(priv->ppio, &link_up);
967 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
973 * DPDK callback to enable promiscuous mode.
976 * Pointer to Ethernet device structure.
979 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
981 struct mrvl_priv *priv = dev->data->dev_private;
990 ret = pp2_ppio_set_promisc(priv->ppio, 1);
992 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
996 * DPDK callback to enable allmulti mode.
999 * Pointer to Ethernet device structure.
1002 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
1004 struct mrvl_priv *priv = dev->data->dev_private;
1013 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
1015 MRVL_LOG(ERR, "Failed enable all-multicast mode");
1019 * DPDK callback to disable promiscuous mode.
1022 * Pointer to Ethernet device structure.
1025 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
1027 struct mrvl_priv *priv = dev->data->dev_private;
1033 ret = pp2_ppio_set_promisc(priv->ppio, 0);
1035 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
1039 * DPDK callback to disable allmulticast mode.
1042 * Pointer to Ethernet device structure.
1045 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
1047 struct mrvl_priv *priv = dev->data->dev_private;
1053 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
1055 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
1059 * DPDK callback to remove a MAC address.
1062 * Pointer to Ethernet device structure.
1064 * MAC address index.
1067 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
1069 struct mrvl_priv *priv = dev->data->dev_private;
1070 char buf[ETHER_ADDR_FMT_SIZE];
1079 ret = pp2_ppio_remove_mac_addr(priv->ppio,
1080 dev->data->mac_addrs[index].addr_bytes);
1082 ether_format_addr(buf, sizeof(buf),
1083 &dev->data->mac_addrs[index]);
1084 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
1089 * DPDK callback to add a MAC address.
1092 * Pointer to Ethernet device structure.
1094 * MAC address to register.
1096 * MAC address index.
1098 * VMDq pool index to associate address with (unused).
1101 * 0 on success, negative error value otherwise.
1104 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1105 uint32_t index, uint32_t vmdq __rte_unused)
1107 struct mrvl_priv *priv = dev->data->dev_private;
1108 char buf[ETHER_ADDR_FMT_SIZE];
1115 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1122 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1123 * parameter uc_filter_max. Maximum number of mc addresses is then
1124 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1127 * If more than uc_filter_max uc addresses were added to filter list
1128 * then NIC will switch to promiscuous mode automatically.
1130 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1131 * were added to filter list then NIC will switch to all-multicast mode
1134 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1136 ether_format_addr(buf, sizeof(buf), mac_addr);
1137 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1145 * DPDK callback to set the primary MAC address.
1148 * Pointer to Ethernet device structure.
1150 * MAC address to register.
1153 * 0 on success, negative error value otherwise.
1156 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1158 struct mrvl_priv *priv = dev->data->dev_private;
1167 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1169 char buf[ETHER_ADDR_FMT_SIZE];
1170 ether_format_addr(buf, sizeof(buf), mac_addr);
1171 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1178 * DPDK callback to get device statistics.
1181 * Pointer to Ethernet device structure.
1183 * Stats structure output buffer.
1186 * 0 on success, negative error value otherwise.
1189 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1191 struct mrvl_priv *priv = dev->data->dev_private;
1192 struct pp2_ppio_statistics ppio_stats;
1193 uint64_t drop_mac = 0;
1194 unsigned int i, idx, ret;
1199 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1200 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1201 struct pp2_ppio_inq_statistics rx_stats;
1206 idx = rxq->queue_id;
1207 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1209 "rx queue %d stats out of range (0 - %d)",
1210 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1214 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1215 priv->rxq_map[idx].tc,
1216 priv->rxq_map[idx].inq,
1218 if (unlikely(ret)) {
1220 "Failed to update rx queue %d stats", idx);
1224 stats->q_ibytes[idx] = rxq->bytes_recv;
1225 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1226 stats->q_errors[idx] = rx_stats.drop_early +
1227 rx_stats.drop_fullq +
1230 stats->ibytes += rxq->bytes_recv;
1231 drop_mac += rxq->drop_mac;
1234 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1235 struct mrvl_txq *txq = dev->data->tx_queues[i];
1236 struct pp2_ppio_outq_statistics tx_stats;
1241 idx = txq->queue_id;
1242 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1244 "tx queue %d stats out of range (0 - %d)",
1245 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1248 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1250 if (unlikely(ret)) {
1252 "Failed to update tx queue %d stats", idx);
1256 stats->q_opackets[idx] = tx_stats.deq_desc;
1257 stats->q_obytes[idx] = txq->bytes_sent;
1258 stats->obytes += txq->bytes_sent;
1261 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1262 if (unlikely(ret)) {
1263 MRVL_LOG(ERR, "Failed to update port statistics");
1267 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1268 stats->opackets += ppio_stats.tx_packets;
1269 stats->imissed += ppio_stats.rx_fullq_dropped +
1270 ppio_stats.rx_bm_dropped +
1271 ppio_stats.rx_early_dropped +
1272 ppio_stats.rx_fifo_dropped +
1273 ppio_stats.rx_cls_dropped;
1274 stats->ierrors = drop_mac;
1280 * DPDK callback to clear device statistics.
1283 * Pointer to Ethernet device structure.
1286 mrvl_stats_reset(struct rte_eth_dev *dev)
1288 struct mrvl_priv *priv = dev->data->dev_private;
1294 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1295 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1297 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1298 priv->rxq_map[i].inq, NULL, 1);
1299 rxq->bytes_recv = 0;
1303 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1304 struct mrvl_txq *txq = dev->data->tx_queues[i];
1306 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1307 txq->bytes_sent = 0;
1310 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1314 * DPDK callback to get extended statistics.
1317 * Pointer to Ethernet device structure.
1319 * Pointer to xstats table.
1321 * Number of entries in xstats table.
1323 * Negative value on error, number of read xstats otherwise.
1326 mrvl_xstats_get(struct rte_eth_dev *dev,
1327 struct rte_eth_xstat *stats, unsigned int n)
1329 struct mrvl_priv *priv = dev->data->dev_private;
1330 struct pp2_ppio_statistics ppio_stats;
1336 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1337 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1340 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1341 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1342 mrvl_xstats_tbl[i].offset);
1343 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1344 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1345 mrvl_xstats_tbl[i].offset);
1350 stats[i].value = val;
1357 * DPDK callback to reset extended statistics.
1360 * Pointer to Ethernet device structure.
1363 mrvl_xstats_reset(struct rte_eth_dev *dev)
1365 mrvl_stats_reset(dev);
1369 * DPDK callback to get extended statistics names.
1371 * @param dev (unused)
1372 * Pointer to Ethernet device structure.
1373 * @param xstats_names
1374 * Pointer to xstats names table.
1376 * Size of the xstats names table.
1378 * Number of read names.
1381 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1382 struct rte_eth_xstat_name *xstats_names,
1388 return RTE_DIM(mrvl_xstats_tbl);
1390 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1391 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s",
1392 mrvl_xstats_tbl[i].name);
1398 * DPDK callback to get information about the device.
1401 * Pointer to Ethernet device structure (unused).
1403 * Info structure output buffer.
1406 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1407 struct rte_eth_dev_info *info)
1409 info->speed_capa = ETH_LINK_SPEED_10M |
1410 ETH_LINK_SPEED_100M |
1414 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1415 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1416 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1418 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1419 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1420 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1422 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1423 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1424 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1426 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1427 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1429 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1430 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1432 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1433 ETH_RSS_NONFRAG_IPV4_TCP |
1434 ETH_RSS_NONFRAG_IPV4_UDP;
1436 /* By default packets are dropped if no descriptors are available */
1437 info->default_rxconf.rx_drop_en = 1;
1439 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1443 * Return supported packet types.
1446 * Pointer to Ethernet device structure (unused).
1449 * Const pointer to the table with supported packet types.
1451 static const uint32_t *
1452 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1454 static const uint32_t ptypes[] = {
1456 RTE_PTYPE_L2_ETHER_VLAN,
1457 RTE_PTYPE_L2_ETHER_QINQ,
1459 RTE_PTYPE_L3_IPV4_EXT,
1460 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1462 RTE_PTYPE_L3_IPV6_EXT,
1463 RTE_PTYPE_L2_ETHER_ARP,
1472 * DPDK callback to get information about specific receive queue.
1475 * Pointer to Ethernet device structure.
1476 * @param rx_queue_id
1477 * Receive queue index.
1479 * Receive queue information structure.
1481 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1482 struct rte_eth_rxq_info *qinfo)
1484 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1485 struct mrvl_priv *priv = dev->data->dev_private;
1486 int inq = priv->rxq_map[rx_queue_id].inq;
1487 int tc = priv->rxq_map[rx_queue_id].tc;
1488 struct pp2_ppio_tc_params *tc_params =
1489 &priv->ppio_params.inqs_params.tcs_params[tc];
1492 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1496 * DPDK callback to get information about specific transmit queue.
1499 * Pointer to Ethernet device structure.
1500 * @param tx_queue_id
1501 * Transmit queue index.
1503 * Transmit queue information structure.
1505 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1506 struct rte_eth_txq_info *qinfo)
1508 struct mrvl_priv *priv = dev->data->dev_private;
1509 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1512 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1513 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1517 * DPDK callback to Configure a VLAN filter.
1520 * Pointer to Ethernet device structure.
1522 * VLAN ID to filter.
1527 * 0 on success, negative error value otherwise.
1530 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1532 struct mrvl_priv *priv = dev->data->dev_private;
1540 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1541 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1545 * Release buffers to hardware bpool (buffer-pool)
1548 * Receive queue pointer.
1550 * Number of buffers to release to bpool.
1553 * 0 on success, negative error value otherwise.
1556 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1558 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1559 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1561 unsigned int core_id;
1562 struct pp2_hif *hif;
1563 struct pp2_bpool *bpool;
1565 core_id = rte_lcore_id();
1566 if (core_id == LCORE_ID_ANY)
1569 hif = mrvl_get_hif(rxq->priv, core_id);
1573 bpool = rxq->priv->bpool;
1575 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1579 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1581 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1583 for (i = 0; i < num; i++) {
1584 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1585 != cookie_addr_high) {
1587 "mbuf virtual addr high 0x%lx out of range",
1588 (uint64_t)mbufs[i] >> 32);
1592 entries[i].buff.addr =
1593 rte_mbuf_data_iova_default(mbufs[i]);
1594 entries[i].buff.cookie = (uint64_t)mbufs[i];
1595 entries[i].bpool = bpool;
1598 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1599 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1606 for (; i < num; i++)
1607 rte_pktmbuf_free(mbufs[i]);
1613 * DPDK callback to configure the receive queue.
1616 * Pointer to Ethernet device structure.
1620 * Number of descriptors to configure in queue.
1622 * NUMA socket on which memory must be allocated.
1624 * Thresholds parameters.
1626 * Memory pool for buffer allocations.
1629 * 0 on success, negative error value otherwise.
1632 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1633 unsigned int socket,
1634 const struct rte_eth_rxconf *conf,
1635 struct rte_mempool *mp)
1637 struct mrvl_priv *priv = dev->data->dev_private;
1638 struct mrvl_rxq *rxq;
1639 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp);
1640 uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1644 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1646 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1648 * Unknown TC mapping, mapping will not have a correct queue.
1650 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1651 idx, priv->ppio_id);
1655 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS;
1656 if (frame_size < max_rx_pkt_len) {
1658 "Mbuf size must be increased to %u bytes to hold up "
1659 "to %u bytes of data.",
1660 buf_size + max_rx_pkt_len - frame_size,
1662 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1663 MRVL_LOG(INFO, "Setting max rx pkt len to %u",
1664 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1667 if (dev->data->rx_queues[idx]) {
1668 rte_free(dev->data->rx_queues[idx]);
1669 dev->data->rx_queues[idx] = NULL;
1672 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1678 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1679 rxq->queue_id = idx;
1680 rxq->port_id = dev->data->port_id;
1681 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1683 tc = priv->rxq_map[rxq->queue_id].tc,
1684 inq = priv->rxq_map[rxq->queue_id].inq;
1685 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1688 ret = mrvl_fill_bpool(rxq, desc);
1694 priv->bpool_init_size += desc;
1696 dev->data->rx_queues[idx] = rxq;
1702 * DPDK callback to release the receive queue.
1705 * Generic receive queue pointer.
1708 mrvl_rx_queue_release(void *rxq)
1710 struct mrvl_rxq *q = rxq;
1711 struct pp2_ppio_tc_params *tc_params;
1712 int i, num, tc, inq;
1713 struct pp2_hif *hif;
1714 unsigned int core_id = rte_lcore_id();
1716 if (core_id == LCORE_ID_ANY)
1722 hif = mrvl_get_hif(q->priv, core_id);
1727 tc = q->priv->rxq_map[q->queue_id].tc;
1728 inq = q->priv->rxq_map[q->queue_id].inq;
1729 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1730 num = tc_params->inqs_params[inq].size;
1731 for (i = 0; i < num; i++) {
1732 struct pp2_buff_inf inf;
1735 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1736 addr = cookie_addr_high | inf.cookie;
1737 rte_pktmbuf_free((struct rte_mbuf *)addr);
1744 * DPDK callback to configure the transmit queue.
1747 * Pointer to Ethernet device structure.
1749 * Transmit queue index.
1751 * Number of descriptors to configure in the queue.
1753 * NUMA socket on which memory must be allocated.
1755 * Tx queue configuration parameters.
1758 * 0 on success, negative error value otherwise.
1761 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1762 unsigned int socket,
1763 const struct rte_eth_txconf *conf)
1765 struct mrvl_priv *priv = dev->data->dev_private;
1766 struct mrvl_txq *txq;
1768 if (dev->data->tx_queues[idx]) {
1769 rte_free(dev->data->tx_queues[idx]);
1770 dev->data->tx_queues[idx] = NULL;
1773 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1778 txq->queue_id = idx;
1779 txq->port_id = dev->data->port_id;
1780 txq->tx_deferred_start = conf->tx_deferred_start;
1781 dev->data->tx_queues[idx] = txq;
1783 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1789 * DPDK callback to release the transmit queue.
1792 * Generic transmit queue pointer.
1795 mrvl_tx_queue_release(void *txq)
1797 struct mrvl_txq *q = txq;
1806 * DPDK callback to get flow control configuration.
1809 * Pointer to Ethernet device structure.
1811 * Pointer to the flow control configuration.
1814 * 0 on success, negative error value otherwise.
1817 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1819 struct mrvl_priv *priv = dev->data->dev_private;
1825 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1827 MRVL_LOG(ERR, "Failed to read rx pause state");
1831 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1837 * DPDK callback to set flow control configuration.
1840 * Pointer to Ethernet device structure.
1842 * Pointer to the flow control configuration.
1845 * 0 on success, negative error value otherwise.
1848 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1850 struct mrvl_priv *priv = dev->data->dev_private;
1855 if (fc_conf->high_water ||
1856 fc_conf->low_water ||
1857 fc_conf->pause_time ||
1858 fc_conf->mac_ctrl_frame_fwd ||
1860 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1865 if (fc_conf->mode == RTE_FC_NONE ||
1866 fc_conf->mode == RTE_FC_RX_PAUSE) {
1869 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1870 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1873 "Failed to change flowctrl on RX side");
1882 * Update RSS hash configuration
1885 * Pointer to Ethernet device structure.
1887 * Pointer to RSS configuration.
1890 * 0 on success, negative error value otherwise.
1893 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1894 struct rte_eth_rss_conf *rss_conf)
1896 struct mrvl_priv *priv = dev->data->dev_private;
1901 return mrvl_configure_rss(priv, rss_conf);
1905 * DPDK callback to get RSS hash configuration.
1908 * Pointer to Ethernet device structure.
1910 * Pointer to RSS configuration.
1916 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1917 struct rte_eth_rss_conf *rss_conf)
1919 struct mrvl_priv *priv = dev->data->dev_private;
1920 enum pp2_ppio_hash_type hash_type =
1921 priv->ppio_params.inqs_params.hash_type;
1923 rss_conf->rss_key = NULL;
1925 if (hash_type == PP2_PPIO_HASH_T_NONE)
1926 rss_conf->rss_hf = 0;
1927 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1928 rss_conf->rss_hf = ETH_RSS_IPV4;
1929 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1930 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1931 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1932 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1938 * DPDK callback to get rte_flow callbacks.
1941 * Pointer to the device structure.
1945 * Flow filter operation.
1947 * Pointer to pass the flow ops.
1950 * 0 on success, negative error value otherwise.
1953 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1954 enum rte_filter_type filter_type,
1955 enum rte_filter_op filter_op, void *arg)
1957 switch (filter_type) {
1958 case RTE_ETH_FILTER_GENERIC:
1959 if (filter_op != RTE_ETH_FILTER_GET)
1961 *(const void **)arg = &mrvl_flow_ops;
1964 MRVL_LOG(WARNING, "Filter type (%d) not supported",
1971 * DPDK callback to get rte_mtr callbacks.
1974 * Pointer to the device structure.
1976 * Pointer to pass the mtr ops.
1982 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
1984 *(const void **)ops = &mrvl_mtr_ops;
1990 * DPDK callback to get rte_tm callbacks.
1993 * Pointer to the device structure.
1995 * Pointer to pass the tm ops.
2001 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2003 *(const void **)ops = &mrvl_tm_ops;
2008 static const struct eth_dev_ops mrvl_ops = {
2009 .dev_configure = mrvl_dev_configure,
2010 .dev_start = mrvl_dev_start,
2011 .dev_stop = mrvl_dev_stop,
2012 .dev_set_link_up = mrvl_dev_set_link_up,
2013 .dev_set_link_down = mrvl_dev_set_link_down,
2014 .dev_close = mrvl_dev_close,
2015 .link_update = mrvl_link_update,
2016 .promiscuous_enable = mrvl_promiscuous_enable,
2017 .allmulticast_enable = mrvl_allmulticast_enable,
2018 .promiscuous_disable = mrvl_promiscuous_disable,
2019 .allmulticast_disable = mrvl_allmulticast_disable,
2020 .mac_addr_remove = mrvl_mac_addr_remove,
2021 .mac_addr_add = mrvl_mac_addr_add,
2022 .mac_addr_set = mrvl_mac_addr_set,
2023 .mtu_set = mrvl_mtu_set,
2024 .stats_get = mrvl_stats_get,
2025 .stats_reset = mrvl_stats_reset,
2026 .xstats_get = mrvl_xstats_get,
2027 .xstats_reset = mrvl_xstats_reset,
2028 .xstats_get_names = mrvl_xstats_get_names,
2029 .dev_infos_get = mrvl_dev_infos_get,
2030 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
2031 .rxq_info_get = mrvl_rxq_info_get,
2032 .txq_info_get = mrvl_txq_info_get,
2033 .vlan_filter_set = mrvl_vlan_filter_set,
2034 .tx_queue_start = mrvl_tx_queue_start,
2035 .tx_queue_stop = mrvl_tx_queue_stop,
2036 .rx_queue_setup = mrvl_rx_queue_setup,
2037 .rx_queue_release = mrvl_rx_queue_release,
2038 .tx_queue_setup = mrvl_tx_queue_setup,
2039 .tx_queue_release = mrvl_tx_queue_release,
2040 .flow_ctrl_get = mrvl_flow_ctrl_get,
2041 .flow_ctrl_set = mrvl_flow_ctrl_set,
2042 .rss_hash_update = mrvl_rss_hash_update,
2043 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
2044 .filter_ctrl = mrvl_eth_filter_ctrl,
2045 .mtr_ops_get = mrvl_mtr_ops_get,
2046 .tm_ops_get = mrvl_tm_ops_get,
2050 * Return packet type information and l3/l4 offsets.
2053 * Pointer to the received packet descriptor.
2060 * Packet type information.
2062 static inline uint64_t
2063 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2064 uint8_t *l3_offset, uint8_t *l4_offset)
2066 enum pp2_inq_l3_type l3_type;
2067 enum pp2_inq_l4_type l4_type;
2068 enum pp2_inq_vlan_tag vlan_tag;
2069 uint64_t packet_type;
2071 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2072 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2073 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
2075 packet_type = RTE_PTYPE_L2_ETHER;
2078 case PP2_INQ_VLAN_TAG_SINGLE:
2079 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
2081 case PP2_INQ_VLAN_TAG_DOUBLE:
2082 case PP2_INQ_VLAN_TAG_TRIPLE:
2083 packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
2090 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2091 packet_type |= RTE_PTYPE_L3_IPV4;
2093 case PP2_INQ_L3_TYPE_IPV4_OK:
2094 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2096 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2097 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2099 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2100 packet_type |= RTE_PTYPE_L3_IPV6;
2102 case PP2_INQ_L3_TYPE_IPV6_EXT:
2103 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2105 case PP2_INQ_L3_TYPE_ARP:
2106 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2108 * In case of ARP l4_offset is set to wrong value.
2109 * Set it to proper one so that later on mbuf->l3_len can be
2110 * calculated subtracting l4_offset and l3_offset.
2112 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2115 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
2120 case PP2_INQ_L4_TYPE_TCP:
2121 packet_type |= RTE_PTYPE_L4_TCP;
2123 case PP2_INQ_L4_TYPE_UDP:
2124 packet_type |= RTE_PTYPE_L4_UDP;
2127 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
2135 * Get offload information from the received packet descriptor.
2138 * Pointer to the received packet descriptor.
2141 * Mbuf offload flags.
2143 static inline uint64_t
2144 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
2147 enum pp2_inq_desc_status status;
2149 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2150 if (unlikely(status != PP2_DESC_ERR_OK))
2151 flags = PKT_RX_IP_CKSUM_BAD;
2153 flags = PKT_RX_IP_CKSUM_GOOD;
2155 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2156 if (unlikely(status != PP2_DESC_ERR_OK))
2157 flags |= PKT_RX_L4_CKSUM_BAD;
2159 flags |= PKT_RX_L4_CKSUM_GOOD;
2165 * DPDK callback for receive.
2168 * Generic pointer to the receive queue.
2170 * Array to store received packets.
2172 * Maximum number of packets in array.
2175 * Number of packets successfully received.
2178 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2180 struct mrvl_rxq *q = rxq;
2181 struct pp2_ppio_desc descs[nb_pkts];
2182 struct pp2_bpool *bpool;
2183 int i, ret, rx_done = 0;
2185 struct pp2_hif *hif;
2186 unsigned int core_id = rte_lcore_id();
2188 hif = mrvl_get_hif(q->priv, core_id);
2190 if (unlikely(!q->priv->ppio || !hif))
2193 bpool = q->priv->bpool;
2195 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2196 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2197 if (unlikely(ret < 0)) {
2198 MRVL_LOG(ERR, "Failed to receive packets");
2201 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2203 for (i = 0; i < nb_pkts; i++) {
2204 struct rte_mbuf *mbuf;
2205 uint8_t l3_offset, l4_offset;
2206 enum pp2_inq_desc_status status;
2209 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2210 struct pp2_ppio_desc *pref_desc;
2213 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2214 pref_addr = cookie_addr_high |
2215 pp2_ppio_inq_desc_get_cookie(pref_desc);
2216 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2217 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2220 addr = cookie_addr_high |
2221 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2222 mbuf = (struct rte_mbuf *)addr;
2223 rte_pktmbuf_reset(mbuf);
2225 /* drop packet in case of mac, overrun or resource error */
2226 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2227 if (unlikely(status != PP2_DESC_ERR_OK)) {
2228 struct pp2_buff_inf binf = {
2229 .addr = rte_mbuf_data_iova_default(mbuf),
2230 .cookie = (uint64_t)mbuf,
2233 pp2_bpool_put_buff(hif, bpool, &binf);
2234 mrvl_port_bpool_size
2235 [bpool->pp2_id][bpool->id][core_id]++;
2240 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2241 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2242 mbuf->data_len = mbuf->pkt_len;
2243 mbuf->port = q->port_id;
2245 mrvl_desc_to_packet_type_and_offset(&descs[i],
2248 mbuf->l2_len = l3_offset;
2249 mbuf->l3_len = l4_offset - l3_offset;
2251 if (likely(q->cksum_enabled))
2252 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2254 rx_pkts[rx_done++] = mbuf;
2255 q->bytes_recv += mbuf->pkt_len;
2258 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2259 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2261 if (unlikely(num <= q->priv->bpool_min_size ||
2262 (!rx_done && num < q->priv->bpool_init_size))) {
2263 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2265 MRVL_LOG(ERR, "Failed to fill bpool");
2266 } else if (unlikely(num > q->priv->bpool_max_size)) {
2268 int pkt_to_remove = num - q->priv->bpool_init_size;
2269 struct rte_mbuf *mbuf;
2270 struct pp2_buff_inf buff;
2273 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
2274 bpool->pp2_id, q->priv->ppio->port_id,
2275 bpool->id, pkt_to_remove, num,
2276 q->priv->bpool_init_size);
2278 for (i = 0; i < pkt_to_remove; i++) {
2279 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2282 mbuf = (struct rte_mbuf *)
2283 (cookie_addr_high | buff.cookie);
2284 rte_pktmbuf_free(mbuf);
2286 mrvl_port_bpool_size
2287 [bpool->pp2_id][bpool->id][core_id] -= i;
2289 rte_spinlock_unlock(&q->priv->lock);
2296 * Prepare offload information.
2300 * @param packet_type
2301 * Packet type bitfield.
2303 * Pointer to the pp2_ouq_l3_type structure.
2305 * Pointer to the pp2_outq_l4_type structure.
2306 * @param gen_l3_cksum
2307 * Will be set to 1 in case l3 checksum is computed.
2309 * Will be set to 1 in case l4 checksum is computed.
2312 * 0 on success, negative error value otherwise.
2315 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2316 enum pp2_outq_l3_type *l3_type,
2317 enum pp2_outq_l4_type *l4_type,
2322 * Based on ol_flags prepare information
2323 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2326 if (ol_flags & PKT_TX_IPV4) {
2327 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2328 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2329 } else if (ol_flags & PKT_TX_IPV6) {
2330 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2331 /* no checksum for ipv6 header */
2334 /* if something different then stop processing */
2338 ol_flags &= PKT_TX_L4_MASK;
2339 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2340 ol_flags == PKT_TX_TCP_CKSUM) {
2341 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2343 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2344 ol_flags == PKT_TX_UDP_CKSUM) {
2345 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2348 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2349 /* no checksum for other type */
2357 * Release already sent buffers to bpool (buffer-pool).
2360 * Pointer to the port structure.
2362 * Pointer to the MUSDK hardware interface.
2364 * Pointer to the shadow queue.
2368 * Force releasing packets.
2371 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2372 unsigned int core_id, struct mrvl_shadow_txq *sq,
2375 struct buff_release_entry *entry;
2376 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2379 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2381 sq->num_to_release += nb_done;
2383 if (likely(!force &&
2384 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2387 nb_done = sq->num_to_release;
2388 sq->num_to_release = 0;
2390 for (i = 0; i < nb_done; i++) {
2391 entry = &sq->ent[sq->tail + num];
2392 if (unlikely(!entry->buff.addr)) {
2394 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2395 sq->tail, (u64)entry->buff.cookie,
2396 (u64)entry->buff.addr);
2401 if (unlikely(!entry->bpool)) {
2402 struct rte_mbuf *mbuf;
2404 mbuf = (struct rte_mbuf *)
2405 (cookie_addr_high | entry->buff.cookie);
2406 rte_pktmbuf_free(mbuf);
2411 mrvl_port_bpool_size
2412 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2414 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2419 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2421 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2428 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2429 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2435 * DPDK callback for transmit.
2438 * Generic pointer transmit queue.
2440 * Packets to transmit.
2442 * Number of packets in array.
2445 * Number of packets successfully transmitted.
2448 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2450 struct mrvl_txq *q = txq;
2451 struct mrvl_shadow_txq *sq;
2452 struct pp2_hif *hif;
2453 struct pp2_ppio_desc descs[nb_pkts];
2454 unsigned int core_id = rte_lcore_id();
2455 int i, ret, bytes_sent = 0;
2456 uint16_t num, sq_free_size;
2459 hif = mrvl_get_hif(q->priv, core_id);
2460 sq = &q->shadow_txqs[core_id];
2462 if (unlikely(!q->priv->ppio || !hif))
2466 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2467 sq, q->queue_id, 0);
2469 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2470 if (unlikely(nb_pkts > sq_free_size)) {
2472 "No room in shadow queue for %d packets! %d packets will be sent.",
2473 nb_pkts, sq_free_size);
2474 nb_pkts = sq_free_size;
2477 for (i = 0; i < nb_pkts; i++) {
2478 struct rte_mbuf *mbuf = tx_pkts[i];
2479 int gen_l3_cksum, gen_l4_cksum;
2480 enum pp2_outq_l3_type l3_type;
2481 enum pp2_outq_l4_type l4_type;
2483 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2484 struct rte_mbuf *pref_pkt_hdr;
2486 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2487 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2488 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2491 mrvl_fill_shadowq(sq, mbuf);
2492 mrvl_fill_desc(&descs[i], mbuf);
2494 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2496 * in case unsupported ol_flags were passed
2497 * do not update descriptor offload information
2499 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2500 &l3_type, &l4_type, &gen_l3_cksum,
2505 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2507 mbuf->l2_len + mbuf->l3_len,
2508 gen_l3_cksum, gen_l4_cksum);
2512 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2513 /* number of packets that were not sent */
2514 if (unlikely(num > nb_pkts)) {
2515 for (i = nb_pkts; i < num; i++) {
2516 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2517 MRVL_PP2_TX_SHADOWQ_MASK;
2518 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2520 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2522 sq->size -= num - nb_pkts;
2525 q->bytes_sent += bytes_sent;
2530 /** DPDK callback for S/G transmit.
2533 * Generic pointer transmit queue.
2535 * Packets to transmit.
2537 * Number of packets in array.
2540 * Number of packets successfully transmitted.
2543 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
2546 struct mrvl_txq *q = txq;
2547 struct mrvl_shadow_txq *sq;
2548 struct pp2_hif *hif;
2549 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS];
2550 struct pp2_ppio_sg_pkts pkts;
2551 uint8_t frags[nb_pkts];
2552 unsigned int core_id = rte_lcore_id();
2553 int i, j, ret, bytes_sent = 0;
2554 int tail, tail_first;
2555 uint16_t num, sq_free_size;
2556 uint16_t nb_segs, total_descs = 0;
2559 hif = mrvl_get_hif(q->priv, core_id);
2560 sq = &q->shadow_txqs[core_id];
2564 if (unlikely(!q->priv->ppio || !hif))
2568 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2569 sq, q->queue_id, 0);
2571 /* Save shadow queue free size */
2572 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2575 for (i = 0; i < nb_pkts; i++) {
2576 struct rte_mbuf *mbuf = tx_pkts[i];
2577 struct rte_mbuf *seg = NULL;
2578 int gen_l3_cksum, gen_l4_cksum;
2579 enum pp2_outq_l3_type l3_type;
2580 enum pp2_outq_l4_type l4_type;
2582 nb_segs = mbuf->nb_segs;
2584 total_descs += nb_segs;
2587 * Check if total_descs does not exceed
2588 * shadow queue free size
2590 if (unlikely(total_descs > sq_free_size)) {
2591 total_descs -= nb_segs;
2593 "No room in shadow queue for %d packets! "
2594 "%d packets will be sent.\n",
2599 /* Check if nb_segs does not exceed the max nb of desc per
2602 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) {
2603 total_descs -= nb_segs;
2605 "Too many segments. Packet won't be sent.\n");
2609 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2610 struct rte_mbuf *pref_pkt_hdr;
2612 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2613 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2614 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2617 pkts.frags[pkts.num] = nb_segs;
2621 for (j = 0; j < nb_segs - 1; j++) {
2622 /* For the subsequent segments, set shadow queue
2625 mrvl_fill_shadowq(sq, NULL);
2626 mrvl_fill_desc(&descs[tail], seg);
2631 /* Put first mbuf info in last shadow queue entry */
2632 mrvl_fill_shadowq(sq, mbuf);
2633 /* Update descriptor with last segment */
2634 mrvl_fill_desc(&descs[tail++], seg);
2636 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2637 /* In case unsupported ol_flags were passed
2638 * do not update descriptor offload information
2640 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2641 &l3_type, &l4_type, &gen_l3_cksum,
2646 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type,
2647 l4_type, mbuf->l2_len,
2648 mbuf->l2_len + mbuf->l3_len,
2649 gen_l3_cksum, gen_l4_cksum);
2653 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs,
2654 &total_descs, &pkts);
2655 /* number of packets that were not sent */
2656 if (unlikely(num > total_descs)) {
2657 for (i = total_descs; i < num; i++) {
2658 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2659 MRVL_PP2_TX_SHADOWQ_MASK;
2661 addr = sq->ent[sq->head].buff.cookie;
2664 rte_pktmbuf_pkt_len((struct rte_mbuf *)
2665 (cookie_addr_high | addr));
2667 sq->size -= num - total_descs;
2671 q->bytes_sent += bytes_sent;
2677 * Initialize packet processor.
2680 * 0 on success, negative error value otherwise.
2685 struct pp2_init_params init_params;
2687 memset(&init_params, 0, sizeof(init_params));
2688 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2689 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2690 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2692 return pp2_init(&init_params);
2696 * Deinitialize packet processor.
2699 * 0 on success, negative error value otherwise.
2702 mrvl_deinit_pp2(void)
2708 * Create private device structure.
2711 * Pointer to the port name passed in the initialization parameters.
2714 * Pointer to the newly allocated private device structure.
2716 static struct mrvl_priv *
2717 mrvl_priv_create(const char *dev_name)
2719 struct pp2_bpool_params bpool_params;
2720 char match[MRVL_MATCH_LEN];
2721 struct mrvl_priv *priv;
2724 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2728 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2729 &priv->pp_id, &priv->ppio_id);
2733 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2734 PP2_BPOOL_NUM_POOLS);
2737 priv->bpool_bit = bpool_bit;
2739 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2741 memset(&bpool_params, 0, sizeof(bpool_params));
2742 bpool_params.match = match;
2743 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2744 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2746 goto out_clear_bpool_bit;
2748 priv->ppio_params.type = PP2_PPIO_T_NIC;
2749 rte_spinlock_init(&priv->lock);
2752 out_clear_bpool_bit:
2753 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2760 * Create device representing Ethernet port.
2763 * Pointer to the port's name.
2766 * 0 on success, negative error value otherwise.
2769 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2771 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2772 struct rte_eth_dev *eth_dev;
2773 struct mrvl_priv *priv;
2776 eth_dev = rte_eth_dev_allocate(name);
2780 priv = mrvl_priv_create(name);
2786 eth_dev->data->mac_addrs =
2787 rte_zmalloc("mac_addrs",
2788 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2789 if (!eth_dev->data->mac_addrs) {
2790 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2795 memset(&req, 0, sizeof(req));
2796 strcpy(req.ifr_name, name);
2797 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2801 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2802 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2804 eth_dev->data->kdrv = RTE_KDRV_NONE;
2805 eth_dev->data->dev_private = priv;
2806 eth_dev->device = &vdev->device;
2807 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2808 mrvl_set_tx_function(eth_dev);
2809 eth_dev->dev_ops = &mrvl_ops;
2811 rte_eth_dev_probing_finish(eth_dev);
2814 rte_free(eth_dev->data->mac_addrs);
2816 rte_eth_dev_release_port(eth_dev);
2824 * Cleanup previously created device representing Ethernet port.
2827 * Pointer to the port name.
2830 mrvl_eth_dev_destroy(const char *name)
2832 struct rte_eth_dev *eth_dev;
2833 struct mrvl_priv *priv;
2835 eth_dev = rte_eth_dev_allocated(name);
2839 priv = eth_dev->data->dev_private;
2840 pp2_bpool_deinit(priv->bpool);
2841 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2843 rte_free(eth_dev->data->mac_addrs);
2844 rte_eth_dev_release_port(eth_dev);
2848 * Callback used by rte_kvargs_process() during argument parsing.
2851 * Pointer to the parsed key (unused).
2853 * Pointer to the parsed value.
2855 * Pointer to the extra arguments which contains address of the
2856 * table of pointers to parsed interface names.
2862 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2865 struct mrvl_ifnames *ifnames = extra_args;
2867 ifnames->names[ifnames->idx++] = value;
2873 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2876 mrvl_deinit_hifs(void)
2880 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2882 pp2_hif_deinit(hifs[i]);
2884 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2885 memset(hifs, 0, sizeof(hifs));
2889 * DPDK callback to register the virtual device.
2892 * Pointer to the virtual device.
2895 * 0 on success, negative error value otherwise.
2898 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2900 struct rte_kvargs *kvlist;
2901 struct mrvl_ifnames ifnames;
2903 uint32_t i, ifnum, cfgnum;
2906 params = rte_vdev_device_args(vdev);
2910 kvlist = rte_kvargs_parse(params, valid_args);
2914 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2915 if (ifnum > RTE_DIM(ifnames.names))
2916 goto out_free_kvlist;
2919 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2920 mrvl_get_ifnames, &ifnames);
2924 * The below system initialization should be done only once,
2925 * on the first provided configuration file
2927 if (!mrvl_qos_cfg) {
2928 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2929 MRVL_LOG(INFO, "Parsing config file!");
2931 MRVL_LOG(ERR, "Cannot handle more than one config file!");
2932 goto out_free_kvlist;
2933 } else if (cfgnum == 1) {
2934 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2935 mrvl_get_qoscfg, &mrvl_qos_cfg);
2942 MRVL_LOG(INFO, "Perform MUSDK initializations");
2944 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
2946 goto out_free_kvlist;
2948 ret = mrvl_init_pp2();
2950 MRVL_LOG(ERR, "Failed to init PP!");
2951 rte_mvep_deinit(MVEP_MOD_T_PP2);
2952 goto out_free_kvlist;
2955 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2956 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2958 mrvl_lcore_first = RTE_MAX_LCORE;
2959 mrvl_lcore_last = 0;
2962 for (i = 0; i < ifnum; i++) {
2963 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
2964 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2968 mrvl_dev_num += ifnum;
2970 rte_kvargs_free(kvlist);
2975 mrvl_eth_dev_destroy(ifnames.names[i]);
2977 if (mrvl_dev_num == 0) {
2979 rte_mvep_deinit(MVEP_MOD_T_PP2);
2982 rte_kvargs_free(kvlist);
2988 * DPDK callback to remove virtual device.
2991 * Pointer to the removed virtual device.
2994 * 0 on success, negative error value otherwise.
2997 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
3002 name = rte_vdev_device_name(vdev);
3006 MRVL_LOG(INFO, "Removing %s", name);
3008 RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */
3009 char ifname[RTE_ETH_NAME_MAX_LEN];
3011 rte_eth_dev_get_name_by_port(i, ifname);
3012 mrvl_eth_dev_destroy(ifname);
3016 if (mrvl_dev_num == 0) {
3017 MRVL_LOG(INFO, "Perform MUSDK deinit");
3020 rte_mvep_deinit(MVEP_MOD_T_PP2);
3026 static struct rte_vdev_driver pmd_mrvl_drv = {
3027 .probe = rte_pmd_mrvl_probe,
3028 .remove = rte_pmd_mrvl_remove,
3031 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
3032 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
3034 RTE_INIT(mrvl_init_log)
3036 mrvl_logtype = rte_log_register("pmd.net.mvpp2");
3037 if (mrvl_logtype >= 0)
3038 rte_log_set_level(mrvl_logtype, RTE_LOG_NOTICE);