drivers/net/mvpp2/mrvl_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017-2021 Marvell International Ltd.
   3  * Copyright(c) 2017-2021 Semihalf.
   4  * All rights reserved.
   5  */
   6
   7 #include <rte_string_fns.h>
   8 #include <ethdev_driver.h>
   9 #include <rte_kvargs.h>
  10 #include <rte_log.h>
  11 #include <rte_malloc.h>
  12 #include <rte_bus_vdev.h>
  13
  14 #include <fcntl.h>
  15 #include <linux/ethtool.h>
  16 #include <linux/sockios.h>
  17 #include <net/if.h>
  18 #include <net/if_arp.h>
  19 #include <sys/ioctl.h>
  20 #include <sys/socket.h>
  21 #include <sys/stat.h>
  22 #include <sys/types.h>
  23
  24 #include <rte_mvep_common.h>
  25 #include "mrvl_ethdev.h"
  26 #include "mrvl_qos.h"
  27 #include "mrvl_flow.h"
  28 #include "mrvl_mtr.h"
  29 #include "mrvl_tm.h"
  30
  31 /* bitmask with reserved hifs */
  32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
  33 /* bitmask with reserved bpools */
  34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
  35 /* bitmask with reserved kernel RSS tables */
  36 #define MRVL_MUSDK_RSS_RESERVED 0x0F
  37 /* maximum number of available hifs */
  38 #define MRVL_MUSDK_HIFS_MAX 9
  39
  40 /* prefetch shift */
  41 #define MRVL_MUSDK_PREFETCH_SHIFT 2
  42
  43 /* TCAM has 25 entries reserved for uc/mc filter entries */
  44 #define MRVL_MAC_ADDRS_MAX 25
  45 #define MRVL_MATCH_LEN 16
  46 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
  47 /* Maximum allowable packet size */
  48 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
  49
  50 #define MRVL_IFACE_NAME_ARG "iface"
  51 #define MRVL_CFG_ARG "cfg"
  52
  53 #define MRVL_BURST_SIZE 64
  54
  55 #define MRVL_ARP_LENGTH 28
  56
  57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
  58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
  59
  60 /** Port Rx offload capabilities */
  61 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
  62                           DEV_RX_OFFLOAD_JUMBO_FRAME | \
  63                           DEV_RX_OFFLOAD_CHECKSUM)
  64
  65 /** Port Tx offloads capabilities */
  66 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
  67                           DEV_TX_OFFLOAD_UDP_CKSUM | \
  68                           DEV_TX_OFFLOAD_TCP_CKSUM | \
  69                           DEV_TX_OFFLOAD_MULTI_SEGS)
  70
  71 static const char * const valid_args[] = {
  72         MRVL_IFACE_NAME_ARG,
  73         MRVL_CFG_ARG,
  74         NULL
  75 };
  76
  77 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
  78 static struct pp2_hif *hifs[RTE_MAX_LCORE];
  79 static int used_bpools[PP2_NUM_PKT_PROC] = {
  80         [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
  81 };
  82
  83 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
  84 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
  85 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
  86
  87 struct mrvl_ifnames {
  88         const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
  89         int idx;
  90 };
  91
  92 /*
  93  * To use buffer harvesting based on loopback port shadow queue structure
  94  * was introduced for buffers information bookkeeping.
  95  *
  96  * Before sending the packet, related buffer information (pp2_buff_inf) is
  97  * stored in shadow queue. After packet is transmitted no longer used
  98  * packet buffer is released back to it's original hardware pool,
  99  * on condition it originated from interface.
 100  * In case it  was generated by application itself i.e: mbuf->port field is
 101  * 0xff then its released to software mempool.
 102  */
 103 struct mrvl_shadow_txq {
 104         int head;           /* write index - used when sending buffers */
 105         int tail;           /* read index - used when releasing buffers */
 106         u16 size;           /* queue occupied size */
 107         u16 num_to_release; /* number of descriptors sent, that can be
 108                              * released
 109                              */
 110         struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
 111 };
 112
 113 struct mrvl_rxq {
 114         struct mrvl_priv *priv;
 115         struct rte_mempool *mp;
 116         int queue_id;
 117         int port_id;
 118         int cksum_enabled;
 119         uint64_t bytes_recv;
 120         uint64_t drop_mac;
 121 };
 122
 123 struct mrvl_txq {
 124         struct mrvl_priv *priv;
 125         int queue_id;
 126         int port_id;
 127         uint64_t bytes_sent;
 128         struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
 129         int tx_deferred_start;
 130 };
 131
 132 static int mrvl_lcore_first;
 133 static int mrvl_lcore_last;
 134 static int mrvl_dev_num;
 135
 136 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
 137 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
 138                         struct pp2_hif *hif, unsigned int core_id,
 139                         struct mrvl_shadow_txq *sq, int qid, int force);
 140
 141 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
 142                                   uint16_t nb_pkts);
 143 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
 144                                      uint16_t nb_pkts);
 145 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev);
 146 static void mrvl_deinit_pp2(void);
 147 static void mrvl_deinit_hifs(void);
 148
 149 static int
 150 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 151                   uint32_t index, uint32_t vmdq __rte_unused);
 152 static int
 153 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
 154 static int
 155 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
 156 static int mrvl_promiscuous_enable(struct rte_eth_dev *dev);
 157 static int mrvl_allmulticast_enable(struct rte_eth_dev *dev);
 158
 159 #define MRVL_XSTATS_TBL_ENTRY(name) { \
 160         #name, offsetof(struct pp2_ppio_statistics, name),      \
 161         sizeof(((struct pp2_ppio_statistics *)0)->name)         \
 162 }
 163
 164 /* Table with xstats data */
 165 static struct {
 166         const char *name;
 167         unsigned int offset;
 168         unsigned int size;
 169 } mrvl_xstats_tbl[] = {
 170         MRVL_XSTATS_TBL_ENTRY(rx_bytes),
 171         MRVL_XSTATS_TBL_ENTRY(rx_packets),
 172         MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
 173         MRVL_XSTATS_TBL_ENTRY(rx_errors),
 174         MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
 175         MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
 176         MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
 177         MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
 178         MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
 179         MRVL_XSTATS_TBL_ENTRY(tx_bytes),
 180         MRVL_XSTATS_TBL_ENTRY(tx_packets),
 181         MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
 182         MRVL_XSTATS_TBL_ENTRY(tx_errors)
 183 };
 184
 185 static inline void
 186 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf)
 187 {
 188         sq->ent[sq->head].buff.cookie = (uint64_t)buf;
 189         sq->ent[sq->head].buff.addr = buf ?
 190                 rte_mbuf_data_iova_default(buf) : 0;
 191
 192         sq->ent[sq->head].bpool =
 193                 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS ||
 194                  buf->refcnt > 1)) ? NULL :
 195                  mrvl_port_to_bpool_lookup[buf->port];
 196
 197         sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
 198         sq->size++;
 199 }
 200
 201 static inline void
 202 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf)
 203 {
 204         pp2_ppio_outq_desc_reset(desc);
 205         pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf));
 206         pp2_ppio_outq_desc_set_pkt_offset(desc, 0);
 207         pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf));
 208 }
 209
 210 static inline int
 211 mrvl_get_bpool_size(int pp2_id, int pool_id)
 212 {
 213         int i;
 214         int size = 0;
 215
 216         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
 217                 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
 218
 219         return size;
 220 }
 221
 222 static inline int
 223 mrvl_reserve_bit(int *bitmap, int max)
 224 {
 225         int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
 226
 227         if (n >= max)
 228                 return -1;
 229
 230         *bitmap |= 1 << n;
 231
 232         return n;
 233 }
 234
 235 static int
 236 mrvl_init_hif(int core_id)
 237 {
 238         struct pp2_hif_params params;
 239         char match[MRVL_MATCH_LEN];
 240         int ret;
 241
 242         ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
 243         if (ret < 0) {
 244                 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
 245                 return ret;
 246         }
 247
 248         snprintf(match, sizeof(match), "hif-%d", ret);
 249         memset(&params, 0, sizeof(params));
 250         params.match = match;
 251         params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
 252         ret = pp2_hif_init(&params, &hifs[core_id]);
 253         if (ret) {
 254                 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
 255                 return ret;
 256         }
 257
 258         return 0;
 259 }
 260
 261 static inline struct pp2_hif*
 262 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
 263 {
 264         int ret;
 265
 266         if (likely(hifs[core_id] != NULL))
 267                 return hifs[core_id];
 268
 269         rte_spinlock_lock(&priv->lock);
 270
 271         ret = mrvl_init_hif(core_id);
 272         if (ret < 0) {
 273                 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
 274                 goto out;
 275         }
 276
 277         if (core_id < mrvl_lcore_first)
 278                 mrvl_lcore_first = core_id;
 279
 280         if (core_id > mrvl_lcore_last)
 281                 mrvl_lcore_last = core_id;
 282 out:
 283         rte_spinlock_unlock(&priv->lock);
 284
 285         return hifs[core_id];
 286 }
 287
 288 /**
 289  * Set tx burst function according to offload flag
 290  *
 291  * @param dev
 292  *   Pointer to Ethernet device structure.
 293  */
 294 static void
 295 mrvl_set_tx_function(struct rte_eth_dev *dev)
 296 {
 297         struct mrvl_priv *priv = dev->data->dev_private;
 298
 299         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
 300         if (priv->multiseg) {
 301                 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n");
 302                 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst;
 303         } else {
 304                 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n");
 305                 dev->tx_pkt_burst = mrvl_tx_pkt_burst;
 306         }
 307 }
 308
 309 /**
 310  * Configure rss based on dpdk rss configuration.
 311  *
 312  * @param priv
 313  *   Pointer to private structure.
 314  * @param rss_conf
 315  *   Pointer to RSS configuration.
 316  *
 317  * @return
 318  *   0 on success, negative error value otherwise.
 319  */
 320 static int
 321 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
 322 {
 323         if (rss_conf->rss_key)
 324                 MRVL_LOG(WARNING, "Changing hash key is not supported");
 325
 326         if (rss_conf->rss_hf == 0) {
 327                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 328         } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
 329                 priv->ppio_params.inqs_params.hash_type =
 330                         PP2_PPIO_HASH_T_2_TUPLE;
 331         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
 332                 priv->ppio_params.inqs_params.hash_type =
 333                         PP2_PPIO_HASH_T_5_TUPLE;
 334                 priv->rss_hf_tcp = 1;
 335         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
 336                 priv->ppio_params.inqs_params.hash_type =
 337                         PP2_PPIO_HASH_T_5_TUPLE;
 338                 priv->rss_hf_tcp = 0;
 339         } else {
 340                 return -EINVAL;
 341         }
 342
 343         return 0;
 344 }
 345
 346 /**
 347  * Ethernet device configuration.
 348  *
 349  * Prepare the driver for a given number of TX and RX queues and
 350  * configure RSS.
 351  *
 352  * @param dev
 353  *   Pointer to Ethernet device structure.
 354  *
 355  * @return
 356  *   0 on success, negative error value otherwise.
 357  */
 358 static int
 359 mrvl_dev_configure(struct rte_eth_dev *dev)
 360 {
 361         struct mrvl_priv *priv = dev->data->dev_private;
 362         int ret;
 363
 364         if (priv->ppio) {
 365                 MRVL_LOG(INFO, "Device reconfiguration is not supported");
 366                 return -EINVAL;
 367         }
 368
 369         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
 370             dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
 371                 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
 372                         dev->data->dev_conf.rxmode.mq_mode);
 373                 return -EINVAL;
 374         }
 375
 376         if (dev->data->dev_conf.rxmode.split_hdr_size) {
 377                 MRVL_LOG(INFO, "Split headers not supported");
 378                 return -EINVAL;
 379         }
 380
 381         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 382                 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
 383                                  MRVL_PP2_ETH_HDRS_LEN;
 384
 385         if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 386                 priv->multiseg = 1;
 387
 388         ret = mrvl_configure_rxqs(priv, dev->data->port_id,
 389                                   dev->data->nb_rx_queues);
 390         if (ret < 0)
 391                 return ret;
 392
 393         ret = mrvl_configure_txqs(priv, dev->data->port_id,
 394                                   dev->data->nb_tx_queues);
 395         if (ret < 0)
 396                 return ret;
 397
 398         priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
 399         priv->ppio_params.maintain_stats = 1;
 400         priv->nb_rx_queues = dev->data->nb_rx_queues;
 401
 402         ret = mrvl_tm_init(dev);
 403         if (ret < 0)
 404                 return ret;
 405
 406         if (dev->data->nb_rx_queues == 1 &&
 407             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 408                 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
 409                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 410
 411                 return 0;
 412         }
 413
 414         return mrvl_configure_rss(priv,
 415                         &dev->data->dev_conf.rx_adv_conf.rss_conf);
 416 }
 417
 418 /**
 419  * DPDK callback to change the MTU.
 420  *
 421  * Setting the MTU affects hardware MRU (packets larger than the MRU
 422  * will be dropped).
 423  *
 424  * @param dev
 425  *   Pointer to Ethernet device structure.
 426  * @param mtu
 427  *   New MTU.
 428  *
 429  * @return
 430  *   0 on success, negative error value otherwise.
 431  */
 432 static int
 433 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 434 {
 435         struct mrvl_priv *priv = dev->data->dev_private;
 436         uint16_t mru;
 437         uint16_t mbuf_data_size = 0; /* SW buffer size */
 438         int ret;
 439
 440         mru = MRVL_PP2_MTU_TO_MRU(mtu);
 441         /*
 442          * min_rx_buf_size is equal to mbuf data size
 443          * if pmd didn't set it differently
 444          */
 445         mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 446         /* Prevent PMD from:
 447          * - setting mru greater than the mbuf size resulting in
 448          * hw and sw buffer size mismatch
 449          * - setting mtu that requires the support of scattered packets
 450          * when this feature has not been enabled/supported so far
 451          * (TODO check scattered_rx flag here once scattered RX is supported).
 452          */
 453         if (mru - RTE_ETHER_CRC_LEN + MRVL_PKT_OFFS > mbuf_data_size) {
 454                 mru = mbuf_data_size + RTE_ETHER_CRC_LEN - MRVL_PKT_OFFS;
 455                 mtu = MRVL_PP2_MRU_TO_MTU(mru);
 456                 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted "
 457                         "by current mbuf size: %u. Set MTU to %u, MRU to %u",
 458                         mbuf_data_size, mtu, mru);
 459         }
 460
 461         if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) {
 462                 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru);
 463                 return -EINVAL;
 464         }
 465
 466         dev->data->mtu = mtu;
 467         dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE;
 468
 469         if (!priv->ppio)
 470                 return 0;
 471
 472         ret = pp2_ppio_set_mru(priv->ppio, mru);
 473         if (ret) {
 474                 MRVL_LOG(ERR, "Failed to change MRU");
 475                 return ret;
 476         }
 477
 478         ret = pp2_ppio_set_mtu(priv->ppio, mtu);
 479         if (ret) {
 480                 MRVL_LOG(ERR, "Failed to change MTU");
 481                 return ret;
 482         }
 483
 484         return 0;
 485 }
 486
 487 /**
 488  * DPDK callback to bring the link up.
 489  *
 490  * @param dev
 491  *   Pointer to Ethernet device structure.
 492  *
 493  * @return
 494  *   0 on success, negative error value otherwise.
 495  */
 496 static int
 497 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
 498 {
 499         struct mrvl_priv *priv = dev->data->dev_private;
 500         int ret;
 501
 502         if (!priv->ppio) {
 503                 dev->data->dev_link.link_status = ETH_LINK_UP;
 504                 return 0;
 505         }
 506
 507         ret = pp2_ppio_enable(priv->ppio);
 508         if (ret)
 509                 return ret;
 510
 511         /*
 512          * mtu/mru can be updated if pp2_ppio_enable() was called at least once
 513          * as pp2_ppio_enable() changes port->t_mode from default 0 to
 514          * PP2_TRAFFIC_INGRESS_EGRESS.
 515          *
 516          * Set mtu to default DPDK value here.
 517          */
 518         ret = mrvl_mtu_set(dev, dev->data->mtu);
 519         if (ret) {
 520                 pp2_ppio_disable(priv->ppio);
 521                 return ret;
 522         }
 523
 524         dev->data->dev_link.link_status = ETH_LINK_UP;
 525         return 0;
 526 }
 527
 528 /**
 529  * DPDK callback to bring the link down.
 530  *
 531  * @param dev
 532  *   Pointer to Ethernet device structure.
 533  *
 534  * @return
 535  *   0 on success, negative error value otherwise.
 536  */
 537 static int
 538 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
 539 {
 540         struct mrvl_priv *priv = dev->data->dev_private;
 541         int ret;
 542
 543         if (!priv->ppio) {
 544                 dev->data->dev_link.link_status = ETH_LINK_DOWN;
 545                 return 0;
 546         }
 547         ret = pp2_ppio_disable(priv->ppio);
 548         if (ret)
 549                 return ret;
 550
 551         dev->data->dev_link.link_status = ETH_LINK_DOWN;
 552         return 0;
 553 }
 554
 555 /**
 556  * DPDK callback to start tx queue.
 557  *
 558  * @param dev
 559  *   Pointer to Ethernet device structure.
 560  * @param queue_id
 561  *   Transmit queue index.
 562  *
 563  * @return
 564  *   0 on success, negative error value otherwise.
 565  */
 566 static int
 567 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
 568 {
 569         struct mrvl_priv *priv = dev->data->dev_private;
 570         int ret;
 571
 572         if (!priv)
 573                 return -EPERM;
 574
 575         /* passing 1 enables given tx queue */
 576         ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
 577         if (ret) {
 578                 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
 579                 return ret;
 580         }
 581
 582         dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 583
 584         return 0;
 585 }
 586
 587 /**
 588  * DPDK callback to stop tx queue.
 589  *
 590  * @param dev
 591  *   Pointer to Ethernet device structure.
 592  * @param queue_id
 593  *   Transmit queue index.
 594  *
 595  * @return
 596  *   0 on success, negative error value otherwise.
 597  */
 598 static int
 599 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
 600 {
 601         struct mrvl_priv *priv = dev->data->dev_private;
 602         int ret;
 603
 604         if (!priv->ppio)
 605                 return -EPERM;
 606
 607         /* passing 0 disables given tx queue */
 608         ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
 609         if (ret) {
 610                 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
 611                 return ret;
 612         }
 613
 614         dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 615
 616         return 0;
 617 }
 618
 619 /**
 620  * DPDK callback to start the device.
 621  *
 622  * @param dev
 623  *   Pointer to Ethernet device structure.
 624  *
 625  * @return
 626  *   0 on success, negative errno value on failure.
 627  */
 628 static int
 629 mrvl_dev_start(struct rte_eth_dev *dev)
 630 {
 631         struct mrvl_priv *priv = dev->data->dev_private;
 632         char match[MRVL_MATCH_LEN];
 633         int ret = 0, i, def_init_size;
 634         uint32_t j;
 635         struct rte_vlan_filter_conf *vfc;
 636         struct rte_ether_addr *mac_addr;
 637
 638         if (priv->ppio)
 639                 return mrvl_dev_set_link_up(dev);
 640
 641         snprintf(match, sizeof(match), "ppio-%d:%d",
 642                  priv->pp_id, priv->ppio_id);
 643         priv->ppio_params.match = match;
 644
 645         /*
 646          * Calculate the minimum bpool size for refill feature as follows:
 647          * 2 default burst sizes multiply by number of rx queues.
 648          * If the bpool size will be below this value, new buffers will
 649          * be added to the pool.
 650          */
 651         priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
 652
 653         /* In case initial bpool size configured in queues setup is
 654          * smaller than minimum size add more buffers
 655          */
 656         def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
 657         if (priv->bpool_init_size < def_init_size) {
 658                 int buffs_to_add = def_init_size - priv->bpool_init_size;
 659
 660                 priv->bpool_init_size += buffs_to_add;
 661                 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
 662                 if (ret)
 663                         MRVL_LOG(ERR, "Failed to add buffers to bpool");
 664         }
 665
 666         /*
 667          * Calculate the maximum bpool size for refill feature as follows:
 668          * maximum number of descriptors in rx queue multiply by number
 669          * of rx queues plus minimum bpool size.
 670          * In case the bpool size will exceed this value, superfluous buffers
 671          * will be removed
 672          */
 673         priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
 674                                 priv->bpool_min_size;
 675
 676         ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
 677         if (ret) {
 678                 MRVL_LOG(ERR, "Failed to init ppio");
 679                 return ret;
 680         }
 681
 682         /*
 683          * In case there are some some stale uc/mc mac addresses flush them
 684          * here. It cannot be done during mrvl_dev_close() as port information
 685          * is already gone at that point (due to pp2_ppio_deinit() in
 686          * mrvl_dev_stop()).
 687          */
 688         if (!priv->uc_mc_flushed) {
 689                 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
 690                 if (ret) {
 691                         MRVL_LOG(ERR,
 692                                 "Failed to flush uc/mc filter list");
 693                         goto out;
 694                 }
 695                 priv->uc_mc_flushed = 1;
 696         }
 697
 698         ret = mrvl_mtu_set(dev, dev->data->mtu);
 699         if (ret)
 700                 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu);
 701
 702         if (!rte_is_zero_ether_addr(&dev->data->mac_addrs[0]))
 703                 mrvl_mac_addr_set(dev, &dev->data->mac_addrs[0]);
 704
 705         for (i = 1; i < MRVL_MAC_ADDRS_MAX; i++) {
 706                 mac_addr = &dev->data->mac_addrs[i];
 707
 708                 /* skip zero address */
 709                 if (rte_is_zero_ether_addr(mac_addr))
 710                         continue;
 711
 712                 mrvl_mac_addr_add(dev, mac_addr, i, 0);
 713         }
 714
 715         if (dev->data->all_multicast == 1)
 716                 mrvl_allmulticast_enable(dev);
 717
 718         vfc = &dev->data->vlan_filter_conf;
 719         for (j = 0; j < RTE_DIM(vfc->ids); j++) {
 720                 uint64_t vlan;
 721                 uint64_t vbit;
 722                 uint64_t ids = vfc->ids[j];
 723
 724                 if (ids == 0)
 725                         continue;
 726
 727                 while (ids) {
 728                         vlan = 64 * j;
 729                         /* count trailing zeroes */
 730                         vbit = ~ids & (ids - 1);
 731                         /* clear least significant bit set */
 732                         ids ^= (ids ^ (ids - 1)) ^ vbit;
 733                         for (; vbit; vlan++)
 734                                 vbit >>= 1;
 735                         ret = mrvl_vlan_filter_set(dev, vlan, 1);
 736                         if (ret) {
 737                                 MRVL_LOG(ERR, "Failed to setup VLAN filter\n");
 738                                 goto out;
 739                         }
 740                 }
 741         }
 742
 743         /* For default QoS config, don't start classifier. */
 744         if (mrvl_qos_cfg  &&
 745             mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) {
 746                 ret = mrvl_start_qos_mapping(priv);
 747                 if (ret) {
 748                         MRVL_LOG(ERR, "Failed to setup QoS mapping");
 749                         goto out;
 750                 }
 751         }
 752
 753         if (dev->data->promiscuous == 1)
 754                 mrvl_promiscuous_enable(dev);
 755
 756         if (dev->data->dev_link.link_status == ETH_LINK_UP) {
 757                 ret = mrvl_dev_set_link_up(dev);
 758                 if (ret) {
 759                         MRVL_LOG(ERR, "Failed to set link up");
 760                         dev->data->dev_link.link_status = ETH_LINK_DOWN;
 761                         goto out;
 762                 }
 763         }
 764
 765         /* start tx queues */
 766         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 767                 struct mrvl_txq *txq = dev->data->tx_queues[i];
 768
 769                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
 770
 771                 if (!txq->tx_deferred_start)
 772                         continue;
 773
 774                 /*
 775                  * All txqs are started by default. Stop them
 776                  * so that tx_deferred_start works as expected.
 777                  */
 778                 ret = mrvl_tx_queue_stop(dev, i);
 779                 if (ret)
 780                         goto out;
 781         }
 782
 783         mrvl_flow_init(dev);
 784         mrvl_mtr_init(dev);
 785         mrvl_set_tx_function(dev);
 786
 787         return 0;
 788 out:
 789         MRVL_LOG(ERR, "Failed to start device");
 790         pp2_ppio_deinit(priv->ppio);
 791         return ret;
 792 }
 793
 794 /**
 795  * Flush receive queues.
 796  *
 797  * @param dev
 798  *   Pointer to Ethernet device structure.
 799  */
 800 static void
 801 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
 802 {
 803         int i;
 804
 805         MRVL_LOG(INFO, "Flushing rx queues");
 806         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 807                 int ret, num;
 808
 809                 do {
 810                         struct mrvl_rxq *q = dev->data->rx_queues[i];
 811                         struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
 812
 813                         num = MRVL_PP2_RXD_MAX;
 814                         ret = pp2_ppio_recv(q->priv->ppio,
 815                                             q->priv->rxq_map[q->queue_id].tc,
 816                                             q->priv->rxq_map[q->queue_id].inq,
 817                                             descs, (uint16_t *)&num);
 818                 } while (ret == 0 && num);
 819         }
 820 }
 821
 822 /**
 823  * Flush transmit shadow queues.
 824  *
 825  * @param dev
 826  *   Pointer to Ethernet device structure.
 827  */
 828 static void
 829 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
 830 {
 831         int i, j;
 832         struct mrvl_txq *txq;
 833
 834         MRVL_LOG(INFO, "Flushing tx shadow queues");
 835         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 836                 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
 837
 838                 for (j = 0; j < RTE_MAX_LCORE; j++) {
 839                         struct mrvl_shadow_txq *sq;
 840
 841                         if (!hifs[j])
 842                                 continue;
 843
 844                         sq = &txq->shadow_txqs[j];
 845                         mrvl_free_sent_buffers(txq->priv->ppio,
 846                                 hifs[j], j, sq, txq->queue_id, 1);
 847                         while (sq->tail != sq->head) {
 848                                 uint64_t addr = cookie_addr_high |
 849                                         sq->ent[sq->tail].buff.cookie;
 850                                 rte_pktmbuf_free(
 851                                         (struct rte_mbuf *)addr);
 852                                 sq->tail = (sq->tail + 1) &
 853                                             MRVL_PP2_TX_SHADOWQ_MASK;
 854                         }
 855                         memset(sq, 0, sizeof(*sq));
 856                 }
 857         }
 858 }
 859
 860 /**
 861  * Flush hardware bpool (buffer-pool).
 862  *
 863  * @param dev
 864  *   Pointer to Ethernet device structure.
 865  */
 866 static void
 867 mrvl_flush_bpool(struct rte_eth_dev *dev)
 868 {
 869         struct mrvl_priv *priv = dev->data->dev_private;
 870         struct pp2_hif *hif;
 871         uint32_t num;
 872         int ret;
 873         unsigned int core_id = rte_lcore_id();
 874
 875         if (core_id == LCORE_ID_ANY)
 876                 core_id = rte_get_main_lcore();
 877
 878         hif = mrvl_get_hif(priv, core_id);
 879
 880         ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
 881         if (ret) {
 882                 MRVL_LOG(ERR, "Failed to get bpool buffers number");
 883                 return;
 884         }
 885
 886         while (num--) {
 887                 struct pp2_buff_inf inf;
 888                 uint64_t addr;
 889
 890                 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
 891                 if (ret)
 892                         break;
 893
 894                 addr = cookie_addr_high | inf.cookie;
 895                 rte_pktmbuf_free((struct rte_mbuf *)addr);
 896         }
 897 }
 898
 899 /**
 900  * DPDK callback to stop the device.
 901  *
 902  * @param dev
 903  *   Pointer to Ethernet device structure.
 904  */
 905 static int
 906 mrvl_dev_stop(struct rte_eth_dev *dev)
 907 {
 908         return mrvl_dev_set_link_down(dev);
 909 }
 910
 911 /**
 912  * DPDK callback to close the device.
 913  *
 914  * @param dev
 915  *   Pointer to Ethernet device structure.
 916  */
 917 static int
 918 mrvl_dev_close(struct rte_eth_dev *dev)
 919 {
 920         struct mrvl_priv *priv = dev->data->dev_private;
 921         size_t i;
 922
 923         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 924                 return 0;
 925
 926         mrvl_flush_rx_queues(dev);
 927         mrvl_flush_tx_shadow_queues(dev);
 928         mrvl_flow_deinit(dev);
 929         mrvl_mtr_deinit(dev);
 930
 931         for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
 932                 struct pp2_ppio_tc_params *tc_params =
 933                         &priv->ppio_params.inqs_params.tcs_params[i];
 934
 935                 if (tc_params->inqs_params) {
 936                         rte_free(tc_params->inqs_params);
 937                         tc_params->inqs_params = NULL;
 938                 }
 939         }
 940
 941         if (priv->cls_tbl) {
 942                 pp2_cls_tbl_deinit(priv->cls_tbl);
 943                 priv->cls_tbl = NULL;
 944         }
 945
 946         if (priv->qos_tbl) {
 947                 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
 948                 priv->qos_tbl = NULL;
 949         }
 950
 951         mrvl_flush_bpool(dev);
 952         mrvl_tm_deinit(dev);
 953
 954         if (priv->ppio) {
 955                 pp2_ppio_deinit(priv->ppio);
 956                 priv->ppio = NULL;
 957         }
 958
 959         /* policer must be released after ppio deinitialization */
 960         if (priv->default_policer) {
 961                 pp2_cls_plcr_deinit(priv->default_policer);
 962                 priv->default_policer = NULL;
 963         }
 964
 965
 966         if (priv->bpool) {
 967                 pp2_bpool_deinit(priv->bpool);
 968                 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
 969                 priv->bpool = NULL;
 970         }
 971
 972         mrvl_dev_num--;
 973
 974         if (mrvl_dev_num == 0) {
 975                 MRVL_LOG(INFO, "Perform MUSDK deinit");
 976                 mrvl_deinit_hifs();
 977                 mrvl_deinit_pp2();
 978                 rte_mvep_deinit(MVEP_MOD_T_PP2);
 979         }
 980
 981         return 0;
 982 }
 983
 984 /**
 985  * DPDK callback to retrieve physical link information.
 986  *
 987  * @param dev
 988  *   Pointer to Ethernet device structure.
 989  * @param wait_to_complete
 990  *   Wait for request completion (ignored).
 991  *
 992  * @return
 993  *   0 on success, negative error value otherwise.
 994  */
 995 static int
 996 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
 997 {
 998         /*
 999          * TODO
1000          * once MUSDK provides necessary API use it here
1001          */
1002         struct mrvl_priv *priv = dev->data->dev_private;
1003         struct ethtool_cmd edata;
1004         struct ifreq req;
1005         int ret, fd, link_up;
1006
1007         if (!priv->ppio)
1008                 return -EPERM;
1009
1010         edata.cmd = ETHTOOL_GSET;
1011
1012         strcpy(req.ifr_name, dev->data->name);
1013         req.ifr_data = (void *)&edata;
1014
1015         fd = socket(AF_INET, SOCK_DGRAM, 0);
1016         if (fd == -1)
1017                 return -EFAULT;
1018
1019         ret = ioctl(fd, SIOCETHTOOL, &req);
1020         if (ret == -1) {
1021                 close(fd);
1022                 return -EFAULT;
1023         }
1024
1025         close(fd);
1026
1027         switch (ethtool_cmd_speed(&edata)) {
1028         case SPEED_10:
1029                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
1030                 break;
1031         case SPEED_100:
1032                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
1033                 break;
1034         case SPEED_1000:
1035                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
1036                 break;
1037         case SPEED_10000:
1038                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
1039                 break;
1040         default:
1041                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
1042         }
1043
1044         dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
1045                                                          ETH_LINK_HALF_DUPLEX;
1046         dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
1047                                                            ETH_LINK_FIXED;
1048         pp2_ppio_get_link_state(priv->ppio, &link_up);
1049         dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1050
1051         return 0;
1052 }
1053
1054 /**
1055  * DPDK callback to enable promiscuous mode.
1056  *
1057  * @param dev
1058  *   Pointer to Ethernet device structure.
1059  *
1060  * @return
1061  *   0 on success, negative error value otherwise.
1062  */
1063 static int
1064 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
1065 {
1066         struct mrvl_priv *priv = dev->data->dev_private;
1067         int ret;
1068
1069         if (priv->isolated)
1070                 return -ENOTSUP;
1071
1072         if (!priv->ppio)
1073                 return 0;
1074
1075         ret = pp2_ppio_set_promisc(priv->ppio, 1);
1076         if (ret) {
1077                 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
1078                 return -EAGAIN;
1079         }
1080
1081         return 0;
1082 }
1083
1084 /**
1085  * DPDK callback to enable allmulti mode.
1086  *
1087  * @param dev
1088  *   Pointer to Ethernet device structure.
1089  *
1090  * @return
1091  *   0 on success, negative error value otherwise.
1092  */
1093 static int
1094 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
1095 {
1096         struct mrvl_priv *priv = dev->data->dev_private;
1097         int ret;
1098
1099         if (priv->isolated)
1100                 return -ENOTSUP;
1101
1102         if (!priv->ppio)
1103                 return 0;
1104
1105         ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
1106         if (ret) {
1107                 MRVL_LOG(ERR, "Failed enable all-multicast mode");
1108                 return -EAGAIN;
1109         }
1110
1111         return 0;
1112 }
1113
1114 /**
1115  * DPDK callback to disable promiscuous mode.
1116  *
1117  * @param dev
1118  *   Pointer to Ethernet device structure.
1119  *
1120  * @return
1121  *   0 on success, negative error value otherwise.
1122  */
1123 static int
1124 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
1125 {
1126         struct mrvl_priv *priv = dev->data->dev_private;
1127         int ret;
1128
1129         if (priv->isolated)
1130                 return -ENOTSUP;
1131
1132         if (!priv->ppio)
1133                 return 0;
1134
1135         ret = pp2_ppio_set_promisc(priv->ppio, 0);
1136         if (ret) {
1137                 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
1138                 return -EAGAIN;
1139         }
1140
1141         return 0;
1142 }
1143
1144 /**
1145  * DPDK callback to disable allmulticast mode.
1146  *
1147  * @param dev
1148  *   Pointer to Ethernet device structure.
1149  *
1150  * @return
1151  *   0 on success, negative error value otherwise.
1152  */
1153 static int
1154 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
1155 {
1156         struct mrvl_priv *priv = dev->data->dev_private;
1157         int ret;
1158
1159         if (priv->isolated)
1160                 return -ENOTSUP;
1161
1162         if (!priv->ppio)
1163                 return 0;
1164
1165         ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
1166         if (ret) {
1167                 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
1168                 return -EAGAIN;
1169         }
1170
1171         return 0;
1172 }
1173
1174 /**
1175  * DPDK callback to remove a MAC address.
1176  *
1177  * @param dev
1178  *   Pointer to Ethernet device structure.
1179  * @param index
1180  *   MAC address index.
1181  */
1182 static void
1183 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
1184 {
1185         struct mrvl_priv *priv = dev->data->dev_private;
1186         char buf[RTE_ETHER_ADDR_FMT_SIZE];
1187         int ret;
1188
1189         if (priv->isolated)
1190                 return;
1191
1192         if (!priv->ppio)
1193                 return;
1194
1195         ret = pp2_ppio_remove_mac_addr(priv->ppio,
1196                                        dev->data->mac_addrs[index].addr_bytes);
1197         if (ret) {
1198                 rte_ether_format_addr(buf, sizeof(buf),
1199                                   &dev->data->mac_addrs[index]);
1200                 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
1201         }
1202 }
1203
1204 /**
1205  * DPDK callback to add a MAC address.
1206  *
1207  * @param dev
1208  *   Pointer to Ethernet device structure.
1209  * @param mac_addr
1210  *   MAC address to register.
1211  * @param index
1212  *   MAC address index.
1213  * @param vmdq
1214  *   VMDq pool index to associate address with (unused).
1215  *
1216  * @return
1217  *   0 on success, negative error value otherwise.
1218  */
1219 static int
1220 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1221                   uint32_t index, uint32_t vmdq __rte_unused)
1222 {
1223         struct mrvl_priv *priv = dev->data->dev_private;
1224         char buf[RTE_ETHER_ADDR_FMT_SIZE];
1225         int ret;
1226
1227         if (priv->isolated)
1228                 return -ENOTSUP;
1229
1230         if (!priv->ppio)
1231                 return 0;
1232
1233         if (index == 0)
1234                 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1235                 return -1;
1236
1237         /*
1238          * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1239          * parameter uc_filter_max. Maximum number of mc addresses is then
1240          * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1241          * 21 respectively.
1242          *
1243          * If more than uc_filter_max uc addresses were added to filter list
1244          * then NIC will switch to promiscuous mode automatically.
1245          *
1246          * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1247          * were added to filter list then NIC will switch to all-multicast mode
1248          * automatically.
1249          */
1250         ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1251         if (ret) {
1252                 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1253                 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1254                 return -1;
1255         }
1256
1257         return 0;
1258 }
1259
1260 /**
1261  * DPDK callback to set the primary MAC address.
1262  *
1263  * @param dev
1264  *   Pointer to Ethernet device structure.
1265  * @param mac_addr
1266  *   MAC address to register.
1267  *
1268  * @return
1269  *   0 on success, negative error value otherwise.
1270  */
1271 static int
1272 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1273 {
1274         struct mrvl_priv *priv = dev->data->dev_private;
1275         int ret;
1276
1277         if (priv->isolated)
1278                 return -ENOTSUP;
1279
1280         if (!priv->ppio)
1281                 return 0;
1282
1283         ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1284         if (ret) {
1285                 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1286                 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1287                 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1288         }
1289
1290         return ret;
1291 }
1292
1293 /**
1294  * DPDK callback to get device statistics.
1295  *
1296  * @param dev
1297  *   Pointer to Ethernet device structure.
1298  * @param stats
1299  *   Stats structure output buffer.
1300  *
1301  * @return
1302  *   0 on success, negative error value otherwise.
1303  */
1304 static int
1305 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1306 {
1307         struct mrvl_priv *priv = dev->data->dev_private;
1308         struct pp2_ppio_statistics ppio_stats;
1309         uint64_t drop_mac = 0;
1310         unsigned int i, idx, ret;
1311
1312         if (!priv->ppio)
1313                 return -EPERM;
1314
1315         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1316                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1317                 struct pp2_ppio_inq_statistics rx_stats;
1318
1319                 if (!rxq)
1320                         continue;
1321
1322                 idx = rxq->queue_id;
1323                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1324                         MRVL_LOG(ERR,
1325                                 "rx queue %d stats out of range (0 - %d)",
1326                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1327                         continue;
1328                 }
1329
1330                 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1331                                                   priv->rxq_map[idx].tc,
1332                                                   priv->rxq_map[idx].inq,
1333                                                   &rx_stats, 0);
1334                 if (unlikely(ret)) {
1335                         MRVL_LOG(ERR,
1336                                 "Failed to update rx queue %d stats", idx);
1337                         break;
1338                 }
1339
1340                 stats->q_ibytes[idx] = rxq->bytes_recv;
1341                 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1342                 stats->q_errors[idx] = rx_stats.drop_early +
1343                                        rx_stats.drop_fullq +
1344                                        rx_stats.drop_bm +
1345                                        rxq->drop_mac;
1346                 stats->ibytes += rxq->bytes_recv;
1347                 drop_mac += rxq->drop_mac;
1348         }
1349
1350         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1351                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1352                 struct pp2_ppio_outq_statistics tx_stats;
1353
1354                 if (!txq)
1355                         continue;
1356
1357                 idx = txq->queue_id;
1358                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1359                         MRVL_LOG(ERR,
1360                                 "tx queue %d stats out of range (0 - %d)",
1361                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1362                 }
1363
1364                 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1365                                                    &tx_stats, 0);
1366                 if (unlikely(ret)) {
1367                         MRVL_LOG(ERR,
1368                                 "Failed to update tx queue %d stats", idx);
1369                         break;
1370                 }
1371
1372                 stats->q_opackets[idx] = tx_stats.deq_desc;
1373                 stats->q_obytes[idx] = txq->bytes_sent;
1374                 stats->obytes += txq->bytes_sent;
1375         }
1376
1377         ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1378         if (unlikely(ret)) {
1379                 MRVL_LOG(ERR, "Failed to update port statistics");
1380                 return ret;
1381         }
1382
1383         stats->ipackets += ppio_stats.rx_packets - drop_mac;
1384         stats->opackets += ppio_stats.tx_packets;
1385         stats->imissed += ppio_stats.rx_fullq_dropped +
1386                           ppio_stats.rx_bm_dropped +
1387                           ppio_stats.rx_early_dropped +
1388                           ppio_stats.rx_fifo_dropped +
1389                           ppio_stats.rx_cls_dropped;
1390         stats->ierrors = drop_mac;
1391
1392         return 0;
1393 }
1394
1395 /**
1396  * DPDK callback to clear device statistics.
1397  *
1398  * @param dev
1399  *   Pointer to Ethernet device structure.
1400  *
1401  * @return
1402  *   0 on success, negative error value otherwise.
1403  */
1404 static int
1405 mrvl_stats_reset(struct rte_eth_dev *dev)
1406 {
1407         struct mrvl_priv *priv = dev->data->dev_private;
1408         int i;
1409
1410         if (!priv->ppio)
1411                 return 0;
1412
1413         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1414                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1415
1416                 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1417                                             priv->rxq_map[i].inq, NULL, 1);
1418                 rxq->bytes_recv = 0;
1419                 rxq->drop_mac = 0;
1420         }
1421
1422         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1423                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1424
1425                 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1426                 txq->bytes_sent = 0;
1427         }
1428
1429         return pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1430 }
1431
1432 /**
1433  * DPDK callback to get extended statistics.
1434  *
1435  * @param dev
1436  *   Pointer to Ethernet device structure.
1437  * @param stats
1438  *   Pointer to xstats table.
1439  * @param n
1440  *   Number of entries in xstats table.
1441  * @return
1442  *   Negative value on error, number of read xstats otherwise.
1443  */
1444 static int
1445 mrvl_xstats_get(struct rte_eth_dev *dev,
1446                 struct rte_eth_xstat *stats, unsigned int n)
1447 {
1448         struct mrvl_priv *priv = dev->data->dev_private;
1449         struct pp2_ppio_statistics ppio_stats;
1450         unsigned int i;
1451
1452         if (!stats)
1453                 return 0;
1454
1455         pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1456         for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1457                 uint64_t val;
1458
1459                 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1460                         val = *(uint32_t *)((uint8_t *)&ppio_stats +
1461                                             mrvl_xstats_tbl[i].offset);
1462                 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1463                         val = *(uint64_t *)((uint8_t *)&ppio_stats +
1464                                             mrvl_xstats_tbl[i].offset);
1465                 else
1466                         return -EINVAL;
1467
1468                 stats[i].id = i;
1469                 stats[i].value = val;
1470         }
1471
1472         return n;
1473 }
1474
1475 /**
1476  * DPDK callback to reset extended statistics.
1477  *
1478  * @param dev
1479  *   Pointer to Ethernet device structure.
1480  *
1481  * @return
1482  *   0 on success, negative error value otherwise.
1483  */
1484 static int
1485 mrvl_xstats_reset(struct rte_eth_dev *dev)
1486 {
1487         return mrvl_stats_reset(dev);
1488 }
1489
1490 /**
1491  * DPDK callback to get extended statistics names.
1492  *
1493  * @param dev (unused)
1494  *   Pointer to Ethernet device structure.
1495  * @param xstats_names
1496  *   Pointer to xstats names table.
1497  * @param size
1498  *   Size of the xstats names table.
1499  * @return
1500  *   Number of read names.
1501  */
1502 static int
1503 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1504                       struct rte_eth_xstat_name *xstats_names,
1505                       unsigned int size)
1506 {
1507         unsigned int i;
1508
1509         if (!xstats_names)
1510                 return RTE_DIM(mrvl_xstats_tbl);
1511
1512         for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1513                 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name,
1514                         RTE_ETH_XSTATS_NAME_SIZE);
1515
1516         return size;
1517 }
1518
1519 /**
1520  * DPDK callback to get information about the device.
1521  *
1522  * @param dev
1523  *   Pointer to Ethernet device structure (unused).
1524  * @param info
1525  *   Info structure output buffer.
1526  */
1527 static int
1528 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1529                    struct rte_eth_dev_info *info)
1530 {
1531         info->speed_capa = ETH_LINK_SPEED_10M |
1532                            ETH_LINK_SPEED_100M |
1533                            ETH_LINK_SPEED_1G |
1534                            ETH_LINK_SPEED_10G;
1535
1536         info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1537         info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1538         info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1539
1540         info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1541         info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1542         info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1543
1544         info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1545         info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1546         info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1547
1548         info->rx_offload_capa = MRVL_RX_OFFLOADS;
1549         info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1550
1551         info->tx_offload_capa = MRVL_TX_OFFLOADS;
1552         info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1553
1554         info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1555                                        ETH_RSS_NONFRAG_IPV4_TCP |
1556                                        ETH_RSS_NONFRAG_IPV4_UDP;
1557
1558         /* By default packets are dropped if no descriptors are available */
1559         info->default_rxconf.rx_drop_en = 1;
1560
1561         info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1562
1563         return 0;
1564 }
1565
1566 /**
1567  * Return supported packet types.
1568  *
1569  * @param dev
1570  *   Pointer to Ethernet device structure (unused).
1571  *
1572  * @return
1573  *   Const pointer to the table with supported packet types.
1574  */
1575 static const uint32_t *
1576 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1577 {
1578         static const uint32_t ptypes[] = {
1579                 RTE_PTYPE_L2_ETHER,
1580                 RTE_PTYPE_L2_ETHER_VLAN,
1581                 RTE_PTYPE_L2_ETHER_QINQ,
1582                 RTE_PTYPE_L3_IPV4,
1583                 RTE_PTYPE_L3_IPV4_EXT,
1584                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1585                 RTE_PTYPE_L3_IPV6,
1586                 RTE_PTYPE_L3_IPV6_EXT,
1587                 RTE_PTYPE_L2_ETHER_ARP,
1588                 RTE_PTYPE_L4_TCP,
1589                 RTE_PTYPE_L4_UDP
1590         };
1591
1592         return ptypes;
1593 }
1594
1595 /**
1596  * DPDK callback to get information about specific receive queue.
1597  *
1598  * @param dev
1599  *   Pointer to Ethernet device structure.
1600  * @param rx_queue_id
1601  *   Receive queue index.
1602  * @param qinfo
1603  *   Receive queue information structure.
1604  */
1605 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1606                               struct rte_eth_rxq_info *qinfo)
1607 {
1608         struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1609         struct mrvl_priv *priv = dev->data->dev_private;
1610         int inq = priv->rxq_map[rx_queue_id].inq;
1611         int tc = priv->rxq_map[rx_queue_id].tc;
1612         struct pp2_ppio_tc_params *tc_params =
1613                 &priv->ppio_params.inqs_params.tcs_params[tc];
1614
1615         qinfo->mp = q->mp;
1616         qinfo->nb_desc = tc_params->inqs_params[inq].size;
1617 }
1618
1619 /**
1620  * DPDK callback to get information about specific transmit queue.
1621  *
1622  * @param dev
1623  *   Pointer to Ethernet device structure.
1624  * @param tx_queue_id
1625  *   Transmit queue index.
1626  * @param qinfo
1627  *   Transmit queue information structure.
1628  */
1629 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1630                               struct rte_eth_txq_info *qinfo)
1631 {
1632         struct mrvl_priv *priv = dev->data->dev_private;
1633         struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1634
1635         qinfo->nb_desc =
1636                 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1637         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1638 }
1639
1640 /**
1641  * DPDK callback to Configure a VLAN filter.
1642  *
1643  * @param dev
1644  *   Pointer to Ethernet device structure.
1645  * @param vlan_id
1646  *   VLAN ID to filter.
1647  * @param on
1648  *   Toggle filter.
1649  *
1650  * @return
1651  *   0 on success, negative error value otherwise.
1652  */
1653 static int
1654 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1655 {
1656         struct mrvl_priv *priv = dev->data->dev_private;
1657
1658         if (priv->isolated)
1659                 return -ENOTSUP;
1660
1661         if (!priv->ppio)
1662                 return 0;
1663
1664         return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1665                     pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1666 }
1667
1668 /**
1669  * Release buffers to hardware bpool (buffer-pool)
1670  *
1671  * @param rxq
1672  *   Receive queue pointer.
1673  * @param num
1674  *   Number of buffers to release to bpool.
1675  *
1676  * @return
1677  *   0 on success, negative error value otherwise.
1678  */
1679 static int
1680 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1681 {
1682         struct buff_release_entry entries[num];
1683         struct rte_mbuf *mbufs[num];
1684         int i, ret;
1685         unsigned int core_id;
1686         struct pp2_hif *hif;
1687         struct pp2_bpool *bpool;
1688
1689         core_id = rte_lcore_id();
1690         if (core_id == LCORE_ID_ANY)
1691                 core_id = rte_get_main_lcore();
1692
1693         hif = mrvl_get_hif(rxq->priv, core_id);
1694         if (!hif)
1695                 return -1;
1696
1697         bpool = rxq->priv->bpool;
1698
1699         ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1700         if (ret)
1701                 return ret;
1702
1703         if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1704                 cookie_addr_high =
1705                         (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1706
1707         for (i = 0; i < num; i++) {
1708                 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1709                         != cookie_addr_high) {
1710                         MRVL_LOG(ERR,
1711                                 "mbuf virtual addr high is out of range "
1712                                 "0x%x instead of 0x%x\n",
1713                                 (uint32_t)((uint64_t)mbufs[i] >> 32),
1714                                 (uint32_t)(cookie_addr_high >> 32));
1715                         goto out;
1716                 }
1717
1718                 entries[i].buff.addr =
1719                         rte_mbuf_data_iova_default(mbufs[i]);
1720                 entries[i].buff.cookie = (uintptr_t)mbufs[i];
1721                 entries[i].bpool = bpool;
1722         }
1723
1724         pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1725         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1726
1727         if (i != num)
1728                 goto out;
1729
1730         return 0;
1731 out:
1732         for (; i < num; i++)
1733                 rte_pktmbuf_free(mbufs[i]);
1734
1735         return -1;
1736 }
1737
1738 /**
1739  * DPDK callback to configure the receive queue.
1740  *
1741  * @param dev
1742  *   Pointer to Ethernet device structure.
1743  * @param idx
1744  *   RX queue index.
1745  * @param desc
1746  *   Number of descriptors to configure in queue.
1747  * @param socket
1748  *   NUMA socket on which memory must be allocated.
1749  * @param conf
1750  *   Thresholds parameters.
1751  * @param mp
1752  *   Memory pool for buffer allocations.
1753  *
1754  * @return
1755  *   0 on success, negative error value otherwise.
1756  */
1757 static int
1758 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1759                     unsigned int socket,
1760                     const struct rte_eth_rxconf *conf,
1761                     struct rte_mempool *mp)
1762 {
1763         struct mrvl_priv *priv = dev->data->dev_private;
1764         struct mrvl_rxq *rxq;
1765         uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp);
1766         uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1767         int ret, tc, inq;
1768         uint64_t offloads;
1769
1770         offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1771
1772         if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1773                 /*
1774                  * Unknown TC mapping, mapping will not have a correct queue.
1775                  */
1776                 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1777                         idx, priv->ppio_id);
1778                 return -EFAULT;
1779         }
1780
1781         frame_size = buf_size - RTE_PKTMBUF_HEADROOM -
1782                      MRVL_PKT_EFFEC_OFFS + RTE_ETHER_CRC_LEN;
1783         if (frame_size < max_rx_pkt_len) {
1784                 MRVL_LOG(WARNING,
1785                         "Mbuf size must be increased to %u bytes to hold up "
1786                         "to %u bytes of data.",
1787                         buf_size + max_rx_pkt_len - frame_size,
1788                         max_rx_pkt_len);
1789                 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1790                 MRVL_LOG(INFO, "Setting max rx pkt len to %u",
1791                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
1792         }
1793
1794         if (dev->data->rx_queues[idx]) {
1795                 rte_free(dev->data->rx_queues[idx]);
1796                 dev->data->rx_queues[idx] = NULL;
1797         }
1798
1799         rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1800         if (!rxq)
1801                 return -ENOMEM;
1802
1803         rxq->priv = priv;
1804         rxq->mp = mp;
1805         rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1806         rxq->queue_id = idx;
1807         rxq->port_id = dev->data->port_id;
1808         mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1809
1810         tc = priv->rxq_map[rxq->queue_id].tc,
1811         inq = priv->rxq_map[rxq->queue_id].inq;
1812         priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1813                 desc;
1814
1815         ret = mrvl_fill_bpool(rxq, desc);
1816         if (ret) {
1817                 rte_free(rxq);
1818                 return ret;
1819         }
1820
1821         priv->bpool_init_size += desc;
1822
1823         dev->data->rx_queues[idx] = rxq;
1824
1825         return 0;
1826 }
1827
1828 /**
1829  * DPDK callback to release the receive queue.
1830  *
1831  * @param rxq
1832  *   Generic receive queue pointer.
1833  */
1834 static void
1835 mrvl_rx_queue_release(void *rxq)
1836 {
1837         struct mrvl_rxq *q = rxq;
1838         struct pp2_ppio_tc_params *tc_params;
1839         int i, num, tc, inq;
1840         struct pp2_hif *hif;
1841         unsigned int core_id = rte_lcore_id();
1842
1843         if (core_id == LCORE_ID_ANY)
1844                 core_id = rte_get_main_lcore();
1845
1846         if (!q)
1847                 return;
1848
1849         hif = mrvl_get_hif(q->priv, core_id);
1850
1851         if (!hif)
1852                 return;
1853
1854         tc = q->priv->rxq_map[q->queue_id].tc;
1855         inq = q->priv->rxq_map[q->queue_id].inq;
1856         tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1857         num = tc_params->inqs_params[inq].size;
1858         for (i = 0; i < num; i++) {
1859                 struct pp2_buff_inf inf;
1860                 uint64_t addr;
1861
1862                 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1863                 addr = cookie_addr_high | inf.cookie;
1864                 rte_pktmbuf_free((struct rte_mbuf *)addr);
1865         }
1866
1867         rte_free(q);
1868 }
1869
1870 /**
1871  * DPDK callback to configure the transmit queue.
1872  *
1873  * @param dev
1874  *   Pointer to Ethernet device structure.
1875  * @param idx
1876  *   Transmit queue index.
1877  * @param desc
1878  *   Number of descriptors to configure in the queue.
1879  * @param socket
1880  *   NUMA socket on which memory must be allocated.
1881  * @param conf
1882  *   Tx queue configuration parameters.
1883  *
1884  * @return
1885  *   0 on success, negative error value otherwise.
1886  */
1887 static int
1888 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1889                     unsigned int socket,
1890                     const struct rte_eth_txconf *conf)
1891 {
1892         struct mrvl_priv *priv = dev->data->dev_private;
1893         struct mrvl_txq *txq;
1894
1895         if (dev->data->tx_queues[idx]) {
1896                 rte_free(dev->data->tx_queues[idx]);
1897                 dev->data->tx_queues[idx] = NULL;
1898         }
1899
1900         txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1901         if (!txq)
1902                 return -ENOMEM;
1903
1904         txq->priv = priv;
1905         txq->queue_id = idx;
1906         txq->port_id = dev->data->port_id;
1907         txq->tx_deferred_start = conf->tx_deferred_start;
1908         dev->data->tx_queues[idx] = txq;
1909
1910         priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1911
1912         return 0;
1913 }
1914
1915 /**
1916  * DPDK callback to release the transmit queue.
1917  *
1918  * @param txq
1919  *   Generic transmit queue pointer.
1920  */
1921 static void
1922 mrvl_tx_queue_release(void *txq)
1923 {
1924         struct mrvl_txq *q = txq;
1925
1926         if (!q)
1927                 return;
1928
1929         rte_free(q);
1930 }
1931
1932 /**
1933  * DPDK callback to get flow control configuration.
1934  *
1935  * @param dev
1936  *  Pointer to Ethernet device structure.
1937  * @param fc_conf
1938  *  Pointer to the flow control configuration.
1939  *
1940  * @return
1941  *  0 on success, negative error value otherwise.
1942  */
1943 static int
1944 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1945 {
1946         struct mrvl_priv *priv = dev->data->dev_private;
1947         int ret, en;
1948
1949         if (!priv)
1950                 return -EPERM;
1951
1952         ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1953         if (ret) {
1954                 MRVL_LOG(ERR, "Failed to read rx pause state");
1955                 return ret;
1956         }
1957
1958         fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1959
1960         return 0;
1961 }
1962
1963 /**
1964  * DPDK callback to set flow control configuration.
1965  *
1966  * @param dev
1967  *  Pointer to Ethernet device structure.
1968  * @param fc_conf
1969  *  Pointer to the flow control configuration.
1970  *
1971  * @return
1972  *  0 on success, negative error value otherwise.
1973  */
1974 static int
1975 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1976 {
1977         struct mrvl_priv *priv = dev->data->dev_private;
1978
1979         if (!priv)
1980                 return -EPERM;
1981
1982         if (fc_conf->high_water ||
1983             fc_conf->low_water ||
1984             fc_conf->pause_time ||
1985             fc_conf->mac_ctrl_frame_fwd ||
1986             fc_conf->autoneg) {
1987                 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1988
1989                 return -EINVAL;
1990         }
1991
1992         if (fc_conf->mode == RTE_FC_NONE ||
1993             fc_conf->mode == RTE_FC_RX_PAUSE) {
1994                 int ret, en;
1995
1996                 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1997                 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1998                 if (ret)
1999                         MRVL_LOG(ERR,
2000                                 "Failed to change flowctrl on RX side");
2001
2002                 return ret;
2003         }
2004
2005         return 0;
2006 }
2007
2008 /**
2009  * Update RSS hash configuration
2010  *
2011  * @param dev
2012  *   Pointer to Ethernet device structure.
2013  * @param rss_conf
2014  *   Pointer to RSS configuration.
2015  *
2016  * @return
2017  *   0 on success, negative error value otherwise.
2018  */
2019 static int
2020 mrvl_rss_hash_update(struct rte_eth_dev *dev,
2021                      struct rte_eth_rss_conf *rss_conf)
2022 {
2023         struct mrvl_priv *priv = dev->data->dev_private;
2024
2025         if (priv->isolated)
2026                 return -ENOTSUP;
2027
2028         return mrvl_configure_rss(priv, rss_conf);
2029 }
2030
2031 /**
2032  * DPDK callback to get RSS hash configuration.
2033  *
2034  * @param dev
2035  *   Pointer to Ethernet device structure.
2036  * @rss_conf
2037  *   Pointer to RSS configuration.
2038  *
2039  * @return
2040  *   Always 0.
2041  */
2042 static int
2043 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
2044                        struct rte_eth_rss_conf *rss_conf)
2045 {
2046         struct mrvl_priv *priv = dev->data->dev_private;
2047         enum pp2_ppio_hash_type hash_type =
2048                 priv->ppio_params.inqs_params.hash_type;
2049
2050         rss_conf->rss_key = NULL;
2051
2052         if (hash_type == PP2_PPIO_HASH_T_NONE)
2053                 rss_conf->rss_hf = 0;
2054         else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
2055                 rss_conf->rss_hf = ETH_RSS_IPV4;
2056         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
2057                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
2058         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
2059                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
2060
2061         return 0;
2062 }
2063
2064 /**
2065  * DPDK callback to get rte_flow callbacks.
2066  *
2067  * @param dev
2068  *   Pointer to the device structure.
2069  * @param filer_type
2070  *   Flow filter type.
2071  * @param filter_op
2072  *   Flow filter operation.
2073  * @param arg
2074  *   Pointer to pass the flow ops.
2075  *
2076  * @return
2077  *   0 on success, negative error value otherwise.
2078  */
2079 static int
2080 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
2081                      enum rte_filter_type filter_type,
2082                      enum rte_filter_op filter_op, void *arg)
2083 {
2084         switch (filter_type) {
2085         case RTE_ETH_FILTER_GENERIC:
2086                 if (filter_op != RTE_ETH_FILTER_GET)
2087                         return -EINVAL;
2088                 *(const void **)arg = &mrvl_flow_ops;
2089                 return 0;
2090         default:
2091                 MRVL_LOG(WARNING, "Filter type (%d) not supported",
2092                                 filter_type);
2093                 return -EINVAL;
2094         }
2095 }
2096
2097 /**
2098  * DPDK callback to get rte_mtr callbacks.
2099  *
2100  * @param dev
2101  *   Pointer to the device structure.
2102  * @param ops
2103  *   Pointer to pass the mtr ops.
2104  *
2105  * @return
2106  *   Always 0.
2107  */
2108 static int
2109 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2110 {
2111         *(const void **)ops = &mrvl_mtr_ops;
2112
2113         return 0;
2114 }
2115
2116 /**
2117  * DPDK callback to get rte_tm callbacks.
2118  *
2119  * @param dev
2120  *   Pointer to the device structure.
2121  * @param ops
2122  *   Pointer to pass the tm ops.
2123  *
2124  * @return
2125  *   Always 0.
2126  */
2127 static int
2128 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2129 {
2130         *(const void **)ops = &mrvl_tm_ops;
2131
2132         return 0;
2133 }
2134
2135 static const struct eth_dev_ops mrvl_ops = {
2136         .dev_configure = mrvl_dev_configure,
2137         .dev_start = mrvl_dev_start,
2138         .dev_stop = mrvl_dev_stop,
2139         .dev_set_link_up = mrvl_dev_set_link_up,
2140         .dev_set_link_down = mrvl_dev_set_link_down,
2141         .dev_close = mrvl_dev_close,
2142         .link_update = mrvl_link_update,
2143         .promiscuous_enable = mrvl_promiscuous_enable,
2144         .allmulticast_enable = mrvl_allmulticast_enable,
2145         .promiscuous_disable = mrvl_promiscuous_disable,
2146         .allmulticast_disable = mrvl_allmulticast_disable,
2147         .mac_addr_remove = mrvl_mac_addr_remove,
2148         .mac_addr_add = mrvl_mac_addr_add,
2149         .mac_addr_set = mrvl_mac_addr_set,
2150         .mtu_set = mrvl_mtu_set,
2151         .stats_get = mrvl_stats_get,
2152         .stats_reset = mrvl_stats_reset,
2153         .xstats_get = mrvl_xstats_get,
2154         .xstats_reset = mrvl_xstats_reset,
2155         .xstats_get_names = mrvl_xstats_get_names,
2156         .dev_infos_get = mrvl_dev_infos_get,
2157         .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
2158         .rxq_info_get = mrvl_rxq_info_get,
2159         .txq_info_get = mrvl_txq_info_get,
2160         .vlan_filter_set = mrvl_vlan_filter_set,
2161         .tx_queue_start = mrvl_tx_queue_start,
2162         .tx_queue_stop = mrvl_tx_queue_stop,
2163         .rx_queue_setup = mrvl_rx_queue_setup,
2164         .rx_queue_release = mrvl_rx_queue_release,
2165         .tx_queue_setup = mrvl_tx_queue_setup,
2166         .tx_queue_release = mrvl_tx_queue_release,
2167         .flow_ctrl_get = mrvl_flow_ctrl_get,
2168         .flow_ctrl_set = mrvl_flow_ctrl_set,
2169         .rss_hash_update = mrvl_rss_hash_update,
2170         .rss_hash_conf_get = mrvl_rss_hash_conf_get,
2171         .filter_ctrl = mrvl_eth_filter_ctrl,
2172         .mtr_ops_get = mrvl_mtr_ops_get,
2173         .tm_ops_get = mrvl_tm_ops_get,
2174 };
2175
2176 /**
2177  * Return packet type information and l3/l4 offsets.
2178  *
2179  * @param desc
2180  *   Pointer to the received packet descriptor.
2181  * @param l3_offset
2182  *   l3 packet offset.
2183  * @param l4_offset
2184  *   l4 packet offset.
2185  *
2186  * @return
2187  *   Packet type information.
2188  */
2189 static inline uint64_t
2190 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2191                                     uint8_t *l3_offset, uint8_t *l4_offset)
2192 {
2193         enum pp2_inq_l3_type l3_type;
2194         enum pp2_inq_l4_type l4_type;
2195         enum pp2_inq_vlan_tag vlan_tag;
2196         uint64_t packet_type;
2197
2198         pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2199         pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2200         pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
2201
2202         packet_type = RTE_PTYPE_L2_ETHER;
2203
2204         switch (vlan_tag) {
2205         case PP2_INQ_VLAN_TAG_SINGLE:
2206                 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
2207                 break;
2208         case PP2_INQ_VLAN_TAG_DOUBLE:
2209         case PP2_INQ_VLAN_TAG_TRIPLE:
2210                 packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
2211                 break;
2212         default:
2213                 break;
2214         }
2215
2216         switch (l3_type) {
2217         case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2218                 packet_type |= RTE_PTYPE_L3_IPV4;
2219                 break;
2220         case PP2_INQ_L3_TYPE_IPV4_OK:
2221                 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2222                 break;
2223         case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2224                 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2225                 break;
2226         case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2227                 packet_type |= RTE_PTYPE_L3_IPV6;
2228                 break;
2229         case PP2_INQ_L3_TYPE_IPV6_EXT:
2230                 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2231                 break;
2232         case PP2_INQ_L3_TYPE_ARP:
2233                 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2234                 /*
2235                  * In case of ARP l4_offset is set to wrong value.
2236                  * Set it to proper one so that later on mbuf->l3_len can be
2237                  * calculated subtracting l4_offset and l3_offset.
2238                  */
2239                 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2240                 break;
2241         default:
2242                 break;
2243         }
2244
2245         switch (l4_type) {
2246         case PP2_INQ_L4_TYPE_TCP:
2247                 packet_type |= RTE_PTYPE_L4_TCP;
2248                 break;
2249         case PP2_INQ_L4_TYPE_UDP:
2250                 packet_type |= RTE_PTYPE_L4_UDP;
2251                 break;
2252         default:
2253                 break;
2254         }
2255
2256         return packet_type;
2257 }
2258
2259 /**
2260  * Get offload information from the received packet descriptor.
2261  *
2262  * @param desc
2263  *   Pointer to the received packet descriptor.
2264  *
2265  * @return
2266  *   Mbuf offload flags.
2267  */
2268 static inline uint64_t
2269 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
2270 {
2271         uint64_t flags;
2272         enum pp2_inq_desc_status status;
2273
2274         status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2275         if (unlikely(status != PP2_DESC_ERR_OK))
2276                 flags = PKT_RX_IP_CKSUM_BAD;
2277         else
2278                 flags = PKT_RX_IP_CKSUM_GOOD;
2279
2280         status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2281         if (unlikely(status != PP2_DESC_ERR_OK))
2282                 flags |= PKT_RX_L4_CKSUM_BAD;
2283         else
2284                 flags |= PKT_RX_L4_CKSUM_GOOD;
2285
2286         return flags;
2287 }
2288
2289 /**
2290  * DPDK callback for receive.
2291  *
2292  * @param rxq
2293  *   Generic pointer to the receive queue.
2294  * @param rx_pkts
2295  *   Array to store received packets.
2296  * @param nb_pkts
2297  *   Maximum number of packets in array.
2298  *
2299  * @return
2300  *   Number of packets successfully received.
2301  */
2302 static uint16_t
2303 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2304 {
2305         struct mrvl_rxq *q = rxq;
2306         struct pp2_ppio_desc descs[nb_pkts];
2307         struct pp2_bpool *bpool;
2308         int i, ret, rx_done = 0;
2309         int num;
2310         struct pp2_hif *hif;
2311         unsigned int core_id = rte_lcore_id();
2312
2313         hif = mrvl_get_hif(q->priv, core_id);
2314
2315         if (unlikely(!q->priv->ppio || !hif))
2316                 return 0;
2317
2318         bpool = q->priv->bpool;
2319
2320         ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2321                             q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2322         if (unlikely(ret < 0))
2323                 return 0;
2324
2325         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2326
2327         for (i = 0; i < nb_pkts; i++) {
2328                 struct rte_mbuf *mbuf;
2329                 uint8_t l3_offset, l4_offset;
2330                 enum pp2_inq_desc_status status;
2331                 uint64_t addr;
2332
2333                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2334                         struct pp2_ppio_desc *pref_desc;
2335                         u64 pref_addr;
2336
2337                         pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2338                         pref_addr = cookie_addr_high |
2339                                     pp2_ppio_inq_desc_get_cookie(pref_desc);
2340                         rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2341                         rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2342                 }
2343
2344                 addr = cookie_addr_high |
2345                        pp2_ppio_inq_desc_get_cookie(&descs[i]);
2346                 mbuf = (struct rte_mbuf *)addr;
2347                 rte_pktmbuf_reset(mbuf);
2348
2349                 /* drop packet in case of mac, overrun or resource error */
2350                 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2351                 if (unlikely(status != PP2_DESC_ERR_OK)) {
2352                         struct pp2_buff_inf binf = {
2353                                 .addr = rte_mbuf_data_iova_default(mbuf),
2354                                 .cookie = (uint64_t)mbuf,
2355                         };
2356
2357                         pp2_bpool_put_buff(hif, bpool, &binf);
2358                         mrvl_port_bpool_size
2359                                 [bpool->pp2_id][bpool->id][core_id]++;
2360                         q->drop_mac++;
2361                         continue;
2362                 }
2363
2364                 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2365                 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2366                 mbuf->data_len = mbuf->pkt_len;
2367                 mbuf->port = q->port_id;
2368                 mbuf->packet_type =
2369                         mrvl_desc_to_packet_type_and_offset(&descs[i],
2370                                                             &l3_offset,
2371                                                             &l4_offset);
2372                 mbuf->l2_len = l3_offset;
2373                 mbuf->l3_len = l4_offset - l3_offset;
2374
2375                 if (likely(q->cksum_enabled))
2376                         mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2377
2378                 rx_pkts[rx_done++] = mbuf;
2379                 q->bytes_recv += mbuf->pkt_len;
2380         }
2381
2382         if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2383                 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2384
2385                 if (unlikely(num <= q->priv->bpool_min_size ||
2386                              (!rx_done && num < q->priv->bpool_init_size))) {
2387                         mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2388                 } else if (unlikely(num > q->priv->bpool_max_size)) {
2389                         int i;
2390                         int pkt_to_remove = num - q->priv->bpool_init_size;
2391                         struct rte_mbuf *mbuf;
2392                         struct pp2_buff_inf buff;
2393
2394                         for (i = 0; i < pkt_to_remove; i++) {
2395                                 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2396                                 if (ret)
2397                                         break;
2398                                 mbuf = (struct rte_mbuf *)
2399                                         (cookie_addr_high | buff.cookie);
2400                                 rte_pktmbuf_free(mbuf);
2401                         }
2402                         mrvl_port_bpool_size
2403                                 [bpool->pp2_id][bpool->id][core_id] -= i;
2404                 }
2405                 rte_spinlock_unlock(&q->priv->lock);
2406         }
2407
2408         return rx_done;
2409 }
2410
2411 /**
2412  * Prepare offload information.
2413  *
2414  * @param ol_flags
2415  *   Offload flags.
2416  * @param packet_type
2417  *   Packet type bitfield.
2418  * @param l3_type
2419  *   Pointer to the pp2_ouq_l3_type structure.
2420  * @param l4_type
2421  *   Pointer to the pp2_outq_l4_type structure.
2422  * @param gen_l3_cksum
2423  *   Will be set to 1 in case l3 checksum is computed.
2424  * @param l4_cksum
2425  *   Will be set to 1 in case l4 checksum is computed.
2426  *
2427  * @return
2428  *   0 on success, negative error value otherwise.
2429  */
2430 static inline int
2431 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2432                         enum pp2_outq_l3_type *l3_type,
2433                         enum pp2_outq_l4_type *l4_type,
2434                         int *gen_l3_cksum,
2435                         int *gen_l4_cksum)
2436 {
2437         /*
2438          * Based on ol_flags prepare information
2439          * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2440          * for offloading.
2441          */
2442         if (ol_flags & PKT_TX_IPV4) {
2443                 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2444                 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2445         } else if (ol_flags & PKT_TX_IPV6) {
2446                 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2447                 /* no checksum for ipv6 header */
2448                 *gen_l3_cksum = 0;
2449         } else {
2450                 /* if something different then stop processing */
2451                 return -1;
2452         }
2453
2454         ol_flags &= PKT_TX_L4_MASK;
2455         if ((packet_type & RTE_PTYPE_L4_TCP) &&
2456             ol_flags == PKT_TX_TCP_CKSUM) {
2457                 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2458                 *gen_l4_cksum = 1;
2459         } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2460                    ol_flags == PKT_TX_UDP_CKSUM) {
2461                 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2462                 *gen_l4_cksum = 1;
2463         } else {
2464                 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2465                 /* no checksum for other type */
2466                 *gen_l4_cksum = 0;
2467         }
2468
2469         return 0;
2470 }
2471
2472 /**
2473  * Release already sent buffers to bpool (buffer-pool).
2474  *
2475  * @param ppio
2476  *   Pointer to the port structure.
2477  * @param hif
2478  *   Pointer to the MUSDK hardware interface.
2479  * @param sq
2480  *   Pointer to the shadow queue.
2481  * @param qid
2482  *   Queue id number.
2483  * @param force
2484  *   Force releasing packets.
2485  */
2486 static inline void
2487 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2488                        unsigned int core_id, struct mrvl_shadow_txq *sq,
2489                        int qid, int force)
2490 {
2491         struct buff_release_entry *entry;
2492         uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2493         int i;
2494
2495         pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2496
2497         sq->num_to_release += nb_done;
2498
2499         if (likely(!force &&
2500                    sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2501                 return;
2502
2503         nb_done = sq->num_to_release;
2504         sq->num_to_release = 0;
2505
2506         for (i = 0; i < nb_done; i++) {
2507                 entry = &sq->ent[sq->tail + num];
2508                 if (unlikely(!entry->buff.addr)) {
2509                         MRVL_LOG(ERR,
2510                                 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2511                                 sq->tail, (u64)entry->buff.cookie,
2512                                 (u64)entry->buff.addr);
2513                         skip_bufs = 1;
2514                         goto skip;
2515                 }
2516
2517                 if (unlikely(!entry->bpool)) {
2518                         struct rte_mbuf *mbuf;
2519
2520                         mbuf = (struct rte_mbuf *)entry->buff.cookie;
2521                         rte_pktmbuf_free(mbuf);
2522                         skip_bufs = 1;
2523                         goto skip;
2524                 }
2525
2526                 mrvl_port_bpool_size
2527                         [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2528                 num++;
2529                 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2530                         goto skip;
2531                 continue;
2532 skip:
2533                 if (likely(num))
2534                         pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2535                 num += skip_bufs;
2536                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2537                 sq->size -= num;
2538                 num = 0;
2539                 skip_bufs = 0;
2540         }
2541
2542         if (likely(num)) {
2543                 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2544                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2545                 sq->size -= num;
2546         }
2547 }
2548
2549 /**
2550  * DPDK callback for transmit.
2551  *
2552  * @param txq
2553  *   Generic pointer transmit queue.
2554  * @param tx_pkts
2555  *   Packets to transmit.
2556  * @param nb_pkts
2557  *   Number of packets in array.
2558  *
2559  * @return
2560  *   Number of packets successfully transmitted.
2561  */
2562 static uint16_t
2563 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2564 {
2565         struct mrvl_txq *q = txq;
2566         struct mrvl_shadow_txq *sq;
2567         struct pp2_hif *hif;
2568         struct pp2_ppio_desc descs[nb_pkts];
2569         unsigned int core_id = rte_lcore_id();
2570         int i, ret, bytes_sent = 0;
2571         uint16_t num, sq_free_size;
2572         uint64_t addr;
2573
2574         hif = mrvl_get_hif(q->priv, core_id);
2575         sq = &q->shadow_txqs[core_id];
2576
2577         if (unlikely(!q->priv->ppio || !hif))
2578                 return 0;
2579
2580         if (sq->size)
2581                 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2582                                        sq, q->queue_id, 0);
2583
2584         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2585         if (unlikely(nb_pkts > sq_free_size))
2586                 nb_pkts = sq_free_size;
2587
2588         for (i = 0; i < nb_pkts; i++) {
2589                 struct rte_mbuf *mbuf = tx_pkts[i];
2590                 int gen_l3_cksum, gen_l4_cksum;
2591                 enum pp2_outq_l3_type l3_type;
2592                 enum pp2_outq_l4_type l4_type;
2593
2594                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2595                         struct rte_mbuf *pref_pkt_hdr;
2596
2597                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2598                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
2599                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
2600                 }
2601
2602                 mrvl_fill_shadowq(sq, mbuf);
2603                 mrvl_fill_desc(&descs[i], mbuf);
2604
2605                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2606                 /*
2607                  * in case unsupported ol_flags were passed
2608                  * do not update descriptor offload information
2609                  */
2610                 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2611                                               &l3_type, &l4_type, &gen_l3_cksum,
2612                                               &gen_l4_cksum);
2613                 if (unlikely(ret))
2614                         continue;
2615
2616                 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2617                                                   mbuf->l2_len,
2618                                                   mbuf->l2_len + mbuf->l3_len,
2619                                                   gen_l3_cksum, gen_l4_cksum);
2620         }
2621
2622         num = nb_pkts;
2623         pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2624         /* number of packets that were not sent */
2625         if (unlikely(num > nb_pkts)) {
2626                 for (i = nb_pkts; i < num; i++) {
2627                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2628                                 MRVL_PP2_TX_SHADOWQ_MASK;
2629                         addr = sq->ent[sq->head].buff.cookie;
2630                         bytes_sent -=
2631                                 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2632                 }
2633                 sq->size -= num - nb_pkts;
2634         }
2635
2636         q->bytes_sent += bytes_sent;
2637
2638         return nb_pkts;
2639 }
2640
2641 /** DPDK callback for S/G transmit.
2642  *
2643  * @param txq
2644  *   Generic pointer transmit queue.
2645  * @param tx_pkts
2646  *   Packets to transmit.
2647  * @param nb_pkts
2648  *   Number of packets in array.
2649  *
2650  * @return
2651  *   Number of packets successfully transmitted.
2652  */
2653 static uint16_t
2654 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
2655                      uint16_t nb_pkts)
2656 {
2657         struct mrvl_txq *q = txq;
2658         struct mrvl_shadow_txq *sq;
2659         struct pp2_hif *hif;
2660         struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS];
2661         struct pp2_ppio_sg_pkts pkts;
2662         uint8_t frags[nb_pkts];
2663         unsigned int core_id = rte_lcore_id();
2664         int i, j, ret, bytes_sent = 0;
2665         int tail, tail_first;
2666         uint16_t num, sq_free_size;
2667         uint16_t nb_segs, total_descs = 0;
2668         uint64_t addr;
2669
2670         hif = mrvl_get_hif(q->priv, core_id);
2671         sq = &q->shadow_txqs[core_id];
2672         pkts.frags = frags;
2673         pkts.num = 0;
2674
2675         if (unlikely(!q->priv->ppio || !hif))
2676                 return 0;
2677
2678         if (sq->size)
2679                 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2680                                        sq, q->queue_id, 0);
2681
2682         /* Save shadow queue free size */
2683         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2684
2685         tail = 0;
2686         for (i = 0; i < nb_pkts; i++) {
2687                 struct rte_mbuf *mbuf = tx_pkts[i];
2688                 struct rte_mbuf *seg = NULL;
2689                 int gen_l3_cksum, gen_l4_cksum;
2690                 enum pp2_outq_l3_type l3_type;
2691                 enum pp2_outq_l4_type l4_type;
2692
2693                 nb_segs = mbuf->nb_segs;
2694                 tail_first = tail;
2695                 total_descs += nb_segs;
2696
2697                 /*
2698                  * Check if total_descs does not exceed
2699                  * shadow queue free size
2700                  */
2701                 if (unlikely(total_descs > sq_free_size)) {
2702                         total_descs -= nb_segs;
2703                         break;
2704                 }
2705
2706                 /* Check if nb_segs does not exceed the max nb of desc per
2707                  * fragmented packet
2708                  */
2709                 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) {
2710                         total_descs -= nb_segs;
2711                         RTE_LOG(ERR, PMD,
2712                                 "Too many segments. Packet won't be sent.\n");
2713                         break;
2714                 }
2715
2716                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2717                         struct rte_mbuf *pref_pkt_hdr;
2718
2719                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2720                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
2721                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
2722                 }
2723
2724                 pkts.frags[pkts.num] = nb_segs;
2725                 pkts.num++;
2726
2727                 seg = mbuf;
2728                 for (j = 0; j < nb_segs - 1; j++) {
2729                         /* For the subsequent segments, set shadow queue
2730                          * buffer to NULL
2731                          */
2732                         mrvl_fill_shadowq(sq, NULL);
2733                         mrvl_fill_desc(&descs[tail], seg);
2734
2735                         tail++;
2736                         seg = seg->next;
2737                 }
2738                 /* Put first mbuf info in last shadow queue entry */
2739                 mrvl_fill_shadowq(sq, mbuf);
2740                 /* Update descriptor with last segment */
2741                 mrvl_fill_desc(&descs[tail++], seg);
2742
2743                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2744                 /* In case unsupported ol_flags were passed
2745                  * do not update descriptor offload information
2746                  */
2747                 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2748                                               &l3_type, &l4_type, &gen_l3_cksum,
2749                                               &gen_l4_cksum);
2750                 if (unlikely(ret))
2751                         continue;
2752
2753                 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type,
2754                                                   l4_type, mbuf->l2_len,
2755                                                   mbuf->l2_len + mbuf->l3_len,
2756                                                   gen_l3_cksum, gen_l4_cksum);
2757         }
2758
2759         num = total_descs;
2760         pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs,
2761                          &total_descs, &pkts);
2762         /* number of packets that were not sent */
2763         if (unlikely(num > total_descs)) {
2764                 for (i = total_descs; i < num; i++) {
2765                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2766                                 MRVL_PP2_TX_SHADOWQ_MASK;
2767
2768                         addr = sq->ent[sq->head].buff.cookie;
2769                         if (addr)
2770                                 bytes_sent -=
2771                                         rte_pktmbuf_pkt_len((struct rte_mbuf *)
2772                                                 (cookie_addr_high | addr));
2773                 }
2774                 sq->size -= num - total_descs;
2775                 nb_pkts = pkts.num;
2776         }
2777
2778         q->bytes_sent += bytes_sent;
2779
2780         return nb_pkts;
2781 }
2782
2783 /**
2784  * Initialize packet processor.
2785  *
2786  * @return
2787  *   0 on success, negative error value otherwise.
2788  */
2789 static int
2790 mrvl_init_pp2(void)
2791 {
2792         struct pp2_init_params init_params;
2793
2794         memset(&init_params, 0, sizeof(init_params));
2795         init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2796         init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2797         init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2798
2799         return pp2_init(&init_params);
2800 }
2801
2802 /**
2803  * Deinitialize packet processor.
2804  *
2805  * @return
2806  *   0 on success, negative error value otherwise.
2807  */
2808 static void
2809 mrvl_deinit_pp2(void)
2810 {
2811         pp2_deinit();
2812 }
2813
2814 /**
2815  * Create private device structure.
2816  *
2817  * @param dev_name
2818  *   Pointer to the port name passed in the initialization parameters.
2819  *
2820  * @return
2821  *   Pointer to the newly allocated private device structure.
2822  */
2823 static struct mrvl_priv *
2824 mrvl_priv_create(const char *dev_name)
2825 {
2826         struct pp2_bpool_params bpool_params;
2827         char match[MRVL_MATCH_LEN];
2828         struct mrvl_priv *priv;
2829         int ret, bpool_bit;
2830
2831         priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2832         if (!priv)
2833                 return NULL;
2834
2835         ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2836                                        &priv->pp_id, &priv->ppio_id);
2837         if (ret)
2838                 goto out_free_priv;
2839
2840         bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2841                                      PP2_BPOOL_NUM_POOLS);
2842         if (bpool_bit < 0)
2843                 goto out_free_priv;
2844         priv->bpool_bit = bpool_bit;
2845
2846         snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2847                  priv->bpool_bit);
2848         memset(&bpool_params, 0, sizeof(bpool_params));
2849         bpool_params.match = match;
2850         bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2851         ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2852         if (ret)
2853                 goto out_clear_bpool_bit;
2854
2855         priv->ppio_params.type = PP2_PPIO_T_NIC;
2856         rte_spinlock_init(&priv->lock);
2857
2858         return priv;
2859 out_clear_bpool_bit:
2860         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2861 out_free_priv:
2862         rte_free(priv);
2863         return NULL;
2864 }
2865
2866 /**
2867  * Create device representing Ethernet port.
2868  *
2869  * @param name
2870  *   Pointer to the port's name.
2871  *
2872  * @return
2873  *   0 on success, negative error value otherwise.
2874  */
2875 static int
2876 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2877 {
2878         int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2879         struct rte_eth_dev *eth_dev;
2880         struct mrvl_priv *priv;
2881         struct ifreq req;
2882
2883         eth_dev = rte_eth_dev_allocate(name);
2884         if (!eth_dev)
2885                 return -ENOMEM;
2886
2887         priv = mrvl_priv_create(name);
2888         if (!priv) {
2889                 ret = -ENOMEM;
2890                 goto out_free;
2891         }
2892         eth_dev->data->dev_private = priv;
2893
2894         eth_dev->data->mac_addrs =
2895                 rte_zmalloc("mac_addrs",
2896                             RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2897         if (!eth_dev->data->mac_addrs) {
2898                 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2899                 ret = -ENOMEM;
2900                 goto out_free;
2901         }
2902
2903         memset(&req, 0, sizeof(req));
2904         strcpy(req.ifr_name, name);
2905         ret = ioctl(fd, SIOCGIFHWADDR, &req);
2906         if (ret)
2907                 goto out_free;
2908
2909         memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2910                req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN);
2911
2912         eth_dev->device = &vdev->device;
2913         eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2914         mrvl_set_tx_function(eth_dev);
2915         eth_dev->dev_ops = &mrvl_ops;
2916         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2917
2918         eth_dev->data->dev_link.link_status = ETH_LINK_UP;
2919
2920         rte_eth_dev_probing_finish(eth_dev);
2921         return 0;
2922 out_free:
2923         rte_eth_dev_release_port(eth_dev);
2924
2925         return ret;
2926 }
2927
2928 /**
2929  * Callback used by rte_kvargs_process() during argument parsing.
2930  *
2931  * @param key
2932  *   Pointer to the parsed key (unused).
2933  * @param value
2934  *   Pointer to the parsed value.
2935  * @param extra_args
2936  *   Pointer to the extra arguments which contains address of the
2937  *   table of pointers to parsed interface names.
2938  *
2939  * @return
2940  *   Always 0.
2941  */
2942 static int
2943 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2944                  void *extra_args)
2945 {
2946         struct mrvl_ifnames *ifnames = extra_args;
2947
2948         ifnames->names[ifnames->idx++] = value;
2949
2950         return 0;
2951 }
2952
2953 /**
2954  * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2955  */
2956 static void
2957 mrvl_deinit_hifs(void)
2958 {
2959         int i;
2960
2961         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2962                 if (hifs[i])
2963                         pp2_hif_deinit(hifs[i]);
2964         }
2965         used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2966         memset(hifs, 0, sizeof(hifs));
2967 }
2968
2969 /**
2970  * DPDK callback to register the virtual device.
2971  *
2972  * @param vdev
2973  *   Pointer to the virtual device.
2974  *
2975  * @return
2976  *   0 on success, negative error value otherwise.
2977  */
2978 static int
2979 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2980 {
2981         struct rte_kvargs *kvlist;
2982         struct mrvl_ifnames ifnames;
2983         int ret = -EINVAL;
2984         uint32_t i, ifnum, cfgnum;
2985         const char *params;
2986
2987         params = rte_vdev_device_args(vdev);
2988         if (!params)
2989                 return -EINVAL;
2990
2991         kvlist = rte_kvargs_parse(params, valid_args);
2992         if (!kvlist)
2993                 return -EINVAL;
2994
2995         ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2996         if (ifnum > RTE_DIM(ifnames.names))
2997                 goto out_free_kvlist;
2998
2999         ifnames.idx = 0;
3000         rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
3001                            mrvl_get_ifnames, &ifnames);
3002
3003
3004         /*
3005          * The below system initialization should be done only once,
3006          * on the first provided configuration file
3007          */
3008         if (!mrvl_qos_cfg) {
3009                 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
3010                 MRVL_LOG(INFO, "Parsing config file!");
3011                 if (cfgnum > 1) {
3012                         MRVL_LOG(ERR, "Cannot handle more than one config file!");
3013                         goto out_free_kvlist;
3014                 } else if (cfgnum == 1) {
3015                         rte_kvargs_process(kvlist, MRVL_CFG_ARG,
3016                                            mrvl_get_qoscfg, &mrvl_qos_cfg);
3017                 }
3018         }
3019
3020         if (mrvl_dev_num)
3021                 goto init_devices;
3022
3023         MRVL_LOG(INFO, "Perform MUSDK initializations");
3024
3025         ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
3026         if (ret)
3027                 goto out_free_kvlist;
3028
3029         ret = mrvl_init_pp2();
3030         if (ret) {
3031                 MRVL_LOG(ERR, "Failed to init PP!");
3032                 rte_mvep_deinit(MVEP_MOD_T_PP2);
3033                 goto out_free_kvlist;
3034         }
3035
3036         memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
3037         memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
3038
3039         mrvl_lcore_first = RTE_MAX_LCORE;
3040         mrvl_lcore_last = 0;
3041
3042 init_devices:
3043         for (i = 0; i < ifnum; i++) {
3044                 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
3045                 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
3046                 if (ret)
3047                         goto out_cleanup;
3048                 mrvl_dev_num++;
3049         }
3050
3051         rte_kvargs_free(kvlist);
3052
3053         return 0;
3054 out_cleanup:
3055         rte_pmd_mrvl_remove(vdev);
3056
3057 out_free_kvlist:
3058         rte_kvargs_free(kvlist);
3059
3060         return ret;
3061 }
3062
3063 /**
3064  * DPDK callback to remove virtual device.
3065  *
3066  * @param vdev
3067  *   Pointer to the removed virtual device.
3068  *
3069  * @return
3070  *   0 on success, negative error value otherwise.
3071  */
3072 static int
3073 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
3074 {
3075         uint16_t port_id;
3076         int ret = 0;
3077
3078         RTE_ETH_FOREACH_DEV(port_id) {
3079                 if (rte_eth_devices[port_id].device != &vdev->device)
3080                         continue;
3081                 ret |= rte_eth_dev_close(port_id);
3082         }
3083
3084         return ret == 0 ? 0 : -EIO;
3085 }
3086
3087 static struct rte_vdev_driver pmd_mrvl_drv = {
3088         .probe = rte_pmd_mrvl_probe,
3089         .remove = rte_pmd_mrvl_remove,
3090 };
3091
3092 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
3093 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
3094 RTE_LOG_REGISTER(mrvl_logtype, pmd.net.mvpp2, NOTICE);