drivers/net/mvpp2/mrvl_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017-2021 Marvell International Ltd.
   3  * Copyright(c) 2017-2021 Semihalf.
   4  * All rights reserved.
   5  */
   6
   7 #include <rte_string_fns.h>
   8 #include <ethdev_driver.h>
   9 #include <rte_kvargs.h>
  10 #include <rte_log.h>
  11 #include <rte_malloc.h>
  12 #include <rte_bus_vdev.h>
  13
  14 #include <fcntl.h>
  15 #include <linux/ethtool.h>
  16 #include <linux/sockios.h>
  17 #include <net/if.h>
  18 #include <net/if_arp.h>
  19 #include <sys/ioctl.h>
  20 #include <sys/socket.h>
  21 #include <sys/stat.h>
  22 #include <sys/types.h>
  23
  24 #include <rte_mvep_common.h>
  25 #include "mrvl_ethdev.h"
  26 #include "mrvl_qos.h"
  27 #include "mrvl_flow.h"
  28 #include "mrvl_mtr.h"
  29 #include "mrvl_tm.h"
  30
  31 /* bitmask with reserved hifs */
  32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
  33 /* bitmask with reserved bpools */
  34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
  35 /* bitmask with reserved kernel RSS tables */
  36 #define MRVL_MUSDK_RSS_RESERVED 0x0F
  37 /* maximum number of available hifs */
  38 #define MRVL_MUSDK_HIFS_MAX 9
  39
  40 /* prefetch shift */
  41 #define MRVL_MUSDK_PREFETCH_SHIFT 2
  42
  43 /* TCAM has 25 entries reserved for uc/mc filter entries
  44  * + 1 for primary mac address
  45  */
  46 #define MRVL_MAC_ADDRS_MAX (1 + 25)
  47 #define MRVL_MATCH_LEN 16
  48 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
  49 /* Maximum allowable packet size */
  50 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
  51
  52 #define MRVL_IFACE_NAME_ARG "iface"
  53 #define MRVL_CFG_ARG "cfg"
  54
  55 #define MRVL_ARP_LENGTH 28
  56
  57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
  58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
  59
  60 /** Port Rx offload capabilities */
  61 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
  62                           DEV_RX_OFFLOAD_CHECKSUM)
  63
  64 /** Port Tx offloads capabilities */
  65 #define MRVL_TX_OFFLOAD_CHECKSUM (DEV_TX_OFFLOAD_IPV4_CKSUM | \
  66                                   DEV_TX_OFFLOAD_UDP_CKSUM  | \
  67                                   DEV_TX_OFFLOAD_TCP_CKSUM)
  68 #define MRVL_TX_OFFLOADS (MRVL_TX_OFFLOAD_CHECKSUM | \
  69                           DEV_TX_OFFLOAD_MULTI_SEGS)
  70
  71 #define MRVL_TX_PKT_OFFLOADS (PKT_TX_IP_CKSUM | \
  72                               PKT_TX_TCP_CKSUM | \
  73                               PKT_TX_UDP_CKSUM)
  74
  75 static const char * const valid_args[] = {
  76         MRVL_IFACE_NAME_ARG,
  77         MRVL_CFG_ARG,
  78         NULL
  79 };
  80
  81 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
  82 static struct pp2_hif *hifs[RTE_MAX_LCORE];
  83 static int used_bpools[PP2_NUM_PKT_PROC] = {
  84         [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
  85 };
  86
  87 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
  88 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
  89 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
  90 static int dummy_pool_id[PP2_NUM_PKT_PROC];
  91 struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC] = {0};
  92
  93 struct mrvl_ifnames {
  94         const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
  95         int idx;
  96 };
  97
  98 /*
  99  * To use buffer harvesting based on loopback port shadow queue structure
 100  * was introduced for buffers information bookkeeping.
 101  *
 102  * Before sending the packet, related buffer information (pp2_buff_inf) is
 103  * stored in shadow queue. After packet is transmitted no longer used
 104  * packet buffer is released back to it's original hardware pool,
 105  * on condition it originated from interface.
 106  * In case it  was generated by application itself i.e: mbuf->port field is
 107  * 0xff then its released to software mempool.
 108  */
 109 struct mrvl_shadow_txq {
 110         int head;           /* write index - used when sending buffers */
 111         int tail;           /* read index - used when releasing buffers */
 112         u16 size;           /* queue occupied size */
 113         u16 num_to_release; /* number of descriptors sent, that can be
 114                              * released
 115                              */
 116         struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
 117 };
 118
 119 struct mrvl_rxq {
 120         struct mrvl_priv *priv;
 121         struct rte_mempool *mp;
 122         int queue_id;
 123         int port_id;
 124         int cksum_enabled;
 125         uint64_t bytes_recv;
 126         uint64_t drop_mac;
 127 };
 128
 129 struct mrvl_txq {
 130         struct mrvl_priv *priv;
 131         int queue_id;
 132         int port_id;
 133         uint64_t bytes_sent;
 134         struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
 135         int tx_deferred_start;
 136 };
 137
 138 static int mrvl_lcore_first;
 139 static int mrvl_lcore_last;
 140 static int mrvl_dev_num;
 141
 142 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
 143 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
 144                         struct pp2_hif *hif, unsigned int core_id,
 145                         struct mrvl_shadow_txq *sq, int qid, int force);
 146
 147 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
 148                                   uint16_t nb_pkts);
 149 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
 150                                      uint16_t nb_pkts);
 151 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev);
 152 static void mrvl_deinit_pp2(void);
 153 static void mrvl_deinit_hifs(void);
 154
 155 static int
 156 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 157                   uint32_t index, uint32_t vmdq __rte_unused);
 158 static int
 159 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
 160 static int
 161 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
 162 static int mrvl_promiscuous_enable(struct rte_eth_dev *dev);
 163 static int mrvl_allmulticast_enable(struct rte_eth_dev *dev);
 164 static int
 165 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
 166
 167 #define MRVL_XSTATS_TBL_ENTRY(name) { \
 168         #name, offsetof(struct pp2_ppio_statistics, name),      \
 169         sizeof(((struct pp2_ppio_statistics *)0)->name)         \
 170 }
 171
 172 /* Table with xstats data */
 173 static struct {
 174         const char *name;
 175         unsigned int offset;
 176         unsigned int size;
 177 } mrvl_xstats_tbl[] = {
 178         MRVL_XSTATS_TBL_ENTRY(rx_bytes),
 179         MRVL_XSTATS_TBL_ENTRY(rx_packets),
 180         MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
 181         MRVL_XSTATS_TBL_ENTRY(rx_errors),
 182         MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
 183         MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
 184         MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
 185         MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
 186         MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
 187         MRVL_XSTATS_TBL_ENTRY(tx_bytes),
 188         MRVL_XSTATS_TBL_ENTRY(tx_packets),
 189         MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
 190         MRVL_XSTATS_TBL_ENTRY(tx_errors)
 191 };
 192
 193 static inline int
 194 mrvl_reserve_bit(int *bitmap, int max)
 195 {
 196         int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
 197
 198         if (n >= max)
 199                 return -1;
 200
 201         *bitmap |= 1 << n;
 202
 203         return n;
 204 }
 205
 206 static int
 207 mrvl_pp2_fixup_init(void)
 208 {
 209         struct pp2_bpool_params bpool_params;
 210         char                    name[15];
 211         int                     err, i;
 212
 213         memset(dummy_pool, 0, sizeof(dummy_pool));
 214         for (i = 0; i < pp2_get_num_inst(); i++) {
 215                 dummy_pool_id[i] = mrvl_reserve_bit(&used_bpools[i],
 216                                              PP2_BPOOL_NUM_POOLS);
 217                 if (dummy_pool_id[i] < 0) {
 218                         MRVL_LOG(ERR, "Can't find free pool\n");
 219                         return -1;
 220                 }
 221
 222                 memset(name, 0, sizeof(name));
 223                 snprintf(name, sizeof(name), "pool-%d:%d", i, dummy_pool_id[i]);
 224                 memset(&bpool_params, 0, sizeof(bpool_params));
 225                 bpool_params.match = name;
 226                 bpool_params.buff_len = MRVL_PKT_OFFS;
 227                 bpool_params.dummy_short_pool = 1;
 228                 err = pp2_bpool_init(&bpool_params, &dummy_pool[i]);
 229                 if (err != 0 || !dummy_pool[i]) {
 230                         MRVL_LOG(ERR, "BPool init failed!\n");
 231                         used_bpools[i] &= ~(1 << dummy_pool_id[i]);
 232                         return -1;
 233                 }
 234         }
 235
 236         return 0;
 237 }
 238
 239 /**
 240  * Initialize packet processor.
 241  *
 242  * @return
 243  *   0 on success, negative error value otherwise.
 244  */
 245 static int
 246 mrvl_init_pp2(void)
 247 {
 248         struct pp2_init_params  init_params;
 249         int                     err;
 250
 251         memset(&init_params, 0, sizeof(init_params));
 252         init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
 253         init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
 254         init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
 255         if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs)
 256                 memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs,
 257                        sizeof(struct pp2_parse_udfs));
 258         err = pp2_init(&init_params);
 259         if (err != 0) {
 260                 MRVL_LOG(ERR, "PP2 init failed");
 261                 return -1;
 262         }
 263
 264         err = mrvl_pp2_fixup_init();
 265         if (err != 0) {
 266                 MRVL_LOG(ERR, "PP2 fixup init failed");
 267                 return -1;
 268         }
 269
 270         return 0;
 271 }
 272
 273 static void
 274 mrvl_pp2_fixup_deinit(void)
 275 {
 276         int i;
 277
 278         for (i = 0; i < PP2_NUM_PKT_PROC; i++) {
 279                 if (!dummy_pool[i])
 280                         continue;
 281                 pp2_bpool_deinit(dummy_pool[i]);
 282                 used_bpools[i] &= ~(1 << dummy_pool_id[i]);
 283         }
 284 }
 285
 286 /**
 287  * Deinitialize packet processor.
 288  *
 289  * @return
 290  *   0 on success, negative error value otherwise.
 291  */
 292 static void
 293 mrvl_deinit_pp2(void)
 294 {
 295         mrvl_pp2_fixup_deinit();
 296         pp2_deinit();
 297 }
 298
 299 static inline void
 300 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf)
 301 {
 302         sq->ent[sq->head].buff.cookie = (uint64_t)buf;
 303         sq->ent[sq->head].buff.addr = buf ?
 304                 rte_mbuf_data_iova_default(buf) : 0;
 305
 306         sq->ent[sq->head].bpool =
 307                 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS ||
 308                  buf->refcnt > 1)) ? NULL :
 309                  mrvl_port_to_bpool_lookup[buf->port];
 310
 311         sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
 312         sq->size++;
 313 }
 314
 315 /**
 316  * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
 317  */
 318 static void
 319 mrvl_deinit_hifs(void)
 320 {
 321         int i;
 322
 323         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
 324                 if (hifs[i])
 325                         pp2_hif_deinit(hifs[i]);
 326         }
 327         used_hifs = MRVL_MUSDK_HIFS_RESERVED;
 328         memset(hifs, 0, sizeof(hifs));
 329 }
 330
 331 static inline void
 332 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf)
 333 {
 334         pp2_ppio_outq_desc_reset(desc);
 335         pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf));
 336         pp2_ppio_outq_desc_set_pkt_offset(desc, 0);
 337         pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf));
 338 }
 339
 340 static inline int
 341 mrvl_get_bpool_size(int pp2_id, int pool_id)
 342 {
 343         int i;
 344         int size = 0;
 345
 346         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
 347                 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
 348
 349         return size;
 350 }
 351
 352 static int
 353 mrvl_init_hif(int core_id)
 354 {
 355         struct pp2_hif_params params;
 356         char match[MRVL_MATCH_LEN];
 357         int ret;
 358
 359         ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
 360         if (ret < 0) {
 361                 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
 362                 return ret;
 363         }
 364
 365         snprintf(match, sizeof(match), "hif-%d", ret);
 366         memset(&params, 0, sizeof(params));
 367         params.match = match;
 368         params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
 369         ret = pp2_hif_init(&params, &hifs[core_id]);
 370         if (ret) {
 371                 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
 372                 return ret;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static inline struct pp2_hif*
 379 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
 380 {
 381         int ret;
 382
 383         if (likely(hifs[core_id] != NULL))
 384                 return hifs[core_id];
 385
 386         rte_spinlock_lock(&priv->lock);
 387
 388         ret = mrvl_init_hif(core_id);
 389         if (ret < 0) {
 390                 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
 391                 goto out;
 392         }
 393
 394         if (core_id < mrvl_lcore_first)
 395                 mrvl_lcore_first = core_id;
 396
 397         if (core_id > mrvl_lcore_last)
 398                 mrvl_lcore_last = core_id;
 399 out:
 400         rte_spinlock_unlock(&priv->lock);
 401
 402         return hifs[core_id];
 403 }
 404
 405 /**
 406  * Set tx burst function according to offload flag
 407  *
 408  * @param dev
 409  *   Pointer to Ethernet device structure.
 410  */
 411 static void
 412 mrvl_set_tx_function(struct rte_eth_dev *dev)
 413 {
 414         struct mrvl_priv *priv = dev->data->dev_private;
 415
 416         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
 417         if (priv->multiseg) {
 418                 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n");
 419                 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst;
 420         } else {
 421                 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n");
 422                 dev->tx_pkt_burst = mrvl_tx_pkt_burst;
 423         }
 424 }
 425
 426 /**
 427  * Configure rss based on dpdk rss configuration.
 428  *
 429  * @param priv
 430  *   Pointer to private structure.
 431  * @param rss_conf
 432  *   Pointer to RSS configuration.
 433  *
 434  * @return
 435  *   0 on success, negative error value otherwise.
 436  */
 437 static int
 438 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
 439 {
 440         if (rss_conf->rss_key)
 441                 MRVL_LOG(WARNING, "Changing hash key is not supported");
 442
 443         if (rss_conf->rss_hf == 0) {
 444                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 445         } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
 446                 priv->ppio_params.inqs_params.hash_type =
 447                         PP2_PPIO_HASH_T_2_TUPLE;
 448         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
 449                 priv->ppio_params.inqs_params.hash_type =
 450                         PP2_PPIO_HASH_T_5_TUPLE;
 451                 priv->rss_hf_tcp = 1;
 452         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
 453                 priv->ppio_params.inqs_params.hash_type =
 454                         PP2_PPIO_HASH_T_5_TUPLE;
 455                 priv->rss_hf_tcp = 0;
 456         } else {
 457                 return -EINVAL;
 458         }
 459
 460         return 0;
 461 }
 462
 463 /**
 464  * Ethernet device configuration.
 465  *
 466  * Prepare the driver for a given number of TX and RX queues and
 467  * configure RSS.
 468  *
 469  * @param dev
 470  *   Pointer to Ethernet device structure.
 471  *
 472  * @return
 473  *   0 on success, negative error value otherwise.
 474  */
 475 static int
 476 mrvl_dev_configure(struct rte_eth_dev *dev)
 477 {
 478         struct mrvl_priv *priv = dev->data->dev_private;
 479         int ret;
 480
 481         if (priv->ppio) {
 482                 MRVL_LOG(INFO, "Device reconfiguration is not supported");
 483                 return -EINVAL;
 484         }
 485
 486         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
 487             dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
 488                 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
 489                         dev->data->dev_conf.rxmode.mq_mode);
 490                 return -EINVAL;
 491         }
 492
 493         if (dev->data->dev_conf.rxmode.split_hdr_size) {
 494                 MRVL_LOG(INFO, "Split headers not supported");
 495                 return -EINVAL;
 496         }
 497
 498         if (dev->data->dev_conf.rxmode.mtu > priv->max_mtu) {
 499                 MRVL_LOG(ERR, "MTU %u is larger than max_mtu %u\n",
 500                          dev->data->dev_conf.rxmode.mtu,
 501                          priv->max_mtu);
 502                 return -EINVAL;
 503         }
 504
 505         if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 506                 priv->multiseg = 1;
 507
 508         ret = mrvl_configure_rxqs(priv, dev->data->port_id,
 509                                   dev->data->nb_rx_queues);
 510         if (ret < 0)
 511                 return ret;
 512
 513         ret = mrvl_configure_txqs(priv, dev->data->port_id,
 514                                   dev->data->nb_tx_queues);
 515         if (ret < 0)
 516                 return ret;
 517
 518         priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
 519         priv->ppio_params.maintain_stats = 1;
 520         priv->nb_rx_queues = dev->data->nb_rx_queues;
 521
 522         ret = mrvl_tm_init(dev);
 523         if (ret < 0)
 524                 return ret;
 525
 526         if (dev->data->nb_rx_queues == 1 &&
 527             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 528                 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
 529                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 530                 priv->configured = 1;
 531                 return 0;
 532         }
 533
 534         ret = mrvl_configure_rss(priv,
 535                         &dev->data->dev_conf.rx_adv_conf.rss_conf);
 536         if (ret < 0)
 537                 return ret;
 538
 539         priv->configured = 1;
 540
 541         return 0;
 542 }
 543
 544 /**
 545  * DPDK callback to change the MTU.
 546  *
 547  * Setting the MTU affects hardware MRU (packets larger than the MRU
 548  * will be dropped).
 549  *
 550  * @param dev
 551  *   Pointer to Ethernet device structure.
 552  * @param mtu
 553  *   New MTU.
 554  *
 555  * @return
 556  *   0 on success, negative error value otherwise.
 557  */
 558 static int
 559 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 560 {
 561         struct mrvl_priv *priv = dev->data->dev_private;
 562         uint16_t mru;
 563         uint16_t mbuf_data_size = 0; /* SW buffer size */
 564         int ret;
 565
 566         mru = MRVL_PP2_MTU_TO_MRU(mtu);
 567         /*
 568          * min_rx_buf_size is equal to mbuf data size
 569          * if pmd didn't set it differently
 570          */
 571         mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 572         /* Prevent PMD from:
 573          * - setting mru greater than the mbuf size resulting in
 574          * hw and sw buffer size mismatch
 575          * - setting mtu that requires the support of scattered packets
 576          * when this feature has not been enabled/supported so far
 577          * (TODO check scattered_rx flag here once scattered RX is supported).
 578          */
 579         if (mru - RTE_ETHER_CRC_LEN + MRVL_PKT_OFFS > mbuf_data_size) {
 580                 mru = mbuf_data_size + RTE_ETHER_CRC_LEN - MRVL_PKT_OFFS;
 581                 mtu = MRVL_PP2_MRU_TO_MTU(mru);
 582                 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted "
 583                         "by current mbuf size: %u. Set MTU to %u, MRU to %u",
 584                         mbuf_data_size, mtu, mru);
 585         }
 586
 587         if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) {
 588                 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru);
 589                 return -EINVAL;
 590         }
 591
 592         if (!priv->ppio)
 593                 return 0;
 594
 595         ret = pp2_ppio_set_mru(priv->ppio, mru);
 596         if (ret) {
 597                 MRVL_LOG(ERR, "Failed to change MRU");
 598                 return ret;
 599         }
 600
 601         ret = pp2_ppio_set_mtu(priv->ppio, mtu);
 602         if (ret) {
 603                 MRVL_LOG(ERR, "Failed to change MTU");
 604                 return ret;
 605         }
 606
 607         return 0;
 608 }
 609
 610 /**
 611  * DPDK callback to bring the link up.
 612  *
 613  * @param dev
 614  *   Pointer to Ethernet device structure.
 615  *
 616  * @return
 617  *   0 on success, negative error value otherwise.
 618  */
 619 static int
 620 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
 621 {
 622         struct mrvl_priv *priv = dev->data->dev_private;
 623         int ret;
 624
 625         if (!priv->ppio) {
 626                 dev->data->dev_link.link_status = ETH_LINK_UP;
 627                 return 0;
 628         }
 629
 630         ret = pp2_ppio_enable(priv->ppio);
 631         if (ret)
 632                 return ret;
 633
 634         /*
 635          * mtu/mru can be updated if pp2_ppio_enable() was called at least once
 636          * as pp2_ppio_enable() changes port->t_mode from default 0 to
 637          * PP2_TRAFFIC_INGRESS_EGRESS.
 638          *
 639          * Set mtu to default DPDK value here.
 640          */
 641         ret = mrvl_mtu_set(dev, dev->data->mtu);
 642         if (ret) {
 643                 pp2_ppio_disable(priv->ppio);
 644                 return ret;
 645         }
 646
 647         dev->data->dev_link.link_status = ETH_LINK_UP;
 648         return 0;
 649 }
 650
 651 /**
 652  * DPDK callback to bring the link down.
 653  *
 654  * @param dev
 655  *   Pointer to Ethernet device structure.
 656  *
 657  * @return
 658  *   0 on success, negative error value otherwise.
 659  */
 660 static int
 661 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
 662 {
 663         struct mrvl_priv *priv = dev->data->dev_private;
 664         int ret;
 665
 666         if (!priv->ppio) {
 667                 dev->data->dev_link.link_status = ETH_LINK_DOWN;
 668                 return 0;
 669         }
 670         ret = pp2_ppio_disable(priv->ppio);
 671         if (ret)
 672                 return ret;
 673
 674         dev->data->dev_link.link_status = ETH_LINK_DOWN;
 675         return 0;
 676 }
 677
 678 /**
 679  * DPDK callback to start tx queue.
 680  *
 681  * @param dev
 682  *   Pointer to Ethernet device structure.
 683  * @param queue_id
 684  *   Transmit queue index.
 685  *
 686  * @return
 687  *   0 on success, negative error value otherwise.
 688  */
 689 static int
 690 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
 691 {
 692         struct mrvl_priv *priv = dev->data->dev_private;
 693         int ret;
 694
 695         if (!priv)
 696                 return -EPERM;
 697
 698         /* passing 1 enables given tx queue */
 699         ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
 700         if (ret) {
 701                 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
 702                 return ret;
 703         }
 704
 705         dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 706
 707         return 0;
 708 }
 709
 710 /**
 711  * DPDK callback to stop tx queue.
 712  *
 713  * @param dev
 714  *   Pointer to Ethernet device structure.
 715  * @param queue_id
 716  *   Transmit queue index.
 717  *
 718  * @return
 719  *   0 on success, negative error value otherwise.
 720  */
 721 static int
 722 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
 723 {
 724         struct mrvl_priv *priv = dev->data->dev_private;
 725         int ret;
 726
 727         if (!priv->ppio)
 728                 return -EPERM;
 729
 730         /* passing 0 disables given tx queue */
 731         ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
 732         if (ret) {
 733                 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
 734                 return ret;
 735         }
 736
 737         dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 738
 739         return 0;
 740 }
 741
 742 /**
 743  * Populate VLAN Filter configuration.
 744  *
 745  * @param dev
 746  *   Pointer to Ethernet device structure.
 747  * @param on
 748  *   Toggle filter.
 749  *
 750  * @return
 751  *   0 on success, negative error value otherwise.
 752  */
 753 static int mrvl_populate_vlan_table(struct rte_eth_dev *dev, int on)
 754 {
 755         uint32_t j;
 756         int ret;
 757         struct rte_vlan_filter_conf *vfc;
 758
 759         vfc = &dev->data->vlan_filter_conf;
 760         for (j = 0; j < RTE_DIM(vfc->ids); j++) {
 761                 uint64_t vlan;
 762                 uint64_t vbit;
 763                 uint64_t ids = vfc->ids[j];
 764
 765                 if (ids == 0)
 766                         continue;
 767
 768                 while (ids) {
 769                         vlan = 64 * j;
 770                         /* count trailing zeroes */
 771                         vbit = ~ids & (ids - 1);
 772                         /* clear least significant bit set */
 773                         ids ^= (ids ^ (ids - 1)) ^ vbit;
 774                         for (; vbit; vlan++)
 775                                 vbit >>= 1;
 776                         ret = mrvl_vlan_filter_set(dev, vlan, on);
 777                         if (ret) {
 778                                 MRVL_LOG(ERR, "Failed to setup VLAN filter\n");
 779                                 return ret;
 780                         }
 781                 }
 782         }
 783
 784         return 0;
 785 }
 786
 787 /**
 788  * DPDK callback to start the device.
 789  *
 790  * @param dev
 791  *   Pointer to Ethernet device structure.
 792  *
 793  * @return
 794  *   0 on success, negative errno value on failure.
 795  */
 796 static int
 797 mrvl_dev_start(struct rte_eth_dev *dev)
 798 {
 799         struct mrvl_priv *priv = dev->data->dev_private;
 800         char match[MRVL_MATCH_LEN];
 801         int ret = 0, i, def_init_size;
 802         struct rte_ether_addr *mac_addr;
 803
 804         if (priv->ppio)
 805                 return mrvl_dev_set_link_up(dev);
 806
 807         snprintf(match, sizeof(match), "ppio-%d:%d",
 808                  priv->pp_id, priv->ppio_id);
 809         priv->ppio_params.match = match;
 810         priv->ppio_params.eth_start_hdr = PP2_PPIO_HDR_ETH;
 811         priv->forward_bad_frames = 0;
 812         priv->fill_bpool_buffs = MRVL_BURST_SIZE;
 813
 814         if (mrvl_cfg) {
 815                 priv->ppio_params.eth_start_hdr =
 816                         mrvl_cfg->port[dev->data->port_id].eth_start_hdr;
 817                 priv->forward_bad_frames =
 818                         mrvl_cfg->port[dev->data->port_id].forward_bad_frames;
 819                 priv->fill_bpool_buffs =
 820                         mrvl_cfg->port[dev->data->port_id].fill_bpool_buffs;
 821         }
 822
 823         /*
 824          * Calculate the minimum bpool size for refill feature as follows:
 825          * 2 default burst sizes multiply by number of rx queues.
 826          * If the bpool size will be below this value, new buffers will
 827          * be added to the pool.
 828          */
 829         priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
 830
 831         /* In case initial bpool size configured in queues setup is
 832          * smaller than minimum size add more buffers
 833          */
 834         def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
 835         if (priv->bpool_init_size < def_init_size) {
 836                 int buffs_to_add = def_init_size - priv->bpool_init_size;
 837
 838                 priv->bpool_init_size += buffs_to_add;
 839                 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
 840                 if (ret)
 841                         MRVL_LOG(ERR, "Failed to add buffers to bpool");
 842         }
 843
 844         /*
 845          * Calculate the maximum bpool size for refill feature as follows:
 846          * maximum number of descriptors in rx queue multiply by number
 847          * of rx queues plus minimum bpool size.
 848          * In case the bpool size will exceed this value, superfluous buffers
 849          * will be removed
 850          */
 851         priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
 852                                 priv->bpool_min_size;
 853
 854         ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
 855         if (ret) {
 856                 MRVL_LOG(ERR, "Failed to init ppio");
 857                 return ret;
 858         }
 859
 860         /*
 861          * In case there are some some stale uc/mc mac addresses flush them
 862          * here. It cannot be done during mrvl_dev_close() as port information
 863          * is already gone at that point (due to pp2_ppio_deinit() in
 864          * mrvl_dev_stop()).
 865          */
 866         if (!priv->uc_mc_flushed) {
 867                 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
 868                 if (ret) {
 869                         MRVL_LOG(ERR,
 870                                 "Failed to flush uc/mc filter list");
 871                         goto out;
 872                 }
 873                 priv->uc_mc_flushed = 1;
 874         }
 875
 876         ret = mrvl_mtu_set(dev, dev->data->mtu);
 877         if (ret)
 878                 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu);
 879
 880         if (!rte_is_zero_ether_addr(&dev->data->mac_addrs[0]))
 881                 mrvl_mac_addr_set(dev, &dev->data->mac_addrs[0]);
 882
 883         for (i = 1; i < MRVL_MAC_ADDRS_MAX; i++) {
 884                 mac_addr = &dev->data->mac_addrs[i];
 885
 886                 /* skip zero address */
 887                 if (rte_is_zero_ether_addr(mac_addr))
 888                         continue;
 889
 890                 mrvl_mac_addr_add(dev, mac_addr, i, 0);
 891         }
 892
 893         if (dev->data->all_multicast == 1)
 894                 mrvl_allmulticast_enable(dev);
 895
 896         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
 897                 ret = mrvl_populate_vlan_table(dev, 1);
 898                 if (ret) {
 899                         MRVL_LOG(ERR, "Failed to populate VLAN table");
 900                         goto out;
 901                 }
 902         }
 903
 904         /* For default QoS config, don't start classifier. */
 905         if (mrvl_cfg  &&
 906             mrvl_cfg->port[dev->data->port_id].use_qos_global_defaults == 0) {
 907                 ret = mrvl_start_qos_mapping(priv);
 908                 if (ret) {
 909                         MRVL_LOG(ERR, "Failed to setup QoS mapping");
 910                         goto out;
 911                 }
 912         }
 913
 914         ret = pp2_ppio_set_loopback(priv->ppio, dev->data->dev_conf.lpbk_mode);
 915         if (ret) {
 916                 MRVL_LOG(ERR, "Failed to set loopback");
 917                 goto out;
 918         }
 919
 920         if (dev->data->promiscuous == 1)
 921                 mrvl_promiscuous_enable(dev);
 922
 923         if (priv->flow_ctrl) {
 924                 ret = mrvl_flow_ctrl_set(dev, &priv->fc_conf);
 925                 if (ret) {
 926                         MRVL_LOG(ERR, "Failed to configure flow control");
 927                         goto out;
 928                 }
 929                 priv->flow_ctrl = 0;
 930         }
 931
 932         if (dev->data->dev_link.link_status == ETH_LINK_UP) {
 933                 ret = mrvl_dev_set_link_up(dev);
 934                 if (ret) {
 935                         MRVL_LOG(ERR, "Failed to set link up");
 936                         dev->data->dev_link.link_status = ETH_LINK_DOWN;
 937                         goto out;
 938                 }
 939         }
 940
 941         /* start tx queues */
 942         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 943                 struct mrvl_txq *txq = dev->data->tx_queues[i];
 944
 945                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
 946
 947                 if (!txq->tx_deferred_start)
 948                         continue;
 949
 950                 /*
 951                  * All txqs are started by default. Stop them
 952                  * so that tx_deferred_start works as expected.
 953                  */
 954                 ret = mrvl_tx_queue_stop(dev, i);
 955                 if (ret)
 956                         goto out;
 957         }
 958
 959         mrvl_flow_init(dev);
 960         mrvl_mtr_init(dev);
 961         mrvl_set_tx_function(dev);
 962
 963         return 0;
 964 out:
 965         MRVL_LOG(ERR, "Failed to start device");
 966         pp2_ppio_deinit(priv->ppio);
 967         return ret;
 968 }
 969
 970 /**
 971  * Flush receive queues.
 972  *
 973  * @param dev
 974  *   Pointer to Ethernet device structure.
 975  */
 976 static void
 977 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
 978 {
 979         int i;
 980
 981         MRVL_LOG(INFO, "Flushing rx queues");
 982         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 983                 int ret, num;
 984
 985                 do {
 986                         struct mrvl_rxq *q = dev->data->rx_queues[i];
 987                         struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
 988
 989                         num = MRVL_PP2_RXD_MAX;
 990                         ret = pp2_ppio_recv(q->priv->ppio,
 991                                             q->priv->rxq_map[q->queue_id].tc,
 992                                             q->priv->rxq_map[q->queue_id].inq,
 993                                             descs, (uint16_t *)&num);
 994                 } while (ret == 0 && num);
 995         }
 996 }
 997
 998 /**
 999  * Flush transmit shadow queues.
1000  *
1001  * @param dev
1002  *   Pointer to Ethernet device structure.
1003  */
1004 static void
1005 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
1006 {
1007         int i, j;
1008         struct mrvl_txq *txq;
1009
1010         MRVL_LOG(INFO, "Flushing tx shadow queues");
1011         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1012                 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
1013
1014                 for (j = 0; j < RTE_MAX_LCORE; j++) {
1015                         struct mrvl_shadow_txq *sq;
1016
1017                         if (!hifs[j])
1018                                 continue;
1019
1020                         sq = &txq->shadow_txqs[j];
1021                         mrvl_free_sent_buffers(txq->priv->ppio,
1022                                 hifs[j], j, sq, txq->queue_id, 1);
1023                         while (sq->tail != sq->head) {
1024                                 uint64_t addr = cookie_addr_high |
1025                                         sq->ent[sq->tail].buff.cookie;
1026                                 rte_pktmbuf_free(
1027                                         (struct rte_mbuf *)addr);
1028                                 sq->tail = (sq->tail + 1) &
1029                                             MRVL_PP2_TX_SHADOWQ_MASK;
1030                         }
1031                         memset(sq, 0, sizeof(*sq));
1032                 }
1033         }
1034 }
1035
1036 /**
1037  * Flush hardware bpool (buffer-pool).
1038  *
1039  * @param dev
1040  *   Pointer to Ethernet device structure.
1041  */
1042 static void
1043 mrvl_flush_bpool(struct rte_eth_dev *dev)
1044 {
1045         struct mrvl_priv *priv = dev->data->dev_private;
1046         struct pp2_hif *hif;
1047         uint32_t num;
1048         int ret;
1049         unsigned int core_id = rte_lcore_id();
1050
1051         if (core_id == LCORE_ID_ANY)
1052                 core_id = rte_get_main_lcore();
1053
1054         hif = mrvl_get_hif(priv, core_id);
1055
1056         ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
1057         if (ret) {
1058                 MRVL_LOG(ERR, "Failed to get bpool buffers number");
1059                 return;
1060         }
1061
1062         while (num--) {
1063                 struct pp2_buff_inf inf;
1064                 uint64_t addr;
1065
1066                 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
1067                 if (ret)
1068                         break;
1069
1070                 addr = cookie_addr_high | inf.cookie;
1071                 rte_pktmbuf_free((struct rte_mbuf *)addr);
1072         }
1073 }
1074
1075 /**
1076  * DPDK callback to stop the device.
1077  *
1078  * @param dev
1079  *   Pointer to Ethernet device structure.
1080  */
1081 static int
1082 mrvl_dev_stop(struct rte_eth_dev *dev)
1083 {
1084         return mrvl_dev_set_link_down(dev);
1085 }
1086
1087 /**
1088  * DPDK callback to close the device.
1089  *
1090  * @param dev
1091  *   Pointer to Ethernet device structure.
1092  */
1093 static int
1094 mrvl_dev_close(struct rte_eth_dev *dev)
1095 {
1096         struct mrvl_priv *priv = dev->data->dev_private;
1097         size_t i;
1098
1099         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1100                 return 0;
1101
1102         mrvl_flush_rx_queues(dev);
1103         mrvl_flush_tx_shadow_queues(dev);
1104         mrvl_flow_deinit(dev);
1105         mrvl_mtr_deinit(dev);
1106
1107         for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
1108                 struct pp2_ppio_tc_params *tc_params =
1109                         &priv->ppio_params.inqs_params.tcs_params[i];
1110
1111                 if (tc_params->inqs_params) {
1112                         rte_free(tc_params->inqs_params);
1113                         tc_params->inqs_params = NULL;
1114                 }
1115         }
1116
1117         if (priv->cls_tbl) {
1118                 pp2_cls_tbl_deinit(priv->cls_tbl);
1119                 priv->cls_tbl = NULL;
1120         }
1121
1122         if (priv->qos_tbl) {
1123                 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
1124                 priv->qos_tbl = NULL;
1125         }
1126
1127         mrvl_flush_bpool(dev);
1128         mrvl_tm_deinit(dev);
1129
1130         if (priv->ppio) {
1131                 pp2_ppio_deinit(priv->ppio);
1132                 priv->ppio = NULL;
1133         }
1134
1135         /* policer must be released after ppio deinitialization */
1136         if (priv->default_policer) {
1137                 pp2_cls_plcr_deinit(priv->default_policer);
1138                 priv->default_policer = NULL;
1139         }
1140
1141
1142         if (priv->bpool) {
1143                 pp2_bpool_deinit(priv->bpool);
1144                 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
1145                 priv->bpool = NULL;
1146         }
1147
1148         mrvl_dev_num--;
1149
1150         if (mrvl_dev_num == 0) {
1151                 MRVL_LOG(INFO, "Perform MUSDK deinit");
1152                 mrvl_deinit_hifs();
1153                 mrvl_deinit_pp2();
1154                 rte_mvep_deinit(MVEP_MOD_T_PP2);
1155         }
1156
1157         return 0;
1158 }
1159
1160 /**
1161  * DPDK callback to retrieve physical link information.
1162  *
1163  * @param dev
1164  *   Pointer to Ethernet device structure.
1165  * @param wait_to_complete
1166  *   Wait for request completion (ignored).
1167  *
1168  * @return
1169  *   0 on success, negative error value otherwise.
1170  */
1171 static int
1172 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
1173 {
1174         /*
1175          * TODO
1176          * once MUSDK provides necessary API use it here
1177          */
1178         struct mrvl_priv *priv = dev->data->dev_private;
1179         struct ethtool_cmd edata;
1180         struct ifreq req;
1181         int ret, fd, link_up;
1182
1183         if (!priv->ppio)
1184                 return -EPERM;
1185
1186         edata.cmd = ETHTOOL_GSET;
1187
1188         strcpy(req.ifr_name, dev->data->name);
1189         req.ifr_data = (void *)&edata;
1190
1191         fd = socket(AF_INET, SOCK_DGRAM, 0);
1192         if (fd == -1)
1193                 return -EFAULT;
1194
1195         ret = ioctl(fd, SIOCETHTOOL, &req);
1196         if (ret == -1) {
1197                 close(fd);
1198                 return -EFAULT;
1199         }
1200
1201         close(fd);
1202
1203         switch (ethtool_cmd_speed(&edata)) {
1204         case SPEED_10:
1205                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
1206                 break;
1207         case SPEED_100:
1208                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
1209                 break;
1210         case SPEED_1000:
1211                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
1212                 break;
1213         case SPEED_2500:
1214                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_2_5G;
1215                 break;
1216         case SPEED_10000:
1217                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
1218                 break;
1219         default:
1220                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
1221         }
1222
1223         dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
1224                                                          ETH_LINK_HALF_DUPLEX;
1225         dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
1226                                                            ETH_LINK_FIXED;
1227         pp2_ppio_get_link_state(priv->ppio, &link_up);
1228         dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1229
1230         return 0;
1231 }
1232
1233 /**
1234  * DPDK callback to enable promiscuous mode.
1235  *
1236  * @param dev
1237  *   Pointer to Ethernet device structure.
1238  *
1239  * @return
1240  *   0 on success, negative error value otherwise.
1241  */
1242 static int
1243 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
1244 {
1245         struct mrvl_priv *priv = dev->data->dev_private;
1246         int ret;
1247
1248         if (priv->isolated)
1249                 return -ENOTSUP;
1250
1251         if (!priv->ppio)
1252                 return 0;
1253
1254         ret = pp2_ppio_set_promisc(priv->ppio, 1);
1255         if (ret) {
1256                 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
1257                 return -EAGAIN;
1258         }
1259
1260         return 0;
1261 }
1262
1263 /**
1264  * DPDK callback to enable allmulti mode.
1265  *
1266  * @param dev
1267  *   Pointer to Ethernet device structure.
1268  *
1269  * @return
1270  *   0 on success, negative error value otherwise.
1271  */
1272 static int
1273 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
1274 {
1275         struct mrvl_priv *priv = dev->data->dev_private;
1276         int ret;
1277
1278         if (priv->isolated)
1279                 return -ENOTSUP;
1280
1281         if (!priv->ppio)
1282                 return 0;
1283
1284         ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
1285         if (ret) {
1286                 MRVL_LOG(ERR, "Failed enable all-multicast mode");
1287                 return -EAGAIN;
1288         }
1289
1290         return 0;
1291 }
1292
1293 /**
1294  * DPDK callback to disable promiscuous mode.
1295  *
1296  * @param dev
1297  *   Pointer to Ethernet device structure.
1298  *
1299  * @return
1300  *   0 on success, negative error value otherwise.
1301  */
1302 static int
1303 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
1304 {
1305         struct mrvl_priv *priv = dev->data->dev_private;
1306         int ret;
1307
1308         if (priv->isolated)
1309                 return -ENOTSUP;
1310
1311         if (!priv->ppio)
1312                 return 0;
1313
1314         ret = pp2_ppio_set_promisc(priv->ppio, 0);
1315         if (ret) {
1316                 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
1317                 return -EAGAIN;
1318         }
1319
1320         return 0;
1321 }
1322
1323 /**
1324  * DPDK callback to disable allmulticast mode.
1325  *
1326  * @param dev
1327  *   Pointer to Ethernet device structure.
1328  *
1329  * @return
1330  *   0 on success, negative error value otherwise.
1331  */
1332 static int
1333 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
1334 {
1335         struct mrvl_priv *priv = dev->data->dev_private;
1336         int ret;
1337
1338         if (priv->isolated)
1339                 return -ENOTSUP;
1340
1341         if (!priv->ppio)
1342                 return 0;
1343
1344         ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
1345         if (ret) {
1346                 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
1347                 return -EAGAIN;
1348         }
1349
1350         return 0;
1351 }
1352
1353 /**
1354  * DPDK callback to remove a MAC address.
1355  *
1356  * @param dev
1357  *   Pointer to Ethernet device structure.
1358  * @param index
1359  *   MAC address index.
1360  */
1361 static void
1362 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
1363 {
1364         struct mrvl_priv *priv = dev->data->dev_private;
1365         char buf[RTE_ETHER_ADDR_FMT_SIZE];
1366         int ret;
1367
1368         if (priv->isolated)
1369                 return;
1370
1371         if (!priv->ppio)
1372                 return;
1373
1374         ret = pp2_ppio_remove_mac_addr(priv->ppio,
1375                                        dev->data->mac_addrs[index].addr_bytes);
1376         if (ret) {
1377                 rte_ether_format_addr(buf, sizeof(buf),
1378                                   &dev->data->mac_addrs[index]);
1379                 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
1380         }
1381 }
1382
1383 /**
1384  * DPDK callback to add a MAC address.
1385  *
1386  * @param dev
1387  *   Pointer to Ethernet device structure.
1388  * @param mac_addr
1389  *   MAC address to register.
1390  * @param index
1391  *   MAC address index.
1392  * @param vmdq
1393  *   VMDq pool index to associate address with (unused).
1394  *
1395  * @return
1396  *   0 on success, negative error value otherwise.
1397  */
1398 static int
1399 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1400                   uint32_t index, uint32_t vmdq __rte_unused)
1401 {
1402         struct mrvl_priv *priv = dev->data->dev_private;
1403         char buf[RTE_ETHER_ADDR_FMT_SIZE];
1404         int ret;
1405
1406         if (priv->isolated)
1407                 return -ENOTSUP;
1408
1409         if (!priv->ppio)
1410                 return 0;
1411
1412         if (index == 0)
1413                 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1414                 return -1;
1415
1416         /*
1417          * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1418          * parameter uc_filter_max. Maximum number of mc addresses is then
1419          * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1420          * 21 respectively.
1421          *
1422          * If more than uc_filter_max uc addresses were added to filter list
1423          * then NIC will switch to promiscuous mode automatically.
1424          *
1425          * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1426          * were added to filter list then NIC will switch to all-multicast mode
1427          * automatically.
1428          */
1429         ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1430         if (ret) {
1431                 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1432                 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1433                 return -1;
1434         }
1435
1436         return 0;
1437 }
1438
1439 /**
1440  * DPDK callback to set the primary MAC address.
1441  *
1442  * @param dev
1443  *   Pointer to Ethernet device structure.
1444  * @param mac_addr
1445  *   MAC address to register.
1446  *
1447  * @return
1448  *   0 on success, negative error value otherwise.
1449  */
1450 static int
1451 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1452 {
1453         struct mrvl_priv *priv = dev->data->dev_private;
1454         int ret;
1455
1456         if (priv->isolated)
1457                 return -ENOTSUP;
1458
1459         if (!priv->ppio)
1460                 return 0;
1461
1462         ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1463         if (ret) {
1464                 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1465                 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1466                 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1467         }
1468
1469         return ret;
1470 }
1471
1472 /**
1473  * DPDK callback to get device statistics.
1474  *
1475  * @param dev
1476  *   Pointer to Ethernet device structure.
1477  * @param stats
1478  *   Stats structure output buffer.
1479  *
1480  * @return
1481  *   0 on success, negative error value otherwise.
1482  */
1483 static int
1484 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1485 {
1486         struct mrvl_priv *priv = dev->data->dev_private;
1487         struct pp2_ppio_statistics ppio_stats;
1488         uint64_t drop_mac = 0;
1489         unsigned int i, idx, ret;
1490
1491         if (!priv->ppio)
1492                 return -EPERM;
1493
1494         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1495                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1496                 struct pp2_ppio_inq_statistics rx_stats;
1497
1498                 if (!rxq)
1499                         continue;
1500
1501                 idx = rxq->queue_id;
1502                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1503                         MRVL_LOG(ERR,
1504                                 "rx queue %d stats out of range (0 - %d)",
1505                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1506                         continue;
1507                 }
1508
1509                 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1510                                                   priv->rxq_map[idx].tc,
1511                                                   priv->rxq_map[idx].inq,
1512                                                   &rx_stats, 0);
1513                 if (unlikely(ret)) {
1514                         MRVL_LOG(ERR,
1515                                 "Failed to update rx queue %d stats", idx);
1516                         break;
1517                 }
1518
1519                 stats->q_ibytes[idx] = rxq->bytes_recv;
1520                 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1521                 stats->q_errors[idx] = rx_stats.drop_early +
1522                                        rx_stats.drop_fullq +
1523                                        rx_stats.drop_bm +
1524                                        rxq->drop_mac;
1525                 stats->ibytes += rxq->bytes_recv;
1526                 drop_mac += rxq->drop_mac;
1527         }
1528
1529         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1530                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1531                 struct pp2_ppio_outq_statistics tx_stats;
1532
1533                 if (!txq)
1534                         continue;
1535
1536                 idx = txq->queue_id;
1537                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1538                         MRVL_LOG(ERR,
1539                                 "tx queue %d stats out of range (0 - %d)",
1540                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1541                 }
1542
1543                 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1544                                                    &tx_stats, 0);
1545                 if (unlikely(ret)) {
1546                         MRVL_LOG(ERR,
1547                                 "Failed to update tx queue %d stats", idx);
1548                         break;
1549                 }
1550
1551                 stats->q_opackets[idx] = tx_stats.deq_desc;
1552                 stats->q_obytes[idx] = txq->bytes_sent;
1553                 stats->obytes += txq->bytes_sent;
1554         }
1555
1556         ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1557         if (unlikely(ret)) {
1558                 MRVL_LOG(ERR, "Failed to update port statistics");
1559                 return ret;
1560         }
1561
1562         stats->ipackets += ppio_stats.rx_packets - drop_mac;
1563         stats->opackets += ppio_stats.tx_packets;
1564         stats->imissed += ppio_stats.rx_fullq_dropped +
1565                           ppio_stats.rx_bm_dropped +
1566                           ppio_stats.rx_early_dropped +
1567                           ppio_stats.rx_fifo_dropped +
1568                           ppio_stats.rx_cls_dropped;
1569         stats->ierrors = drop_mac;
1570
1571         return 0;
1572 }
1573
1574 /**
1575  * DPDK callback to clear device statistics.
1576  *
1577  * @param dev
1578  *   Pointer to Ethernet device structure.
1579  *
1580  * @return
1581  *   0 on success, negative error value otherwise.
1582  */
1583 static int
1584 mrvl_stats_reset(struct rte_eth_dev *dev)
1585 {
1586         struct mrvl_priv *priv = dev->data->dev_private;
1587         int i;
1588
1589         if (!priv->ppio)
1590                 return 0;
1591
1592         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1593                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1594
1595                 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1596                                             priv->rxq_map[i].inq, NULL, 1);
1597                 rxq->bytes_recv = 0;
1598                 rxq->drop_mac = 0;
1599         }
1600
1601         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1602                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1603
1604                 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1605                 txq->bytes_sent = 0;
1606         }
1607
1608         return pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1609 }
1610
1611 /**
1612  * DPDK callback to get extended statistics.
1613  *
1614  * @param dev
1615  *   Pointer to Ethernet device structure.
1616  * @param stats
1617  *   Pointer to xstats table.
1618  * @param n
1619  *   Number of entries in xstats table.
1620  * @return
1621  *   Negative value on error, number of read xstats otherwise.
1622  */
1623 static int
1624 mrvl_xstats_get(struct rte_eth_dev *dev,
1625                 struct rte_eth_xstat *stats, unsigned int n)
1626 {
1627         struct mrvl_priv *priv = dev->data->dev_private;
1628         struct pp2_ppio_statistics ppio_stats;
1629         unsigned int i;
1630
1631         if (!stats)
1632                 return 0;
1633
1634         pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1635         for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1636                 uint64_t val;
1637
1638                 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1639                         val = *(uint32_t *)((uint8_t *)&ppio_stats +
1640                                             mrvl_xstats_tbl[i].offset);
1641                 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1642                         val = *(uint64_t *)((uint8_t *)&ppio_stats +
1643                                             mrvl_xstats_tbl[i].offset);
1644                 else
1645                         return -EINVAL;
1646
1647                 stats[i].id = i;
1648                 stats[i].value = val;
1649         }
1650
1651         return n;
1652 }
1653
1654 /**
1655  * DPDK callback to reset extended statistics.
1656  *
1657  * @param dev
1658  *   Pointer to Ethernet device structure.
1659  *
1660  * @return
1661  *   0 on success, negative error value otherwise.
1662  */
1663 static int
1664 mrvl_xstats_reset(struct rte_eth_dev *dev)
1665 {
1666         return mrvl_stats_reset(dev);
1667 }
1668
1669 /**
1670  * DPDK callback to get extended statistics names.
1671  *
1672  * @param dev (unused)
1673  *   Pointer to Ethernet device structure.
1674  * @param xstats_names
1675  *   Pointer to xstats names table.
1676  * @param size
1677  *   Size of the xstats names table.
1678  * @return
1679  *   Number of read names.
1680  */
1681 static int
1682 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1683                       struct rte_eth_xstat_name *xstats_names,
1684                       unsigned int size)
1685 {
1686         unsigned int i;
1687
1688         if (!xstats_names)
1689                 return RTE_DIM(mrvl_xstats_tbl);
1690
1691         for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1692                 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name,
1693                         RTE_ETH_XSTATS_NAME_SIZE);
1694
1695         return size;
1696 }
1697
1698 /**
1699  * DPDK callback to get information about the device.
1700  *
1701  * @param dev
1702  *   Pointer to Ethernet device structure (unused).
1703  * @param info
1704  *   Info structure output buffer.
1705  */
1706 static int
1707 mrvl_dev_infos_get(struct rte_eth_dev *dev,
1708                    struct rte_eth_dev_info *info)
1709 {
1710         struct mrvl_priv *priv = dev->data->dev_private;
1711
1712         info->speed_capa = ETH_LINK_SPEED_10M |
1713                            ETH_LINK_SPEED_100M |
1714                            ETH_LINK_SPEED_1G |
1715                            ETH_LINK_SPEED_2_5G |
1716                            ETH_LINK_SPEED_10G;
1717
1718         info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1719         info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1720         info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1721
1722         info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1723         info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1724         info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1725
1726         info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1727         info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1728         info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1729
1730         info->rx_offload_capa = MRVL_RX_OFFLOADS;
1731         info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1732
1733         info->tx_offload_capa = MRVL_TX_OFFLOADS;
1734         info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1735
1736         info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1737                                        ETH_RSS_NONFRAG_IPV4_TCP |
1738                                        ETH_RSS_NONFRAG_IPV4_UDP;
1739
1740         /* By default packets are dropped if no descriptors are available */
1741         info->default_rxconf.rx_drop_en = 1;
1742
1743         info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1744         info->max_mtu = priv->max_mtu;
1745
1746         return 0;
1747 }
1748
1749 /**
1750  * Return supported packet types.
1751  *
1752  * @param dev
1753  *   Pointer to Ethernet device structure (unused).
1754  *
1755  * @return
1756  *   Const pointer to the table with supported packet types.
1757  */
1758 static const uint32_t *
1759 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1760 {
1761         static const uint32_t ptypes[] = {
1762                 RTE_PTYPE_L2_ETHER,
1763                 RTE_PTYPE_L2_ETHER_VLAN,
1764                 RTE_PTYPE_L2_ETHER_QINQ,
1765                 RTE_PTYPE_L3_IPV4,
1766                 RTE_PTYPE_L3_IPV4_EXT,
1767                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1768                 RTE_PTYPE_L3_IPV6,
1769                 RTE_PTYPE_L3_IPV6_EXT,
1770                 RTE_PTYPE_L2_ETHER_ARP,
1771                 RTE_PTYPE_L4_TCP,
1772                 RTE_PTYPE_L4_UDP
1773         };
1774
1775         return ptypes;
1776 }
1777
1778 /**
1779  * DPDK callback to get information about specific receive queue.
1780  *
1781  * @param dev
1782  *   Pointer to Ethernet device structure.
1783  * @param rx_queue_id
1784  *   Receive queue index.
1785  * @param qinfo
1786  *   Receive queue information structure.
1787  */
1788 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1789                               struct rte_eth_rxq_info *qinfo)
1790 {
1791         struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1792         struct mrvl_priv *priv = dev->data->dev_private;
1793         int inq = priv->rxq_map[rx_queue_id].inq;
1794         int tc = priv->rxq_map[rx_queue_id].tc;
1795         struct pp2_ppio_tc_params *tc_params =
1796                 &priv->ppio_params.inqs_params.tcs_params[tc];
1797
1798         qinfo->mp = q->mp;
1799         qinfo->nb_desc = tc_params->inqs_params[inq].size;
1800 }
1801
1802 /**
1803  * DPDK callback to get information about specific transmit queue.
1804  *
1805  * @param dev
1806  *   Pointer to Ethernet device structure.
1807  * @param tx_queue_id
1808  *   Transmit queue index.
1809  * @param qinfo
1810  *   Transmit queue information structure.
1811  */
1812 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1813                               struct rte_eth_txq_info *qinfo)
1814 {
1815         struct mrvl_priv *priv = dev->data->dev_private;
1816         struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1817
1818         qinfo->nb_desc =
1819                 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1820         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1821 }
1822
1823 /**
1824  * DPDK callback to Configure a VLAN filter.
1825  *
1826  * @param dev
1827  *   Pointer to Ethernet device structure.
1828  * @param vlan_id
1829  *   VLAN ID to filter.
1830  * @param on
1831  *   Toggle filter.
1832  *
1833  * @return
1834  *   0 on success, negative error value otherwise.
1835  */
1836 static int
1837 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1838 {
1839         struct mrvl_priv *priv = dev->data->dev_private;
1840
1841         if (priv->isolated)
1842                 return -ENOTSUP;
1843
1844         if (!priv->ppio)
1845                 return 0;
1846
1847         return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1848                     pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1849 }
1850
1851 /**
1852  * DPDK callback to Configure VLAN offload.
1853  *
1854  * @param dev
1855  *   Pointer to Ethernet device structure.
1856  * @param mask
1857  *   VLAN offload mask.
1858  *
1859  * @return
1860  *   0 on success, negative error value otherwise.
1861  */
1862 static int mrvl_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1863 {
1864         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1865         int ret;
1866
1867         if (mask & ETH_VLAN_STRIP_MASK) {
1868                 MRVL_LOG(ERR, "VLAN stripping is not supported\n");
1869                 return -ENOTSUP;
1870         }
1871
1872         if (mask & ETH_VLAN_FILTER_MASK) {
1873                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1874                         ret = mrvl_populate_vlan_table(dev, 1);
1875                 else
1876                         ret = mrvl_populate_vlan_table(dev, 0);
1877
1878                 if (ret)
1879                         return ret;
1880         }
1881
1882         if (mask & ETH_VLAN_EXTEND_MASK) {
1883                 MRVL_LOG(ERR, "Extend VLAN not supported\n");
1884                 return -ENOTSUP;
1885         }
1886
1887         return 0;
1888 }
1889
1890 /**
1891  * Release buffers to hardware bpool (buffer-pool)
1892  *
1893  * @param rxq
1894  *   Receive queue pointer.
1895  * @param num
1896  *   Number of buffers to release to bpool.
1897  *
1898  * @return
1899  *   0 on success, negative error value otherwise.
1900  */
1901 static int
1902 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1903 {
1904         struct buff_release_entry entries[num];
1905         struct rte_mbuf *mbufs[num];
1906         int i, ret;
1907         unsigned int core_id;
1908         struct pp2_hif *hif;
1909         struct pp2_bpool *bpool;
1910
1911         core_id = rte_lcore_id();
1912         if (core_id == LCORE_ID_ANY)
1913                 core_id = rte_get_main_lcore();
1914
1915         hif = mrvl_get_hif(rxq->priv, core_id);
1916         if (!hif)
1917                 return -1;
1918
1919         bpool = rxq->priv->bpool;
1920
1921         ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1922         if (ret)
1923                 return ret;
1924
1925         if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1926                 cookie_addr_high =
1927                         (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1928
1929         for (i = 0; i < num; i++) {
1930                 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1931                         != cookie_addr_high) {
1932                         MRVL_LOG(ERR,
1933                                 "mbuf virtual addr high is out of range "
1934                                 "0x%x instead of 0x%x\n",
1935                                 (uint32_t)((uint64_t)mbufs[i] >> 32),
1936                                 (uint32_t)(cookie_addr_high >> 32));
1937                         goto out;
1938                 }
1939
1940                 entries[i].buff.addr =
1941                         rte_mbuf_data_iova_default(mbufs[i]);
1942                 entries[i].buff.cookie = (uintptr_t)mbufs[i];
1943                 entries[i].bpool = bpool;
1944         }
1945
1946         pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1947         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1948
1949         if (i != num)
1950                 goto out;
1951
1952         return 0;
1953 out:
1954         for (; i < num; i++)
1955                 rte_pktmbuf_free(mbufs[i]);
1956
1957         return -1;
1958 }
1959
1960 /**
1961  * DPDK callback to configure the receive queue.
1962  *
1963  * @param dev
1964  *   Pointer to Ethernet device structure.
1965  * @param idx
1966  *   RX queue index.
1967  * @param desc
1968  *   Number of descriptors to configure in queue.
1969  * @param socket
1970  *   NUMA socket on which memory must be allocated.
1971  * @param conf
1972  *   Thresholds parameters.
1973  * @param mp
1974  *   Memory pool for buffer allocations.
1975  *
1976  * @return
1977  *   0 on success, negative error value otherwise.
1978  */
1979 static int
1980 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1981                     unsigned int socket,
1982                     const struct rte_eth_rxconf *conf,
1983                     struct rte_mempool *mp)
1984 {
1985         struct mrvl_priv *priv = dev->data->dev_private;
1986         struct mrvl_rxq *rxq;
1987         uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp);
1988         uint32_t max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN;
1989         int ret, tc, inq;
1990         uint64_t offloads;
1991
1992         offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1993
1994         if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1995                 /*
1996                  * Unknown TC mapping, mapping will not have a correct queue.
1997                  */
1998                 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1999                         idx, priv->ppio_id);
2000                 return -EFAULT;
2001         }
2002
2003         frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS;
2004         if (frame_size < max_rx_pktlen) {
2005                 MRVL_LOG(WARNING,
2006                         "Mbuf size must be increased to %u bytes to hold up "
2007                         "to %u bytes of data.",
2008                         max_rx_pktlen + buf_size - frame_size,
2009                         max_rx_pktlen);
2010                 dev->data->mtu = frame_size - RTE_ETHER_HDR_LEN;
2011                 MRVL_LOG(INFO, "Setting MTU to %u", dev->data->mtu);
2012         }
2013
2014         if (dev->data->rx_queues[idx]) {
2015                 rte_free(dev->data->rx_queues[idx]);
2016                 dev->data->rx_queues[idx] = NULL;
2017         }
2018
2019         rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
2020         if (!rxq)
2021                 return -ENOMEM;
2022
2023         rxq->priv = priv;
2024         rxq->mp = mp;
2025         rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
2026         rxq->queue_id = idx;
2027         rxq->port_id = dev->data->port_id;
2028         mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
2029
2030         tc = priv->rxq_map[rxq->queue_id].tc,
2031         inq = priv->rxq_map[rxq->queue_id].inq;
2032         priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
2033                 desc;
2034
2035         ret = mrvl_fill_bpool(rxq, desc);
2036         if (ret) {
2037                 rte_free(rxq);
2038                 return ret;
2039         }
2040
2041         priv->bpool_init_size += desc;
2042
2043         dev->data->rx_queues[idx] = rxq;
2044
2045         return 0;
2046 }
2047
2048 /**
2049  * DPDK callback to release the receive queue.
2050  *
2051  * @param dev
2052  *   Pointer to Ethernet device structure.
2053  * @param qid
2054  *   Receive queue index.
2055  */
2056 static void
2057 mrvl_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2058 {
2059         struct mrvl_rxq *q = dev->data->rx_queues[qid];
2060         struct pp2_ppio_tc_params *tc_params;
2061         int i, num, tc, inq;
2062         struct pp2_hif *hif;
2063         unsigned int core_id = rte_lcore_id();
2064
2065         if (core_id == LCORE_ID_ANY)
2066                 core_id = rte_get_main_lcore();
2067
2068         if (!q)
2069                 return;
2070
2071         hif = mrvl_get_hif(q->priv, core_id);
2072
2073         if (!hif)
2074                 return;
2075
2076         tc = q->priv->rxq_map[q->queue_id].tc;
2077         inq = q->priv->rxq_map[q->queue_id].inq;
2078         tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
2079         num = tc_params->inqs_params[inq].size;
2080         for (i = 0; i < num; i++) {
2081                 struct pp2_buff_inf inf;
2082                 uint64_t addr;
2083
2084                 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
2085                 addr = cookie_addr_high | inf.cookie;
2086                 rte_pktmbuf_free((struct rte_mbuf *)addr);
2087         }
2088
2089         rte_free(q);
2090 }
2091
2092 /**
2093  * DPDK callback to configure the transmit queue.
2094  *
2095  * @param dev
2096  *   Pointer to Ethernet device structure.
2097  * @param idx
2098  *   Transmit queue index.
2099  * @param desc
2100  *   Number of descriptors to configure in the queue.
2101  * @param socket
2102  *   NUMA socket on which memory must be allocated.
2103  * @param conf
2104  *   Tx queue configuration parameters.
2105  *
2106  * @return
2107  *   0 on success, negative error value otherwise.
2108  */
2109 static int
2110 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2111                     unsigned int socket,
2112                     const struct rte_eth_txconf *conf)
2113 {
2114         struct mrvl_priv *priv = dev->data->dev_private;
2115         struct mrvl_txq *txq;
2116
2117         if (dev->data->tx_queues[idx]) {
2118                 rte_free(dev->data->tx_queues[idx]);
2119                 dev->data->tx_queues[idx] = NULL;
2120         }
2121
2122         txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
2123         if (!txq)
2124                 return -ENOMEM;
2125
2126         txq->priv = priv;
2127         txq->queue_id = idx;
2128         txq->port_id = dev->data->port_id;
2129         txq->tx_deferred_start = conf->tx_deferred_start;
2130         dev->data->tx_queues[idx] = txq;
2131
2132         priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
2133
2134         return 0;
2135 }
2136
2137 /**
2138  * DPDK callback to release the transmit queue.
2139  *
2140  * @param dev
2141  *   Pointer to Ethernet device structure.
2142  * @param qid
2143  *   Transmit queue index.
2144  */
2145 static void
2146 mrvl_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2147 {
2148         struct mrvl_txq *q = dev->data->tx_queues[qid];
2149
2150         if (!q)
2151                 return;
2152
2153         rte_free(q);
2154 }
2155
2156 /**
2157  * DPDK callback to get flow control configuration.
2158  *
2159  * @param dev
2160  *  Pointer to Ethernet device structure.
2161  * @param fc_conf
2162  *  Pointer to the flow control configuration.
2163  *
2164  * @return
2165  *  0 on success, negative error value otherwise.
2166  */
2167 static int
2168 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2169 {
2170         struct mrvl_priv *priv = dev->data->dev_private;
2171         int ret, en;
2172
2173         if (!priv->ppio) {
2174                 memcpy(fc_conf, &priv->fc_conf, sizeof(struct rte_eth_fc_conf));
2175                 return 0;
2176         }
2177
2178         fc_conf->autoneg = 1;
2179         ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
2180         if (ret) {
2181                 MRVL_LOG(ERR, "Failed to read rx pause state");
2182                 return ret;
2183         }
2184
2185         fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
2186
2187         ret = pp2_ppio_get_tx_pause(priv->ppio, &en);
2188         if (ret) {
2189                 MRVL_LOG(ERR, "Failed to read tx pause state");
2190                 return ret;
2191         }
2192
2193         if (en) {
2194                 if (fc_conf->mode == RTE_FC_NONE)
2195                         fc_conf->mode = RTE_FC_TX_PAUSE;
2196                 else
2197                         fc_conf->mode = RTE_FC_FULL;
2198         }
2199
2200         return 0;
2201 }
2202
2203 /**
2204  * DPDK callback to set flow control configuration.
2205  *
2206  * @param dev
2207  *  Pointer to Ethernet device structure.
2208  * @param fc_conf
2209  *  Pointer to the flow control configuration.
2210  *
2211  * @return
2212  *  0 on success, negative error value otherwise.
2213  */
2214 static int
2215 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2216 {
2217         struct mrvl_priv *priv = dev->data->dev_private;
2218         struct pp2_ppio_tx_pause_params mrvl_pause_params;
2219         int ret;
2220         int rx_en, tx_en;
2221
2222         if (fc_conf->high_water ||
2223             fc_conf->low_water ||
2224             fc_conf->pause_time ||
2225             fc_conf->mac_ctrl_frame_fwd) {
2226                 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
2227
2228                 return -EINVAL;
2229         }
2230
2231         if (fc_conf->autoneg == 0) {
2232                 MRVL_LOG(ERR, "Flowctrl Autoneg disable is not supported");
2233                 return -EINVAL;
2234         }
2235
2236         if (!priv->ppio) {
2237                 memcpy(&priv->fc_conf, fc_conf, sizeof(struct rte_eth_fc_conf));
2238                 priv->flow_ctrl = 1;
2239                 return 0;
2240         }
2241
2242         switch (fc_conf->mode) {
2243         case RTE_FC_FULL:
2244                 rx_en = 1;
2245                 tx_en = 1;
2246                 break;
2247         case RTE_FC_TX_PAUSE:
2248                 rx_en = 0;
2249                 tx_en = 1;
2250                 break;
2251         case RTE_FC_RX_PAUSE:
2252                 rx_en = 1;
2253                 tx_en = 0;
2254                 break;
2255         case RTE_FC_NONE:
2256                 rx_en = 0;
2257                 tx_en = 0;
2258                 break;
2259         default:
2260                 MRVL_LOG(ERR, "Incorrect Flow control flag (%d)",
2261                          fc_conf->mode);
2262                 return -EINVAL;
2263         }
2264
2265         /* Set RX flow control */
2266         ret = pp2_ppio_set_rx_pause(priv->ppio, rx_en);
2267         if (ret) {
2268                 MRVL_LOG(ERR, "Failed to change RX flowctrl");
2269                 return ret;
2270         }
2271
2272         /* Set TX flow control */
2273         mrvl_pause_params.en = tx_en;
2274         /* all inqs participate in xon/xoff decision */
2275         mrvl_pause_params.use_tc_pause_inqs = 0;
2276         ret = pp2_ppio_set_tx_pause(priv->ppio, &mrvl_pause_params);
2277         if (ret) {
2278                 MRVL_LOG(ERR, "Failed to change TX flowctrl");
2279                 return ret;
2280         }
2281
2282         return 0;
2283 }
2284
2285 /**
2286  * Update RSS hash configuration
2287  *
2288  * @param dev
2289  *   Pointer to Ethernet device structure.
2290  * @param rss_conf
2291  *   Pointer to RSS configuration.
2292  *
2293  * @return
2294  *   0 on success, negative error value otherwise.
2295  */
2296 static int
2297 mrvl_rss_hash_update(struct rte_eth_dev *dev,
2298                      struct rte_eth_rss_conf *rss_conf)
2299 {
2300         struct mrvl_priv *priv = dev->data->dev_private;
2301
2302         if (priv->isolated)
2303                 return -ENOTSUP;
2304
2305         return mrvl_configure_rss(priv, rss_conf);
2306 }
2307
2308 /**
2309  * DPDK callback to get RSS hash configuration.
2310  *
2311  * @param dev
2312  *   Pointer to Ethernet device structure.
2313  * @rss_conf
2314  *   Pointer to RSS configuration.
2315  *
2316  * @return
2317  *   Always 0.
2318  */
2319 static int
2320 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
2321                        struct rte_eth_rss_conf *rss_conf)
2322 {
2323         struct mrvl_priv *priv = dev->data->dev_private;
2324         enum pp2_ppio_hash_type hash_type =
2325                 priv->ppio_params.inqs_params.hash_type;
2326
2327         rss_conf->rss_key = NULL;
2328
2329         if (hash_type == PP2_PPIO_HASH_T_NONE)
2330                 rss_conf->rss_hf = 0;
2331         else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
2332                 rss_conf->rss_hf = ETH_RSS_IPV4;
2333         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
2334                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
2335         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
2336                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
2337
2338         return 0;
2339 }
2340
2341 /**
2342  * DPDK callback to get rte_flow callbacks.
2343  *
2344  * @param dev
2345  *   Pointer to the device structure.
2346  * @param ops
2347  *   Pointer to pass the flow ops.
2348  *
2349  * @return
2350  *   0 on success, negative error value otherwise.
2351  */
2352 static int
2353 mrvl_eth_flow_ops_get(struct rte_eth_dev *dev __rte_unused,
2354                       const struct rte_flow_ops **ops)
2355 {
2356         *ops = &mrvl_flow_ops;
2357         return 0;
2358 }
2359
2360 /**
2361  * DPDK callback to get rte_mtr callbacks.
2362  *
2363  * @param dev
2364  *   Pointer to the device structure.
2365  * @param ops
2366  *   Pointer to pass the mtr ops.
2367  *
2368  * @return
2369  *   Always 0.
2370  */
2371 static int
2372 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2373 {
2374         *(const void **)ops = &mrvl_mtr_ops;
2375
2376         return 0;
2377 }
2378
2379 /**
2380  * DPDK callback to get rte_tm callbacks.
2381  *
2382  * @param dev
2383  *   Pointer to the device structure.
2384  * @param ops
2385  *   Pointer to pass the tm ops.
2386  *
2387  * @return
2388  *   Always 0.
2389  */
2390 static int
2391 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2392 {
2393         *(const void **)ops = &mrvl_tm_ops;
2394
2395         return 0;
2396 }
2397
2398 static const struct eth_dev_ops mrvl_ops = {
2399         .dev_configure = mrvl_dev_configure,
2400         .dev_start = mrvl_dev_start,
2401         .dev_stop = mrvl_dev_stop,
2402         .dev_set_link_up = mrvl_dev_set_link_up,
2403         .dev_set_link_down = mrvl_dev_set_link_down,
2404         .dev_close = mrvl_dev_close,
2405         .link_update = mrvl_link_update,
2406         .promiscuous_enable = mrvl_promiscuous_enable,
2407         .allmulticast_enable = mrvl_allmulticast_enable,
2408         .promiscuous_disable = mrvl_promiscuous_disable,
2409         .allmulticast_disable = mrvl_allmulticast_disable,
2410         .mac_addr_remove = mrvl_mac_addr_remove,
2411         .mac_addr_add = mrvl_mac_addr_add,
2412         .mac_addr_set = mrvl_mac_addr_set,
2413         .mtu_set = mrvl_mtu_set,
2414         .stats_get = mrvl_stats_get,
2415         .stats_reset = mrvl_stats_reset,
2416         .xstats_get = mrvl_xstats_get,
2417         .xstats_reset = mrvl_xstats_reset,
2418         .xstats_get_names = mrvl_xstats_get_names,
2419         .dev_infos_get = mrvl_dev_infos_get,
2420         .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
2421         .rxq_info_get = mrvl_rxq_info_get,
2422         .txq_info_get = mrvl_txq_info_get,
2423         .vlan_filter_set = mrvl_vlan_filter_set,
2424         .vlan_offload_set = mrvl_vlan_offload_set,
2425         .tx_queue_start = mrvl_tx_queue_start,
2426         .tx_queue_stop = mrvl_tx_queue_stop,
2427         .rx_queue_setup = mrvl_rx_queue_setup,
2428         .rx_queue_release = mrvl_rx_queue_release,
2429         .tx_queue_setup = mrvl_tx_queue_setup,
2430         .tx_queue_release = mrvl_tx_queue_release,
2431         .flow_ctrl_get = mrvl_flow_ctrl_get,
2432         .flow_ctrl_set = mrvl_flow_ctrl_set,
2433         .rss_hash_update = mrvl_rss_hash_update,
2434         .rss_hash_conf_get = mrvl_rss_hash_conf_get,
2435         .flow_ops_get = mrvl_eth_flow_ops_get,
2436         .mtr_ops_get = mrvl_mtr_ops_get,
2437         .tm_ops_get = mrvl_tm_ops_get,
2438 };
2439
2440 /**
2441  * Return packet type information and l3/l4 offsets.
2442  *
2443  * @param desc
2444  *   Pointer to the received packet descriptor.
2445  * @param l3_offset
2446  *   l3 packet offset.
2447  * @param l4_offset
2448  *   l4 packet offset.
2449  *
2450  * @return
2451  *   Packet type information.
2452  */
2453 static inline uint64_t
2454 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2455                                     uint8_t *l3_offset, uint8_t *l4_offset)
2456 {
2457         enum pp2_inq_l3_type l3_type;
2458         enum pp2_inq_l4_type l4_type;
2459         enum pp2_inq_vlan_tag vlan_tag;
2460         uint64_t packet_type;
2461
2462         pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2463         pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2464         pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
2465
2466         packet_type = RTE_PTYPE_L2_ETHER;
2467
2468         switch (vlan_tag) {
2469         case PP2_INQ_VLAN_TAG_SINGLE:
2470                 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
2471                 break;
2472         case PP2_INQ_VLAN_TAG_DOUBLE:
2473         case PP2_INQ_VLAN_TAG_TRIPLE:
2474                 packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
2475                 break;
2476         default:
2477                 break;
2478         }
2479
2480         switch (l3_type) {
2481         case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2482                 packet_type |= RTE_PTYPE_L3_IPV4;
2483                 break;
2484         case PP2_INQ_L3_TYPE_IPV4_OK:
2485                 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2486                 break;
2487         case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2488                 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2489                 break;
2490         case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2491                 packet_type |= RTE_PTYPE_L3_IPV6;
2492                 break;
2493         case PP2_INQ_L3_TYPE_IPV6_EXT:
2494                 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2495                 break;
2496         case PP2_INQ_L3_TYPE_ARP:
2497                 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2498                 /*
2499                  * In case of ARP l4_offset is set to wrong value.
2500                  * Set it to proper one so that later on mbuf->l3_len can be
2501                  * calculated subtracting l4_offset and l3_offset.
2502                  */
2503                 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2504                 break;
2505         default:
2506                 break;
2507         }
2508
2509         switch (l4_type) {
2510         case PP2_INQ_L4_TYPE_TCP:
2511                 packet_type |= RTE_PTYPE_L4_TCP;
2512                 break;
2513         case PP2_INQ_L4_TYPE_UDP:
2514                 packet_type |= RTE_PTYPE_L4_UDP;
2515                 break;
2516         default:
2517                 break;
2518         }
2519
2520         return packet_type;
2521 }
2522
2523 /**
2524  * Get offload information from the received packet descriptor.
2525  *
2526  * @param desc
2527  *   Pointer to the received packet descriptor.
2528  *
2529  * @return
2530  *   Mbuf offload flags.
2531  */
2532 static inline uint64_t
2533 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc, uint64_t packet_type)
2534 {
2535         uint64_t flags = 0;
2536         enum pp2_inq_desc_status status;
2537
2538         if (RTE_ETH_IS_IPV4_HDR(packet_type)) {
2539                 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2540                 if (unlikely(status != PP2_DESC_ERR_OK))
2541                         flags |= PKT_RX_IP_CKSUM_BAD;
2542                 else
2543                         flags |= PKT_RX_IP_CKSUM_GOOD;
2544         }
2545
2546         if (((packet_type & RTE_PTYPE_L4_UDP) == RTE_PTYPE_L4_UDP) ||
2547             ((packet_type & RTE_PTYPE_L4_TCP) == RTE_PTYPE_L4_TCP)) {
2548                 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2549                 if (unlikely(status != PP2_DESC_ERR_OK))
2550                         flags |= PKT_RX_L4_CKSUM_BAD;
2551                 else
2552                         flags |= PKT_RX_L4_CKSUM_GOOD;
2553         }
2554
2555         return flags;
2556 }
2557
2558 /**
2559  * DPDK callback for receive.
2560  *
2561  * @param rxq
2562  *   Generic pointer to the receive queue.
2563  * @param rx_pkts
2564  *   Array to store received packets.
2565  * @param nb_pkts
2566  *   Maximum number of packets in array.
2567  *
2568  * @return
2569  *   Number of packets successfully received.
2570  */
2571 static uint16_t
2572 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2573 {
2574         struct mrvl_rxq *q = rxq;
2575         struct pp2_ppio_desc descs[nb_pkts];
2576         struct pp2_bpool *bpool;
2577         int i, ret, rx_done = 0;
2578         int num;
2579         struct pp2_hif *hif;
2580         unsigned int core_id = rte_lcore_id();
2581
2582         hif = mrvl_get_hif(q->priv, core_id);
2583
2584         if (unlikely(!q->priv->ppio || !hif))
2585                 return 0;
2586
2587         bpool = q->priv->bpool;
2588
2589         ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2590                             q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2591         if (unlikely(ret < 0))
2592                 return 0;
2593
2594         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2595
2596         for (i = 0; i < nb_pkts; i++) {
2597                 struct rte_mbuf *mbuf;
2598                 uint8_t l3_offset, l4_offset;
2599                 enum pp2_inq_desc_status status;
2600                 uint64_t addr;
2601
2602                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2603                         struct pp2_ppio_desc *pref_desc;
2604                         u64 pref_addr;
2605
2606                         pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2607                         pref_addr = cookie_addr_high |
2608                                     pp2_ppio_inq_desc_get_cookie(pref_desc);
2609                         rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2610                         rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2611                 }
2612
2613                 addr = cookie_addr_high |
2614                        pp2_ppio_inq_desc_get_cookie(&descs[i]);
2615                 mbuf = (struct rte_mbuf *)addr;
2616                 rte_pktmbuf_reset(mbuf);
2617
2618                 /* drop packet in case of mac, overrun or resource error */
2619                 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2620                 if ((unlikely(status != PP2_DESC_ERR_OK)) &&
2621                         !(q->priv->forward_bad_frames)) {
2622                         struct pp2_buff_inf binf = {
2623                                 .addr = rte_mbuf_data_iova_default(mbuf),
2624                                 .cookie = (uint64_t)mbuf,
2625                         };
2626
2627                         pp2_bpool_put_buff(hif, bpool, &binf);
2628                         mrvl_port_bpool_size
2629                                 [bpool->pp2_id][bpool->id][core_id]++;
2630                         q->drop_mac++;
2631                         continue;
2632                 }
2633
2634                 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2635                 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2636                 mbuf->data_len = mbuf->pkt_len;
2637                 mbuf->port = q->port_id;
2638                 mbuf->packet_type =
2639                         mrvl_desc_to_packet_type_and_offset(&descs[i],
2640                                                             &l3_offset,
2641                                                             &l4_offset);
2642                 mbuf->l2_len = l3_offset;
2643                 mbuf->l3_len = l4_offset - l3_offset;
2644
2645                 if (likely(q->cksum_enabled))
2646                         mbuf->ol_flags =
2647                                 mrvl_desc_to_ol_flags(&descs[i],
2648                                                       mbuf->packet_type);
2649
2650                 rx_pkts[rx_done++] = mbuf;
2651                 q->bytes_recv += mbuf->pkt_len;
2652         }
2653
2654         if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2655                 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2656
2657                 if (unlikely(num <= q->priv->bpool_min_size ||
2658                              (!rx_done && num < q->priv->bpool_init_size))) {
2659                         mrvl_fill_bpool(q, q->priv->fill_bpool_buffs);
2660                 } else if (unlikely(num > q->priv->bpool_max_size)) {
2661                         int i;
2662                         int pkt_to_remove = num - q->priv->bpool_init_size;
2663                         struct rte_mbuf *mbuf;
2664                         struct pp2_buff_inf buff;
2665
2666                         for (i = 0; i < pkt_to_remove; i++) {
2667                                 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2668                                 if (ret)
2669                                         break;
2670                                 mbuf = (struct rte_mbuf *)
2671                                         (cookie_addr_high | buff.cookie);
2672                                 rte_pktmbuf_free(mbuf);
2673                         }
2674                         mrvl_port_bpool_size
2675                                 [bpool->pp2_id][bpool->id][core_id] -= i;
2676                 }
2677                 rte_spinlock_unlock(&q->priv->lock);
2678         }
2679
2680         return rx_done;
2681 }
2682
2683 /**
2684  * Prepare offload information.
2685  *
2686  * @param ol_flags
2687  *   Offload flags.
2688  * @param l3_type
2689  *   Pointer to the pp2_ouq_l3_type structure.
2690  * @param l4_type
2691  *   Pointer to the pp2_outq_l4_type structure.
2692  * @param gen_l3_cksum
2693  *   Will be set to 1 in case l3 checksum is computed.
2694  * @param l4_cksum
2695  *   Will be set to 1 in case l4 checksum is computed.
2696  */
2697 static inline void
2698 mrvl_prepare_proto_info(uint64_t ol_flags,
2699                         enum pp2_outq_l3_type *l3_type,
2700                         enum pp2_outq_l4_type *l4_type,
2701                         int *gen_l3_cksum,
2702                         int *gen_l4_cksum)
2703 {
2704         /*
2705          * Based on ol_flags prepare information
2706          * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2707          * for offloading.
2708          * in most of the checksum cases ipv4 must be set, so this is the
2709          * default value
2710          */
2711         *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2712         *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2713
2714         if (ol_flags & PKT_TX_IPV6) {
2715                 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2716                 /* no checksum for ipv6 header */
2717                 *gen_l3_cksum = 0;
2718         }
2719
2720         if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) {
2721                 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2722                 *gen_l4_cksum = 1;
2723         } else if ((ol_flags & PKT_TX_L4_MASK) ==  PKT_TX_UDP_CKSUM) {
2724                 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2725                 *gen_l4_cksum = 1;
2726         } else {
2727                 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2728                 /* no checksum for other type */
2729                 *gen_l4_cksum = 0;
2730         }
2731 }
2732
2733 /**
2734  * Release already sent buffers to bpool (buffer-pool).
2735  *
2736  * @param ppio
2737  *   Pointer to the port structure.
2738  * @param hif
2739  *   Pointer to the MUSDK hardware interface.
2740  * @param sq
2741  *   Pointer to the shadow queue.
2742  * @param qid
2743  *   Queue id number.
2744  * @param force
2745  *   Force releasing packets.
2746  */
2747 static inline void
2748 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2749                        unsigned int core_id, struct mrvl_shadow_txq *sq,
2750                        int qid, int force)
2751 {
2752         struct buff_release_entry *entry;
2753         uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2754         int i;
2755
2756         pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2757
2758         sq->num_to_release += nb_done;
2759
2760         if (likely(!force &&
2761                    sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2762                 return;
2763
2764         nb_done = sq->num_to_release;
2765         sq->num_to_release = 0;
2766
2767         for (i = 0; i < nb_done; i++) {
2768                 entry = &sq->ent[sq->tail + num];
2769                 if (unlikely(!entry->buff.addr)) {
2770                         MRVL_LOG(ERR,
2771                                 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2772                                 sq->tail, (u64)entry->buff.cookie,
2773                                 (u64)entry->buff.addr);
2774                         skip_bufs = 1;
2775                         goto skip;
2776                 }
2777
2778                 if (unlikely(!entry->bpool)) {
2779                         struct rte_mbuf *mbuf;
2780
2781                         mbuf = (struct rte_mbuf *)entry->buff.cookie;
2782                         rte_pktmbuf_free(mbuf);
2783                         skip_bufs = 1;
2784                         goto skip;
2785                 }
2786
2787                 mrvl_port_bpool_size
2788                         [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2789                 num++;
2790                 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2791                         goto skip;
2792                 continue;
2793 skip:
2794                 if (likely(num))
2795                         pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2796                 num += skip_bufs;
2797                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2798                 sq->size -= num;
2799                 num = 0;
2800                 skip_bufs = 0;
2801         }
2802
2803         if (likely(num)) {
2804                 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2805                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2806                 sq->size -= num;
2807         }
2808 }
2809
2810 /**
2811  * DPDK callback for transmit.
2812  *
2813  * @param txq
2814  *   Generic pointer transmit queue.
2815  * @param tx_pkts
2816  *   Packets to transmit.
2817  * @param nb_pkts
2818  *   Number of packets in array.
2819  *
2820  * @return
2821  *   Number of packets successfully transmitted.
2822  */
2823 static uint16_t
2824 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2825 {
2826         struct mrvl_txq *q = txq;
2827         struct mrvl_shadow_txq *sq;
2828         struct pp2_hif *hif;
2829         struct pp2_ppio_desc descs[nb_pkts];
2830         unsigned int core_id = rte_lcore_id();
2831         int i, bytes_sent = 0;
2832         uint16_t num, sq_free_size;
2833         uint64_t addr;
2834
2835         hif = mrvl_get_hif(q->priv, core_id);
2836         sq = &q->shadow_txqs[core_id];
2837
2838         if (unlikely(!q->priv->ppio || !hif))
2839                 return 0;
2840
2841         if (sq->size)
2842                 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2843                                        sq, q->queue_id, 0);
2844
2845         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2846         if (unlikely(nb_pkts > sq_free_size))
2847                 nb_pkts = sq_free_size;
2848
2849         for (i = 0; i < nb_pkts; i++) {
2850                 struct rte_mbuf *mbuf = tx_pkts[i];
2851                 int gen_l3_cksum, gen_l4_cksum;
2852                 enum pp2_outq_l3_type l3_type;
2853                 enum pp2_outq_l4_type l4_type;
2854
2855                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2856                         struct rte_mbuf *pref_pkt_hdr;
2857
2858                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2859                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
2860                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
2861                 }
2862
2863                 mrvl_fill_shadowq(sq, mbuf);
2864                 mrvl_fill_desc(&descs[i], mbuf);
2865
2866                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2867                 /*
2868                  * in case unsupported ol_flags were passed
2869                  * do not update descriptor offload information
2870                  */
2871                 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS))
2872                         continue;
2873                 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type,
2874                                         &gen_l3_cksum, &gen_l4_cksum);
2875
2876                 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2877                                                   mbuf->l2_len,
2878                                                   mbuf->l2_len + mbuf->l3_len,
2879                                                   gen_l3_cksum, gen_l4_cksum);
2880         }
2881
2882         num = nb_pkts;
2883         pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2884         /* number of packets that were not sent */
2885         if (unlikely(num > nb_pkts)) {
2886                 for (i = nb_pkts; i < num; i++) {
2887                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2888                                 MRVL_PP2_TX_SHADOWQ_MASK;
2889                         addr = sq->ent[sq->head].buff.cookie;
2890                         bytes_sent -=
2891                                 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2892                 }
2893                 sq->size -= num - nb_pkts;
2894         }
2895
2896         q->bytes_sent += bytes_sent;
2897
2898         return nb_pkts;
2899 }
2900
2901 /** DPDK callback for S/G transmit.
2902  *
2903  * @param txq
2904  *   Generic pointer transmit queue.
2905  * @param tx_pkts
2906  *   Packets to transmit.
2907  * @param nb_pkts
2908  *   Number of packets in array.
2909  *
2910  * @return
2911  *   Number of packets successfully transmitted.
2912  */
2913 static uint16_t
2914 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
2915                      uint16_t nb_pkts)
2916 {
2917         struct mrvl_txq *q = txq;
2918         struct mrvl_shadow_txq *sq;
2919         struct pp2_hif *hif;
2920         struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS];
2921         struct pp2_ppio_sg_pkts pkts;
2922         uint8_t frags[nb_pkts];
2923         unsigned int core_id = rte_lcore_id();
2924         int i, j, bytes_sent = 0;
2925         int tail, tail_first;
2926         uint16_t num, sq_free_size;
2927         uint16_t nb_segs, total_descs = 0;
2928         uint64_t addr;
2929
2930         hif = mrvl_get_hif(q->priv, core_id);
2931         sq = &q->shadow_txqs[core_id];
2932         pkts.frags = frags;
2933         pkts.num = 0;
2934
2935         if (unlikely(!q->priv->ppio || !hif))
2936                 return 0;
2937
2938         if (sq->size)
2939                 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2940                                        sq, q->queue_id, 0);
2941
2942         /* Save shadow queue free size */
2943         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2944
2945         tail = 0;
2946         for (i = 0; i < nb_pkts; i++) {
2947                 struct rte_mbuf *mbuf = tx_pkts[i];
2948                 struct rte_mbuf *seg = NULL;
2949                 int gen_l3_cksum, gen_l4_cksum;
2950                 enum pp2_outq_l3_type l3_type;
2951                 enum pp2_outq_l4_type l4_type;
2952
2953                 nb_segs = mbuf->nb_segs;
2954                 tail_first = tail;
2955                 total_descs += nb_segs;
2956
2957                 /*
2958                  * Check if total_descs does not exceed
2959                  * shadow queue free size
2960                  */
2961                 if (unlikely(total_descs > sq_free_size)) {
2962                         total_descs -= nb_segs;
2963                         break;
2964                 }
2965
2966                 /* Check if nb_segs does not exceed the max nb of desc per
2967                  * fragmented packet
2968                  */
2969                 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) {
2970                         total_descs -= nb_segs;
2971                         RTE_LOG(ERR, PMD,
2972                                 "Too many segments. Packet won't be sent.\n");
2973                         break;
2974                 }
2975
2976                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2977                         struct rte_mbuf *pref_pkt_hdr;
2978
2979                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2980                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
2981                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
2982                 }
2983
2984                 pkts.frags[pkts.num] = nb_segs;
2985                 pkts.num++;
2986
2987                 seg = mbuf;
2988                 for (j = 0; j < nb_segs - 1; j++) {
2989                         /* For the subsequent segments, set shadow queue
2990                          * buffer to NULL
2991                          */
2992                         mrvl_fill_shadowq(sq, NULL);
2993                         mrvl_fill_desc(&descs[tail], seg);
2994
2995                         tail++;
2996                         seg = seg->next;
2997                 }
2998                 /* Put first mbuf info in last shadow queue entry */
2999                 mrvl_fill_shadowq(sq, mbuf);
3000                 /* Update descriptor with last segment */
3001                 mrvl_fill_desc(&descs[tail++], seg);
3002
3003                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
3004                 /* In case unsupported ol_flags were passed
3005                  * do not update descriptor offload information
3006                  */
3007                 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS))
3008                         continue;
3009                 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type,
3010                                         &gen_l3_cksum, &gen_l4_cksum);
3011
3012                 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type,
3013                                                   l4_type, mbuf->l2_len,
3014                                                   mbuf->l2_len + mbuf->l3_len,
3015                                                   gen_l3_cksum, gen_l4_cksum);
3016         }
3017
3018         num = total_descs;
3019         pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs,
3020                          &total_descs, &pkts);
3021         /* number of packets that were not sent */
3022         if (unlikely(num > total_descs)) {
3023                 for (i = total_descs; i < num; i++) {
3024                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
3025                                 MRVL_PP2_TX_SHADOWQ_MASK;
3026
3027                         addr = sq->ent[sq->head].buff.cookie;
3028                         if (addr)
3029                                 bytes_sent -=
3030                                         rte_pktmbuf_pkt_len((struct rte_mbuf *)
3031                                                 (cookie_addr_high | addr));
3032                 }
3033                 sq->size -= num - total_descs;
3034                 nb_pkts = pkts.num;
3035         }
3036
3037         q->bytes_sent += bytes_sent;
3038
3039         return nb_pkts;
3040 }
3041
3042 /**
3043  * Create private device structure.
3044  *
3045  * @param dev_name
3046  *   Pointer to the port name passed in the initialization parameters.
3047  *
3048  * @return
3049  *   Pointer to the newly allocated private device structure.
3050  */
3051 static struct mrvl_priv *
3052 mrvl_priv_create(const char *dev_name)
3053 {
3054         struct pp2_bpool_params bpool_params;
3055         char match[MRVL_MATCH_LEN];
3056         struct mrvl_priv *priv;
3057         uint16_t max_frame_size;
3058         int ret, bpool_bit;
3059
3060         priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
3061         if (!priv)
3062                 return NULL;
3063
3064         ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
3065                                        &priv->pp_id, &priv->ppio_id);
3066         if (ret)
3067                 goto out_free_priv;
3068
3069         ret = pp2_ppio_get_l4_cksum_max_frame_size(priv->pp_id, priv->ppio_id,
3070                                                    &max_frame_size);
3071         if (ret)
3072                 goto out_free_priv;
3073
3074         priv->max_mtu = max_frame_size + RTE_ETHER_CRC_LEN -
3075                 MRVL_PP2_ETH_HDRS_LEN;
3076
3077         bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
3078                                      PP2_BPOOL_NUM_POOLS);
3079         if (bpool_bit < 0)
3080                 goto out_free_priv;
3081         priv->bpool_bit = bpool_bit;
3082
3083         snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
3084                  priv->bpool_bit);
3085         memset(&bpool_params, 0, sizeof(bpool_params));
3086         bpool_params.match = match;
3087         bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
3088         ret = pp2_bpool_init(&bpool_params, &priv->bpool);
3089         if (ret)
3090                 goto out_clear_bpool_bit;
3091
3092         priv->ppio_params.type = PP2_PPIO_T_NIC;
3093         rte_spinlock_init(&priv->lock);
3094
3095         return priv;
3096 out_clear_bpool_bit:
3097         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
3098 out_free_priv:
3099         rte_free(priv);
3100         return NULL;
3101 }
3102
3103 /**
3104  * Create device representing Ethernet port.
3105  *
3106  * @param name
3107  *   Pointer to the port's name.
3108  *
3109  * @return
3110  *   0 on success, negative error value otherwise.
3111  */
3112 static int
3113 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
3114 {
3115         int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
3116         struct rte_eth_dev *eth_dev;
3117         struct mrvl_priv *priv;
3118         struct ifreq req;
3119
3120         eth_dev = rte_eth_dev_allocate(name);
3121         if (!eth_dev)
3122                 return -ENOMEM;
3123
3124         priv = mrvl_priv_create(name);
3125         if (!priv) {
3126                 ret = -ENOMEM;
3127                 goto out_free;
3128         }
3129         eth_dev->data->dev_private = priv;
3130
3131         eth_dev->data->mac_addrs =
3132                 rte_zmalloc("mac_addrs",
3133                             RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
3134         if (!eth_dev->data->mac_addrs) {
3135                 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
3136                 ret = -ENOMEM;
3137                 goto out_free;
3138         }
3139
3140         memset(&req, 0, sizeof(req));
3141         strcpy(req.ifr_name, name);
3142         ret = ioctl(fd, SIOCGIFHWADDR, &req);
3143         if (ret)
3144                 goto out_free;
3145
3146         memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
3147                req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN);
3148
3149         eth_dev->device = &vdev->device;
3150         eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
3151         mrvl_set_tx_function(eth_dev);
3152         eth_dev->dev_ops = &mrvl_ops;
3153         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
3154
3155         eth_dev->data->dev_link.link_status = ETH_LINK_UP;
3156
3157         rte_eth_dev_probing_finish(eth_dev);
3158         return 0;
3159 out_free:
3160         rte_eth_dev_release_port(eth_dev);
3161
3162         return ret;
3163 }
3164
3165 /**
3166  * Callback used by rte_kvargs_process() during argument parsing.
3167  *
3168  * @param key
3169  *   Pointer to the parsed key (unused).
3170  * @param value
3171  *   Pointer to the parsed value.
3172  * @param extra_args
3173  *   Pointer to the extra arguments which contains address of the
3174  *   table of pointers to parsed interface names.
3175  *
3176  * @return
3177  *   Always 0.
3178  */
3179 static int
3180 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
3181                  void *extra_args)
3182 {
3183         struct mrvl_ifnames *ifnames = extra_args;
3184
3185         ifnames->names[ifnames->idx++] = value;
3186
3187         return 0;
3188 }
3189
3190 /**
3191  * DPDK callback to register the virtual device.
3192  *
3193  * @param vdev
3194  *   Pointer to the virtual device.
3195  *
3196  * @return
3197  *   0 on success, negative error value otherwise.
3198  */
3199 static int
3200 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
3201 {
3202         struct rte_kvargs *kvlist;
3203         struct mrvl_ifnames ifnames;
3204         int ret = -EINVAL;
3205         uint32_t i, ifnum, cfgnum;
3206         const char *params;
3207
3208         params = rte_vdev_device_args(vdev);
3209         if (!params)
3210                 return -EINVAL;
3211
3212         kvlist = rte_kvargs_parse(params, valid_args);
3213         if (!kvlist)
3214                 return -EINVAL;
3215
3216         ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
3217         if (ifnum > RTE_DIM(ifnames.names))
3218                 goto out_free_kvlist;
3219
3220         ifnames.idx = 0;
3221         rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
3222                            mrvl_get_ifnames, &ifnames);
3223
3224
3225         /*
3226          * The below system initialization should be done only once,
3227          * on the first provided configuration file
3228          */
3229         if (!mrvl_cfg) {
3230                 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
3231                 MRVL_LOG(INFO, "Parsing config file!");
3232                 if (cfgnum > 1) {
3233                         MRVL_LOG(ERR, "Cannot handle more than one config file!");
3234                         goto out_free_kvlist;
3235                 } else if (cfgnum == 1) {
3236                         rte_kvargs_process(kvlist, MRVL_CFG_ARG,
3237                                            mrvl_get_cfg, &mrvl_cfg);
3238                 }
3239         }
3240
3241         if (mrvl_dev_num)
3242                 goto init_devices;
3243
3244         MRVL_LOG(INFO, "Perform MUSDK initializations");
3245
3246         ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
3247         if (ret)
3248                 goto out_free_kvlist;
3249
3250         ret = mrvl_init_pp2();
3251         if (ret) {
3252                 MRVL_LOG(ERR, "Failed to init PP!");
3253                 rte_mvep_deinit(MVEP_MOD_T_PP2);
3254                 goto out_free_kvlist;
3255         }
3256
3257         memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
3258         memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
3259
3260         mrvl_lcore_first = RTE_MAX_LCORE;
3261         mrvl_lcore_last = 0;
3262
3263 init_devices:
3264         for (i = 0; i < ifnum; i++) {
3265                 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
3266                 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
3267                 if (ret)
3268                         goto out_cleanup;
3269                 mrvl_dev_num++;
3270         }
3271
3272         rte_kvargs_free(kvlist);
3273
3274         return 0;
3275 out_cleanup:
3276         rte_pmd_mrvl_remove(vdev);
3277
3278 out_free_kvlist:
3279         rte_kvargs_free(kvlist);
3280
3281         return ret;
3282 }
3283
3284 /**
3285  * DPDK callback to remove virtual device.
3286  *
3287  * @param vdev
3288  *   Pointer to the removed virtual device.
3289  *
3290  * @return
3291  *   0 on success, negative error value otherwise.
3292  */
3293 static int
3294 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
3295 {
3296         uint16_t port_id;
3297         int ret = 0;
3298
3299         RTE_ETH_FOREACH_DEV(port_id) {
3300                 if (rte_eth_devices[port_id].device != &vdev->device)
3301                         continue;
3302                 ret |= rte_eth_dev_close(port_id);
3303         }
3304
3305         return ret == 0 ? 0 : -EIO;
3306 }
3307
3308 static struct rte_vdev_driver pmd_mrvl_drv = {
3309         .probe = rte_pmd_mrvl_probe,
3310         .remove = rte_pmd_mrvl_remove,
3311 };
3312
3313 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
3314 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
3315 RTE_LOG_REGISTER_DEFAULT(mrvl_logtype, NOTICE);