1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_ethdev_driver.h>
8 #include <rte_kvargs.h>
10 #include <rte_malloc.h>
11 #include <rte_bus_vdev.h>
14 #include <linux/ethtool.h>
15 #include <linux/sockios.h>
17 #include <net/if_arp.h>
18 #include <sys/ioctl.h>
19 #include <sys/socket.h>
21 #include <sys/types.h>
23 #include <rte_mvep_common.h>
24 #include "mrvl_ethdev.h"
27 /* bitmask with reserved hifs */
28 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
29 /* bitmask with reserved bpools */
30 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
31 /* bitmask with reserved kernel RSS tables */
32 #define MRVL_MUSDK_RSS_RESERVED 0x01
33 /* maximum number of available hifs */
34 #define MRVL_MUSDK_HIFS_MAX 9
37 #define MRVL_MUSDK_PREFETCH_SHIFT 2
39 /* TCAM has 25 entries reserved for uc/mc filter entries */
40 #define MRVL_MAC_ADDRS_MAX 25
41 #define MRVL_MATCH_LEN 16
42 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
43 /* Maximum allowable packet size */
44 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
46 #define MRVL_IFACE_NAME_ARG "iface"
47 #define MRVL_CFG_ARG "cfg"
49 #define MRVL_BURST_SIZE 64
51 #define MRVL_ARP_LENGTH 28
53 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
55 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
56 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
58 /** Port Rx offload capabilities */
59 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
60 DEV_RX_OFFLOAD_JUMBO_FRAME | \
61 DEV_RX_OFFLOAD_CHECKSUM)
63 /** Port Tx offloads capabilities */
64 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
65 DEV_TX_OFFLOAD_UDP_CKSUM | \
66 DEV_TX_OFFLOAD_TCP_CKSUM)
68 static const char * const valid_args[] = {
74 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
75 static struct pp2_hif *hifs[RTE_MAX_LCORE];
76 static int used_bpools[PP2_NUM_PKT_PROC] = {
77 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
80 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
81 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
82 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
87 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
92 * To use buffer harvesting based on loopback port shadow queue structure
93 * was introduced for buffers information bookkeeping.
95 * Before sending the packet, related buffer information (pp2_buff_inf) is
96 * stored in shadow queue. After packet is transmitted no longer used
97 * packet buffer is released back to it's original hardware pool,
98 * on condition it originated from interface.
99 * In case it was generated by application itself i.e: mbuf->port field is
100 * 0xff then its released to software mempool.
102 struct mrvl_shadow_txq {
103 int head; /* write index - used when sending buffers */
104 int tail; /* read index - used when releasing buffers */
105 u16 size; /* queue occupied size */
106 u16 num_to_release; /* number of buffers sent, that can be released */
107 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
111 struct mrvl_priv *priv;
112 struct rte_mempool *mp;
121 struct mrvl_priv *priv;
125 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
126 int tx_deferred_start;
129 static int mrvl_lcore_first;
130 static int mrvl_lcore_last;
131 static int mrvl_dev_num;
133 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
134 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
135 struct pp2_hif *hif, unsigned int core_id,
136 struct mrvl_shadow_txq *sq, int qid, int force);
138 #define MRVL_XSTATS_TBL_ENTRY(name) { \
139 #name, offsetof(struct pp2_ppio_statistics, name), \
140 sizeof(((struct pp2_ppio_statistics *)0)->name) \
143 /* Table with xstats data */
148 } mrvl_xstats_tbl[] = {
149 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
150 MRVL_XSTATS_TBL_ENTRY(rx_packets),
151 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
152 MRVL_XSTATS_TBL_ENTRY(rx_errors),
153 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
154 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
155 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
156 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
157 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
158 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
159 MRVL_XSTATS_TBL_ENTRY(tx_packets),
160 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
161 MRVL_XSTATS_TBL_ENTRY(tx_errors)
165 mrvl_get_bpool_size(int pp2_id, int pool_id)
170 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
171 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
177 mrvl_reserve_bit(int *bitmap, int max)
179 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
190 mrvl_init_hif(int core_id)
192 struct pp2_hif_params params;
193 char match[MRVL_MATCH_LEN];
196 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
198 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
202 snprintf(match, sizeof(match), "hif-%d", ret);
203 memset(¶ms, 0, sizeof(params));
204 params.match = match;
205 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
206 ret = pp2_hif_init(¶ms, &hifs[core_id]);
208 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
215 static inline struct pp2_hif*
216 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
220 if (likely(hifs[core_id] != NULL))
221 return hifs[core_id];
223 rte_spinlock_lock(&priv->lock);
225 ret = mrvl_init_hif(core_id);
227 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
231 if (core_id < mrvl_lcore_first)
232 mrvl_lcore_first = core_id;
234 if (core_id > mrvl_lcore_last)
235 mrvl_lcore_last = core_id;
237 rte_spinlock_unlock(&priv->lock);
239 return hifs[core_id];
243 * Configure rss based on dpdk rss configuration.
246 * Pointer to private structure.
248 * Pointer to RSS configuration.
251 * 0 on success, negative error value otherwise.
254 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
256 if (rss_conf->rss_key)
257 MRVL_LOG(WARNING, "Changing hash key is not supported");
259 if (rss_conf->rss_hf == 0) {
260 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
261 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
262 priv->ppio_params.inqs_params.hash_type =
263 PP2_PPIO_HASH_T_2_TUPLE;
264 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
265 priv->ppio_params.inqs_params.hash_type =
266 PP2_PPIO_HASH_T_5_TUPLE;
267 priv->rss_hf_tcp = 1;
268 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
269 priv->ppio_params.inqs_params.hash_type =
270 PP2_PPIO_HASH_T_5_TUPLE;
271 priv->rss_hf_tcp = 0;
280 * Ethernet device configuration.
282 * Prepare the driver for a given number of TX and RX queues and
286 * Pointer to Ethernet device structure.
289 * 0 on success, negative error value otherwise.
292 mrvl_dev_configure(struct rte_eth_dev *dev)
294 struct mrvl_priv *priv = dev->data->dev_private;
298 MRVL_LOG(INFO, "Device reconfiguration is not supported");
302 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
303 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
304 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
305 dev->data->dev_conf.rxmode.mq_mode);
309 if (dev->data->dev_conf.rxmode.split_hdr_size) {
310 MRVL_LOG(INFO, "Split headers not supported");
314 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
315 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
316 ETHER_HDR_LEN - ETHER_CRC_LEN;
318 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
319 dev->data->nb_rx_queues);
323 ret = mrvl_configure_txqs(priv, dev->data->port_id,
324 dev->data->nb_tx_queues);
328 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
329 priv->ppio_params.maintain_stats = 1;
330 priv->nb_rx_queues = dev->data->nb_rx_queues;
332 if (dev->data->nb_rx_queues == 1 &&
333 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
334 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
335 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
340 return mrvl_configure_rss(priv,
341 &dev->data->dev_conf.rx_adv_conf.rss_conf);
345 * DPDK callback to change the MTU.
347 * Setting the MTU affects hardware MRU (packets larger than the MRU
351 * Pointer to Ethernet device structure.
356 * 0 on success, negative error value otherwise.
359 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
361 struct mrvl_priv *priv = dev->data->dev_private;
362 /* extra MV_MH_SIZE bytes are required for Marvell tag */
363 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
366 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
372 ret = pp2_ppio_set_mru(priv->ppio, mru);
376 return pp2_ppio_set_mtu(priv->ppio, mtu);
380 * DPDK callback to bring the link up.
383 * Pointer to Ethernet device structure.
386 * 0 on success, negative error value otherwise.
389 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
391 struct mrvl_priv *priv = dev->data->dev_private;
397 ret = pp2_ppio_enable(priv->ppio);
402 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
403 * as pp2_ppio_enable() changes port->t_mode from default 0 to
404 * PP2_TRAFFIC_INGRESS_EGRESS.
406 * Set mtu to default DPDK value here.
408 ret = mrvl_mtu_set(dev, dev->data->mtu);
410 pp2_ppio_disable(priv->ppio);
416 * DPDK callback to bring the link down.
419 * Pointer to Ethernet device structure.
422 * 0 on success, negative error value otherwise.
425 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
427 struct mrvl_priv *priv = dev->data->dev_private;
432 return pp2_ppio_disable(priv->ppio);
436 * DPDK callback to start tx queue.
439 * Pointer to Ethernet device structure.
441 * Transmit queue index.
444 * 0 on success, negative error value otherwise.
447 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
449 struct mrvl_priv *priv = dev->data->dev_private;
455 /* passing 1 enables given tx queue */
456 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
458 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
462 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
468 * DPDK callback to stop tx queue.
471 * Pointer to Ethernet device structure.
473 * Transmit queue index.
476 * 0 on success, negative error value otherwise.
479 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
481 struct mrvl_priv *priv = dev->data->dev_private;
487 /* passing 0 disables given tx queue */
488 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
490 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
494 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
500 * DPDK callback to start the device.
503 * Pointer to Ethernet device structure.
506 * 0 on success, negative errno value on failure.
509 mrvl_dev_start(struct rte_eth_dev *dev)
511 struct mrvl_priv *priv = dev->data->dev_private;
512 char match[MRVL_MATCH_LEN];
513 int ret = 0, i, def_init_size;
516 return mrvl_dev_set_link_up(dev);
518 snprintf(match, sizeof(match), "ppio-%d:%d",
519 priv->pp_id, priv->ppio_id);
520 priv->ppio_params.match = match;
523 * Calculate the minimum bpool size for refill feature as follows:
524 * 2 default burst sizes multiply by number of rx queues.
525 * If the bpool size will be below this value, new buffers will
526 * be added to the pool.
528 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
530 /* In case initial bpool size configured in queues setup is
531 * smaller than minimum size add more buffers
533 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
534 if (priv->bpool_init_size < def_init_size) {
535 int buffs_to_add = def_init_size - priv->bpool_init_size;
537 priv->bpool_init_size += buffs_to_add;
538 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
540 MRVL_LOG(ERR, "Failed to add buffers to bpool");
544 * Calculate the maximum bpool size for refill feature as follows:
545 * maximum number of descriptors in rx queue multiply by number
546 * of rx queues plus minimum bpool size.
547 * In case the bpool size will exceed this value, superfluous buffers
550 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
551 priv->bpool_min_size;
553 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
555 MRVL_LOG(ERR, "Failed to init ppio");
560 * In case there are some some stale uc/mc mac addresses flush them
561 * here. It cannot be done during mrvl_dev_close() as port information
562 * is already gone at that point (due to pp2_ppio_deinit() in
565 if (!priv->uc_mc_flushed) {
566 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
569 "Failed to flush uc/mc filter list");
572 priv->uc_mc_flushed = 1;
575 if (!priv->vlan_flushed) {
576 ret = pp2_ppio_flush_vlan(priv->ppio);
578 MRVL_LOG(ERR, "Failed to flush vlan list");
581 * once pp2_ppio_flush_vlan() is supported jump to out
585 priv->vlan_flushed = 1;
588 /* For default QoS config, don't start classifier. */
590 ret = mrvl_start_qos_mapping(priv);
592 MRVL_LOG(ERR, "Failed to setup QoS mapping");
597 ret = mrvl_dev_set_link_up(dev);
599 MRVL_LOG(ERR, "Failed to set link up");
603 /* start tx queues */
604 for (i = 0; i < dev->data->nb_tx_queues; i++) {
605 struct mrvl_txq *txq = dev->data->tx_queues[i];
607 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
609 if (!txq->tx_deferred_start)
613 * All txqs are started by default. Stop them
614 * so that tx_deferred_start works as expected.
616 ret = mrvl_tx_queue_stop(dev, i);
623 MRVL_LOG(ERR, "Failed to start device");
624 pp2_ppio_deinit(priv->ppio);
629 * Flush receive queues.
632 * Pointer to Ethernet device structure.
635 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
639 MRVL_LOG(INFO, "Flushing rx queues");
640 for (i = 0; i < dev->data->nb_rx_queues; i++) {
644 struct mrvl_rxq *q = dev->data->rx_queues[i];
645 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
647 num = MRVL_PP2_RXD_MAX;
648 ret = pp2_ppio_recv(q->priv->ppio,
649 q->priv->rxq_map[q->queue_id].tc,
650 q->priv->rxq_map[q->queue_id].inq,
651 descs, (uint16_t *)&num);
652 } while (ret == 0 && num);
657 * Flush transmit shadow queues.
660 * Pointer to Ethernet device structure.
663 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
666 struct mrvl_txq *txq;
668 MRVL_LOG(INFO, "Flushing tx shadow queues");
669 for (i = 0; i < dev->data->nb_tx_queues; i++) {
670 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
672 for (j = 0; j < RTE_MAX_LCORE; j++) {
673 struct mrvl_shadow_txq *sq;
678 sq = &txq->shadow_txqs[j];
679 mrvl_free_sent_buffers(txq->priv->ppio,
680 hifs[j], j, sq, txq->queue_id, 1);
681 while (sq->tail != sq->head) {
682 uint64_t addr = cookie_addr_high |
683 sq->ent[sq->tail].buff.cookie;
685 (struct rte_mbuf *)addr);
686 sq->tail = (sq->tail + 1) &
687 MRVL_PP2_TX_SHADOWQ_MASK;
689 memset(sq, 0, sizeof(*sq));
695 * Flush hardware bpool (buffer-pool).
698 * Pointer to Ethernet device structure.
701 mrvl_flush_bpool(struct rte_eth_dev *dev)
703 struct mrvl_priv *priv = dev->data->dev_private;
707 unsigned int core_id = rte_lcore_id();
709 if (core_id == LCORE_ID_ANY)
712 hif = mrvl_get_hif(priv, core_id);
714 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
716 MRVL_LOG(ERR, "Failed to get bpool buffers number");
721 struct pp2_buff_inf inf;
724 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
728 addr = cookie_addr_high | inf.cookie;
729 rte_pktmbuf_free((struct rte_mbuf *)addr);
734 * DPDK callback to stop the device.
737 * Pointer to Ethernet device structure.
740 mrvl_dev_stop(struct rte_eth_dev *dev)
742 mrvl_dev_set_link_down(dev);
746 * DPDK callback to close the device.
749 * Pointer to Ethernet device structure.
752 mrvl_dev_close(struct rte_eth_dev *dev)
754 struct mrvl_priv *priv = dev->data->dev_private;
757 mrvl_flush_rx_queues(dev);
758 mrvl_flush_tx_shadow_queues(dev);
760 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
761 struct pp2_ppio_tc_params *tc_params =
762 &priv->ppio_params.inqs_params.tcs_params[i];
764 if (tc_params->inqs_params) {
765 rte_free(tc_params->inqs_params);
766 tc_params->inqs_params = NULL;
771 pp2_cls_tbl_deinit(priv->cls_tbl);
772 priv->cls_tbl = NULL;
776 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
777 priv->qos_tbl = NULL;
780 mrvl_flush_bpool(dev);
783 pp2_ppio_deinit(priv->ppio);
787 /* policer must be released after ppio deinitialization */
789 pp2_cls_plcr_deinit(priv->policer);
790 priv->policer = NULL;
795 * DPDK callback to retrieve physical link information.
798 * Pointer to Ethernet device structure.
799 * @param wait_to_complete
800 * Wait for request completion (ignored).
803 * 0 on success, negative error value otherwise.
806 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
810 * once MUSDK provides necessary API use it here
812 struct mrvl_priv *priv = dev->data->dev_private;
813 struct ethtool_cmd edata;
815 int ret, fd, link_up;
820 edata.cmd = ETHTOOL_GSET;
822 strcpy(req.ifr_name, dev->data->name);
823 req.ifr_data = (void *)&edata;
825 fd = socket(AF_INET, SOCK_DGRAM, 0);
829 ret = ioctl(fd, SIOCETHTOOL, &req);
837 switch (ethtool_cmd_speed(&edata)) {
839 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
842 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
845 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
848 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
851 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
854 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
855 ETH_LINK_HALF_DUPLEX;
856 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
858 pp2_ppio_get_link_state(priv->ppio, &link_up);
859 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
865 * DPDK callback to enable promiscuous mode.
868 * Pointer to Ethernet device structure.
871 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
873 struct mrvl_priv *priv = dev->data->dev_private;
882 ret = pp2_ppio_set_promisc(priv->ppio, 1);
884 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
888 * DPDK callback to enable allmulti mode.
891 * Pointer to Ethernet device structure.
894 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
896 struct mrvl_priv *priv = dev->data->dev_private;
905 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
907 MRVL_LOG(ERR, "Failed enable all-multicast mode");
911 * DPDK callback to disable promiscuous mode.
914 * Pointer to Ethernet device structure.
917 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
919 struct mrvl_priv *priv = dev->data->dev_private;
925 ret = pp2_ppio_set_promisc(priv->ppio, 0);
927 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
931 * DPDK callback to disable allmulticast mode.
934 * Pointer to Ethernet device structure.
937 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
939 struct mrvl_priv *priv = dev->data->dev_private;
945 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
947 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
951 * DPDK callback to remove a MAC address.
954 * Pointer to Ethernet device structure.
959 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
961 struct mrvl_priv *priv = dev->data->dev_private;
962 char buf[ETHER_ADDR_FMT_SIZE];
971 ret = pp2_ppio_remove_mac_addr(priv->ppio,
972 dev->data->mac_addrs[index].addr_bytes);
974 ether_format_addr(buf, sizeof(buf),
975 &dev->data->mac_addrs[index]);
976 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
981 * DPDK callback to add a MAC address.
984 * Pointer to Ethernet device structure.
986 * MAC address to register.
990 * VMDq pool index to associate address with (unused).
993 * 0 on success, negative error value otherwise.
996 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
997 uint32_t index, uint32_t vmdq __rte_unused)
999 struct mrvl_priv *priv = dev->data->dev_private;
1000 char buf[ETHER_ADDR_FMT_SIZE];
1007 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1014 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1015 * parameter uc_filter_max. Maximum number of mc addresses is then
1016 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1019 * If more than uc_filter_max uc addresses were added to filter list
1020 * then NIC will switch to promiscuous mode automatically.
1022 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1023 * were added to filter list then NIC will switch to all-multicast mode
1026 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1028 ether_format_addr(buf, sizeof(buf), mac_addr);
1029 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1037 * DPDK callback to set the primary MAC address.
1040 * Pointer to Ethernet device structure.
1042 * MAC address to register.
1045 * 0 on success, negative error value otherwise.
1048 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1050 struct mrvl_priv *priv = dev->data->dev_private;
1059 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1061 char buf[ETHER_ADDR_FMT_SIZE];
1062 ether_format_addr(buf, sizeof(buf), mac_addr);
1063 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1070 * DPDK callback to get device statistics.
1073 * Pointer to Ethernet device structure.
1075 * Stats structure output buffer.
1078 * 0 on success, negative error value otherwise.
1081 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1083 struct mrvl_priv *priv = dev->data->dev_private;
1084 struct pp2_ppio_statistics ppio_stats;
1085 uint64_t drop_mac = 0;
1086 unsigned int i, idx, ret;
1091 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1092 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1093 struct pp2_ppio_inq_statistics rx_stats;
1098 idx = rxq->queue_id;
1099 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1101 "rx queue %d stats out of range (0 - %d)",
1102 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1106 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1107 priv->rxq_map[idx].tc,
1108 priv->rxq_map[idx].inq,
1110 if (unlikely(ret)) {
1112 "Failed to update rx queue %d stats", idx);
1116 stats->q_ibytes[idx] = rxq->bytes_recv;
1117 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1118 stats->q_errors[idx] = rx_stats.drop_early +
1119 rx_stats.drop_fullq +
1122 stats->ibytes += rxq->bytes_recv;
1123 drop_mac += rxq->drop_mac;
1126 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1127 struct mrvl_txq *txq = dev->data->tx_queues[i];
1128 struct pp2_ppio_outq_statistics tx_stats;
1133 idx = txq->queue_id;
1134 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1136 "tx queue %d stats out of range (0 - %d)",
1137 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1140 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1142 if (unlikely(ret)) {
1144 "Failed to update tx queue %d stats", idx);
1148 stats->q_opackets[idx] = tx_stats.deq_desc;
1149 stats->q_obytes[idx] = txq->bytes_sent;
1150 stats->obytes += txq->bytes_sent;
1153 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1154 if (unlikely(ret)) {
1155 MRVL_LOG(ERR, "Failed to update port statistics");
1159 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1160 stats->opackets += ppio_stats.tx_packets;
1161 stats->imissed += ppio_stats.rx_fullq_dropped +
1162 ppio_stats.rx_bm_dropped +
1163 ppio_stats.rx_early_dropped +
1164 ppio_stats.rx_fifo_dropped +
1165 ppio_stats.rx_cls_dropped;
1166 stats->ierrors = drop_mac;
1172 * DPDK callback to clear device statistics.
1175 * Pointer to Ethernet device structure.
1178 mrvl_stats_reset(struct rte_eth_dev *dev)
1180 struct mrvl_priv *priv = dev->data->dev_private;
1186 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1187 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1189 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1190 priv->rxq_map[i].inq, NULL, 1);
1191 rxq->bytes_recv = 0;
1195 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1196 struct mrvl_txq *txq = dev->data->tx_queues[i];
1198 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1199 txq->bytes_sent = 0;
1202 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1206 * DPDK callback to get extended statistics.
1209 * Pointer to Ethernet device structure.
1211 * Pointer to xstats table.
1213 * Number of entries in xstats table.
1215 * Negative value on error, number of read xstats otherwise.
1218 mrvl_xstats_get(struct rte_eth_dev *dev,
1219 struct rte_eth_xstat *stats, unsigned int n)
1221 struct mrvl_priv *priv = dev->data->dev_private;
1222 struct pp2_ppio_statistics ppio_stats;
1228 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1229 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1232 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1233 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1234 mrvl_xstats_tbl[i].offset);
1235 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1236 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1237 mrvl_xstats_tbl[i].offset);
1242 stats[i].value = val;
1249 * DPDK callback to reset extended statistics.
1252 * Pointer to Ethernet device structure.
1255 mrvl_xstats_reset(struct rte_eth_dev *dev)
1257 mrvl_stats_reset(dev);
1261 * DPDK callback to get extended statistics names.
1263 * @param dev (unused)
1264 * Pointer to Ethernet device structure.
1265 * @param xstats_names
1266 * Pointer to xstats names table.
1268 * Size of the xstats names table.
1270 * Number of read names.
1273 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1274 struct rte_eth_xstat_name *xstats_names,
1280 return RTE_DIM(mrvl_xstats_tbl);
1282 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1283 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s",
1284 mrvl_xstats_tbl[i].name);
1290 * DPDK callback to get information about the device.
1293 * Pointer to Ethernet device structure (unused).
1295 * Info structure output buffer.
1298 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1299 struct rte_eth_dev_info *info)
1301 info->speed_capa = ETH_LINK_SPEED_10M |
1302 ETH_LINK_SPEED_100M |
1306 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1307 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1308 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1310 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1311 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1312 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1314 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1315 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1316 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1318 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1319 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1321 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1322 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1324 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1325 ETH_RSS_NONFRAG_IPV4_TCP |
1326 ETH_RSS_NONFRAG_IPV4_UDP;
1328 /* By default packets are dropped if no descriptors are available */
1329 info->default_rxconf.rx_drop_en = 1;
1331 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1335 * Return supported packet types.
1338 * Pointer to Ethernet device structure (unused).
1341 * Const pointer to the table with supported packet types.
1343 static const uint32_t *
1344 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1346 static const uint32_t ptypes[] = {
1348 RTE_PTYPE_L2_ETHER_VLAN,
1349 RTE_PTYPE_L2_ETHER_QINQ,
1351 RTE_PTYPE_L3_IPV4_EXT,
1352 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1354 RTE_PTYPE_L3_IPV6_EXT,
1355 RTE_PTYPE_L2_ETHER_ARP,
1364 * DPDK callback to get information about specific receive queue.
1367 * Pointer to Ethernet device structure.
1368 * @param rx_queue_id
1369 * Receive queue index.
1371 * Receive queue information structure.
1373 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1374 struct rte_eth_rxq_info *qinfo)
1376 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1377 struct mrvl_priv *priv = dev->data->dev_private;
1378 int inq = priv->rxq_map[rx_queue_id].inq;
1379 int tc = priv->rxq_map[rx_queue_id].tc;
1380 struct pp2_ppio_tc_params *tc_params =
1381 &priv->ppio_params.inqs_params.tcs_params[tc];
1384 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1388 * DPDK callback to get information about specific transmit queue.
1391 * Pointer to Ethernet device structure.
1392 * @param tx_queue_id
1393 * Transmit queue index.
1395 * Transmit queue information structure.
1397 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1398 struct rte_eth_txq_info *qinfo)
1400 struct mrvl_priv *priv = dev->data->dev_private;
1401 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1404 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1405 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1409 * DPDK callback to Configure a VLAN filter.
1412 * Pointer to Ethernet device structure.
1414 * VLAN ID to filter.
1419 * 0 on success, negative error value otherwise.
1422 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1424 struct mrvl_priv *priv = dev->data->dev_private;
1432 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1433 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1437 * Release buffers to hardware bpool (buffer-pool)
1440 * Receive queue pointer.
1442 * Number of buffers to release to bpool.
1445 * 0 on success, negative error value otherwise.
1448 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1450 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1451 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1453 unsigned int core_id;
1454 struct pp2_hif *hif;
1455 struct pp2_bpool *bpool;
1457 core_id = rte_lcore_id();
1458 if (core_id == LCORE_ID_ANY)
1461 hif = mrvl_get_hif(rxq->priv, core_id);
1465 bpool = rxq->priv->bpool;
1467 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1471 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1473 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1475 for (i = 0; i < num; i++) {
1476 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1477 != cookie_addr_high) {
1479 "mbuf virtual addr high 0x%lx out of range",
1480 (uint64_t)mbufs[i] >> 32);
1484 entries[i].buff.addr =
1485 rte_mbuf_data_iova_default(mbufs[i]);
1486 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1487 entries[i].bpool = bpool;
1490 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1491 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1498 for (; i < num; i++)
1499 rte_pktmbuf_free(mbufs[i]);
1505 * DPDK callback to configure the receive queue.
1508 * Pointer to Ethernet device structure.
1512 * Number of descriptors to configure in queue.
1514 * NUMA socket on which memory must be allocated.
1516 * Thresholds parameters.
1518 * Memory pool for buffer allocations.
1521 * 0 on success, negative error value otherwise.
1524 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1525 unsigned int socket,
1526 const struct rte_eth_rxconf *conf,
1527 struct rte_mempool *mp)
1529 struct mrvl_priv *priv = dev->data->dev_private;
1530 struct mrvl_rxq *rxq;
1532 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1536 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1538 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1540 * Unknown TC mapping, mapping will not have a correct queue.
1542 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1543 idx, priv->ppio_id);
1547 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1548 MRVL_PKT_EFFEC_OFFS;
1549 if (min_size < max_rx_pkt_len) {
1551 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.",
1552 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1553 MRVL_PKT_EFFEC_OFFS,
1558 if (dev->data->rx_queues[idx]) {
1559 rte_free(dev->data->rx_queues[idx]);
1560 dev->data->rx_queues[idx] = NULL;
1563 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1569 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1570 rxq->queue_id = idx;
1571 rxq->port_id = dev->data->port_id;
1572 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1574 tc = priv->rxq_map[rxq->queue_id].tc,
1575 inq = priv->rxq_map[rxq->queue_id].inq;
1576 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1579 ret = mrvl_fill_bpool(rxq, desc);
1585 priv->bpool_init_size += desc;
1587 dev->data->rx_queues[idx] = rxq;
1593 * DPDK callback to release the receive queue.
1596 * Generic receive queue pointer.
1599 mrvl_rx_queue_release(void *rxq)
1601 struct mrvl_rxq *q = rxq;
1602 struct pp2_ppio_tc_params *tc_params;
1603 int i, num, tc, inq;
1604 struct pp2_hif *hif;
1605 unsigned int core_id = rte_lcore_id();
1607 if (core_id == LCORE_ID_ANY)
1613 hif = mrvl_get_hif(q->priv, core_id);
1618 tc = q->priv->rxq_map[q->queue_id].tc;
1619 inq = q->priv->rxq_map[q->queue_id].inq;
1620 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1621 num = tc_params->inqs_params[inq].size;
1622 for (i = 0; i < num; i++) {
1623 struct pp2_buff_inf inf;
1626 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1627 addr = cookie_addr_high | inf.cookie;
1628 rte_pktmbuf_free((struct rte_mbuf *)addr);
1635 * DPDK callback to configure the transmit queue.
1638 * Pointer to Ethernet device structure.
1640 * Transmit queue index.
1642 * Number of descriptors to configure in the queue.
1644 * NUMA socket on which memory must be allocated.
1646 * Tx queue configuration parameters.
1649 * 0 on success, negative error value otherwise.
1652 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1653 unsigned int socket,
1654 const struct rte_eth_txconf *conf)
1656 struct mrvl_priv *priv = dev->data->dev_private;
1657 struct mrvl_txq *txq;
1659 if (dev->data->tx_queues[idx]) {
1660 rte_free(dev->data->tx_queues[idx]);
1661 dev->data->tx_queues[idx] = NULL;
1664 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1669 txq->queue_id = idx;
1670 txq->port_id = dev->data->port_id;
1671 txq->tx_deferred_start = conf->tx_deferred_start;
1672 dev->data->tx_queues[idx] = txq;
1674 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1680 * DPDK callback to release the transmit queue.
1683 * Generic transmit queue pointer.
1686 mrvl_tx_queue_release(void *txq)
1688 struct mrvl_txq *q = txq;
1697 * DPDK callback to get flow control configuration.
1700 * Pointer to Ethernet device structure.
1702 * Pointer to the flow control configuration.
1705 * 0 on success, negative error value otherwise.
1708 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1710 struct mrvl_priv *priv = dev->data->dev_private;
1716 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1718 MRVL_LOG(ERR, "Failed to read rx pause state");
1722 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1728 * DPDK callback to set flow control configuration.
1731 * Pointer to Ethernet device structure.
1733 * Pointer to the flow control configuration.
1736 * 0 on success, negative error value otherwise.
1739 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1741 struct mrvl_priv *priv = dev->data->dev_private;
1746 if (fc_conf->high_water ||
1747 fc_conf->low_water ||
1748 fc_conf->pause_time ||
1749 fc_conf->mac_ctrl_frame_fwd ||
1751 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1756 if (fc_conf->mode == RTE_FC_NONE ||
1757 fc_conf->mode == RTE_FC_RX_PAUSE) {
1760 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1761 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1764 "Failed to change flowctrl on RX side");
1773 * Update RSS hash configuration
1776 * Pointer to Ethernet device structure.
1778 * Pointer to RSS configuration.
1781 * 0 on success, negative error value otherwise.
1784 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1785 struct rte_eth_rss_conf *rss_conf)
1787 struct mrvl_priv *priv = dev->data->dev_private;
1792 return mrvl_configure_rss(priv, rss_conf);
1796 * DPDK callback to get RSS hash configuration.
1799 * Pointer to Ethernet device structure.
1801 * Pointer to RSS configuration.
1807 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1808 struct rte_eth_rss_conf *rss_conf)
1810 struct mrvl_priv *priv = dev->data->dev_private;
1811 enum pp2_ppio_hash_type hash_type =
1812 priv->ppio_params.inqs_params.hash_type;
1814 rss_conf->rss_key = NULL;
1816 if (hash_type == PP2_PPIO_HASH_T_NONE)
1817 rss_conf->rss_hf = 0;
1818 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1819 rss_conf->rss_hf = ETH_RSS_IPV4;
1820 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1821 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1822 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1823 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1829 * DPDK callback to get rte_flow callbacks.
1832 * Pointer to the device structure.
1836 * Flow filter operation.
1838 * Pointer to pass the flow ops.
1841 * 0 on success, negative error value otherwise.
1844 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1845 enum rte_filter_type filter_type,
1846 enum rte_filter_op filter_op, void *arg)
1848 switch (filter_type) {
1849 case RTE_ETH_FILTER_GENERIC:
1850 if (filter_op != RTE_ETH_FILTER_GET)
1852 *(const void **)arg = &mrvl_flow_ops;
1855 MRVL_LOG(WARNING, "Filter type (%d) not supported",
1861 static const struct eth_dev_ops mrvl_ops = {
1862 .dev_configure = mrvl_dev_configure,
1863 .dev_start = mrvl_dev_start,
1864 .dev_stop = mrvl_dev_stop,
1865 .dev_set_link_up = mrvl_dev_set_link_up,
1866 .dev_set_link_down = mrvl_dev_set_link_down,
1867 .dev_close = mrvl_dev_close,
1868 .link_update = mrvl_link_update,
1869 .promiscuous_enable = mrvl_promiscuous_enable,
1870 .allmulticast_enable = mrvl_allmulticast_enable,
1871 .promiscuous_disable = mrvl_promiscuous_disable,
1872 .allmulticast_disable = mrvl_allmulticast_disable,
1873 .mac_addr_remove = mrvl_mac_addr_remove,
1874 .mac_addr_add = mrvl_mac_addr_add,
1875 .mac_addr_set = mrvl_mac_addr_set,
1876 .mtu_set = mrvl_mtu_set,
1877 .stats_get = mrvl_stats_get,
1878 .stats_reset = mrvl_stats_reset,
1879 .xstats_get = mrvl_xstats_get,
1880 .xstats_reset = mrvl_xstats_reset,
1881 .xstats_get_names = mrvl_xstats_get_names,
1882 .dev_infos_get = mrvl_dev_infos_get,
1883 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1884 .rxq_info_get = mrvl_rxq_info_get,
1885 .txq_info_get = mrvl_txq_info_get,
1886 .vlan_filter_set = mrvl_vlan_filter_set,
1887 .tx_queue_start = mrvl_tx_queue_start,
1888 .tx_queue_stop = mrvl_tx_queue_stop,
1889 .rx_queue_setup = mrvl_rx_queue_setup,
1890 .rx_queue_release = mrvl_rx_queue_release,
1891 .tx_queue_setup = mrvl_tx_queue_setup,
1892 .tx_queue_release = mrvl_tx_queue_release,
1893 .flow_ctrl_get = mrvl_flow_ctrl_get,
1894 .flow_ctrl_set = mrvl_flow_ctrl_set,
1895 .rss_hash_update = mrvl_rss_hash_update,
1896 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1897 .filter_ctrl = mrvl_eth_filter_ctrl,
1901 * Return packet type information and l3/l4 offsets.
1904 * Pointer to the received packet descriptor.
1911 * Packet type information.
1913 static inline uint64_t
1914 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1915 uint8_t *l3_offset, uint8_t *l4_offset)
1917 enum pp2_inq_l3_type l3_type;
1918 enum pp2_inq_l4_type l4_type;
1919 enum pp2_inq_vlan_tag vlan_tag;
1920 uint64_t packet_type;
1922 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1923 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1924 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
1926 packet_type = RTE_PTYPE_L2_ETHER;
1929 case PP2_INQ_VLAN_TAG_SINGLE:
1930 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
1932 case PP2_INQ_VLAN_TAG_DOUBLE:
1933 case PP2_INQ_VLAN_TAG_TRIPLE:
1934 packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
1941 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1942 packet_type |= RTE_PTYPE_L3_IPV4;
1944 case PP2_INQ_L3_TYPE_IPV4_OK:
1945 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1947 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1948 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1950 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1951 packet_type |= RTE_PTYPE_L3_IPV6;
1953 case PP2_INQ_L3_TYPE_IPV6_EXT:
1954 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1956 case PP2_INQ_L3_TYPE_ARP:
1957 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1959 * In case of ARP l4_offset is set to wrong value.
1960 * Set it to proper one so that later on mbuf->l3_len can be
1961 * calculated subtracting l4_offset and l3_offset.
1963 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1966 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
1971 case PP2_INQ_L4_TYPE_TCP:
1972 packet_type |= RTE_PTYPE_L4_TCP;
1974 case PP2_INQ_L4_TYPE_UDP:
1975 packet_type |= RTE_PTYPE_L4_UDP;
1978 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
1986 * Get offload information from the received packet descriptor.
1989 * Pointer to the received packet descriptor.
1992 * Mbuf offload flags.
1994 static inline uint64_t
1995 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1998 enum pp2_inq_desc_status status;
2000 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2001 if (unlikely(status != PP2_DESC_ERR_OK))
2002 flags = PKT_RX_IP_CKSUM_BAD;
2004 flags = PKT_RX_IP_CKSUM_GOOD;
2006 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2007 if (unlikely(status != PP2_DESC_ERR_OK))
2008 flags |= PKT_RX_L4_CKSUM_BAD;
2010 flags |= PKT_RX_L4_CKSUM_GOOD;
2016 * DPDK callback for receive.
2019 * Generic pointer to the receive queue.
2021 * Array to store received packets.
2023 * Maximum number of packets in array.
2026 * Number of packets successfully received.
2029 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2031 struct mrvl_rxq *q = rxq;
2032 struct pp2_ppio_desc descs[nb_pkts];
2033 struct pp2_bpool *bpool;
2034 int i, ret, rx_done = 0;
2036 struct pp2_hif *hif;
2037 unsigned int core_id = rte_lcore_id();
2039 hif = mrvl_get_hif(q->priv, core_id);
2041 if (unlikely(!q->priv->ppio || !hif))
2044 bpool = q->priv->bpool;
2046 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2047 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2048 if (unlikely(ret < 0)) {
2049 MRVL_LOG(ERR, "Failed to receive packets");
2052 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2054 for (i = 0; i < nb_pkts; i++) {
2055 struct rte_mbuf *mbuf;
2056 uint8_t l3_offset, l4_offset;
2057 enum pp2_inq_desc_status status;
2060 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2061 struct pp2_ppio_desc *pref_desc;
2064 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2065 pref_addr = cookie_addr_high |
2066 pp2_ppio_inq_desc_get_cookie(pref_desc);
2067 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2068 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2071 addr = cookie_addr_high |
2072 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2073 mbuf = (struct rte_mbuf *)addr;
2074 rte_pktmbuf_reset(mbuf);
2076 /* drop packet in case of mac, overrun or resource error */
2077 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2078 if (unlikely(status != PP2_DESC_ERR_OK)) {
2079 struct pp2_buff_inf binf = {
2080 .addr = rte_mbuf_data_iova_default(mbuf),
2081 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
2084 pp2_bpool_put_buff(hif, bpool, &binf);
2085 mrvl_port_bpool_size
2086 [bpool->pp2_id][bpool->id][core_id]++;
2091 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2092 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2093 mbuf->data_len = mbuf->pkt_len;
2094 mbuf->port = q->port_id;
2096 mrvl_desc_to_packet_type_and_offset(&descs[i],
2099 mbuf->l2_len = l3_offset;
2100 mbuf->l3_len = l4_offset - l3_offset;
2102 if (likely(q->cksum_enabled))
2103 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2105 rx_pkts[rx_done++] = mbuf;
2106 q->bytes_recv += mbuf->pkt_len;
2109 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2110 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2112 if (unlikely(num <= q->priv->bpool_min_size ||
2113 (!rx_done && num < q->priv->bpool_init_size))) {
2114 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2116 MRVL_LOG(ERR, "Failed to fill bpool");
2117 } else if (unlikely(num > q->priv->bpool_max_size)) {
2119 int pkt_to_remove = num - q->priv->bpool_init_size;
2120 struct rte_mbuf *mbuf;
2121 struct pp2_buff_inf buff;
2124 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
2125 bpool->pp2_id, q->priv->ppio->port_id,
2126 bpool->id, pkt_to_remove, num,
2127 q->priv->bpool_init_size);
2129 for (i = 0; i < pkt_to_remove; i++) {
2130 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2133 mbuf = (struct rte_mbuf *)
2134 (cookie_addr_high | buff.cookie);
2135 rte_pktmbuf_free(mbuf);
2137 mrvl_port_bpool_size
2138 [bpool->pp2_id][bpool->id][core_id] -= i;
2140 rte_spinlock_unlock(&q->priv->lock);
2147 * Prepare offload information.
2151 * @param packet_type
2152 * Packet type bitfield.
2154 * Pointer to the pp2_ouq_l3_type structure.
2156 * Pointer to the pp2_outq_l4_type structure.
2157 * @param gen_l3_cksum
2158 * Will be set to 1 in case l3 checksum is computed.
2160 * Will be set to 1 in case l4 checksum is computed.
2163 * 0 on success, negative error value otherwise.
2166 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2167 enum pp2_outq_l3_type *l3_type,
2168 enum pp2_outq_l4_type *l4_type,
2173 * Based on ol_flags prepare information
2174 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2177 if (ol_flags & PKT_TX_IPV4) {
2178 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2179 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2180 } else if (ol_flags & PKT_TX_IPV6) {
2181 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2182 /* no checksum for ipv6 header */
2185 /* if something different then stop processing */
2189 ol_flags &= PKT_TX_L4_MASK;
2190 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2191 ol_flags == PKT_TX_TCP_CKSUM) {
2192 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2194 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2195 ol_flags == PKT_TX_UDP_CKSUM) {
2196 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2199 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2200 /* no checksum for other type */
2208 * Release already sent buffers to bpool (buffer-pool).
2211 * Pointer to the port structure.
2213 * Pointer to the MUSDK hardware interface.
2215 * Pointer to the shadow queue.
2219 * Force releasing packets.
2222 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2223 unsigned int core_id, struct mrvl_shadow_txq *sq,
2226 struct buff_release_entry *entry;
2227 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2230 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2232 sq->num_to_release += nb_done;
2234 if (likely(!force &&
2235 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2238 nb_done = sq->num_to_release;
2239 sq->num_to_release = 0;
2241 for (i = 0; i < nb_done; i++) {
2242 entry = &sq->ent[sq->tail + num];
2243 if (unlikely(!entry->buff.addr)) {
2245 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2246 sq->tail, (u64)entry->buff.cookie,
2247 (u64)entry->buff.addr);
2252 if (unlikely(!entry->bpool)) {
2253 struct rte_mbuf *mbuf;
2255 mbuf = (struct rte_mbuf *)
2256 (cookie_addr_high | entry->buff.cookie);
2257 rte_pktmbuf_free(mbuf);
2262 mrvl_port_bpool_size
2263 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2265 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2270 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2272 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2279 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2280 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2286 * DPDK callback for transmit.
2289 * Generic pointer transmit queue.
2291 * Packets to transmit.
2293 * Number of packets in array.
2296 * Number of packets successfully transmitted.
2299 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2301 struct mrvl_txq *q = txq;
2302 struct mrvl_shadow_txq *sq;
2303 struct pp2_hif *hif;
2304 struct pp2_ppio_desc descs[nb_pkts];
2305 unsigned int core_id = rte_lcore_id();
2306 int i, ret, bytes_sent = 0;
2307 uint16_t num, sq_free_size;
2310 hif = mrvl_get_hif(q->priv, core_id);
2311 sq = &q->shadow_txqs[core_id];
2313 if (unlikely(!q->priv->ppio || !hif))
2317 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2318 sq, q->queue_id, 0);
2320 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2321 if (unlikely(nb_pkts > sq_free_size)) {
2323 "No room in shadow queue for %d packets! %d packets will be sent.",
2324 nb_pkts, sq_free_size);
2325 nb_pkts = sq_free_size;
2328 for (i = 0; i < nb_pkts; i++) {
2329 struct rte_mbuf *mbuf = tx_pkts[i];
2330 int gen_l3_cksum, gen_l4_cksum;
2331 enum pp2_outq_l3_type l3_type;
2332 enum pp2_outq_l4_type l4_type;
2334 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2335 struct rte_mbuf *pref_pkt_hdr;
2337 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2338 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2339 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2342 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2343 sq->ent[sq->head].buff.addr =
2344 rte_mbuf_data_iova_default(mbuf);
2345 sq->ent[sq->head].bpool =
2346 (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
2347 mbuf->refcnt > 1)) ? NULL :
2348 mrvl_port_to_bpool_lookup[mbuf->port];
2349 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2352 pp2_ppio_outq_desc_reset(&descs[i]);
2353 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2354 rte_pktmbuf_iova(mbuf));
2355 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2356 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2357 rte_pktmbuf_pkt_len(mbuf));
2359 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2361 * in case unsupported ol_flags were passed
2362 * do not update descriptor offload information
2364 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2365 &l3_type, &l4_type, &gen_l3_cksum,
2370 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2372 mbuf->l2_len + mbuf->l3_len,
2373 gen_l3_cksum, gen_l4_cksum);
2377 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2378 /* number of packets that were not sent */
2379 if (unlikely(num > nb_pkts)) {
2380 for (i = nb_pkts; i < num; i++) {
2381 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2382 MRVL_PP2_TX_SHADOWQ_MASK;
2383 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2385 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2387 sq->size -= num - nb_pkts;
2390 q->bytes_sent += bytes_sent;
2396 * Initialize packet processor.
2399 * 0 on success, negative error value otherwise.
2404 struct pp2_init_params init_params;
2406 memset(&init_params, 0, sizeof(init_params));
2407 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2408 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2409 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2411 return pp2_init(&init_params);
2415 * Deinitialize packet processor.
2418 * 0 on success, negative error value otherwise.
2421 mrvl_deinit_pp2(void)
2427 * Create private device structure.
2430 * Pointer to the port name passed in the initialization parameters.
2433 * Pointer to the newly allocated private device structure.
2435 static struct mrvl_priv *
2436 mrvl_priv_create(const char *dev_name)
2438 struct pp2_bpool_params bpool_params;
2439 char match[MRVL_MATCH_LEN];
2440 struct mrvl_priv *priv;
2443 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2447 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2448 &priv->pp_id, &priv->ppio_id);
2452 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2453 PP2_BPOOL_NUM_POOLS);
2456 priv->bpool_bit = bpool_bit;
2458 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2460 memset(&bpool_params, 0, sizeof(bpool_params));
2461 bpool_params.match = match;
2462 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2463 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2465 goto out_clear_bpool_bit;
2467 priv->ppio_params.type = PP2_PPIO_T_NIC;
2468 rte_spinlock_init(&priv->lock);
2471 out_clear_bpool_bit:
2472 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2479 * Create device representing Ethernet port.
2482 * Pointer to the port's name.
2485 * 0 on success, negative error value otherwise.
2488 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2490 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2491 struct rte_eth_dev *eth_dev;
2492 struct mrvl_priv *priv;
2495 eth_dev = rte_eth_dev_allocate(name);
2499 priv = mrvl_priv_create(name);
2505 eth_dev->data->mac_addrs =
2506 rte_zmalloc("mac_addrs",
2507 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2508 if (!eth_dev->data->mac_addrs) {
2509 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2514 memset(&req, 0, sizeof(req));
2515 strcpy(req.ifr_name, name);
2516 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2520 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2521 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2523 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2524 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2525 eth_dev->data->kdrv = RTE_KDRV_NONE;
2526 eth_dev->data->dev_private = priv;
2527 eth_dev->device = &vdev->device;
2528 eth_dev->dev_ops = &mrvl_ops;
2530 rte_eth_dev_probing_finish(eth_dev);
2533 rte_free(eth_dev->data->mac_addrs);
2535 rte_eth_dev_release_port(eth_dev);
2543 * Cleanup previously created device representing Ethernet port.
2546 * Pointer to the port name.
2549 mrvl_eth_dev_destroy(const char *name)
2551 struct rte_eth_dev *eth_dev;
2552 struct mrvl_priv *priv;
2554 eth_dev = rte_eth_dev_allocated(name);
2558 priv = eth_dev->data->dev_private;
2559 pp2_bpool_deinit(priv->bpool);
2560 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2562 rte_free(eth_dev->data->mac_addrs);
2563 rte_eth_dev_release_port(eth_dev);
2567 * Callback used by rte_kvargs_process() during argument parsing.
2570 * Pointer to the parsed key (unused).
2572 * Pointer to the parsed value.
2574 * Pointer to the extra arguments which contains address of the
2575 * table of pointers to parsed interface names.
2581 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2584 struct mrvl_ifnames *ifnames = extra_args;
2586 ifnames->names[ifnames->idx++] = value;
2592 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2595 mrvl_deinit_hifs(void)
2599 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2601 pp2_hif_deinit(hifs[i]);
2603 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2604 memset(hifs, 0, sizeof(hifs));
2608 * DPDK callback to register the virtual device.
2611 * Pointer to the virtual device.
2614 * 0 on success, negative error value otherwise.
2617 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2619 struct rte_kvargs *kvlist;
2620 struct mrvl_ifnames ifnames;
2622 uint32_t i, ifnum, cfgnum;
2625 params = rte_vdev_device_args(vdev);
2629 kvlist = rte_kvargs_parse(params, valid_args);
2633 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2634 if (ifnum > RTE_DIM(ifnames.names))
2635 goto out_free_kvlist;
2638 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2639 mrvl_get_ifnames, &ifnames);
2643 * The below system initialization should be done only once,
2644 * on the first provided configuration file
2646 if (!mrvl_qos_cfg) {
2647 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2648 MRVL_LOG(INFO, "Parsing config file!");
2650 MRVL_LOG(ERR, "Cannot handle more than one config file!");
2651 goto out_free_kvlist;
2652 } else if (cfgnum == 1) {
2653 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2654 mrvl_get_qoscfg, &mrvl_qos_cfg);
2661 MRVL_LOG(INFO, "Perform MUSDK initializations");
2663 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
2665 goto out_free_kvlist;
2667 ret = mrvl_init_pp2();
2669 MRVL_LOG(ERR, "Failed to init PP!");
2670 rte_mvep_deinit(MVEP_MOD_T_PP2);
2671 goto out_free_kvlist;
2674 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2675 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2677 mrvl_lcore_first = RTE_MAX_LCORE;
2678 mrvl_lcore_last = 0;
2681 for (i = 0; i < ifnum; i++) {
2682 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
2683 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2687 mrvl_dev_num += ifnum;
2689 rte_kvargs_free(kvlist);
2694 mrvl_eth_dev_destroy(ifnames.names[i]);
2696 if (mrvl_dev_num == 0) {
2698 rte_mvep_deinit(MVEP_MOD_T_PP2);
2701 rte_kvargs_free(kvlist);
2707 * DPDK callback to remove virtual device.
2710 * Pointer to the removed virtual device.
2713 * 0 on success, negative error value otherwise.
2716 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2721 name = rte_vdev_device_name(vdev);
2725 MRVL_LOG(INFO, "Removing %s", name);
2727 RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */
2728 char ifname[RTE_ETH_NAME_MAX_LEN];
2730 rte_eth_dev_get_name_by_port(i, ifname);
2731 mrvl_eth_dev_destroy(ifname);
2735 if (mrvl_dev_num == 0) {
2736 MRVL_LOG(INFO, "Perform MUSDK deinit");
2739 rte_mvep_deinit(MVEP_MOD_T_PP2);
2745 static struct rte_vdev_driver pmd_mrvl_drv = {
2746 .probe = rte_pmd_mrvl_probe,
2747 .remove = rte_pmd_mrvl_remove,
2750 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
2751 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
2753 RTE_INIT(mrvl_init_log)
2755 mrvl_logtype = rte_log_register("pmd.net.mvpp2");
2756 if (mrvl_logtype >= 0)
2757 rte_log_set_level(mrvl_logtype, RTE_LOG_NOTICE);