1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_ethdev_driver.h>
8 #include <rte_kvargs.h>
10 #include <rte_malloc.h>
11 #include <rte_bus_vdev.h>
13 /* Unluckily, container_of is defined by both DPDK and MUSDK,
14 * we'll declare only one version.
16 * Note that it is not used in this PMD anyway.
23 #include <linux/ethtool.h>
24 #include <linux/sockios.h>
26 #include <net/if_arp.h>
27 #include <sys/ioctl.h>
28 #include <sys/socket.h>
30 #include <sys/types.h>
32 #include "mrvl_ethdev.h"
35 /* bitmask with reserved hifs */
36 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
37 /* bitmask with reserved bpools */
38 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
39 /* bitmask with reserved kernel RSS tables */
40 #define MRVL_MUSDK_RSS_RESERVED 0x01
41 /* maximum number of available hifs */
42 #define MRVL_MUSDK_HIFS_MAX 9
45 #define MRVL_MUSDK_PREFETCH_SHIFT 2
47 /* TCAM has 25 entries reserved for uc/mc filter entries */
48 #define MRVL_MAC_ADDRS_MAX 25
49 #define MRVL_MATCH_LEN 16
50 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
51 /* Maximum allowable packet size */
52 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
54 #define MRVL_IFACE_NAME_ARG "iface"
55 #define MRVL_CFG_ARG "cfg"
57 #define MRVL_BURST_SIZE 64
59 #define MRVL_ARP_LENGTH 28
61 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
63 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
64 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
66 /* Memory size (in bytes) for MUSDK dma buffers */
67 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
69 /** Port Rx offload capabilities */
70 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
71 DEV_RX_OFFLOAD_JUMBO_FRAME | \
72 DEV_RX_OFFLOAD_CRC_STRIP | \
73 DEV_RX_OFFLOAD_CHECKSUM)
75 /** Port Tx offloads capabilities */
76 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
77 DEV_TX_OFFLOAD_UDP_CKSUM | \
78 DEV_TX_OFFLOAD_TCP_CKSUM)
80 static const char * const valid_args[] = {
86 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
87 static struct pp2_hif *hifs[RTE_MAX_LCORE];
88 static int used_bpools[PP2_NUM_PKT_PROC] = {
89 MRVL_MUSDK_BPOOLS_RESERVED,
90 MRVL_MUSDK_BPOOLS_RESERVED
93 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
94 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
95 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
98 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
103 * To use buffer harvesting based on loopback port shadow queue structure
104 * was introduced for buffers information bookkeeping.
106 * Before sending the packet, related buffer information (pp2_buff_inf) is
107 * stored in shadow queue. After packet is transmitted no longer used
108 * packet buffer is released back to it's original hardware pool,
109 * on condition it originated from interface.
110 * In case it was generated by application itself i.e: mbuf->port field is
111 * 0xff then its released to software mempool.
113 struct mrvl_shadow_txq {
114 int head; /* write index - used when sending buffers */
115 int tail; /* read index - used when releasing buffers */
116 u16 size; /* queue occupied size */
117 u16 num_to_release; /* number of buffers sent, that can be released */
118 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
122 struct mrvl_priv *priv;
123 struct rte_mempool *mp;
132 struct mrvl_priv *priv;
136 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
137 int tx_deferred_start;
140 static int mrvl_lcore_first;
141 static int mrvl_lcore_last;
142 static int mrvl_dev_num;
144 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
145 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
146 struct pp2_hif *hif, unsigned int core_id,
147 struct mrvl_shadow_txq *sq, int qid, int force);
149 #define MRVL_XSTATS_TBL_ENTRY(name) { \
150 #name, offsetof(struct pp2_ppio_statistics, name), \
151 sizeof(((struct pp2_ppio_statistics *)0)->name) \
154 /* Table with xstats data */
159 } mrvl_xstats_tbl[] = {
160 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
161 MRVL_XSTATS_TBL_ENTRY(rx_packets),
162 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
163 MRVL_XSTATS_TBL_ENTRY(rx_errors),
164 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
165 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
166 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
167 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
168 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
169 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
170 MRVL_XSTATS_TBL_ENTRY(tx_packets),
171 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
172 MRVL_XSTATS_TBL_ENTRY(tx_errors)
176 mrvl_get_bpool_size(int pp2_id, int pool_id)
181 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
182 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
188 mrvl_reserve_bit(int *bitmap, int max)
190 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
201 mrvl_init_hif(int core_id)
203 struct pp2_hif_params params;
204 char match[MRVL_MATCH_LEN];
207 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
209 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
213 snprintf(match, sizeof(match), "hif-%d", ret);
214 memset(¶ms, 0, sizeof(params));
215 params.match = match;
216 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
217 ret = pp2_hif_init(¶ms, &hifs[core_id]);
219 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
226 static inline struct pp2_hif*
227 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
231 if (likely(hifs[core_id] != NULL))
232 return hifs[core_id];
234 rte_spinlock_lock(&priv->lock);
236 ret = mrvl_init_hif(core_id);
238 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
242 if (core_id < mrvl_lcore_first)
243 mrvl_lcore_first = core_id;
245 if (core_id > mrvl_lcore_last)
246 mrvl_lcore_last = core_id;
248 rte_spinlock_unlock(&priv->lock);
250 return hifs[core_id];
254 * Configure rss based on dpdk rss configuration.
257 * Pointer to private structure.
259 * Pointer to RSS configuration.
262 * 0 on success, negative error value otherwise.
265 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
267 if (rss_conf->rss_key)
268 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
270 if (rss_conf->rss_hf == 0) {
271 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
272 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
273 priv->ppio_params.inqs_params.hash_type =
274 PP2_PPIO_HASH_T_2_TUPLE;
275 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
276 priv->ppio_params.inqs_params.hash_type =
277 PP2_PPIO_HASH_T_5_TUPLE;
278 priv->rss_hf_tcp = 1;
279 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
280 priv->ppio_params.inqs_params.hash_type =
281 PP2_PPIO_HASH_T_5_TUPLE;
282 priv->rss_hf_tcp = 0;
291 * Ethernet device configuration.
293 * Prepare the driver for a given number of TX and RX queues and
297 * Pointer to Ethernet device structure.
300 * 0 on success, negative error value otherwise.
303 mrvl_dev_configure(struct rte_eth_dev *dev)
305 struct mrvl_priv *priv = dev->data->dev_private;
308 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
309 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
310 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
311 dev->data->dev_conf.rxmode.mq_mode);
315 if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
317 "L2 CRC stripping is always enabled in hw\n");
318 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
321 if (dev->data->dev_conf.rxmode.split_hdr_size) {
322 RTE_LOG(INFO, PMD, "Split headers not supported\n");
326 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
327 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
328 ETHER_HDR_LEN - ETHER_CRC_LEN;
330 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
331 dev->data->nb_rx_queues);
335 ret = mrvl_configure_txqs(priv, dev->data->port_id,
336 dev->data->nb_tx_queues);
340 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
341 priv->ppio_params.maintain_stats = 1;
342 priv->nb_rx_queues = dev->data->nb_rx_queues;
344 if (dev->data->nb_rx_queues == 1 &&
345 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
346 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
347 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
352 return mrvl_configure_rss(priv,
353 &dev->data->dev_conf.rx_adv_conf.rss_conf);
357 * DPDK callback to change the MTU.
359 * Setting the MTU affects hardware MRU (packets larger than the MRU
363 * Pointer to Ethernet device structure.
368 * 0 on success, negative error value otherwise.
371 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
373 struct mrvl_priv *priv = dev->data->dev_private;
374 /* extra MV_MH_SIZE bytes are required for Marvell tag */
375 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
378 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
384 ret = pp2_ppio_set_mru(priv->ppio, mru);
388 return pp2_ppio_set_mtu(priv->ppio, mtu);
392 * DPDK callback to bring the link up.
395 * Pointer to Ethernet device structure.
398 * 0 on success, negative error value otherwise.
401 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
403 struct mrvl_priv *priv = dev->data->dev_private;
409 ret = pp2_ppio_enable(priv->ppio);
414 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
415 * as pp2_ppio_enable() changes port->t_mode from default 0 to
416 * PP2_TRAFFIC_INGRESS_EGRESS.
418 * Set mtu to default DPDK value here.
420 ret = mrvl_mtu_set(dev, dev->data->mtu);
422 pp2_ppio_disable(priv->ppio);
428 * DPDK callback to bring the link down.
431 * Pointer to Ethernet device structure.
434 * 0 on success, negative error value otherwise.
437 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
439 struct mrvl_priv *priv = dev->data->dev_private;
444 return pp2_ppio_disable(priv->ppio);
448 * DPDK callback to start tx queue.
451 * Pointer to Ethernet device structure.
453 * Transmit queue index.
456 * 0 on success, negative error value otherwise.
459 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
461 struct mrvl_priv *priv = dev->data->dev_private;
467 /* passing 1 enables given tx queue */
468 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
470 RTE_LOG(ERR, PMD, "Failed to start txq %d\n", queue_id);
474 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
480 * DPDK callback to stop tx queue.
483 * Pointer to Ethernet device structure.
485 * Transmit queue index.
488 * 0 on success, negative error value otherwise.
491 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
493 struct mrvl_priv *priv = dev->data->dev_private;
499 /* passing 0 disables given tx queue */
500 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
502 RTE_LOG(ERR, PMD, "Failed to stop txq %d\n", queue_id);
506 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
512 * DPDK callback to start the device.
515 * Pointer to Ethernet device structure.
518 * 0 on success, negative errno value on failure.
521 mrvl_dev_start(struct rte_eth_dev *dev)
523 struct mrvl_priv *priv = dev->data->dev_private;
524 char match[MRVL_MATCH_LEN];
525 int ret = 0, i, def_init_size;
527 snprintf(match, sizeof(match), "ppio-%d:%d",
528 priv->pp_id, priv->ppio_id);
529 priv->ppio_params.match = match;
532 * Calculate the minimum bpool size for refill feature as follows:
533 * 2 default burst sizes multiply by number of rx queues.
534 * If the bpool size will be below this value, new buffers will
535 * be added to the pool.
537 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
539 /* In case initial bpool size configured in queues setup is
540 * smaller than minimum size add more buffers
542 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
543 if (priv->bpool_init_size < def_init_size) {
544 int buffs_to_add = def_init_size - priv->bpool_init_size;
546 priv->bpool_init_size += buffs_to_add;
547 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
549 RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
553 * Calculate the maximum bpool size for refill feature as follows:
554 * maximum number of descriptors in rx queue multiply by number
555 * of rx queues plus minimum bpool size.
556 * In case the bpool size will exceed this value, superfluous buffers
559 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
560 priv->bpool_min_size;
562 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
564 RTE_LOG(ERR, PMD, "Failed to init ppio\n");
569 * In case there are some some stale uc/mc mac addresses flush them
570 * here. It cannot be done during mrvl_dev_close() as port information
571 * is already gone at that point (due to pp2_ppio_deinit() in
574 if (!priv->uc_mc_flushed) {
575 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
578 "Failed to flush uc/mc filter list\n");
581 priv->uc_mc_flushed = 1;
584 if (!priv->vlan_flushed) {
585 ret = pp2_ppio_flush_vlan(priv->ppio);
587 RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
590 * once pp2_ppio_flush_vlan() is supported jump to out
594 priv->vlan_flushed = 1;
597 /* For default QoS config, don't start classifier. */
599 ret = mrvl_start_qos_mapping(priv);
601 RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n");
606 ret = mrvl_dev_set_link_up(dev);
608 RTE_LOG(ERR, PMD, "Failed to set link up\n");
612 /* start tx queues */
613 for (i = 0; i < dev->data->nb_tx_queues; i++) {
614 struct mrvl_txq *txq = dev->data->tx_queues[i];
616 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
618 if (!txq->tx_deferred_start)
622 * All txqs are started by default. Stop them
623 * so that tx_deferred_start works as expected.
625 ret = mrvl_tx_queue_stop(dev, i);
632 RTE_LOG(ERR, PMD, "Failed to start device\n");
633 pp2_ppio_deinit(priv->ppio);
638 * Flush receive queues.
641 * Pointer to Ethernet device structure.
644 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
648 RTE_LOG(INFO, PMD, "Flushing rx queues\n");
649 for (i = 0; i < dev->data->nb_rx_queues; i++) {
653 struct mrvl_rxq *q = dev->data->rx_queues[i];
654 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
656 num = MRVL_PP2_RXD_MAX;
657 ret = pp2_ppio_recv(q->priv->ppio,
658 q->priv->rxq_map[q->queue_id].tc,
659 q->priv->rxq_map[q->queue_id].inq,
660 descs, (uint16_t *)&num);
661 } while (ret == 0 && num);
666 * Flush transmit shadow queues.
669 * Pointer to Ethernet device structure.
672 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
675 struct mrvl_txq *txq;
677 RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
678 for (i = 0; i < dev->data->nb_tx_queues; i++) {
679 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
681 for (j = 0; j < RTE_MAX_LCORE; j++) {
682 struct mrvl_shadow_txq *sq;
687 sq = &txq->shadow_txqs[j];
688 mrvl_free_sent_buffers(txq->priv->ppio,
689 hifs[j], j, sq, txq->queue_id, 1);
690 while (sq->tail != sq->head) {
691 uint64_t addr = cookie_addr_high |
692 sq->ent[sq->tail].buff.cookie;
694 (struct rte_mbuf *)addr);
695 sq->tail = (sq->tail + 1) &
696 MRVL_PP2_TX_SHADOWQ_MASK;
698 memset(sq, 0, sizeof(*sq));
704 * Flush hardware bpool (buffer-pool).
707 * Pointer to Ethernet device structure.
710 mrvl_flush_bpool(struct rte_eth_dev *dev)
712 struct mrvl_priv *priv = dev->data->dev_private;
716 unsigned int core_id = rte_lcore_id();
718 if (core_id == LCORE_ID_ANY)
721 hif = mrvl_get_hif(priv, core_id);
723 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
725 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
730 struct pp2_buff_inf inf;
733 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
737 addr = cookie_addr_high | inf.cookie;
738 rte_pktmbuf_free((struct rte_mbuf *)addr);
743 * DPDK callback to stop the device.
746 * Pointer to Ethernet device structure.
749 mrvl_dev_stop(struct rte_eth_dev *dev)
751 struct mrvl_priv *priv = dev->data->dev_private;
753 mrvl_dev_set_link_down(dev);
754 mrvl_flush_rx_queues(dev);
755 mrvl_flush_tx_shadow_queues(dev);
757 pp2_cls_tbl_deinit(priv->cls_tbl);
758 priv->cls_tbl = NULL;
761 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
762 priv->qos_tbl = NULL;
765 pp2_ppio_deinit(priv->ppio);
768 /* policer must be released after ppio deinitialization */
770 pp2_cls_plcr_deinit(priv->policer);
771 priv->policer = NULL;
776 * DPDK callback to close the device.
779 * Pointer to Ethernet device structure.
782 mrvl_dev_close(struct rte_eth_dev *dev)
784 struct mrvl_priv *priv = dev->data->dev_private;
787 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
788 struct pp2_ppio_tc_params *tc_params =
789 &priv->ppio_params.inqs_params.tcs_params[i];
791 if (tc_params->inqs_params) {
792 rte_free(tc_params->inqs_params);
793 tc_params->inqs_params = NULL;
797 mrvl_flush_bpool(dev);
801 * DPDK callback to retrieve physical link information.
804 * Pointer to Ethernet device structure.
805 * @param wait_to_complete
806 * Wait for request completion (ignored).
809 * 0 on success, negative error value otherwise.
812 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
816 * once MUSDK provides necessary API use it here
818 struct mrvl_priv *priv = dev->data->dev_private;
819 struct ethtool_cmd edata;
821 int ret, fd, link_up;
826 edata.cmd = ETHTOOL_GSET;
828 strcpy(req.ifr_name, dev->data->name);
829 req.ifr_data = (void *)&edata;
831 fd = socket(AF_INET, SOCK_DGRAM, 0);
835 ret = ioctl(fd, SIOCETHTOOL, &req);
843 switch (ethtool_cmd_speed(&edata)) {
845 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
848 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
851 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
854 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
857 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
860 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
861 ETH_LINK_HALF_DUPLEX;
862 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
864 pp2_ppio_get_link_state(priv->ppio, &link_up);
865 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
871 * DPDK callback to enable promiscuous mode.
874 * Pointer to Ethernet device structure.
877 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
879 struct mrvl_priv *priv = dev->data->dev_private;
888 ret = pp2_ppio_set_promisc(priv->ppio, 1);
890 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
894 * DPDK callback to enable allmulti mode.
897 * Pointer to Ethernet device structure.
900 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
902 struct mrvl_priv *priv = dev->data->dev_private;
911 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
913 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
917 * DPDK callback to disable promiscuous mode.
920 * Pointer to Ethernet device structure.
923 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
925 struct mrvl_priv *priv = dev->data->dev_private;
931 ret = pp2_ppio_set_promisc(priv->ppio, 0);
933 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
937 * DPDK callback to disable allmulticast mode.
940 * Pointer to Ethernet device structure.
943 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
945 struct mrvl_priv *priv = dev->data->dev_private;
951 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
953 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
957 * DPDK callback to remove a MAC address.
960 * Pointer to Ethernet device structure.
965 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
967 struct mrvl_priv *priv = dev->data->dev_private;
968 char buf[ETHER_ADDR_FMT_SIZE];
977 ret = pp2_ppio_remove_mac_addr(priv->ppio,
978 dev->data->mac_addrs[index].addr_bytes);
980 ether_format_addr(buf, sizeof(buf),
981 &dev->data->mac_addrs[index]);
982 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
987 * DPDK callback to add a MAC address.
990 * Pointer to Ethernet device structure.
992 * MAC address to register.
996 * VMDq pool index to associate address with (unused).
999 * 0 on success, negative error value otherwise.
1002 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1003 uint32_t index, uint32_t vmdq __rte_unused)
1005 struct mrvl_priv *priv = dev->data->dev_private;
1006 char buf[ETHER_ADDR_FMT_SIZE];
1013 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1020 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1021 * parameter uc_filter_max. Maximum number of mc addresses is then
1022 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1025 * If more than uc_filter_max uc addresses were added to filter list
1026 * then NIC will switch to promiscuous mode automatically.
1028 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1029 * were added to filter list then NIC will switch to all-multicast mode
1032 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1034 ether_format_addr(buf, sizeof(buf), mac_addr);
1035 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
1043 * DPDK callback to set the primary MAC address.
1046 * Pointer to Ethernet device structure.
1048 * MAC address to register.
1051 * 0 on success, negative error value otherwise.
1054 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1056 struct mrvl_priv *priv = dev->data->dev_private;
1065 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1067 char buf[ETHER_ADDR_FMT_SIZE];
1068 ether_format_addr(buf, sizeof(buf), mac_addr);
1069 RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf);
1076 * DPDK callback to get device statistics.
1079 * Pointer to Ethernet device structure.
1081 * Stats structure output buffer.
1084 * 0 on success, negative error value otherwise.
1087 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1089 struct mrvl_priv *priv = dev->data->dev_private;
1090 struct pp2_ppio_statistics ppio_stats;
1091 uint64_t drop_mac = 0;
1092 unsigned int i, idx, ret;
1097 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1098 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1099 struct pp2_ppio_inq_statistics rx_stats;
1104 idx = rxq->queue_id;
1105 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1107 "rx queue %d stats out of range (0 - %d)\n",
1108 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1112 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1113 priv->rxq_map[idx].tc,
1114 priv->rxq_map[idx].inq,
1116 if (unlikely(ret)) {
1118 "Failed to update rx queue %d stats\n", idx);
1122 stats->q_ibytes[idx] = rxq->bytes_recv;
1123 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1124 stats->q_errors[idx] = rx_stats.drop_early +
1125 rx_stats.drop_fullq +
1128 stats->ibytes += rxq->bytes_recv;
1129 drop_mac += rxq->drop_mac;
1132 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1133 struct mrvl_txq *txq = dev->data->tx_queues[i];
1134 struct pp2_ppio_outq_statistics tx_stats;
1139 idx = txq->queue_id;
1140 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1142 "tx queue %d stats out of range (0 - %d)\n",
1143 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1146 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1148 if (unlikely(ret)) {
1150 "Failed to update tx queue %d stats\n", idx);
1154 stats->q_opackets[idx] = tx_stats.deq_desc;
1155 stats->q_obytes[idx] = txq->bytes_sent;
1156 stats->obytes += txq->bytes_sent;
1159 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1160 if (unlikely(ret)) {
1161 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
1165 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1166 stats->opackets += ppio_stats.tx_packets;
1167 stats->imissed += ppio_stats.rx_fullq_dropped +
1168 ppio_stats.rx_bm_dropped +
1169 ppio_stats.rx_early_dropped +
1170 ppio_stats.rx_fifo_dropped +
1171 ppio_stats.rx_cls_dropped;
1172 stats->ierrors = drop_mac;
1178 * DPDK callback to clear device statistics.
1181 * Pointer to Ethernet device structure.
1184 mrvl_stats_reset(struct rte_eth_dev *dev)
1186 struct mrvl_priv *priv = dev->data->dev_private;
1192 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1193 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1195 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1196 priv->rxq_map[i].inq, NULL, 1);
1197 rxq->bytes_recv = 0;
1201 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1202 struct mrvl_txq *txq = dev->data->tx_queues[i];
1204 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1205 txq->bytes_sent = 0;
1208 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1212 * DPDK callback to get extended statistics.
1215 * Pointer to Ethernet device structure.
1217 * Pointer to xstats table.
1219 * Number of entries in xstats table.
1221 * Negative value on error, number of read xstats otherwise.
1224 mrvl_xstats_get(struct rte_eth_dev *dev,
1225 struct rte_eth_xstat *stats, unsigned int n)
1227 struct mrvl_priv *priv = dev->data->dev_private;
1228 struct pp2_ppio_statistics ppio_stats;
1234 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1235 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1238 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1239 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1240 mrvl_xstats_tbl[i].offset);
1241 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1242 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1243 mrvl_xstats_tbl[i].offset);
1248 stats[i].value = val;
1255 * DPDK callback to reset extended statistics.
1258 * Pointer to Ethernet device structure.
1261 mrvl_xstats_reset(struct rte_eth_dev *dev)
1263 mrvl_stats_reset(dev);
1267 * DPDK callback to get extended statistics names.
1269 * @param dev (unused)
1270 * Pointer to Ethernet device structure.
1271 * @param xstats_names
1272 * Pointer to xstats names table.
1274 * Size of the xstats names table.
1276 * Number of read names.
1279 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1280 struct rte_eth_xstat_name *xstats_names,
1286 return RTE_DIM(mrvl_xstats_tbl);
1288 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1289 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s",
1290 mrvl_xstats_tbl[i].name);
1296 * DPDK callback to get information about the device.
1299 * Pointer to Ethernet device structure (unused).
1301 * Info structure output buffer.
1304 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1305 struct rte_eth_dev_info *info)
1307 info->speed_capa = ETH_LINK_SPEED_10M |
1308 ETH_LINK_SPEED_100M |
1312 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1313 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1314 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1316 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1317 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1318 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1320 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1321 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1322 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1324 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1325 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1327 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1328 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1330 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1331 ETH_RSS_NONFRAG_IPV4_TCP |
1332 ETH_RSS_NONFRAG_IPV4_UDP;
1334 /* By default packets are dropped if no descriptors are available */
1335 info->default_rxconf.rx_drop_en = 1;
1336 info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
1338 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1342 * Return supported packet types.
1345 * Pointer to Ethernet device structure (unused).
1348 * Const pointer to the table with supported packet types.
1350 static const uint32_t *
1351 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1353 static const uint32_t ptypes[] = {
1356 RTE_PTYPE_L3_IPV4_EXT,
1357 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1359 RTE_PTYPE_L3_IPV6_EXT,
1360 RTE_PTYPE_L2_ETHER_ARP,
1369 * DPDK callback to get information about specific receive queue.
1372 * Pointer to Ethernet device structure.
1373 * @param rx_queue_id
1374 * Receive queue index.
1376 * Receive queue information structure.
1378 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1379 struct rte_eth_rxq_info *qinfo)
1381 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1382 struct mrvl_priv *priv = dev->data->dev_private;
1383 int inq = priv->rxq_map[rx_queue_id].inq;
1384 int tc = priv->rxq_map[rx_queue_id].tc;
1385 struct pp2_ppio_tc_params *tc_params =
1386 &priv->ppio_params.inqs_params.tcs_params[tc];
1389 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1393 * DPDK callback to get information about specific transmit queue.
1396 * Pointer to Ethernet device structure.
1397 * @param tx_queue_id
1398 * Transmit queue index.
1400 * Transmit queue information structure.
1402 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1403 struct rte_eth_txq_info *qinfo)
1405 struct mrvl_priv *priv = dev->data->dev_private;
1406 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1409 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1410 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1414 * DPDK callback to Configure a VLAN filter.
1417 * Pointer to Ethernet device structure.
1419 * VLAN ID to filter.
1424 * 0 on success, negative error value otherwise.
1427 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1429 struct mrvl_priv *priv = dev->data->dev_private;
1437 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1438 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1442 * Release buffers to hardware bpool (buffer-pool)
1445 * Receive queue pointer.
1447 * Number of buffers to release to bpool.
1450 * 0 on success, negative error value otherwise.
1453 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1455 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1456 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1458 unsigned int core_id;
1459 struct pp2_hif *hif;
1460 struct pp2_bpool *bpool;
1462 core_id = rte_lcore_id();
1463 if (core_id == LCORE_ID_ANY)
1466 hif = mrvl_get_hif(rxq->priv, core_id);
1470 bpool = rxq->priv->bpool;
1472 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1476 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1478 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1480 for (i = 0; i < num; i++) {
1481 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1482 != cookie_addr_high) {
1484 "mbuf virtual addr high 0x%lx out of range\n",
1485 (uint64_t)mbufs[i] >> 32);
1489 entries[i].buff.addr =
1490 rte_mbuf_data_iova_default(mbufs[i]);
1491 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1492 entries[i].bpool = bpool;
1495 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1496 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1503 for (; i < num; i++)
1504 rte_pktmbuf_free(mbufs[i]);
1510 * DPDK callback to configure the receive queue.
1513 * Pointer to Ethernet device structure.
1517 * Number of descriptors to configure in queue.
1519 * NUMA socket on which memory must be allocated.
1521 * Thresholds parameters.
1523 * Memory pool for buffer allocations.
1526 * 0 on success, negative error value otherwise.
1529 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1530 unsigned int socket,
1531 const struct rte_eth_rxconf *conf,
1532 struct rte_mempool *mp)
1534 struct mrvl_priv *priv = dev->data->dev_private;
1535 struct mrvl_rxq *rxq;
1537 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1541 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1543 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1545 * Unknown TC mapping, mapping will not have a correct queue.
1547 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1548 idx, priv->ppio_id);
1552 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1553 MRVL_PKT_EFFEC_OFFS;
1554 if (min_size < max_rx_pkt_len) {
1556 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1557 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1558 MRVL_PKT_EFFEC_OFFS,
1563 if (dev->data->rx_queues[idx]) {
1564 rte_free(dev->data->rx_queues[idx]);
1565 dev->data->rx_queues[idx] = NULL;
1568 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1574 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1575 rxq->queue_id = idx;
1576 rxq->port_id = dev->data->port_id;
1577 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1579 tc = priv->rxq_map[rxq->queue_id].tc,
1580 inq = priv->rxq_map[rxq->queue_id].inq;
1581 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1584 ret = mrvl_fill_bpool(rxq, desc);
1590 priv->bpool_init_size += desc;
1592 dev->data->rx_queues[idx] = rxq;
1598 * DPDK callback to release the receive queue.
1601 * Generic receive queue pointer.
1604 mrvl_rx_queue_release(void *rxq)
1606 struct mrvl_rxq *q = rxq;
1607 struct pp2_ppio_tc_params *tc_params;
1608 int i, num, tc, inq;
1609 struct pp2_hif *hif;
1610 unsigned int core_id = rte_lcore_id();
1612 if (core_id == LCORE_ID_ANY)
1615 hif = mrvl_get_hif(q->priv, core_id);
1620 tc = q->priv->rxq_map[q->queue_id].tc;
1621 inq = q->priv->rxq_map[q->queue_id].inq;
1622 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1623 num = tc_params->inqs_params[inq].size;
1624 for (i = 0; i < num; i++) {
1625 struct pp2_buff_inf inf;
1628 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1629 addr = cookie_addr_high | inf.cookie;
1630 rte_pktmbuf_free((struct rte_mbuf *)addr);
1637 * DPDK callback to configure the transmit queue.
1640 * Pointer to Ethernet device structure.
1642 * Transmit queue index.
1644 * Number of descriptors to configure in the queue.
1646 * NUMA socket on which memory must be allocated.
1648 * Tx queue configuration parameters.
1651 * 0 on success, negative error value otherwise.
1654 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1655 unsigned int socket,
1656 const struct rte_eth_txconf *conf)
1658 struct mrvl_priv *priv = dev->data->dev_private;
1659 struct mrvl_txq *txq;
1661 if (dev->data->tx_queues[idx]) {
1662 rte_free(dev->data->tx_queues[idx]);
1663 dev->data->tx_queues[idx] = NULL;
1666 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1671 txq->queue_id = idx;
1672 txq->port_id = dev->data->port_id;
1673 txq->tx_deferred_start = conf->tx_deferred_start;
1674 dev->data->tx_queues[idx] = txq;
1676 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1682 * DPDK callback to release the transmit queue.
1685 * Generic transmit queue pointer.
1688 mrvl_tx_queue_release(void *txq)
1690 struct mrvl_txq *q = txq;
1699 * DPDK callback to get flow control configuration.
1702 * Pointer to Ethernet device structure.
1704 * Pointer to the flow control configuration.
1707 * 0 on success, negative error value otherwise.
1710 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1712 struct mrvl_priv *priv = dev->data->dev_private;
1718 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1720 RTE_LOG(ERR, PMD, "Failed to read rx pause state\n");
1724 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1730 * DPDK callback to set flow control configuration.
1733 * Pointer to Ethernet device structure.
1735 * Pointer to the flow control configuration.
1738 * 0 on success, negative error value otherwise.
1741 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1743 struct mrvl_priv *priv = dev->data->dev_private;
1748 if (fc_conf->high_water ||
1749 fc_conf->low_water ||
1750 fc_conf->pause_time ||
1751 fc_conf->mac_ctrl_frame_fwd ||
1753 RTE_LOG(ERR, PMD, "Flowctrl parameter is not supported\n");
1758 if (fc_conf->mode == RTE_FC_NONE ||
1759 fc_conf->mode == RTE_FC_RX_PAUSE) {
1762 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1763 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1766 "Failed to change flowctrl on RX side\n");
1775 * Update RSS hash configuration
1778 * Pointer to Ethernet device structure.
1780 * Pointer to RSS configuration.
1783 * 0 on success, negative error value otherwise.
1786 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1787 struct rte_eth_rss_conf *rss_conf)
1789 struct mrvl_priv *priv = dev->data->dev_private;
1794 return mrvl_configure_rss(priv, rss_conf);
1798 * DPDK callback to get RSS hash configuration.
1801 * Pointer to Ethernet device structure.
1803 * Pointer to RSS configuration.
1809 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1810 struct rte_eth_rss_conf *rss_conf)
1812 struct mrvl_priv *priv = dev->data->dev_private;
1813 enum pp2_ppio_hash_type hash_type =
1814 priv->ppio_params.inqs_params.hash_type;
1816 rss_conf->rss_key = NULL;
1818 if (hash_type == PP2_PPIO_HASH_T_NONE)
1819 rss_conf->rss_hf = 0;
1820 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1821 rss_conf->rss_hf = ETH_RSS_IPV4;
1822 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1823 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1824 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1825 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1831 * DPDK callback to get rte_flow callbacks.
1834 * Pointer to the device structure.
1838 * Flow filter operation.
1840 * Pointer to pass the flow ops.
1843 * 0 on success, negative error value otherwise.
1846 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1847 enum rte_filter_type filter_type,
1848 enum rte_filter_op filter_op, void *arg)
1850 switch (filter_type) {
1851 case RTE_ETH_FILTER_GENERIC:
1852 if (filter_op != RTE_ETH_FILTER_GET)
1854 *(const void **)arg = &mrvl_flow_ops;
1857 RTE_LOG(WARNING, PMD, "Filter type (%d) not supported",
1863 static const struct eth_dev_ops mrvl_ops = {
1864 .dev_configure = mrvl_dev_configure,
1865 .dev_start = mrvl_dev_start,
1866 .dev_stop = mrvl_dev_stop,
1867 .dev_set_link_up = mrvl_dev_set_link_up,
1868 .dev_set_link_down = mrvl_dev_set_link_down,
1869 .dev_close = mrvl_dev_close,
1870 .link_update = mrvl_link_update,
1871 .promiscuous_enable = mrvl_promiscuous_enable,
1872 .allmulticast_enable = mrvl_allmulticast_enable,
1873 .promiscuous_disable = mrvl_promiscuous_disable,
1874 .allmulticast_disable = mrvl_allmulticast_disable,
1875 .mac_addr_remove = mrvl_mac_addr_remove,
1876 .mac_addr_add = mrvl_mac_addr_add,
1877 .mac_addr_set = mrvl_mac_addr_set,
1878 .mtu_set = mrvl_mtu_set,
1879 .stats_get = mrvl_stats_get,
1880 .stats_reset = mrvl_stats_reset,
1881 .xstats_get = mrvl_xstats_get,
1882 .xstats_reset = mrvl_xstats_reset,
1883 .xstats_get_names = mrvl_xstats_get_names,
1884 .dev_infos_get = mrvl_dev_infos_get,
1885 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1886 .rxq_info_get = mrvl_rxq_info_get,
1887 .txq_info_get = mrvl_txq_info_get,
1888 .vlan_filter_set = mrvl_vlan_filter_set,
1889 .tx_queue_start = mrvl_tx_queue_start,
1890 .tx_queue_stop = mrvl_tx_queue_stop,
1891 .rx_queue_setup = mrvl_rx_queue_setup,
1892 .rx_queue_release = mrvl_rx_queue_release,
1893 .tx_queue_setup = mrvl_tx_queue_setup,
1894 .tx_queue_release = mrvl_tx_queue_release,
1895 .flow_ctrl_get = mrvl_flow_ctrl_get,
1896 .flow_ctrl_set = mrvl_flow_ctrl_set,
1897 .rss_hash_update = mrvl_rss_hash_update,
1898 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1899 .filter_ctrl = mrvl_eth_filter_ctrl,
1903 * Return packet type information and l3/l4 offsets.
1906 * Pointer to the received packet descriptor.
1913 * Packet type information.
1915 static inline uint64_t
1916 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1917 uint8_t *l3_offset, uint8_t *l4_offset)
1919 enum pp2_inq_l3_type l3_type;
1920 enum pp2_inq_l4_type l4_type;
1921 uint64_t packet_type;
1923 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1924 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1926 packet_type = RTE_PTYPE_L2_ETHER;
1929 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1930 packet_type |= RTE_PTYPE_L3_IPV4;
1932 case PP2_INQ_L3_TYPE_IPV4_OK:
1933 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1935 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1936 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1938 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1939 packet_type |= RTE_PTYPE_L3_IPV6;
1941 case PP2_INQ_L3_TYPE_IPV6_EXT:
1942 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1944 case PP2_INQ_L3_TYPE_ARP:
1945 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1947 * In case of ARP l4_offset is set to wrong value.
1948 * Set it to proper one so that later on mbuf->l3_len can be
1949 * calculated subtracting l4_offset and l3_offset.
1951 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1954 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1959 case PP2_INQ_L4_TYPE_TCP:
1960 packet_type |= RTE_PTYPE_L4_TCP;
1962 case PP2_INQ_L4_TYPE_UDP:
1963 packet_type |= RTE_PTYPE_L4_UDP;
1966 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1974 * Get offload information from the received packet descriptor.
1977 * Pointer to the received packet descriptor.
1980 * Mbuf offload flags.
1982 static inline uint64_t
1983 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1986 enum pp2_inq_desc_status status;
1988 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1989 if (unlikely(status != PP2_DESC_ERR_OK))
1990 flags = PKT_RX_IP_CKSUM_BAD;
1992 flags = PKT_RX_IP_CKSUM_GOOD;
1994 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1995 if (unlikely(status != PP2_DESC_ERR_OK))
1996 flags |= PKT_RX_L4_CKSUM_BAD;
1998 flags |= PKT_RX_L4_CKSUM_GOOD;
2004 * DPDK callback for receive.
2007 * Generic pointer to the receive queue.
2009 * Array to store received packets.
2011 * Maximum number of packets in array.
2014 * Number of packets successfully received.
2017 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2019 struct mrvl_rxq *q = rxq;
2020 struct pp2_ppio_desc descs[nb_pkts];
2021 struct pp2_bpool *bpool;
2022 int i, ret, rx_done = 0;
2024 struct pp2_hif *hif;
2025 unsigned int core_id = rte_lcore_id();
2027 hif = mrvl_get_hif(q->priv, core_id);
2029 if (unlikely(!q->priv->ppio || !hif))
2032 bpool = q->priv->bpool;
2034 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2035 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2036 if (unlikely(ret < 0)) {
2037 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
2040 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2042 for (i = 0; i < nb_pkts; i++) {
2043 struct rte_mbuf *mbuf;
2044 uint8_t l3_offset, l4_offset;
2045 enum pp2_inq_desc_status status;
2048 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2049 struct pp2_ppio_desc *pref_desc;
2052 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2053 pref_addr = cookie_addr_high |
2054 pp2_ppio_inq_desc_get_cookie(pref_desc);
2055 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2056 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2059 addr = cookie_addr_high |
2060 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2061 mbuf = (struct rte_mbuf *)addr;
2062 rte_pktmbuf_reset(mbuf);
2064 /* drop packet in case of mac, overrun or resource error */
2065 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2066 if (unlikely(status != PP2_DESC_ERR_OK)) {
2067 struct pp2_buff_inf binf = {
2068 .addr = rte_mbuf_data_iova_default(mbuf),
2069 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
2072 pp2_bpool_put_buff(hif, bpool, &binf);
2073 mrvl_port_bpool_size
2074 [bpool->pp2_id][bpool->id][core_id]++;
2079 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2080 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2081 mbuf->data_len = mbuf->pkt_len;
2082 mbuf->port = q->port_id;
2084 mrvl_desc_to_packet_type_and_offset(&descs[i],
2087 mbuf->l2_len = l3_offset;
2088 mbuf->l3_len = l4_offset - l3_offset;
2090 if (likely(q->cksum_enabled))
2091 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2093 rx_pkts[rx_done++] = mbuf;
2094 q->bytes_recv += mbuf->pkt_len;
2097 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2098 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2100 if (unlikely(num <= q->priv->bpool_min_size ||
2101 (!rx_done && num < q->priv->bpool_init_size))) {
2102 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2104 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
2105 } else if (unlikely(num > q->priv->bpool_max_size)) {
2107 int pkt_to_remove = num - q->priv->bpool_init_size;
2108 struct rte_mbuf *mbuf;
2109 struct pp2_buff_inf buff;
2112 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
2113 bpool->pp2_id, q->priv->ppio->port_id,
2114 bpool->id, pkt_to_remove, num,
2115 q->priv->bpool_init_size);
2117 for (i = 0; i < pkt_to_remove; i++) {
2118 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2121 mbuf = (struct rte_mbuf *)
2122 (cookie_addr_high | buff.cookie);
2123 rte_pktmbuf_free(mbuf);
2125 mrvl_port_bpool_size
2126 [bpool->pp2_id][bpool->id][core_id] -= i;
2128 rte_spinlock_unlock(&q->priv->lock);
2135 * Prepare offload information.
2139 * @param packet_type
2140 * Packet type bitfield.
2142 * Pointer to the pp2_ouq_l3_type structure.
2144 * Pointer to the pp2_outq_l4_type structure.
2145 * @param gen_l3_cksum
2146 * Will be set to 1 in case l3 checksum is computed.
2148 * Will be set to 1 in case l4 checksum is computed.
2151 * 0 on success, negative error value otherwise.
2154 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2155 enum pp2_outq_l3_type *l3_type,
2156 enum pp2_outq_l4_type *l4_type,
2161 * Based on ol_flags prepare information
2162 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2165 if (ol_flags & PKT_TX_IPV4) {
2166 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2167 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2168 } else if (ol_flags & PKT_TX_IPV6) {
2169 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2170 /* no checksum for ipv6 header */
2173 /* if something different then stop processing */
2177 ol_flags &= PKT_TX_L4_MASK;
2178 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2179 ol_flags == PKT_TX_TCP_CKSUM) {
2180 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2182 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2183 ol_flags == PKT_TX_UDP_CKSUM) {
2184 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2187 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2188 /* no checksum for other type */
2196 * Release already sent buffers to bpool (buffer-pool).
2199 * Pointer to the port structure.
2201 * Pointer to the MUSDK hardware interface.
2203 * Pointer to the shadow queue.
2207 * Force releasing packets.
2210 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2211 unsigned int core_id, struct mrvl_shadow_txq *sq,
2214 struct buff_release_entry *entry;
2215 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2218 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2220 sq->num_to_release += nb_done;
2222 if (likely(!force &&
2223 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2226 nb_done = sq->num_to_release;
2227 sq->num_to_release = 0;
2229 for (i = 0; i < nb_done; i++) {
2230 entry = &sq->ent[sq->tail + num];
2231 if (unlikely(!entry->buff.addr)) {
2233 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
2234 sq->tail, (u64)entry->buff.cookie,
2235 (u64)entry->buff.addr);
2240 if (unlikely(!entry->bpool)) {
2241 struct rte_mbuf *mbuf;
2243 mbuf = (struct rte_mbuf *)
2244 (cookie_addr_high | entry->buff.cookie);
2245 rte_pktmbuf_free(mbuf);
2250 mrvl_port_bpool_size
2251 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2253 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2258 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2260 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2267 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2268 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2274 * DPDK callback for transmit.
2277 * Generic pointer transmit queue.
2279 * Packets to transmit.
2281 * Number of packets in array.
2284 * Number of packets successfully transmitted.
2287 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2289 struct mrvl_txq *q = txq;
2290 struct mrvl_shadow_txq *sq;
2291 struct pp2_hif *hif;
2292 struct pp2_ppio_desc descs[nb_pkts];
2293 unsigned int core_id = rte_lcore_id();
2294 int i, ret, bytes_sent = 0;
2295 uint16_t num, sq_free_size;
2298 hif = mrvl_get_hif(q->priv, core_id);
2299 sq = &q->shadow_txqs[core_id];
2301 if (unlikely(!q->priv->ppio || !hif))
2305 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2306 sq, q->queue_id, 0);
2308 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2309 if (unlikely(nb_pkts > sq_free_size)) {
2311 "No room in shadow queue for %d packets! %d packets will be sent.\n",
2312 nb_pkts, sq_free_size);
2313 nb_pkts = sq_free_size;
2316 for (i = 0; i < nb_pkts; i++) {
2317 struct rte_mbuf *mbuf = tx_pkts[i];
2318 int gen_l3_cksum, gen_l4_cksum;
2319 enum pp2_outq_l3_type l3_type;
2320 enum pp2_outq_l4_type l4_type;
2322 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2323 struct rte_mbuf *pref_pkt_hdr;
2325 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2326 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2327 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2330 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2331 sq->ent[sq->head].buff.addr =
2332 rte_mbuf_data_iova_default(mbuf);
2333 sq->ent[sq->head].bpool =
2334 (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
2335 mbuf->refcnt > 1)) ? NULL :
2336 mrvl_port_to_bpool_lookup[mbuf->port];
2337 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2340 pp2_ppio_outq_desc_reset(&descs[i]);
2341 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2342 rte_pktmbuf_iova(mbuf));
2343 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2344 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2345 rte_pktmbuf_pkt_len(mbuf));
2347 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2349 * in case unsupported ol_flags were passed
2350 * do not update descriptor offload information
2352 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2353 &l3_type, &l4_type, &gen_l3_cksum,
2358 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2360 mbuf->l2_len + mbuf->l3_len,
2361 gen_l3_cksum, gen_l4_cksum);
2365 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2366 /* number of packets that were not sent */
2367 if (unlikely(num > nb_pkts)) {
2368 for (i = nb_pkts; i < num; i++) {
2369 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2370 MRVL_PP2_TX_SHADOWQ_MASK;
2371 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2373 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2375 sq->size -= num - nb_pkts;
2378 q->bytes_sent += bytes_sent;
2384 * Initialize packet processor.
2387 * 0 on success, negative error value otherwise.
2392 struct pp2_init_params init_params;
2394 memset(&init_params, 0, sizeof(init_params));
2395 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2396 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2397 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2399 return pp2_init(&init_params);
2403 * Deinitialize packet processor.
2406 * 0 on success, negative error value otherwise.
2409 mrvl_deinit_pp2(void)
2415 * Create private device structure.
2418 * Pointer to the port name passed in the initialization parameters.
2421 * Pointer to the newly allocated private device structure.
2423 static struct mrvl_priv *
2424 mrvl_priv_create(const char *dev_name)
2426 struct pp2_bpool_params bpool_params;
2427 char match[MRVL_MATCH_LEN];
2428 struct mrvl_priv *priv;
2431 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2435 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2436 &priv->pp_id, &priv->ppio_id);
2440 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2441 PP2_BPOOL_NUM_POOLS);
2444 priv->bpool_bit = bpool_bit;
2446 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2448 memset(&bpool_params, 0, sizeof(bpool_params));
2449 bpool_params.match = match;
2450 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2451 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2453 goto out_clear_bpool_bit;
2455 priv->ppio_params.type = PP2_PPIO_T_NIC;
2456 rte_spinlock_init(&priv->lock);
2459 out_clear_bpool_bit:
2460 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2467 * Create device representing Ethernet port.
2470 * Pointer to the port's name.
2473 * 0 on success, negative error value otherwise.
2476 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2478 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2479 struct rte_eth_dev *eth_dev;
2480 struct mrvl_priv *priv;
2483 eth_dev = rte_eth_dev_allocate(name);
2487 priv = mrvl_priv_create(name);
2493 eth_dev->data->mac_addrs =
2494 rte_zmalloc("mac_addrs",
2495 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2496 if (!eth_dev->data->mac_addrs) {
2497 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2502 memset(&req, 0, sizeof(req));
2503 strcpy(req.ifr_name, name);
2504 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2508 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2509 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2511 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2512 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2513 eth_dev->data->kdrv = RTE_KDRV_NONE;
2514 eth_dev->data->dev_private = priv;
2515 eth_dev->device = &vdev->device;
2516 eth_dev->dev_ops = &mrvl_ops;
2520 rte_free(eth_dev->data->mac_addrs);
2522 rte_eth_dev_release_port(eth_dev);
2530 * Cleanup previously created device representing Ethernet port.
2533 * Pointer to the port name.
2536 mrvl_eth_dev_destroy(const char *name)
2538 struct rte_eth_dev *eth_dev;
2539 struct mrvl_priv *priv;
2541 eth_dev = rte_eth_dev_allocated(name);
2545 priv = eth_dev->data->dev_private;
2546 pp2_bpool_deinit(priv->bpool);
2547 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2549 rte_free(eth_dev->data->mac_addrs);
2550 rte_eth_dev_release_port(eth_dev);
2554 * Callback used by rte_kvargs_process() during argument parsing.
2557 * Pointer to the parsed key (unused).
2559 * Pointer to the parsed value.
2561 * Pointer to the extra arguments which contains address of the
2562 * table of pointers to parsed interface names.
2568 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2571 struct mrvl_ifnames *ifnames = extra_args;
2573 ifnames->names[ifnames->idx++] = value;
2579 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2582 mrvl_deinit_hifs(void)
2586 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2588 pp2_hif_deinit(hifs[i]);
2590 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2591 memset(hifs, 0, sizeof(hifs));
2595 * DPDK callback to register the virtual device.
2598 * Pointer to the virtual device.
2601 * 0 on success, negative error value otherwise.
2604 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2606 struct rte_kvargs *kvlist;
2607 struct mrvl_ifnames ifnames;
2609 uint32_t i, ifnum, cfgnum;
2612 params = rte_vdev_device_args(vdev);
2616 kvlist = rte_kvargs_parse(params, valid_args);
2620 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2621 if (ifnum > RTE_DIM(ifnames.names))
2622 goto out_free_kvlist;
2625 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2626 mrvl_get_ifnames, &ifnames);
2630 * The below system initialization should be done only once,
2631 * on the first provided configuration file
2633 if (!mrvl_qos_cfg) {
2634 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2635 RTE_LOG(INFO, PMD, "Parsing config file!\n");
2637 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2638 goto out_free_kvlist;
2639 } else if (cfgnum == 1) {
2640 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2641 mrvl_get_qoscfg, &mrvl_qos_cfg);
2648 RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n");
2650 * ret == -EEXIST is correct, it means DMA
2651 * has been already initialized (by another PMD).
2653 ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2656 goto out_free_kvlist;
2659 "DMA memory has been already initialized by a different driver.\n");
2662 ret = mrvl_init_pp2();
2664 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2665 goto out_deinit_dma;
2668 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2669 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2671 mrvl_lcore_first = RTE_MAX_LCORE;
2672 mrvl_lcore_last = 0;
2675 for (i = 0; i < ifnum; i++) {
2676 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]);
2677 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2681 mrvl_dev_num += ifnum;
2683 rte_kvargs_free(kvlist);
2688 mrvl_eth_dev_destroy(ifnames.names[i]);
2690 if (mrvl_dev_num == 0)
2693 if (mrvl_dev_num == 0)
2694 mv_sys_dma_mem_destroy();
2696 rte_kvargs_free(kvlist);
2702 * DPDK callback to remove virtual device.
2705 * Pointer to the removed virtual device.
2708 * 0 on success, negative error value otherwise.
2711 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2716 name = rte_vdev_device_name(vdev);
2720 RTE_LOG(INFO, PMD, "Removing %s\n", name);
2722 RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */
2723 char ifname[RTE_ETH_NAME_MAX_LEN];
2725 rte_eth_dev_get_name_by_port(i, ifname);
2726 mrvl_eth_dev_destroy(ifname);
2730 if (mrvl_dev_num == 0) {
2731 RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n");
2734 mv_sys_dma_mem_destroy();
2740 static struct rte_vdev_driver pmd_mrvl_drv = {
2741 .probe = rte_pmd_mrvl_probe,
2742 .remove = rte_pmd_mrvl_remove,
2745 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
2746 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);