1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_ethdev_driver.h>
8 #include <rte_kvargs.h>
10 #include <rte_malloc.h>
11 #include <rte_bus_vdev.h>
13 /* Unluckily, container_of is defined by both DPDK and MUSDK,
14 * we'll declare only one version.
16 * Note that it is not used in this PMD anyway.
23 #include <linux/ethtool.h>
24 #include <linux/sockios.h>
26 #include <net/if_arp.h>
27 #include <sys/ioctl.h>
28 #include <sys/socket.h>
30 #include <sys/types.h>
32 #include "mrvl_ethdev.h"
35 /* bitmask with reserved hifs */
36 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
37 /* bitmask with reserved bpools */
38 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
39 /* bitmask with reserved kernel RSS tables */
40 #define MRVL_MUSDK_RSS_RESERVED 0x01
41 /* maximum number of available hifs */
42 #define MRVL_MUSDK_HIFS_MAX 9
45 #define MRVL_MUSDK_PREFETCH_SHIFT 2
47 /* TCAM has 25 entries reserved for uc/mc filter entries */
48 #define MRVL_MAC_ADDRS_MAX 25
49 #define MRVL_MATCH_LEN 16
50 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
51 /* Maximum allowable packet size */
52 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
54 #define MRVL_IFACE_NAME_ARG "iface"
55 #define MRVL_CFG_ARG "cfg"
57 #define MRVL_BURST_SIZE 64
59 #define MRVL_ARP_LENGTH 28
61 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
63 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
64 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
66 /* Memory size (in bytes) for MUSDK dma buffers */
67 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
69 /** Port Rx offload capabilities */
70 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
71 DEV_RX_OFFLOAD_JUMBO_FRAME | \
72 DEV_RX_OFFLOAD_CRC_STRIP | \
73 DEV_RX_OFFLOAD_CHECKSUM)
75 /** Port Tx offloads capabilities */
76 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
77 DEV_TX_OFFLOAD_UDP_CKSUM | \
78 DEV_TX_OFFLOAD_TCP_CKSUM)
80 static const char * const valid_args[] = {
86 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
87 static struct pp2_hif *hifs[RTE_MAX_LCORE];
88 static int used_bpools[PP2_NUM_PKT_PROC] = {
89 MRVL_MUSDK_BPOOLS_RESERVED,
90 MRVL_MUSDK_BPOOLS_RESERVED
93 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
94 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
95 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
100 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
105 * To use buffer harvesting based on loopback port shadow queue structure
106 * was introduced for buffers information bookkeeping.
108 * Before sending the packet, related buffer information (pp2_buff_inf) is
109 * stored in shadow queue. After packet is transmitted no longer used
110 * packet buffer is released back to it's original hardware pool,
111 * on condition it originated from interface.
112 * In case it was generated by application itself i.e: mbuf->port field is
113 * 0xff then its released to software mempool.
115 struct mrvl_shadow_txq {
116 int head; /* write index - used when sending buffers */
117 int tail; /* read index - used when releasing buffers */
118 u16 size; /* queue occupied size */
119 u16 num_to_release; /* number of buffers sent, that can be released */
120 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
124 struct mrvl_priv *priv;
125 struct rte_mempool *mp;
134 struct mrvl_priv *priv;
138 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
139 int tx_deferred_start;
142 static int mrvl_lcore_first;
143 static int mrvl_lcore_last;
144 static int mrvl_dev_num;
146 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
147 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
148 struct pp2_hif *hif, unsigned int core_id,
149 struct mrvl_shadow_txq *sq, int qid, int force);
151 #define MRVL_XSTATS_TBL_ENTRY(name) { \
152 #name, offsetof(struct pp2_ppio_statistics, name), \
153 sizeof(((struct pp2_ppio_statistics *)0)->name) \
156 /* Table with xstats data */
161 } mrvl_xstats_tbl[] = {
162 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
163 MRVL_XSTATS_TBL_ENTRY(rx_packets),
164 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
165 MRVL_XSTATS_TBL_ENTRY(rx_errors),
166 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
167 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
168 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
169 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
170 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
171 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
172 MRVL_XSTATS_TBL_ENTRY(tx_packets),
173 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
174 MRVL_XSTATS_TBL_ENTRY(tx_errors)
178 mrvl_get_bpool_size(int pp2_id, int pool_id)
183 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
184 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
190 mrvl_reserve_bit(int *bitmap, int max)
192 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
203 mrvl_init_hif(int core_id)
205 struct pp2_hif_params params;
206 char match[MRVL_MATCH_LEN];
209 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
211 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
215 snprintf(match, sizeof(match), "hif-%d", ret);
216 memset(¶ms, 0, sizeof(params));
217 params.match = match;
218 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
219 ret = pp2_hif_init(¶ms, &hifs[core_id]);
221 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
228 static inline struct pp2_hif*
229 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
233 if (likely(hifs[core_id] != NULL))
234 return hifs[core_id];
236 rte_spinlock_lock(&priv->lock);
238 ret = mrvl_init_hif(core_id);
240 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
244 if (core_id < mrvl_lcore_first)
245 mrvl_lcore_first = core_id;
247 if (core_id > mrvl_lcore_last)
248 mrvl_lcore_last = core_id;
250 rte_spinlock_unlock(&priv->lock);
252 return hifs[core_id];
256 * Configure rss based on dpdk rss configuration.
259 * Pointer to private structure.
261 * Pointer to RSS configuration.
264 * 0 on success, negative error value otherwise.
267 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
269 if (rss_conf->rss_key)
270 MRVL_LOG(WARNING, "Changing hash key is not supported");
272 if (rss_conf->rss_hf == 0) {
273 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
274 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
275 priv->ppio_params.inqs_params.hash_type =
276 PP2_PPIO_HASH_T_2_TUPLE;
277 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
278 priv->ppio_params.inqs_params.hash_type =
279 PP2_PPIO_HASH_T_5_TUPLE;
280 priv->rss_hf_tcp = 1;
281 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
282 priv->ppio_params.inqs_params.hash_type =
283 PP2_PPIO_HASH_T_5_TUPLE;
284 priv->rss_hf_tcp = 0;
293 * Ethernet device configuration.
295 * Prepare the driver for a given number of TX and RX queues and
299 * Pointer to Ethernet device structure.
302 * 0 on success, negative error value otherwise.
305 mrvl_dev_configure(struct rte_eth_dev *dev)
307 struct mrvl_priv *priv = dev->data->dev_private;
310 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
311 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
312 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
313 dev->data->dev_conf.rxmode.mq_mode);
317 if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
319 "L2 CRC stripping is always enabled in hw");
320 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
323 if (dev->data->dev_conf.rxmode.split_hdr_size) {
324 MRVL_LOG(INFO, "Split headers not supported");
328 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
329 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
330 ETHER_HDR_LEN - ETHER_CRC_LEN;
332 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
333 dev->data->nb_rx_queues);
337 ret = mrvl_configure_txqs(priv, dev->data->port_id,
338 dev->data->nb_tx_queues);
342 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
343 priv->ppio_params.maintain_stats = 1;
344 priv->nb_rx_queues = dev->data->nb_rx_queues;
346 if (dev->data->nb_rx_queues == 1 &&
347 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
348 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
349 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
354 return mrvl_configure_rss(priv,
355 &dev->data->dev_conf.rx_adv_conf.rss_conf);
359 * DPDK callback to change the MTU.
361 * Setting the MTU affects hardware MRU (packets larger than the MRU
365 * Pointer to Ethernet device structure.
370 * 0 on success, negative error value otherwise.
373 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
375 struct mrvl_priv *priv = dev->data->dev_private;
376 /* extra MV_MH_SIZE bytes are required for Marvell tag */
377 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
380 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
386 ret = pp2_ppio_set_mru(priv->ppio, mru);
390 return pp2_ppio_set_mtu(priv->ppio, mtu);
394 * DPDK callback to bring the link up.
397 * Pointer to Ethernet device structure.
400 * 0 on success, negative error value otherwise.
403 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
405 struct mrvl_priv *priv = dev->data->dev_private;
411 ret = pp2_ppio_enable(priv->ppio);
416 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
417 * as pp2_ppio_enable() changes port->t_mode from default 0 to
418 * PP2_TRAFFIC_INGRESS_EGRESS.
420 * Set mtu to default DPDK value here.
422 ret = mrvl_mtu_set(dev, dev->data->mtu);
424 pp2_ppio_disable(priv->ppio);
430 * DPDK callback to bring the link down.
433 * Pointer to Ethernet device structure.
436 * 0 on success, negative error value otherwise.
439 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
441 struct mrvl_priv *priv = dev->data->dev_private;
446 return pp2_ppio_disable(priv->ppio);
450 * DPDK callback to start tx queue.
453 * Pointer to Ethernet device structure.
455 * Transmit queue index.
458 * 0 on success, negative error value otherwise.
461 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
463 struct mrvl_priv *priv = dev->data->dev_private;
469 /* passing 1 enables given tx queue */
470 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
472 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
476 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
482 * DPDK callback to stop tx queue.
485 * Pointer to Ethernet device structure.
487 * Transmit queue index.
490 * 0 on success, negative error value otherwise.
493 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
495 struct mrvl_priv *priv = dev->data->dev_private;
501 /* passing 0 disables given tx queue */
502 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
504 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
508 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
514 * DPDK callback to start the device.
517 * Pointer to Ethernet device structure.
520 * 0 on success, negative errno value on failure.
523 mrvl_dev_start(struct rte_eth_dev *dev)
525 struct mrvl_priv *priv = dev->data->dev_private;
526 char match[MRVL_MATCH_LEN];
527 int ret = 0, i, def_init_size;
529 snprintf(match, sizeof(match), "ppio-%d:%d",
530 priv->pp_id, priv->ppio_id);
531 priv->ppio_params.match = match;
534 * Calculate the minimum bpool size for refill feature as follows:
535 * 2 default burst sizes multiply by number of rx queues.
536 * If the bpool size will be below this value, new buffers will
537 * be added to the pool.
539 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
541 /* In case initial bpool size configured in queues setup is
542 * smaller than minimum size add more buffers
544 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
545 if (priv->bpool_init_size < def_init_size) {
546 int buffs_to_add = def_init_size - priv->bpool_init_size;
548 priv->bpool_init_size += buffs_to_add;
549 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
551 MRVL_LOG(ERR, "Failed to add buffers to bpool");
555 * Calculate the maximum bpool size for refill feature as follows:
556 * maximum number of descriptors in rx queue multiply by number
557 * of rx queues plus minimum bpool size.
558 * In case the bpool size will exceed this value, superfluous buffers
561 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
562 priv->bpool_min_size;
564 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
566 MRVL_LOG(ERR, "Failed to init ppio");
571 * In case there are some some stale uc/mc mac addresses flush them
572 * here. It cannot be done during mrvl_dev_close() as port information
573 * is already gone at that point (due to pp2_ppio_deinit() in
576 if (!priv->uc_mc_flushed) {
577 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
580 "Failed to flush uc/mc filter list");
583 priv->uc_mc_flushed = 1;
586 if (!priv->vlan_flushed) {
587 ret = pp2_ppio_flush_vlan(priv->ppio);
589 MRVL_LOG(ERR, "Failed to flush vlan list");
592 * once pp2_ppio_flush_vlan() is supported jump to out
596 priv->vlan_flushed = 1;
599 /* For default QoS config, don't start classifier. */
601 ret = mrvl_start_qos_mapping(priv);
603 MRVL_LOG(ERR, "Failed to setup QoS mapping");
608 ret = mrvl_dev_set_link_up(dev);
610 MRVL_LOG(ERR, "Failed to set link up");
614 /* start tx queues */
615 for (i = 0; i < dev->data->nb_tx_queues; i++) {
616 struct mrvl_txq *txq = dev->data->tx_queues[i];
618 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
620 if (!txq->tx_deferred_start)
624 * All txqs are started by default. Stop them
625 * so that tx_deferred_start works as expected.
627 ret = mrvl_tx_queue_stop(dev, i);
634 MRVL_LOG(ERR, "Failed to start device");
635 pp2_ppio_deinit(priv->ppio);
640 * Flush receive queues.
643 * Pointer to Ethernet device structure.
646 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
650 MRVL_LOG(INFO, "Flushing rx queues");
651 for (i = 0; i < dev->data->nb_rx_queues; i++) {
655 struct mrvl_rxq *q = dev->data->rx_queues[i];
656 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
658 num = MRVL_PP2_RXD_MAX;
659 ret = pp2_ppio_recv(q->priv->ppio,
660 q->priv->rxq_map[q->queue_id].tc,
661 q->priv->rxq_map[q->queue_id].inq,
662 descs, (uint16_t *)&num);
663 } while (ret == 0 && num);
668 * Flush transmit shadow queues.
671 * Pointer to Ethernet device structure.
674 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
677 struct mrvl_txq *txq;
679 MRVL_LOG(INFO, "Flushing tx shadow queues");
680 for (i = 0; i < dev->data->nb_tx_queues; i++) {
681 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
683 for (j = 0; j < RTE_MAX_LCORE; j++) {
684 struct mrvl_shadow_txq *sq;
689 sq = &txq->shadow_txqs[j];
690 mrvl_free_sent_buffers(txq->priv->ppio,
691 hifs[j], j, sq, txq->queue_id, 1);
692 while (sq->tail != sq->head) {
693 uint64_t addr = cookie_addr_high |
694 sq->ent[sq->tail].buff.cookie;
696 (struct rte_mbuf *)addr);
697 sq->tail = (sq->tail + 1) &
698 MRVL_PP2_TX_SHADOWQ_MASK;
700 memset(sq, 0, sizeof(*sq));
706 * Flush hardware bpool (buffer-pool).
709 * Pointer to Ethernet device structure.
712 mrvl_flush_bpool(struct rte_eth_dev *dev)
714 struct mrvl_priv *priv = dev->data->dev_private;
718 unsigned int core_id = rte_lcore_id();
720 if (core_id == LCORE_ID_ANY)
723 hif = mrvl_get_hif(priv, core_id);
725 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
727 MRVL_LOG(ERR, "Failed to get bpool buffers number");
732 struct pp2_buff_inf inf;
735 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
739 addr = cookie_addr_high | inf.cookie;
740 rte_pktmbuf_free((struct rte_mbuf *)addr);
745 * DPDK callback to stop the device.
748 * Pointer to Ethernet device structure.
751 mrvl_dev_stop(struct rte_eth_dev *dev)
753 struct mrvl_priv *priv = dev->data->dev_private;
755 mrvl_dev_set_link_down(dev);
756 mrvl_flush_rx_queues(dev);
757 mrvl_flush_tx_shadow_queues(dev);
759 pp2_cls_tbl_deinit(priv->cls_tbl);
760 priv->cls_tbl = NULL;
763 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
764 priv->qos_tbl = NULL;
767 pp2_ppio_deinit(priv->ppio);
770 /* policer must be released after ppio deinitialization */
772 pp2_cls_plcr_deinit(priv->policer);
773 priv->policer = NULL;
778 * DPDK callback to close the device.
781 * Pointer to Ethernet device structure.
784 mrvl_dev_close(struct rte_eth_dev *dev)
786 struct mrvl_priv *priv = dev->data->dev_private;
789 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
790 struct pp2_ppio_tc_params *tc_params =
791 &priv->ppio_params.inqs_params.tcs_params[i];
793 if (tc_params->inqs_params) {
794 rte_free(tc_params->inqs_params);
795 tc_params->inqs_params = NULL;
799 mrvl_flush_bpool(dev);
803 * DPDK callback to retrieve physical link information.
806 * Pointer to Ethernet device structure.
807 * @param wait_to_complete
808 * Wait for request completion (ignored).
811 * 0 on success, negative error value otherwise.
814 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
818 * once MUSDK provides necessary API use it here
820 struct mrvl_priv *priv = dev->data->dev_private;
821 struct ethtool_cmd edata;
823 int ret, fd, link_up;
828 edata.cmd = ETHTOOL_GSET;
830 strcpy(req.ifr_name, dev->data->name);
831 req.ifr_data = (void *)&edata;
833 fd = socket(AF_INET, SOCK_DGRAM, 0);
837 ret = ioctl(fd, SIOCETHTOOL, &req);
845 switch (ethtool_cmd_speed(&edata)) {
847 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
850 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
853 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
856 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
859 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
862 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
863 ETH_LINK_HALF_DUPLEX;
864 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
866 pp2_ppio_get_link_state(priv->ppio, &link_up);
867 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
873 * DPDK callback to enable promiscuous mode.
876 * Pointer to Ethernet device structure.
879 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
881 struct mrvl_priv *priv = dev->data->dev_private;
890 ret = pp2_ppio_set_promisc(priv->ppio, 1);
892 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
896 * DPDK callback to enable allmulti mode.
899 * Pointer to Ethernet device structure.
902 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
904 struct mrvl_priv *priv = dev->data->dev_private;
913 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
915 MRVL_LOG(ERR, "Failed enable all-multicast mode");
919 * DPDK callback to disable promiscuous mode.
922 * Pointer to Ethernet device structure.
925 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
927 struct mrvl_priv *priv = dev->data->dev_private;
933 ret = pp2_ppio_set_promisc(priv->ppio, 0);
935 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
939 * DPDK callback to disable allmulticast mode.
942 * Pointer to Ethernet device structure.
945 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
947 struct mrvl_priv *priv = dev->data->dev_private;
953 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
955 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
959 * DPDK callback to remove a MAC address.
962 * Pointer to Ethernet device structure.
967 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
969 struct mrvl_priv *priv = dev->data->dev_private;
970 char buf[ETHER_ADDR_FMT_SIZE];
979 ret = pp2_ppio_remove_mac_addr(priv->ppio,
980 dev->data->mac_addrs[index].addr_bytes);
982 ether_format_addr(buf, sizeof(buf),
983 &dev->data->mac_addrs[index]);
984 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
989 * DPDK callback to add a MAC address.
992 * Pointer to Ethernet device structure.
994 * MAC address to register.
998 * VMDq pool index to associate address with (unused).
1001 * 0 on success, negative error value otherwise.
1004 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1005 uint32_t index, uint32_t vmdq __rte_unused)
1007 struct mrvl_priv *priv = dev->data->dev_private;
1008 char buf[ETHER_ADDR_FMT_SIZE];
1015 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1022 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1023 * parameter uc_filter_max. Maximum number of mc addresses is then
1024 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1027 * If more than uc_filter_max uc addresses were added to filter list
1028 * then NIC will switch to promiscuous mode automatically.
1030 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1031 * were added to filter list then NIC will switch to all-multicast mode
1034 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1036 ether_format_addr(buf, sizeof(buf), mac_addr);
1037 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1045 * DPDK callback to set the primary MAC address.
1048 * Pointer to Ethernet device structure.
1050 * MAC address to register.
1053 * 0 on success, negative error value otherwise.
1056 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1058 struct mrvl_priv *priv = dev->data->dev_private;
1067 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1069 char buf[ETHER_ADDR_FMT_SIZE];
1070 ether_format_addr(buf, sizeof(buf), mac_addr);
1071 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1078 * DPDK callback to get device statistics.
1081 * Pointer to Ethernet device structure.
1083 * Stats structure output buffer.
1086 * 0 on success, negative error value otherwise.
1089 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1091 struct mrvl_priv *priv = dev->data->dev_private;
1092 struct pp2_ppio_statistics ppio_stats;
1093 uint64_t drop_mac = 0;
1094 unsigned int i, idx, ret;
1099 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1100 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1101 struct pp2_ppio_inq_statistics rx_stats;
1106 idx = rxq->queue_id;
1107 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1109 "rx queue %d stats out of range (0 - %d)",
1110 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1114 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1115 priv->rxq_map[idx].tc,
1116 priv->rxq_map[idx].inq,
1118 if (unlikely(ret)) {
1120 "Failed to update rx queue %d stats", idx);
1124 stats->q_ibytes[idx] = rxq->bytes_recv;
1125 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1126 stats->q_errors[idx] = rx_stats.drop_early +
1127 rx_stats.drop_fullq +
1130 stats->ibytes += rxq->bytes_recv;
1131 drop_mac += rxq->drop_mac;
1134 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1135 struct mrvl_txq *txq = dev->data->tx_queues[i];
1136 struct pp2_ppio_outq_statistics tx_stats;
1141 idx = txq->queue_id;
1142 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1144 "tx queue %d stats out of range (0 - %d)",
1145 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1148 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1150 if (unlikely(ret)) {
1152 "Failed to update tx queue %d stats", idx);
1156 stats->q_opackets[idx] = tx_stats.deq_desc;
1157 stats->q_obytes[idx] = txq->bytes_sent;
1158 stats->obytes += txq->bytes_sent;
1161 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1162 if (unlikely(ret)) {
1163 MRVL_LOG(ERR, "Failed to update port statistics");
1167 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1168 stats->opackets += ppio_stats.tx_packets;
1169 stats->imissed += ppio_stats.rx_fullq_dropped +
1170 ppio_stats.rx_bm_dropped +
1171 ppio_stats.rx_early_dropped +
1172 ppio_stats.rx_fifo_dropped +
1173 ppio_stats.rx_cls_dropped;
1174 stats->ierrors = drop_mac;
1180 * DPDK callback to clear device statistics.
1183 * Pointer to Ethernet device structure.
1186 mrvl_stats_reset(struct rte_eth_dev *dev)
1188 struct mrvl_priv *priv = dev->data->dev_private;
1194 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1195 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1197 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1198 priv->rxq_map[i].inq, NULL, 1);
1199 rxq->bytes_recv = 0;
1203 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1204 struct mrvl_txq *txq = dev->data->tx_queues[i];
1206 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1207 txq->bytes_sent = 0;
1210 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1214 * DPDK callback to get extended statistics.
1217 * Pointer to Ethernet device structure.
1219 * Pointer to xstats table.
1221 * Number of entries in xstats table.
1223 * Negative value on error, number of read xstats otherwise.
1226 mrvl_xstats_get(struct rte_eth_dev *dev,
1227 struct rte_eth_xstat *stats, unsigned int n)
1229 struct mrvl_priv *priv = dev->data->dev_private;
1230 struct pp2_ppio_statistics ppio_stats;
1236 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1237 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1240 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1241 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1242 mrvl_xstats_tbl[i].offset);
1243 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1244 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1245 mrvl_xstats_tbl[i].offset);
1250 stats[i].value = val;
1257 * DPDK callback to reset extended statistics.
1260 * Pointer to Ethernet device structure.
1263 mrvl_xstats_reset(struct rte_eth_dev *dev)
1265 mrvl_stats_reset(dev);
1269 * DPDK callback to get extended statistics names.
1271 * @param dev (unused)
1272 * Pointer to Ethernet device structure.
1273 * @param xstats_names
1274 * Pointer to xstats names table.
1276 * Size of the xstats names table.
1278 * Number of read names.
1281 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1282 struct rte_eth_xstat_name *xstats_names,
1288 return RTE_DIM(mrvl_xstats_tbl);
1290 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1291 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s",
1292 mrvl_xstats_tbl[i].name);
1298 * DPDK callback to get information about the device.
1301 * Pointer to Ethernet device structure (unused).
1303 * Info structure output buffer.
1306 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1307 struct rte_eth_dev_info *info)
1309 info->speed_capa = ETH_LINK_SPEED_10M |
1310 ETH_LINK_SPEED_100M |
1314 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1315 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1316 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1318 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1319 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1320 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1322 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1323 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1324 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1326 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1327 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1329 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1330 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1332 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1333 ETH_RSS_NONFRAG_IPV4_TCP |
1334 ETH_RSS_NONFRAG_IPV4_UDP;
1336 /* By default packets are dropped if no descriptors are available */
1337 info->default_rxconf.rx_drop_en = 1;
1338 info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
1340 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1344 * Return supported packet types.
1347 * Pointer to Ethernet device structure (unused).
1350 * Const pointer to the table with supported packet types.
1352 static const uint32_t *
1353 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1355 static const uint32_t ptypes[] = {
1358 RTE_PTYPE_L3_IPV4_EXT,
1359 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1361 RTE_PTYPE_L3_IPV6_EXT,
1362 RTE_PTYPE_L2_ETHER_ARP,
1371 * DPDK callback to get information about specific receive queue.
1374 * Pointer to Ethernet device structure.
1375 * @param rx_queue_id
1376 * Receive queue index.
1378 * Receive queue information structure.
1380 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1381 struct rte_eth_rxq_info *qinfo)
1383 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1384 struct mrvl_priv *priv = dev->data->dev_private;
1385 int inq = priv->rxq_map[rx_queue_id].inq;
1386 int tc = priv->rxq_map[rx_queue_id].tc;
1387 struct pp2_ppio_tc_params *tc_params =
1388 &priv->ppio_params.inqs_params.tcs_params[tc];
1391 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1395 * DPDK callback to get information about specific transmit queue.
1398 * Pointer to Ethernet device structure.
1399 * @param tx_queue_id
1400 * Transmit queue index.
1402 * Transmit queue information structure.
1404 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1405 struct rte_eth_txq_info *qinfo)
1407 struct mrvl_priv *priv = dev->data->dev_private;
1408 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1411 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1412 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1416 * DPDK callback to Configure a VLAN filter.
1419 * Pointer to Ethernet device structure.
1421 * VLAN ID to filter.
1426 * 0 on success, negative error value otherwise.
1429 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1431 struct mrvl_priv *priv = dev->data->dev_private;
1439 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1440 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1444 * Release buffers to hardware bpool (buffer-pool)
1447 * Receive queue pointer.
1449 * Number of buffers to release to bpool.
1452 * 0 on success, negative error value otherwise.
1455 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1457 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1458 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1460 unsigned int core_id;
1461 struct pp2_hif *hif;
1462 struct pp2_bpool *bpool;
1464 core_id = rte_lcore_id();
1465 if (core_id == LCORE_ID_ANY)
1468 hif = mrvl_get_hif(rxq->priv, core_id);
1472 bpool = rxq->priv->bpool;
1474 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1478 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1480 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1482 for (i = 0; i < num; i++) {
1483 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1484 != cookie_addr_high) {
1486 "mbuf virtual addr high 0x%lx out of range",
1487 (uint64_t)mbufs[i] >> 32);
1491 entries[i].buff.addr =
1492 rte_mbuf_data_iova_default(mbufs[i]);
1493 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1494 entries[i].bpool = bpool;
1497 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1498 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1505 for (; i < num; i++)
1506 rte_pktmbuf_free(mbufs[i]);
1512 * DPDK callback to configure the receive queue.
1515 * Pointer to Ethernet device structure.
1519 * Number of descriptors to configure in queue.
1521 * NUMA socket on which memory must be allocated.
1523 * Thresholds parameters.
1525 * Memory pool for buffer allocations.
1528 * 0 on success, negative error value otherwise.
1531 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1532 unsigned int socket,
1533 const struct rte_eth_rxconf *conf,
1534 struct rte_mempool *mp)
1536 struct mrvl_priv *priv = dev->data->dev_private;
1537 struct mrvl_rxq *rxq;
1539 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1543 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1545 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1547 * Unknown TC mapping, mapping will not have a correct queue.
1549 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1550 idx, priv->ppio_id);
1554 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1555 MRVL_PKT_EFFEC_OFFS;
1556 if (min_size < max_rx_pkt_len) {
1558 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.",
1559 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1560 MRVL_PKT_EFFEC_OFFS,
1565 if (dev->data->rx_queues[idx]) {
1566 rte_free(dev->data->rx_queues[idx]);
1567 dev->data->rx_queues[idx] = NULL;
1570 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1576 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1577 rxq->queue_id = idx;
1578 rxq->port_id = dev->data->port_id;
1579 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1581 tc = priv->rxq_map[rxq->queue_id].tc,
1582 inq = priv->rxq_map[rxq->queue_id].inq;
1583 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1586 ret = mrvl_fill_bpool(rxq, desc);
1592 priv->bpool_init_size += desc;
1594 dev->data->rx_queues[idx] = rxq;
1600 * DPDK callback to release the receive queue.
1603 * Generic receive queue pointer.
1606 mrvl_rx_queue_release(void *rxq)
1608 struct mrvl_rxq *q = rxq;
1609 struct pp2_ppio_tc_params *tc_params;
1610 int i, num, tc, inq;
1611 struct pp2_hif *hif;
1612 unsigned int core_id = rte_lcore_id();
1614 if (core_id == LCORE_ID_ANY)
1620 hif = mrvl_get_hif(q->priv, core_id);
1625 tc = q->priv->rxq_map[q->queue_id].tc;
1626 inq = q->priv->rxq_map[q->queue_id].inq;
1627 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1628 num = tc_params->inqs_params[inq].size;
1629 for (i = 0; i < num; i++) {
1630 struct pp2_buff_inf inf;
1633 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1634 addr = cookie_addr_high | inf.cookie;
1635 rte_pktmbuf_free((struct rte_mbuf *)addr);
1642 * DPDK callback to configure the transmit queue.
1645 * Pointer to Ethernet device structure.
1647 * Transmit queue index.
1649 * Number of descriptors to configure in the queue.
1651 * NUMA socket on which memory must be allocated.
1653 * Tx queue configuration parameters.
1656 * 0 on success, negative error value otherwise.
1659 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1660 unsigned int socket,
1661 const struct rte_eth_txconf *conf)
1663 struct mrvl_priv *priv = dev->data->dev_private;
1664 struct mrvl_txq *txq;
1666 if (dev->data->tx_queues[idx]) {
1667 rte_free(dev->data->tx_queues[idx]);
1668 dev->data->tx_queues[idx] = NULL;
1671 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1676 txq->queue_id = idx;
1677 txq->port_id = dev->data->port_id;
1678 txq->tx_deferred_start = conf->tx_deferred_start;
1679 dev->data->tx_queues[idx] = txq;
1681 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1687 * DPDK callback to release the transmit queue.
1690 * Generic transmit queue pointer.
1693 mrvl_tx_queue_release(void *txq)
1695 struct mrvl_txq *q = txq;
1704 * DPDK callback to get flow control configuration.
1707 * Pointer to Ethernet device structure.
1709 * Pointer to the flow control configuration.
1712 * 0 on success, negative error value otherwise.
1715 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1717 struct mrvl_priv *priv = dev->data->dev_private;
1723 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1725 MRVL_LOG(ERR, "Failed to read rx pause state");
1729 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1735 * DPDK callback to set flow control configuration.
1738 * Pointer to Ethernet device structure.
1740 * Pointer to the flow control configuration.
1743 * 0 on success, negative error value otherwise.
1746 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1748 struct mrvl_priv *priv = dev->data->dev_private;
1753 if (fc_conf->high_water ||
1754 fc_conf->low_water ||
1755 fc_conf->pause_time ||
1756 fc_conf->mac_ctrl_frame_fwd ||
1758 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1763 if (fc_conf->mode == RTE_FC_NONE ||
1764 fc_conf->mode == RTE_FC_RX_PAUSE) {
1767 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1768 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1771 "Failed to change flowctrl on RX side");
1780 * Update RSS hash configuration
1783 * Pointer to Ethernet device structure.
1785 * Pointer to RSS configuration.
1788 * 0 on success, negative error value otherwise.
1791 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1792 struct rte_eth_rss_conf *rss_conf)
1794 struct mrvl_priv *priv = dev->data->dev_private;
1799 return mrvl_configure_rss(priv, rss_conf);
1803 * DPDK callback to get RSS hash configuration.
1806 * Pointer to Ethernet device structure.
1808 * Pointer to RSS configuration.
1814 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1815 struct rte_eth_rss_conf *rss_conf)
1817 struct mrvl_priv *priv = dev->data->dev_private;
1818 enum pp2_ppio_hash_type hash_type =
1819 priv->ppio_params.inqs_params.hash_type;
1821 rss_conf->rss_key = NULL;
1823 if (hash_type == PP2_PPIO_HASH_T_NONE)
1824 rss_conf->rss_hf = 0;
1825 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1826 rss_conf->rss_hf = ETH_RSS_IPV4;
1827 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1828 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1829 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1830 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1836 * DPDK callback to get rte_flow callbacks.
1839 * Pointer to the device structure.
1843 * Flow filter operation.
1845 * Pointer to pass the flow ops.
1848 * 0 on success, negative error value otherwise.
1851 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1852 enum rte_filter_type filter_type,
1853 enum rte_filter_op filter_op, void *arg)
1855 switch (filter_type) {
1856 case RTE_ETH_FILTER_GENERIC:
1857 if (filter_op != RTE_ETH_FILTER_GET)
1859 *(const void **)arg = &mrvl_flow_ops;
1862 MRVL_LOG(WARNING, "Filter type (%d) not supported",
1868 static const struct eth_dev_ops mrvl_ops = {
1869 .dev_configure = mrvl_dev_configure,
1870 .dev_start = mrvl_dev_start,
1871 .dev_stop = mrvl_dev_stop,
1872 .dev_set_link_up = mrvl_dev_set_link_up,
1873 .dev_set_link_down = mrvl_dev_set_link_down,
1874 .dev_close = mrvl_dev_close,
1875 .link_update = mrvl_link_update,
1876 .promiscuous_enable = mrvl_promiscuous_enable,
1877 .allmulticast_enable = mrvl_allmulticast_enable,
1878 .promiscuous_disable = mrvl_promiscuous_disable,
1879 .allmulticast_disable = mrvl_allmulticast_disable,
1880 .mac_addr_remove = mrvl_mac_addr_remove,
1881 .mac_addr_add = mrvl_mac_addr_add,
1882 .mac_addr_set = mrvl_mac_addr_set,
1883 .mtu_set = mrvl_mtu_set,
1884 .stats_get = mrvl_stats_get,
1885 .stats_reset = mrvl_stats_reset,
1886 .xstats_get = mrvl_xstats_get,
1887 .xstats_reset = mrvl_xstats_reset,
1888 .xstats_get_names = mrvl_xstats_get_names,
1889 .dev_infos_get = mrvl_dev_infos_get,
1890 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1891 .rxq_info_get = mrvl_rxq_info_get,
1892 .txq_info_get = mrvl_txq_info_get,
1893 .vlan_filter_set = mrvl_vlan_filter_set,
1894 .tx_queue_start = mrvl_tx_queue_start,
1895 .tx_queue_stop = mrvl_tx_queue_stop,
1896 .rx_queue_setup = mrvl_rx_queue_setup,
1897 .rx_queue_release = mrvl_rx_queue_release,
1898 .tx_queue_setup = mrvl_tx_queue_setup,
1899 .tx_queue_release = mrvl_tx_queue_release,
1900 .flow_ctrl_get = mrvl_flow_ctrl_get,
1901 .flow_ctrl_set = mrvl_flow_ctrl_set,
1902 .rss_hash_update = mrvl_rss_hash_update,
1903 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1904 .filter_ctrl = mrvl_eth_filter_ctrl,
1908 * Return packet type information and l3/l4 offsets.
1911 * Pointer to the received packet descriptor.
1918 * Packet type information.
1920 static inline uint64_t
1921 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1922 uint8_t *l3_offset, uint8_t *l4_offset)
1924 enum pp2_inq_l3_type l3_type;
1925 enum pp2_inq_l4_type l4_type;
1926 uint64_t packet_type;
1928 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1929 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1931 packet_type = RTE_PTYPE_L2_ETHER;
1934 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1935 packet_type |= RTE_PTYPE_L3_IPV4;
1937 case PP2_INQ_L3_TYPE_IPV4_OK:
1938 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1940 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1941 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1943 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1944 packet_type |= RTE_PTYPE_L3_IPV6;
1946 case PP2_INQ_L3_TYPE_IPV6_EXT:
1947 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1949 case PP2_INQ_L3_TYPE_ARP:
1950 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1952 * In case of ARP l4_offset is set to wrong value.
1953 * Set it to proper one so that later on mbuf->l3_len can be
1954 * calculated subtracting l4_offset and l3_offset.
1956 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1959 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
1964 case PP2_INQ_L4_TYPE_TCP:
1965 packet_type |= RTE_PTYPE_L4_TCP;
1967 case PP2_INQ_L4_TYPE_UDP:
1968 packet_type |= RTE_PTYPE_L4_UDP;
1971 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
1979 * Get offload information from the received packet descriptor.
1982 * Pointer to the received packet descriptor.
1985 * Mbuf offload flags.
1987 static inline uint64_t
1988 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1991 enum pp2_inq_desc_status status;
1993 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1994 if (unlikely(status != PP2_DESC_ERR_OK))
1995 flags = PKT_RX_IP_CKSUM_BAD;
1997 flags = PKT_RX_IP_CKSUM_GOOD;
1999 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2000 if (unlikely(status != PP2_DESC_ERR_OK))
2001 flags |= PKT_RX_L4_CKSUM_BAD;
2003 flags |= PKT_RX_L4_CKSUM_GOOD;
2009 * DPDK callback for receive.
2012 * Generic pointer to the receive queue.
2014 * Array to store received packets.
2016 * Maximum number of packets in array.
2019 * Number of packets successfully received.
2022 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2024 struct mrvl_rxq *q = rxq;
2025 struct pp2_ppio_desc descs[nb_pkts];
2026 struct pp2_bpool *bpool;
2027 int i, ret, rx_done = 0;
2029 struct pp2_hif *hif;
2030 unsigned int core_id = rte_lcore_id();
2032 hif = mrvl_get_hif(q->priv, core_id);
2034 if (unlikely(!q->priv->ppio || !hif))
2037 bpool = q->priv->bpool;
2039 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2040 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2041 if (unlikely(ret < 0)) {
2042 MRVL_LOG(ERR, "Failed to receive packets");
2045 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2047 for (i = 0; i < nb_pkts; i++) {
2048 struct rte_mbuf *mbuf;
2049 uint8_t l3_offset, l4_offset;
2050 enum pp2_inq_desc_status status;
2053 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2054 struct pp2_ppio_desc *pref_desc;
2057 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2058 pref_addr = cookie_addr_high |
2059 pp2_ppio_inq_desc_get_cookie(pref_desc);
2060 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2061 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2064 addr = cookie_addr_high |
2065 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2066 mbuf = (struct rte_mbuf *)addr;
2067 rte_pktmbuf_reset(mbuf);
2069 /* drop packet in case of mac, overrun or resource error */
2070 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2071 if (unlikely(status != PP2_DESC_ERR_OK)) {
2072 struct pp2_buff_inf binf = {
2073 .addr = rte_mbuf_data_iova_default(mbuf),
2074 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
2077 pp2_bpool_put_buff(hif, bpool, &binf);
2078 mrvl_port_bpool_size
2079 [bpool->pp2_id][bpool->id][core_id]++;
2084 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2085 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2086 mbuf->data_len = mbuf->pkt_len;
2087 mbuf->port = q->port_id;
2089 mrvl_desc_to_packet_type_and_offset(&descs[i],
2092 mbuf->l2_len = l3_offset;
2093 mbuf->l3_len = l4_offset - l3_offset;
2095 if (likely(q->cksum_enabled))
2096 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2098 rx_pkts[rx_done++] = mbuf;
2099 q->bytes_recv += mbuf->pkt_len;
2102 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2103 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2105 if (unlikely(num <= q->priv->bpool_min_size ||
2106 (!rx_done && num < q->priv->bpool_init_size))) {
2107 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2109 MRVL_LOG(ERR, "Failed to fill bpool");
2110 } else if (unlikely(num > q->priv->bpool_max_size)) {
2112 int pkt_to_remove = num - q->priv->bpool_init_size;
2113 struct rte_mbuf *mbuf;
2114 struct pp2_buff_inf buff;
2117 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
2118 bpool->pp2_id, q->priv->ppio->port_id,
2119 bpool->id, pkt_to_remove, num,
2120 q->priv->bpool_init_size);
2122 for (i = 0; i < pkt_to_remove; i++) {
2123 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2126 mbuf = (struct rte_mbuf *)
2127 (cookie_addr_high | buff.cookie);
2128 rte_pktmbuf_free(mbuf);
2130 mrvl_port_bpool_size
2131 [bpool->pp2_id][bpool->id][core_id] -= i;
2133 rte_spinlock_unlock(&q->priv->lock);
2140 * Prepare offload information.
2144 * @param packet_type
2145 * Packet type bitfield.
2147 * Pointer to the pp2_ouq_l3_type structure.
2149 * Pointer to the pp2_outq_l4_type structure.
2150 * @param gen_l3_cksum
2151 * Will be set to 1 in case l3 checksum is computed.
2153 * Will be set to 1 in case l4 checksum is computed.
2156 * 0 on success, negative error value otherwise.
2159 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2160 enum pp2_outq_l3_type *l3_type,
2161 enum pp2_outq_l4_type *l4_type,
2166 * Based on ol_flags prepare information
2167 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2170 if (ol_flags & PKT_TX_IPV4) {
2171 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2172 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2173 } else if (ol_flags & PKT_TX_IPV6) {
2174 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2175 /* no checksum for ipv6 header */
2178 /* if something different then stop processing */
2182 ol_flags &= PKT_TX_L4_MASK;
2183 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2184 ol_flags == PKT_TX_TCP_CKSUM) {
2185 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2187 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2188 ol_flags == PKT_TX_UDP_CKSUM) {
2189 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2192 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2193 /* no checksum for other type */
2201 * Release already sent buffers to bpool (buffer-pool).
2204 * Pointer to the port structure.
2206 * Pointer to the MUSDK hardware interface.
2208 * Pointer to the shadow queue.
2212 * Force releasing packets.
2215 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2216 unsigned int core_id, struct mrvl_shadow_txq *sq,
2219 struct buff_release_entry *entry;
2220 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2223 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2225 sq->num_to_release += nb_done;
2227 if (likely(!force &&
2228 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2231 nb_done = sq->num_to_release;
2232 sq->num_to_release = 0;
2234 for (i = 0; i < nb_done; i++) {
2235 entry = &sq->ent[sq->tail + num];
2236 if (unlikely(!entry->buff.addr)) {
2238 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2239 sq->tail, (u64)entry->buff.cookie,
2240 (u64)entry->buff.addr);
2245 if (unlikely(!entry->bpool)) {
2246 struct rte_mbuf *mbuf;
2248 mbuf = (struct rte_mbuf *)
2249 (cookie_addr_high | entry->buff.cookie);
2250 rte_pktmbuf_free(mbuf);
2255 mrvl_port_bpool_size
2256 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2258 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2263 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2265 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2272 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2273 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2279 * DPDK callback for transmit.
2282 * Generic pointer transmit queue.
2284 * Packets to transmit.
2286 * Number of packets in array.
2289 * Number of packets successfully transmitted.
2292 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2294 struct mrvl_txq *q = txq;
2295 struct mrvl_shadow_txq *sq;
2296 struct pp2_hif *hif;
2297 struct pp2_ppio_desc descs[nb_pkts];
2298 unsigned int core_id = rte_lcore_id();
2299 int i, ret, bytes_sent = 0;
2300 uint16_t num, sq_free_size;
2303 hif = mrvl_get_hif(q->priv, core_id);
2304 sq = &q->shadow_txqs[core_id];
2306 if (unlikely(!q->priv->ppio || !hif))
2310 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2311 sq, q->queue_id, 0);
2313 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2314 if (unlikely(nb_pkts > sq_free_size)) {
2316 "No room in shadow queue for %d packets! %d packets will be sent.",
2317 nb_pkts, sq_free_size);
2318 nb_pkts = sq_free_size;
2321 for (i = 0; i < nb_pkts; i++) {
2322 struct rte_mbuf *mbuf = tx_pkts[i];
2323 int gen_l3_cksum, gen_l4_cksum;
2324 enum pp2_outq_l3_type l3_type;
2325 enum pp2_outq_l4_type l4_type;
2327 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2328 struct rte_mbuf *pref_pkt_hdr;
2330 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2331 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2332 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2335 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2336 sq->ent[sq->head].buff.addr =
2337 rte_mbuf_data_iova_default(mbuf);
2338 sq->ent[sq->head].bpool =
2339 (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
2340 mbuf->refcnt > 1)) ? NULL :
2341 mrvl_port_to_bpool_lookup[mbuf->port];
2342 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2345 pp2_ppio_outq_desc_reset(&descs[i]);
2346 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2347 rte_pktmbuf_iova(mbuf));
2348 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2349 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2350 rte_pktmbuf_pkt_len(mbuf));
2352 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2354 * in case unsupported ol_flags were passed
2355 * do not update descriptor offload information
2357 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2358 &l3_type, &l4_type, &gen_l3_cksum,
2363 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2365 mbuf->l2_len + mbuf->l3_len,
2366 gen_l3_cksum, gen_l4_cksum);
2370 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2371 /* number of packets that were not sent */
2372 if (unlikely(num > nb_pkts)) {
2373 for (i = nb_pkts; i < num; i++) {
2374 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2375 MRVL_PP2_TX_SHADOWQ_MASK;
2376 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2378 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2380 sq->size -= num - nb_pkts;
2383 q->bytes_sent += bytes_sent;
2389 * Initialize packet processor.
2392 * 0 on success, negative error value otherwise.
2397 struct pp2_init_params init_params;
2399 memset(&init_params, 0, sizeof(init_params));
2400 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2401 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2402 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2404 return pp2_init(&init_params);
2408 * Deinitialize packet processor.
2411 * 0 on success, negative error value otherwise.
2414 mrvl_deinit_pp2(void)
2420 * Create private device structure.
2423 * Pointer to the port name passed in the initialization parameters.
2426 * Pointer to the newly allocated private device structure.
2428 static struct mrvl_priv *
2429 mrvl_priv_create(const char *dev_name)
2431 struct pp2_bpool_params bpool_params;
2432 char match[MRVL_MATCH_LEN];
2433 struct mrvl_priv *priv;
2436 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2440 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2441 &priv->pp_id, &priv->ppio_id);
2445 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2446 PP2_BPOOL_NUM_POOLS);
2449 priv->bpool_bit = bpool_bit;
2451 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2453 memset(&bpool_params, 0, sizeof(bpool_params));
2454 bpool_params.match = match;
2455 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2456 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2458 goto out_clear_bpool_bit;
2460 priv->ppio_params.type = PP2_PPIO_T_NIC;
2461 rte_spinlock_init(&priv->lock);
2464 out_clear_bpool_bit:
2465 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2472 * Create device representing Ethernet port.
2475 * Pointer to the port's name.
2478 * 0 on success, negative error value otherwise.
2481 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2483 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2484 struct rte_eth_dev *eth_dev;
2485 struct mrvl_priv *priv;
2488 eth_dev = rte_eth_dev_allocate(name);
2492 priv = mrvl_priv_create(name);
2498 eth_dev->data->mac_addrs =
2499 rte_zmalloc("mac_addrs",
2500 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2501 if (!eth_dev->data->mac_addrs) {
2502 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2507 memset(&req, 0, sizeof(req));
2508 strcpy(req.ifr_name, name);
2509 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2513 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2514 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2516 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2517 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2518 eth_dev->data->kdrv = RTE_KDRV_NONE;
2519 eth_dev->data->dev_private = priv;
2520 eth_dev->device = &vdev->device;
2521 eth_dev->dev_ops = &mrvl_ops;
2523 rte_eth_dev_probing_finish(eth_dev);
2526 rte_free(eth_dev->data->mac_addrs);
2528 rte_eth_dev_release_port(eth_dev);
2536 * Cleanup previously created device representing Ethernet port.
2539 * Pointer to the port name.
2542 mrvl_eth_dev_destroy(const char *name)
2544 struct rte_eth_dev *eth_dev;
2545 struct mrvl_priv *priv;
2547 eth_dev = rte_eth_dev_allocated(name);
2551 priv = eth_dev->data->dev_private;
2552 pp2_bpool_deinit(priv->bpool);
2553 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2555 rte_free(eth_dev->data->mac_addrs);
2556 rte_eth_dev_release_port(eth_dev);
2560 * Callback used by rte_kvargs_process() during argument parsing.
2563 * Pointer to the parsed key (unused).
2565 * Pointer to the parsed value.
2567 * Pointer to the extra arguments which contains address of the
2568 * table of pointers to parsed interface names.
2574 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2577 struct mrvl_ifnames *ifnames = extra_args;
2579 ifnames->names[ifnames->idx++] = value;
2585 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2588 mrvl_deinit_hifs(void)
2592 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2594 pp2_hif_deinit(hifs[i]);
2596 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2597 memset(hifs, 0, sizeof(hifs));
2601 * DPDK callback to register the virtual device.
2604 * Pointer to the virtual device.
2607 * 0 on success, negative error value otherwise.
2610 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2612 struct rte_kvargs *kvlist;
2613 struct mrvl_ifnames ifnames;
2615 uint32_t i, ifnum, cfgnum;
2618 params = rte_vdev_device_args(vdev);
2622 kvlist = rte_kvargs_parse(params, valid_args);
2626 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2627 if (ifnum > RTE_DIM(ifnames.names))
2628 goto out_free_kvlist;
2631 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2632 mrvl_get_ifnames, &ifnames);
2636 * The below system initialization should be done only once,
2637 * on the first provided configuration file
2639 if (!mrvl_qos_cfg) {
2640 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2641 MRVL_LOG(INFO, "Parsing config file!");
2643 MRVL_LOG(ERR, "Cannot handle more than one config file!");
2644 goto out_free_kvlist;
2645 } else if (cfgnum == 1) {
2646 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2647 mrvl_get_qoscfg, &mrvl_qos_cfg);
2654 MRVL_LOG(INFO, "Perform MUSDK initializations");
2656 * ret == -EEXIST is correct, it means DMA
2657 * has been already initialized (by another PMD).
2659 ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2662 goto out_free_kvlist;
2665 "DMA memory has been already initialized by a different driver.");
2668 ret = mrvl_init_pp2();
2670 MRVL_LOG(ERR, "Failed to init PP!");
2671 goto out_deinit_dma;
2674 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2675 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2677 mrvl_lcore_first = RTE_MAX_LCORE;
2678 mrvl_lcore_last = 0;
2681 for (i = 0; i < ifnum; i++) {
2682 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
2683 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2687 mrvl_dev_num += ifnum;
2689 rte_kvargs_free(kvlist);
2694 mrvl_eth_dev_destroy(ifnames.names[i]);
2696 if (mrvl_dev_num == 0)
2699 if (mrvl_dev_num == 0)
2700 mv_sys_dma_mem_destroy();
2702 rte_kvargs_free(kvlist);
2708 * DPDK callback to remove virtual device.
2711 * Pointer to the removed virtual device.
2714 * 0 on success, negative error value otherwise.
2717 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2722 name = rte_vdev_device_name(vdev);
2726 MRVL_LOG(INFO, "Removing %s", name);
2728 RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */
2729 char ifname[RTE_ETH_NAME_MAX_LEN];
2731 rte_eth_dev_get_name_by_port(i, ifname);
2732 mrvl_eth_dev_destroy(ifname);
2736 if (mrvl_dev_num == 0) {
2737 MRVL_LOG(INFO, "Perform MUSDK deinit");
2740 mv_sys_dma_mem_destroy();
2746 static struct rte_vdev_driver pmd_mrvl_drv = {
2747 .probe = rte_pmd_mrvl_probe,
2748 .remove = rte_pmd_mrvl_remove,
2751 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
2752 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
2754 RTE_INIT(mrvl_init_log);
2758 mrvl_logtype = rte_log_register("pmd.net.mvpp2");
2759 if (mrvl_logtype >= 0)
2760 rte_log_set_level(mrvl_logtype, RTE_LOG_NOTICE);