1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_string_fns.h>
8 #include <rte_ethdev_driver.h>
9 #include <rte_kvargs.h>
11 #include <rte_malloc.h>
12 #include <rte_bus_vdev.h>
15 #include <linux/ethtool.h>
16 #include <linux/sockios.h>
18 #include <net/if_arp.h>
19 #include <sys/ioctl.h>
20 #include <sys/socket.h>
22 #include <sys/types.h>
24 #include <rte_mvep_common.h>
25 #include "mrvl_ethdev.h"
27 #include "mrvl_flow.h"
31 /* bitmask with reserved hifs */
32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
33 /* bitmask with reserved bpools */
34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
35 /* bitmask with reserved kernel RSS tables */
36 #define MRVL_MUSDK_RSS_RESERVED 0x01
37 /* maximum number of available hifs */
38 #define MRVL_MUSDK_HIFS_MAX 9
41 #define MRVL_MUSDK_PREFETCH_SHIFT 2
43 /* TCAM has 25 entries reserved for uc/mc filter entries */
44 #define MRVL_MAC_ADDRS_MAX 25
45 #define MRVL_MATCH_LEN 16
46 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
47 /* Maximum allowable packet size */
48 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
50 #define MRVL_IFACE_NAME_ARG "iface"
51 #define MRVL_CFG_ARG "cfg"
53 #define MRVL_BURST_SIZE 64
55 #define MRVL_ARP_LENGTH 28
57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
60 /** Port Rx offload capabilities */
61 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
62 DEV_RX_OFFLOAD_JUMBO_FRAME | \
63 DEV_RX_OFFLOAD_CHECKSUM)
65 /** Port Tx offloads capabilities */
66 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
67 DEV_TX_OFFLOAD_UDP_CKSUM | \
68 DEV_TX_OFFLOAD_TCP_CKSUM | \
69 DEV_TX_OFFLOAD_MULTI_SEGS)
71 static const char * const valid_args[] = {
77 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
78 static struct pp2_hif *hifs[RTE_MAX_LCORE];
79 static int used_bpools[PP2_NUM_PKT_PROC] = {
80 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
83 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
84 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
85 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
88 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
93 * To use buffer harvesting based on loopback port shadow queue structure
94 * was introduced for buffers information bookkeeping.
96 * Before sending the packet, related buffer information (pp2_buff_inf) is
97 * stored in shadow queue. After packet is transmitted no longer used
98 * packet buffer is released back to it's original hardware pool,
99 * on condition it originated from interface.
100 * In case it was generated by application itself i.e: mbuf->port field is
101 * 0xff then its released to software mempool.
103 struct mrvl_shadow_txq {
104 int head; /* write index - used when sending buffers */
105 int tail; /* read index - used when releasing buffers */
106 u16 size; /* queue occupied size */
107 u16 num_to_release; /* number of descriptors sent, that can be
110 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
114 struct mrvl_priv *priv;
115 struct rte_mempool *mp;
124 struct mrvl_priv *priv;
128 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
129 int tx_deferred_start;
132 static int mrvl_lcore_first;
133 static int mrvl_lcore_last;
134 static int mrvl_dev_num;
136 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
137 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
138 struct pp2_hif *hif, unsigned int core_id,
139 struct mrvl_shadow_txq *sq, int qid, int force);
141 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
143 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
145 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev);
146 static void mrvl_deinit_pp2(void);
147 static void mrvl_deinit_hifs(void);
150 #define MRVL_XSTATS_TBL_ENTRY(name) { \
151 #name, offsetof(struct pp2_ppio_statistics, name), \
152 sizeof(((struct pp2_ppio_statistics *)0)->name) \
155 /* Table with xstats data */
160 } mrvl_xstats_tbl[] = {
161 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
162 MRVL_XSTATS_TBL_ENTRY(rx_packets),
163 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
164 MRVL_XSTATS_TBL_ENTRY(rx_errors),
165 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
166 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
167 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
168 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
169 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
170 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
171 MRVL_XSTATS_TBL_ENTRY(tx_packets),
172 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
173 MRVL_XSTATS_TBL_ENTRY(tx_errors)
177 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf)
179 sq->ent[sq->head].buff.cookie = (uint64_t)buf;
180 sq->ent[sq->head].buff.addr = buf ?
181 rte_mbuf_data_iova_default(buf) : 0;
183 sq->ent[sq->head].bpool =
184 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS ||
185 buf->refcnt > 1)) ? NULL :
186 mrvl_port_to_bpool_lookup[buf->port];
188 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
193 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf)
195 pp2_ppio_outq_desc_reset(desc);
196 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf));
197 pp2_ppio_outq_desc_set_pkt_offset(desc, 0);
198 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf));
202 mrvl_get_bpool_size(int pp2_id, int pool_id)
207 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
208 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
214 mrvl_reserve_bit(int *bitmap, int max)
216 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
227 mrvl_init_hif(int core_id)
229 struct pp2_hif_params params;
230 char match[MRVL_MATCH_LEN];
233 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
235 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
239 snprintf(match, sizeof(match), "hif-%d", ret);
240 memset(¶ms, 0, sizeof(params));
241 params.match = match;
242 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
243 ret = pp2_hif_init(¶ms, &hifs[core_id]);
245 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
252 static inline struct pp2_hif*
253 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
257 if (likely(hifs[core_id] != NULL))
258 return hifs[core_id];
260 rte_spinlock_lock(&priv->lock);
262 ret = mrvl_init_hif(core_id);
264 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
268 if (core_id < mrvl_lcore_first)
269 mrvl_lcore_first = core_id;
271 if (core_id > mrvl_lcore_last)
272 mrvl_lcore_last = core_id;
274 rte_spinlock_unlock(&priv->lock);
276 return hifs[core_id];
280 * Set tx burst function according to offload flag
283 * Pointer to Ethernet device structure.
286 mrvl_set_tx_function(struct rte_eth_dev *dev)
288 struct mrvl_priv *priv = dev->data->dev_private;
290 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
291 if (priv->multiseg) {
292 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n");
293 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst;
295 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n");
296 dev->tx_pkt_burst = mrvl_tx_pkt_burst;
301 * Configure rss based on dpdk rss configuration.
304 * Pointer to private structure.
306 * Pointer to RSS configuration.
309 * 0 on success, negative error value otherwise.
312 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
314 if (rss_conf->rss_key)
315 MRVL_LOG(WARNING, "Changing hash key is not supported");
317 if (rss_conf->rss_hf == 0) {
318 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
319 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
320 priv->ppio_params.inqs_params.hash_type =
321 PP2_PPIO_HASH_T_2_TUPLE;
322 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
323 priv->ppio_params.inqs_params.hash_type =
324 PP2_PPIO_HASH_T_5_TUPLE;
325 priv->rss_hf_tcp = 1;
326 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
327 priv->ppio_params.inqs_params.hash_type =
328 PP2_PPIO_HASH_T_5_TUPLE;
329 priv->rss_hf_tcp = 0;
338 * Ethernet device configuration.
340 * Prepare the driver for a given number of TX and RX queues and
344 * Pointer to Ethernet device structure.
347 * 0 on success, negative error value otherwise.
350 mrvl_dev_configure(struct rte_eth_dev *dev)
352 struct mrvl_priv *priv = dev->data->dev_private;
356 MRVL_LOG(INFO, "Device reconfiguration is not supported");
360 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
361 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
362 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
363 dev->data->dev_conf.rxmode.mq_mode);
367 if (dev->data->dev_conf.rxmode.split_hdr_size) {
368 MRVL_LOG(INFO, "Split headers not supported");
372 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
373 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
374 MRVL_PP2_ETH_HDRS_LEN;
376 if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
379 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
380 dev->data->nb_rx_queues);
384 ret = mrvl_configure_txqs(priv, dev->data->port_id,
385 dev->data->nb_tx_queues);
389 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
390 priv->ppio_params.maintain_stats = 1;
391 priv->nb_rx_queues = dev->data->nb_rx_queues;
393 ret = mrvl_tm_init(dev);
397 if (dev->data->nb_rx_queues == 1 &&
398 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
399 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
400 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
405 return mrvl_configure_rss(priv,
406 &dev->data->dev_conf.rx_adv_conf.rss_conf);
410 * DPDK callback to change the MTU.
412 * Setting the MTU affects hardware MRU (packets larger than the MRU
416 * Pointer to Ethernet device structure.
421 * 0 on success, negative error value otherwise.
424 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
426 struct mrvl_priv *priv = dev->data->dev_private;
428 uint16_t mbuf_data_size = 0; /* SW buffer size */
431 mru = MRVL_PP2_MTU_TO_MRU(mtu);
433 * min_rx_buf_size is equal to mbuf data size
434 * if pmd didn't set it differently
436 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
438 * - setting mru greater than the mbuf size resulting in
439 * hw and sw buffer size mismatch
440 * - setting mtu that requires the support of scattered packets
441 * when this feature has not been enabled/supported so far
442 * (TODO check scattered_rx flag here once scattered RX is supported).
444 if (mru + MRVL_PKT_OFFS > mbuf_data_size) {
445 mru = mbuf_data_size - MRVL_PKT_OFFS;
446 mtu = MRVL_PP2_MRU_TO_MTU(mru);
447 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted "
448 "by current mbuf size: %u. Set MTU to %u, MRU to %u",
449 mbuf_data_size, mtu, mru);
452 if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) {
453 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru);
457 dev->data->mtu = mtu;
458 dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE;
463 ret = pp2_ppio_set_mru(priv->ppio, mru);
465 MRVL_LOG(ERR, "Failed to change MRU");
469 ret = pp2_ppio_set_mtu(priv->ppio, mtu);
471 MRVL_LOG(ERR, "Failed to change MTU");
479 * DPDK callback to bring the link up.
482 * Pointer to Ethernet device structure.
485 * 0 on success, negative error value otherwise.
488 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
490 struct mrvl_priv *priv = dev->data->dev_private;
496 ret = pp2_ppio_enable(priv->ppio);
501 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
502 * as pp2_ppio_enable() changes port->t_mode from default 0 to
503 * PP2_TRAFFIC_INGRESS_EGRESS.
505 * Set mtu to default DPDK value here.
507 ret = mrvl_mtu_set(dev, dev->data->mtu);
509 pp2_ppio_disable(priv->ppio);
515 * DPDK callback to bring the link down.
518 * Pointer to Ethernet device structure.
521 * 0 on success, negative error value otherwise.
524 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
526 struct mrvl_priv *priv = dev->data->dev_private;
531 return pp2_ppio_disable(priv->ppio);
535 * DPDK callback to start tx queue.
538 * Pointer to Ethernet device structure.
540 * Transmit queue index.
543 * 0 on success, negative error value otherwise.
546 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
548 struct mrvl_priv *priv = dev->data->dev_private;
554 /* passing 1 enables given tx queue */
555 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
557 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
561 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
567 * DPDK callback to stop tx queue.
570 * Pointer to Ethernet device structure.
572 * Transmit queue index.
575 * 0 on success, negative error value otherwise.
578 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
580 struct mrvl_priv *priv = dev->data->dev_private;
586 /* passing 0 disables given tx queue */
587 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
589 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
593 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
599 * DPDK callback to start the device.
602 * Pointer to Ethernet device structure.
605 * 0 on success, negative errno value on failure.
608 mrvl_dev_start(struct rte_eth_dev *dev)
610 struct mrvl_priv *priv = dev->data->dev_private;
611 char match[MRVL_MATCH_LEN];
612 int ret = 0, i, def_init_size;
615 return mrvl_dev_set_link_up(dev);
617 snprintf(match, sizeof(match), "ppio-%d:%d",
618 priv->pp_id, priv->ppio_id);
619 priv->ppio_params.match = match;
622 * Calculate the minimum bpool size for refill feature as follows:
623 * 2 default burst sizes multiply by number of rx queues.
624 * If the bpool size will be below this value, new buffers will
625 * be added to the pool.
627 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
629 /* In case initial bpool size configured in queues setup is
630 * smaller than minimum size add more buffers
632 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
633 if (priv->bpool_init_size < def_init_size) {
634 int buffs_to_add = def_init_size - priv->bpool_init_size;
636 priv->bpool_init_size += buffs_to_add;
637 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
639 MRVL_LOG(ERR, "Failed to add buffers to bpool");
643 * Calculate the maximum bpool size for refill feature as follows:
644 * maximum number of descriptors in rx queue multiply by number
645 * of rx queues plus minimum bpool size.
646 * In case the bpool size will exceed this value, superfluous buffers
649 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
650 priv->bpool_min_size;
652 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
654 MRVL_LOG(ERR, "Failed to init ppio");
659 * In case there are some some stale uc/mc mac addresses flush them
660 * here. It cannot be done during mrvl_dev_close() as port information
661 * is already gone at that point (due to pp2_ppio_deinit() in
664 if (!priv->uc_mc_flushed) {
665 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
668 "Failed to flush uc/mc filter list");
671 priv->uc_mc_flushed = 1;
674 if (!priv->vlan_flushed) {
675 ret = pp2_ppio_flush_vlan(priv->ppio);
677 MRVL_LOG(ERR, "Failed to flush vlan list");
680 * once pp2_ppio_flush_vlan() is supported jump to out
684 priv->vlan_flushed = 1;
686 ret = mrvl_mtu_set(dev, dev->data->mtu);
688 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu);
690 /* For default QoS config, don't start classifier. */
692 mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) {
693 ret = mrvl_start_qos_mapping(priv);
695 MRVL_LOG(ERR, "Failed to setup QoS mapping");
700 ret = mrvl_dev_set_link_up(dev);
702 MRVL_LOG(ERR, "Failed to set link up");
706 /* start tx queues */
707 for (i = 0; i < dev->data->nb_tx_queues; i++) {
708 struct mrvl_txq *txq = dev->data->tx_queues[i];
710 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
712 if (!txq->tx_deferred_start)
716 * All txqs are started by default. Stop them
717 * so that tx_deferred_start works as expected.
719 ret = mrvl_tx_queue_stop(dev, i);
726 mrvl_set_tx_function(dev);
730 MRVL_LOG(ERR, "Failed to start device");
731 pp2_ppio_deinit(priv->ppio);
736 * Flush receive queues.
739 * Pointer to Ethernet device structure.
742 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
746 MRVL_LOG(INFO, "Flushing rx queues");
747 for (i = 0; i < dev->data->nb_rx_queues; i++) {
751 struct mrvl_rxq *q = dev->data->rx_queues[i];
752 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
754 num = MRVL_PP2_RXD_MAX;
755 ret = pp2_ppio_recv(q->priv->ppio,
756 q->priv->rxq_map[q->queue_id].tc,
757 q->priv->rxq_map[q->queue_id].inq,
758 descs, (uint16_t *)&num);
759 } while (ret == 0 && num);
764 * Flush transmit shadow queues.
767 * Pointer to Ethernet device structure.
770 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
773 struct mrvl_txq *txq;
775 MRVL_LOG(INFO, "Flushing tx shadow queues");
776 for (i = 0; i < dev->data->nb_tx_queues; i++) {
777 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
779 for (j = 0; j < RTE_MAX_LCORE; j++) {
780 struct mrvl_shadow_txq *sq;
785 sq = &txq->shadow_txqs[j];
786 mrvl_free_sent_buffers(txq->priv->ppio,
787 hifs[j], j, sq, txq->queue_id, 1);
788 while (sq->tail != sq->head) {
789 uint64_t addr = cookie_addr_high |
790 sq->ent[sq->tail].buff.cookie;
792 (struct rte_mbuf *)addr);
793 sq->tail = (sq->tail + 1) &
794 MRVL_PP2_TX_SHADOWQ_MASK;
796 memset(sq, 0, sizeof(*sq));
802 * Flush hardware bpool (buffer-pool).
805 * Pointer to Ethernet device structure.
808 mrvl_flush_bpool(struct rte_eth_dev *dev)
810 struct mrvl_priv *priv = dev->data->dev_private;
814 unsigned int core_id = rte_lcore_id();
816 if (core_id == LCORE_ID_ANY)
817 core_id = rte_get_master_lcore();
819 hif = mrvl_get_hif(priv, core_id);
821 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
823 MRVL_LOG(ERR, "Failed to get bpool buffers number");
828 struct pp2_buff_inf inf;
831 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
835 addr = cookie_addr_high | inf.cookie;
836 rte_pktmbuf_free((struct rte_mbuf *)addr);
841 * DPDK callback to stop the device.
844 * Pointer to Ethernet device structure.
847 mrvl_dev_stop(struct rte_eth_dev *dev)
849 mrvl_dev_set_link_down(dev);
853 * DPDK callback to close the device.
856 * Pointer to Ethernet device structure.
859 mrvl_dev_close(struct rte_eth_dev *dev)
861 struct mrvl_priv *priv = dev->data->dev_private;
864 mrvl_flush_rx_queues(dev);
865 mrvl_flush_tx_shadow_queues(dev);
866 mrvl_flow_deinit(dev);
867 mrvl_mtr_deinit(dev);
869 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
870 struct pp2_ppio_tc_params *tc_params =
871 &priv->ppio_params.inqs_params.tcs_params[i];
873 if (tc_params->inqs_params) {
874 rte_free(tc_params->inqs_params);
875 tc_params->inqs_params = NULL;
880 pp2_cls_tbl_deinit(priv->cls_tbl);
881 priv->cls_tbl = NULL;
885 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
886 priv->qos_tbl = NULL;
889 mrvl_flush_bpool(dev);
893 pp2_ppio_deinit(priv->ppio);
897 /* policer must be released after ppio deinitialization */
898 if (priv->default_policer) {
899 pp2_cls_plcr_deinit(priv->default_policer);
900 priv->default_policer = NULL;
905 pp2_bpool_deinit(priv->bpool);
906 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
912 if (mrvl_dev_num == 0) {
913 MRVL_LOG(INFO, "Perform MUSDK deinit");
916 rte_mvep_deinit(MVEP_MOD_T_PP2);
921 * DPDK callback to retrieve physical link information.
924 * Pointer to Ethernet device structure.
925 * @param wait_to_complete
926 * Wait for request completion (ignored).
929 * 0 on success, negative error value otherwise.
932 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
936 * once MUSDK provides necessary API use it here
938 struct mrvl_priv *priv = dev->data->dev_private;
939 struct ethtool_cmd edata;
941 int ret, fd, link_up;
946 edata.cmd = ETHTOOL_GSET;
948 strcpy(req.ifr_name, dev->data->name);
949 req.ifr_data = (void *)&edata;
951 fd = socket(AF_INET, SOCK_DGRAM, 0);
955 ret = ioctl(fd, SIOCETHTOOL, &req);
963 switch (ethtool_cmd_speed(&edata)) {
965 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
968 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
971 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
974 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
977 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
980 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
981 ETH_LINK_HALF_DUPLEX;
982 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
984 pp2_ppio_get_link_state(priv->ppio, &link_up);
985 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
991 * DPDK callback to enable promiscuous mode.
994 * Pointer to Ethernet device structure.
997 * 0 on success, negative error value otherwise.
1000 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
1002 struct mrvl_priv *priv = dev->data->dev_private;
1011 ret = pp2_ppio_set_promisc(priv->ppio, 1);
1013 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
1021 * DPDK callback to enable allmulti mode.
1024 * Pointer to Ethernet device structure.
1027 * 0 on success, negative error value otherwise.
1030 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
1032 struct mrvl_priv *priv = dev->data->dev_private;
1041 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
1043 MRVL_LOG(ERR, "Failed enable all-multicast mode");
1051 * DPDK callback to disable promiscuous mode.
1054 * Pointer to Ethernet device structure.
1057 * 0 on success, negative error value otherwise.
1060 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
1062 struct mrvl_priv *priv = dev->data->dev_private;
1068 ret = pp2_ppio_set_promisc(priv->ppio, 0);
1070 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
1078 * DPDK callback to disable allmulticast mode.
1081 * Pointer to Ethernet device structure.
1084 * 0 on success, negative error value otherwise.
1087 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
1089 struct mrvl_priv *priv = dev->data->dev_private;
1095 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
1097 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
1105 * DPDK callback to remove a MAC address.
1108 * Pointer to Ethernet device structure.
1110 * MAC address index.
1113 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
1115 struct mrvl_priv *priv = dev->data->dev_private;
1116 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1125 ret = pp2_ppio_remove_mac_addr(priv->ppio,
1126 dev->data->mac_addrs[index].addr_bytes);
1128 rte_ether_format_addr(buf, sizeof(buf),
1129 &dev->data->mac_addrs[index]);
1130 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
1135 * DPDK callback to add a MAC address.
1138 * Pointer to Ethernet device structure.
1140 * MAC address to register.
1142 * MAC address index.
1144 * VMDq pool index to associate address with (unused).
1147 * 0 on success, negative error value otherwise.
1150 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1151 uint32_t index, uint32_t vmdq __rte_unused)
1153 struct mrvl_priv *priv = dev->data->dev_private;
1154 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1161 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1168 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1169 * parameter uc_filter_max. Maximum number of mc addresses is then
1170 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1173 * If more than uc_filter_max uc addresses were added to filter list
1174 * then NIC will switch to promiscuous mode automatically.
1176 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1177 * were added to filter list then NIC will switch to all-multicast mode
1180 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1182 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1183 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1191 * DPDK callback to set the primary MAC address.
1194 * Pointer to Ethernet device structure.
1196 * MAC address to register.
1199 * 0 on success, negative error value otherwise.
1202 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1204 struct mrvl_priv *priv = dev->data->dev_private;
1213 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1215 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1216 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1217 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1224 * DPDK callback to get device statistics.
1227 * Pointer to Ethernet device structure.
1229 * Stats structure output buffer.
1232 * 0 on success, negative error value otherwise.
1235 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1237 struct mrvl_priv *priv = dev->data->dev_private;
1238 struct pp2_ppio_statistics ppio_stats;
1239 uint64_t drop_mac = 0;
1240 unsigned int i, idx, ret;
1245 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1246 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1247 struct pp2_ppio_inq_statistics rx_stats;
1252 idx = rxq->queue_id;
1253 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1255 "rx queue %d stats out of range (0 - %d)",
1256 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1260 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1261 priv->rxq_map[idx].tc,
1262 priv->rxq_map[idx].inq,
1264 if (unlikely(ret)) {
1266 "Failed to update rx queue %d stats", idx);
1270 stats->q_ibytes[idx] = rxq->bytes_recv;
1271 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1272 stats->q_errors[idx] = rx_stats.drop_early +
1273 rx_stats.drop_fullq +
1276 stats->ibytes += rxq->bytes_recv;
1277 drop_mac += rxq->drop_mac;
1280 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1281 struct mrvl_txq *txq = dev->data->tx_queues[i];
1282 struct pp2_ppio_outq_statistics tx_stats;
1287 idx = txq->queue_id;
1288 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1290 "tx queue %d stats out of range (0 - %d)",
1291 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1294 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1296 if (unlikely(ret)) {
1298 "Failed to update tx queue %d stats", idx);
1302 stats->q_opackets[idx] = tx_stats.deq_desc;
1303 stats->q_obytes[idx] = txq->bytes_sent;
1304 stats->obytes += txq->bytes_sent;
1307 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1308 if (unlikely(ret)) {
1309 MRVL_LOG(ERR, "Failed to update port statistics");
1313 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1314 stats->opackets += ppio_stats.tx_packets;
1315 stats->imissed += ppio_stats.rx_fullq_dropped +
1316 ppio_stats.rx_bm_dropped +
1317 ppio_stats.rx_early_dropped +
1318 ppio_stats.rx_fifo_dropped +
1319 ppio_stats.rx_cls_dropped;
1320 stats->ierrors = drop_mac;
1326 * DPDK callback to clear device statistics.
1329 * Pointer to Ethernet device structure.
1332 * 0 on success, negative error value otherwise.
1335 mrvl_stats_reset(struct rte_eth_dev *dev)
1337 struct mrvl_priv *priv = dev->data->dev_private;
1343 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1344 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1346 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1347 priv->rxq_map[i].inq, NULL, 1);
1348 rxq->bytes_recv = 0;
1352 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1353 struct mrvl_txq *txq = dev->data->tx_queues[i];
1355 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1356 txq->bytes_sent = 0;
1359 return pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1363 * DPDK callback to get extended statistics.
1366 * Pointer to Ethernet device structure.
1368 * Pointer to xstats table.
1370 * Number of entries in xstats table.
1372 * Negative value on error, number of read xstats otherwise.
1375 mrvl_xstats_get(struct rte_eth_dev *dev,
1376 struct rte_eth_xstat *stats, unsigned int n)
1378 struct mrvl_priv *priv = dev->data->dev_private;
1379 struct pp2_ppio_statistics ppio_stats;
1385 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1386 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1389 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1390 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1391 mrvl_xstats_tbl[i].offset);
1392 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1393 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1394 mrvl_xstats_tbl[i].offset);
1399 stats[i].value = val;
1406 * DPDK callback to reset extended statistics.
1409 * Pointer to Ethernet device structure.
1412 * 0 on success, negative error value otherwise.
1415 mrvl_xstats_reset(struct rte_eth_dev *dev)
1417 return mrvl_stats_reset(dev);
1421 * DPDK callback to get extended statistics names.
1423 * @param dev (unused)
1424 * Pointer to Ethernet device structure.
1425 * @param xstats_names
1426 * Pointer to xstats names table.
1428 * Size of the xstats names table.
1430 * Number of read names.
1433 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1434 struct rte_eth_xstat_name *xstats_names,
1440 return RTE_DIM(mrvl_xstats_tbl);
1442 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1443 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name,
1444 RTE_ETH_XSTATS_NAME_SIZE);
1450 * DPDK callback to get information about the device.
1453 * Pointer to Ethernet device structure (unused).
1455 * Info structure output buffer.
1458 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1459 struct rte_eth_dev_info *info)
1461 info->speed_capa = ETH_LINK_SPEED_10M |
1462 ETH_LINK_SPEED_100M |
1466 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1467 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1468 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1470 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1471 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1472 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1474 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1475 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1476 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1478 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1479 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1481 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1482 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1484 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1485 ETH_RSS_NONFRAG_IPV4_TCP |
1486 ETH_RSS_NONFRAG_IPV4_UDP;
1488 /* By default packets are dropped if no descriptors are available */
1489 info->default_rxconf.rx_drop_en = 1;
1491 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1497 * Return supported packet types.
1500 * Pointer to Ethernet device structure (unused).
1503 * Const pointer to the table with supported packet types.
1505 static const uint32_t *
1506 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1508 static const uint32_t ptypes[] = {
1510 RTE_PTYPE_L2_ETHER_VLAN,
1511 RTE_PTYPE_L2_ETHER_QINQ,
1513 RTE_PTYPE_L3_IPV4_EXT,
1514 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1516 RTE_PTYPE_L3_IPV6_EXT,
1517 RTE_PTYPE_L2_ETHER_ARP,
1526 * DPDK callback to get information about specific receive queue.
1529 * Pointer to Ethernet device structure.
1530 * @param rx_queue_id
1531 * Receive queue index.
1533 * Receive queue information structure.
1535 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1536 struct rte_eth_rxq_info *qinfo)
1538 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1539 struct mrvl_priv *priv = dev->data->dev_private;
1540 int inq = priv->rxq_map[rx_queue_id].inq;
1541 int tc = priv->rxq_map[rx_queue_id].tc;
1542 struct pp2_ppio_tc_params *tc_params =
1543 &priv->ppio_params.inqs_params.tcs_params[tc];
1546 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1550 * DPDK callback to get information about specific transmit queue.
1553 * Pointer to Ethernet device structure.
1554 * @param tx_queue_id
1555 * Transmit queue index.
1557 * Transmit queue information structure.
1559 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1560 struct rte_eth_txq_info *qinfo)
1562 struct mrvl_priv *priv = dev->data->dev_private;
1563 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1566 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1567 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1571 * DPDK callback to Configure a VLAN filter.
1574 * Pointer to Ethernet device structure.
1576 * VLAN ID to filter.
1581 * 0 on success, negative error value otherwise.
1584 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1586 struct mrvl_priv *priv = dev->data->dev_private;
1594 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1595 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1599 * Release buffers to hardware bpool (buffer-pool)
1602 * Receive queue pointer.
1604 * Number of buffers to release to bpool.
1607 * 0 on success, negative error value otherwise.
1610 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1612 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1613 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1615 unsigned int core_id;
1616 struct pp2_hif *hif;
1617 struct pp2_bpool *bpool;
1619 core_id = rte_lcore_id();
1620 if (core_id == LCORE_ID_ANY)
1621 core_id = rte_get_master_lcore();
1623 hif = mrvl_get_hif(rxq->priv, core_id);
1627 bpool = rxq->priv->bpool;
1629 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1633 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1635 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1637 for (i = 0; i < num; i++) {
1638 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1639 != cookie_addr_high) {
1641 "mbuf virtual addr high 0x%lx out of range",
1642 (uint64_t)mbufs[i] >> 32);
1646 entries[i].buff.addr =
1647 rte_mbuf_data_iova_default(mbufs[i]);
1648 entries[i].buff.cookie = (uint64_t)mbufs[i];
1649 entries[i].bpool = bpool;
1652 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1653 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1660 for (; i < num; i++)
1661 rte_pktmbuf_free(mbufs[i]);
1667 * DPDK callback to configure the receive queue.
1670 * Pointer to Ethernet device structure.
1674 * Number of descriptors to configure in queue.
1676 * NUMA socket on which memory must be allocated.
1678 * Thresholds parameters.
1680 * Memory pool for buffer allocations.
1683 * 0 on success, negative error value otherwise.
1686 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1687 unsigned int socket,
1688 const struct rte_eth_rxconf *conf,
1689 struct rte_mempool *mp)
1691 struct mrvl_priv *priv = dev->data->dev_private;
1692 struct mrvl_rxq *rxq;
1693 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp);
1694 uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1698 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1700 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1702 * Unknown TC mapping, mapping will not have a correct queue.
1704 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1705 idx, priv->ppio_id);
1709 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS;
1710 if (frame_size < max_rx_pkt_len) {
1712 "Mbuf size must be increased to %u bytes to hold up "
1713 "to %u bytes of data.",
1714 buf_size + max_rx_pkt_len - frame_size,
1716 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1717 MRVL_LOG(INFO, "Setting max rx pkt len to %u",
1718 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1721 if (dev->data->rx_queues[idx]) {
1722 rte_free(dev->data->rx_queues[idx]);
1723 dev->data->rx_queues[idx] = NULL;
1726 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1732 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1733 rxq->queue_id = idx;
1734 rxq->port_id = dev->data->port_id;
1735 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1737 tc = priv->rxq_map[rxq->queue_id].tc,
1738 inq = priv->rxq_map[rxq->queue_id].inq;
1739 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1742 ret = mrvl_fill_bpool(rxq, desc);
1748 priv->bpool_init_size += desc;
1750 dev->data->rx_queues[idx] = rxq;
1756 * DPDK callback to release the receive queue.
1759 * Generic receive queue pointer.
1762 mrvl_rx_queue_release(void *rxq)
1764 struct mrvl_rxq *q = rxq;
1765 struct pp2_ppio_tc_params *tc_params;
1766 int i, num, tc, inq;
1767 struct pp2_hif *hif;
1768 unsigned int core_id = rte_lcore_id();
1770 if (core_id == LCORE_ID_ANY)
1771 core_id = rte_get_master_lcore();
1776 hif = mrvl_get_hif(q->priv, core_id);
1781 tc = q->priv->rxq_map[q->queue_id].tc;
1782 inq = q->priv->rxq_map[q->queue_id].inq;
1783 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1784 num = tc_params->inqs_params[inq].size;
1785 for (i = 0; i < num; i++) {
1786 struct pp2_buff_inf inf;
1789 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1790 addr = cookie_addr_high | inf.cookie;
1791 rte_pktmbuf_free((struct rte_mbuf *)addr);
1798 * DPDK callback to configure the transmit queue.
1801 * Pointer to Ethernet device structure.
1803 * Transmit queue index.
1805 * Number of descriptors to configure in the queue.
1807 * NUMA socket on which memory must be allocated.
1809 * Tx queue configuration parameters.
1812 * 0 on success, negative error value otherwise.
1815 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1816 unsigned int socket,
1817 const struct rte_eth_txconf *conf)
1819 struct mrvl_priv *priv = dev->data->dev_private;
1820 struct mrvl_txq *txq;
1822 if (dev->data->tx_queues[idx]) {
1823 rte_free(dev->data->tx_queues[idx]);
1824 dev->data->tx_queues[idx] = NULL;
1827 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1832 txq->queue_id = idx;
1833 txq->port_id = dev->data->port_id;
1834 txq->tx_deferred_start = conf->tx_deferred_start;
1835 dev->data->tx_queues[idx] = txq;
1837 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1843 * DPDK callback to release the transmit queue.
1846 * Generic transmit queue pointer.
1849 mrvl_tx_queue_release(void *txq)
1851 struct mrvl_txq *q = txq;
1860 * DPDK callback to get flow control configuration.
1863 * Pointer to Ethernet device structure.
1865 * Pointer to the flow control configuration.
1868 * 0 on success, negative error value otherwise.
1871 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1873 struct mrvl_priv *priv = dev->data->dev_private;
1879 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1881 MRVL_LOG(ERR, "Failed to read rx pause state");
1885 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1891 * DPDK callback to set flow control configuration.
1894 * Pointer to Ethernet device structure.
1896 * Pointer to the flow control configuration.
1899 * 0 on success, negative error value otherwise.
1902 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1904 struct mrvl_priv *priv = dev->data->dev_private;
1909 if (fc_conf->high_water ||
1910 fc_conf->low_water ||
1911 fc_conf->pause_time ||
1912 fc_conf->mac_ctrl_frame_fwd ||
1914 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1919 if (fc_conf->mode == RTE_FC_NONE ||
1920 fc_conf->mode == RTE_FC_RX_PAUSE) {
1923 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1924 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1927 "Failed to change flowctrl on RX side");
1936 * Update RSS hash configuration
1939 * Pointer to Ethernet device structure.
1941 * Pointer to RSS configuration.
1944 * 0 on success, negative error value otherwise.
1947 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1948 struct rte_eth_rss_conf *rss_conf)
1950 struct mrvl_priv *priv = dev->data->dev_private;
1955 return mrvl_configure_rss(priv, rss_conf);
1959 * DPDK callback to get RSS hash configuration.
1962 * Pointer to Ethernet device structure.
1964 * Pointer to RSS configuration.
1970 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1971 struct rte_eth_rss_conf *rss_conf)
1973 struct mrvl_priv *priv = dev->data->dev_private;
1974 enum pp2_ppio_hash_type hash_type =
1975 priv->ppio_params.inqs_params.hash_type;
1977 rss_conf->rss_key = NULL;
1979 if (hash_type == PP2_PPIO_HASH_T_NONE)
1980 rss_conf->rss_hf = 0;
1981 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1982 rss_conf->rss_hf = ETH_RSS_IPV4;
1983 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1984 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1985 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1986 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1992 * DPDK callback to get rte_flow callbacks.
1995 * Pointer to the device structure.
1999 * Flow filter operation.
2001 * Pointer to pass the flow ops.
2004 * 0 on success, negative error value otherwise.
2007 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
2008 enum rte_filter_type filter_type,
2009 enum rte_filter_op filter_op, void *arg)
2011 switch (filter_type) {
2012 case RTE_ETH_FILTER_GENERIC:
2013 if (filter_op != RTE_ETH_FILTER_GET)
2015 *(const void **)arg = &mrvl_flow_ops;
2018 MRVL_LOG(WARNING, "Filter type (%d) not supported",
2025 * DPDK callback to get rte_mtr callbacks.
2028 * Pointer to the device structure.
2030 * Pointer to pass the mtr ops.
2036 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2038 *(const void **)ops = &mrvl_mtr_ops;
2044 * DPDK callback to get rte_tm callbacks.
2047 * Pointer to the device structure.
2049 * Pointer to pass the tm ops.
2055 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2057 *(const void **)ops = &mrvl_tm_ops;
2062 static const struct eth_dev_ops mrvl_ops = {
2063 .dev_configure = mrvl_dev_configure,
2064 .dev_start = mrvl_dev_start,
2065 .dev_stop = mrvl_dev_stop,
2066 .dev_set_link_up = mrvl_dev_set_link_up,
2067 .dev_set_link_down = mrvl_dev_set_link_down,
2068 .dev_close = mrvl_dev_close,
2069 .link_update = mrvl_link_update,
2070 .promiscuous_enable = mrvl_promiscuous_enable,
2071 .allmulticast_enable = mrvl_allmulticast_enable,
2072 .promiscuous_disable = mrvl_promiscuous_disable,
2073 .allmulticast_disable = mrvl_allmulticast_disable,
2074 .mac_addr_remove = mrvl_mac_addr_remove,
2075 .mac_addr_add = mrvl_mac_addr_add,
2076 .mac_addr_set = mrvl_mac_addr_set,
2077 .mtu_set = mrvl_mtu_set,
2078 .stats_get = mrvl_stats_get,
2079 .stats_reset = mrvl_stats_reset,
2080 .xstats_get = mrvl_xstats_get,
2081 .xstats_reset = mrvl_xstats_reset,
2082 .xstats_get_names = mrvl_xstats_get_names,
2083 .dev_infos_get = mrvl_dev_infos_get,
2084 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
2085 .rxq_info_get = mrvl_rxq_info_get,
2086 .txq_info_get = mrvl_txq_info_get,
2087 .vlan_filter_set = mrvl_vlan_filter_set,
2088 .tx_queue_start = mrvl_tx_queue_start,
2089 .tx_queue_stop = mrvl_tx_queue_stop,
2090 .rx_queue_setup = mrvl_rx_queue_setup,
2091 .rx_queue_release = mrvl_rx_queue_release,
2092 .tx_queue_setup = mrvl_tx_queue_setup,
2093 .tx_queue_release = mrvl_tx_queue_release,
2094 .flow_ctrl_get = mrvl_flow_ctrl_get,
2095 .flow_ctrl_set = mrvl_flow_ctrl_set,
2096 .rss_hash_update = mrvl_rss_hash_update,
2097 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
2098 .filter_ctrl = mrvl_eth_filter_ctrl,
2099 .mtr_ops_get = mrvl_mtr_ops_get,
2100 .tm_ops_get = mrvl_tm_ops_get,
2104 * Return packet type information and l3/l4 offsets.
2107 * Pointer to the received packet descriptor.
2114 * Packet type information.
2116 static inline uint64_t
2117 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2118 uint8_t *l3_offset, uint8_t *l4_offset)
2120 enum pp2_inq_l3_type l3_type;
2121 enum pp2_inq_l4_type l4_type;
2122 enum pp2_inq_vlan_tag vlan_tag;
2123 uint64_t packet_type;
2125 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2126 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2127 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
2129 packet_type = RTE_PTYPE_L2_ETHER;
2132 case PP2_INQ_VLAN_TAG_SINGLE:
2133 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
2135 case PP2_INQ_VLAN_TAG_DOUBLE:
2136 case PP2_INQ_VLAN_TAG_TRIPLE:
2137 packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
2144 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2145 packet_type |= RTE_PTYPE_L3_IPV4;
2147 case PP2_INQ_L3_TYPE_IPV4_OK:
2148 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2150 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2151 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2153 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2154 packet_type |= RTE_PTYPE_L3_IPV6;
2156 case PP2_INQ_L3_TYPE_IPV6_EXT:
2157 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2159 case PP2_INQ_L3_TYPE_ARP:
2160 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2162 * In case of ARP l4_offset is set to wrong value.
2163 * Set it to proper one so that later on mbuf->l3_len can be
2164 * calculated subtracting l4_offset and l3_offset.
2166 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2169 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
2174 case PP2_INQ_L4_TYPE_TCP:
2175 packet_type |= RTE_PTYPE_L4_TCP;
2177 case PP2_INQ_L4_TYPE_UDP:
2178 packet_type |= RTE_PTYPE_L4_UDP;
2181 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
2189 * Get offload information from the received packet descriptor.
2192 * Pointer to the received packet descriptor.
2195 * Mbuf offload flags.
2197 static inline uint64_t
2198 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
2201 enum pp2_inq_desc_status status;
2203 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2204 if (unlikely(status != PP2_DESC_ERR_OK))
2205 flags = PKT_RX_IP_CKSUM_BAD;
2207 flags = PKT_RX_IP_CKSUM_GOOD;
2209 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2210 if (unlikely(status != PP2_DESC_ERR_OK))
2211 flags |= PKT_RX_L4_CKSUM_BAD;
2213 flags |= PKT_RX_L4_CKSUM_GOOD;
2219 * DPDK callback for receive.
2222 * Generic pointer to the receive queue.
2224 * Array to store received packets.
2226 * Maximum number of packets in array.
2229 * Number of packets successfully received.
2232 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2234 struct mrvl_rxq *q = rxq;
2235 struct pp2_ppio_desc descs[nb_pkts];
2236 struct pp2_bpool *bpool;
2237 int i, ret, rx_done = 0;
2239 struct pp2_hif *hif;
2240 unsigned int core_id = rte_lcore_id();
2242 hif = mrvl_get_hif(q->priv, core_id);
2244 if (unlikely(!q->priv->ppio || !hif))
2247 bpool = q->priv->bpool;
2249 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2250 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2251 if (unlikely(ret < 0)) {
2252 MRVL_LOG(ERR, "Failed to receive packets");
2255 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2257 for (i = 0; i < nb_pkts; i++) {
2258 struct rte_mbuf *mbuf;
2259 uint8_t l3_offset, l4_offset;
2260 enum pp2_inq_desc_status status;
2263 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2264 struct pp2_ppio_desc *pref_desc;
2267 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2268 pref_addr = cookie_addr_high |
2269 pp2_ppio_inq_desc_get_cookie(pref_desc);
2270 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2271 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2274 addr = cookie_addr_high |
2275 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2276 mbuf = (struct rte_mbuf *)addr;
2277 rte_pktmbuf_reset(mbuf);
2279 /* drop packet in case of mac, overrun or resource error */
2280 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2281 if (unlikely(status != PP2_DESC_ERR_OK)) {
2282 struct pp2_buff_inf binf = {
2283 .addr = rte_mbuf_data_iova_default(mbuf),
2284 .cookie = (uint64_t)mbuf,
2287 pp2_bpool_put_buff(hif, bpool, &binf);
2288 mrvl_port_bpool_size
2289 [bpool->pp2_id][bpool->id][core_id]++;
2294 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2295 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2296 mbuf->data_len = mbuf->pkt_len;
2297 mbuf->port = q->port_id;
2299 mrvl_desc_to_packet_type_and_offset(&descs[i],
2302 mbuf->l2_len = l3_offset;
2303 mbuf->l3_len = l4_offset - l3_offset;
2305 if (likely(q->cksum_enabled))
2306 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2308 rx_pkts[rx_done++] = mbuf;
2309 q->bytes_recv += mbuf->pkt_len;
2312 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2313 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2315 if (unlikely(num <= q->priv->bpool_min_size ||
2316 (!rx_done && num < q->priv->bpool_init_size))) {
2317 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2319 MRVL_LOG(ERR, "Failed to fill bpool");
2320 } else if (unlikely(num > q->priv->bpool_max_size)) {
2322 int pkt_to_remove = num - q->priv->bpool_init_size;
2323 struct rte_mbuf *mbuf;
2324 struct pp2_buff_inf buff;
2327 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
2328 bpool->pp2_id, q->priv->ppio->port_id,
2329 bpool->id, pkt_to_remove, num,
2330 q->priv->bpool_init_size);
2332 for (i = 0; i < pkt_to_remove; i++) {
2333 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2336 mbuf = (struct rte_mbuf *)
2337 (cookie_addr_high | buff.cookie);
2338 rte_pktmbuf_free(mbuf);
2340 mrvl_port_bpool_size
2341 [bpool->pp2_id][bpool->id][core_id] -= i;
2343 rte_spinlock_unlock(&q->priv->lock);
2350 * Prepare offload information.
2354 * @param packet_type
2355 * Packet type bitfield.
2357 * Pointer to the pp2_ouq_l3_type structure.
2359 * Pointer to the pp2_outq_l4_type structure.
2360 * @param gen_l3_cksum
2361 * Will be set to 1 in case l3 checksum is computed.
2363 * Will be set to 1 in case l4 checksum is computed.
2366 * 0 on success, negative error value otherwise.
2369 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2370 enum pp2_outq_l3_type *l3_type,
2371 enum pp2_outq_l4_type *l4_type,
2376 * Based on ol_flags prepare information
2377 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2380 if (ol_flags & PKT_TX_IPV4) {
2381 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2382 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2383 } else if (ol_flags & PKT_TX_IPV6) {
2384 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2385 /* no checksum for ipv6 header */
2388 /* if something different then stop processing */
2392 ol_flags &= PKT_TX_L4_MASK;
2393 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2394 ol_flags == PKT_TX_TCP_CKSUM) {
2395 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2397 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2398 ol_flags == PKT_TX_UDP_CKSUM) {
2399 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2402 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2403 /* no checksum for other type */
2411 * Release already sent buffers to bpool (buffer-pool).
2414 * Pointer to the port structure.
2416 * Pointer to the MUSDK hardware interface.
2418 * Pointer to the shadow queue.
2422 * Force releasing packets.
2425 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2426 unsigned int core_id, struct mrvl_shadow_txq *sq,
2429 struct buff_release_entry *entry;
2430 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2433 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2435 sq->num_to_release += nb_done;
2437 if (likely(!force &&
2438 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2441 nb_done = sq->num_to_release;
2442 sq->num_to_release = 0;
2444 for (i = 0; i < nb_done; i++) {
2445 entry = &sq->ent[sq->tail + num];
2446 if (unlikely(!entry->buff.addr)) {
2448 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2449 sq->tail, (u64)entry->buff.cookie,
2450 (u64)entry->buff.addr);
2455 if (unlikely(!entry->bpool)) {
2456 struct rte_mbuf *mbuf;
2458 mbuf = (struct rte_mbuf *)
2459 (cookie_addr_high | entry->buff.cookie);
2460 rte_pktmbuf_free(mbuf);
2465 mrvl_port_bpool_size
2466 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2468 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2473 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2475 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2482 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2483 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2489 * DPDK callback for transmit.
2492 * Generic pointer transmit queue.
2494 * Packets to transmit.
2496 * Number of packets in array.
2499 * Number of packets successfully transmitted.
2502 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2504 struct mrvl_txq *q = txq;
2505 struct mrvl_shadow_txq *sq;
2506 struct pp2_hif *hif;
2507 struct pp2_ppio_desc descs[nb_pkts];
2508 unsigned int core_id = rte_lcore_id();
2509 int i, ret, bytes_sent = 0;
2510 uint16_t num, sq_free_size;
2513 hif = mrvl_get_hif(q->priv, core_id);
2514 sq = &q->shadow_txqs[core_id];
2516 if (unlikely(!q->priv->ppio || !hif))
2520 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2521 sq, q->queue_id, 0);
2523 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2524 if (unlikely(nb_pkts > sq_free_size)) {
2526 "No room in shadow queue for %d packets! %d packets will be sent.",
2527 nb_pkts, sq_free_size);
2528 nb_pkts = sq_free_size;
2531 for (i = 0; i < nb_pkts; i++) {
2532 struct rte_mbuf *mbuf = tx_pkts[i];
2533 int gen_l3_cksum, gen_l4_cksum;
2534 enum pp2_outq_l3_type l3_type;
2535 enum pp2_outq_l4_type l4_type;
2537 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2538 struct rte_mbuf *pref_pkt_hdr;
2540 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2541 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2542 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2545 mrvl_fill_shadowq(sq, mbuf);
2546 mrvl_fill_desc(&descs[i], mbuf);
2548 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2550 * in case unsupported ol_flags were passed
2551 * do not update descriptor offload information
2553 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2554 &l3_type, &l4_type, &gen_l3_cksum,
2559 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2561 mbuf->l2_len + mbuf->l3_len,
2562 gen_l3_cksum, gen_l4_cksum);
2566 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2567 /* number of packets that were not sent */
2568 if (unlikely(num > nb_pkts)) {
2569 for (i = nb_pkts; i < num; i++) {
2570 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2571 MRVL_PP2_TX_SHADOWQ_MASK;
2572 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2574 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2576 sq->size -= num - nb_pkts;
2579 q->bytes_sent += bytes_sent;
2584 /** DPDK callback for S/G transmit.
2587 * Generic pointer transmit queue.
2589 * Packets to transmit.
2591 * Number of packets in array.
2594 * Number of packets successfully transmitted.
2597 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
2600 struct mrvl_txq *q = txq;
2601 struct mrvl_shadow_txq *sq;
2602 struct pp2_hif *hif;
2603 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS];
2604 struct pp2_ppio_sg_pkts pkts;
2605 uint8_t frags[nb_pkts];
2606 unsigned int core_id = rte_lcore_id();
2607 int i, j, ret, bytes_sent = 0;
2608 int tail, tail_first;
2609 uint16_t num, sq_free_size;
2610 uint16_t nb_segs, total_descs = 0;
2613 hif = mrvl_get_hif(q->priv, core_id);
2614 sq = &q->shadow_txqs[core_id];
2618 if (unlikely(!q->priv->ppio || !hif))
2622 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2623 sq, q->queue_id, 0);
2625 /* Save shadow queue free size */
2626 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2629 for (i = 0; i < nb_pkts; i++) {
2630 struct rte_mbuf *mbuf = tx_pkts[i];
2631 struct rte_mbuf *seg = NULL;
2632 int gen_l3_cksum, gen_l4_cksum;
2633 enum pp2_outq_l3_type l3_type;
2634 enum pp2_outq_l4_type l4_type;
2636 nb_segs = mbuf->nb_segs;
2638 total_descs += nb_segs;
2641 * Check if total_descs does not exceed
2642 * shadow queue free size
2644 if (unlikely(total_descs > sq_free_size)) {
2645 total_descs -= nb_segs;
2647 "No room in shadow queue for %d packets! "
2648 "%d packets will be sent.\n",
2653 /* Check if nb_segs does not exceed the max nb of desc per
2656 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) {
2657 total_descs -= nb_segs;
2659 "Too many segments. Packet won't be sent.\n");
2663 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2664 struct rte_mbuf *pref_pkt_hdr;
2666 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2667 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2668 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2671 pkts.frags[pkts.num] = nb_segs;
2675 for (j = 0; j < nb_segs - 1; j++) {
2676 /* For the subsequent segments, set shadow queue
2679 mrvl_fill_shadowq(sq, NULL);
2680 mrvl_fill_desc(&descs[tail], seg);
2685 /* Put first mbuf info in last shadow queue entry */
2686 mrvl_fill_shadowq(sq, mbuf);
2687 /* Update descriptor with last segment */
2688 mrvl_fill_desc(&descs[tail++], seg);
2690 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2691 /* In case unsupported ol_flags were passed
2692 * do not update descriptor offload information
2694 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2695 &l3_type, &l4_type, &gen_l3_cksum,
2700 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type,
2701 l4_type, mbuf->l2_len,
2702 mbuf->l2_len + mbuf->l3_len,
2703 gen_l3_cksum, gen_l4_cksum);
2707 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs,
2708 &total_descs, &pkts);
2709 /* number of packets that were not sent */
2710 if (unlikely(num > total_descs)) {
2711 for (i = total_descs; i < num; i++) {
2712 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2713 MRVL_PP2_TX_SHADOWQ_MASK;
2715 addr = sq->ent[sq->head].buff.cookie;
2718 rte_pktmbuf_pkt_len((struct rte_mbuf *)
2719 (cookie_addr_high | addr));
2721 sq->size -= num - total_descs;
2725 q->bytes_sent += bytes_sent;
2731 * Initialize packet processor.
2734 * 0 on success, negative error value otherwise.
2739 struct pp2_init_params init_params;
2741 memset(&init_params, 0, sizeof(init_params));
2742 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2743 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2744 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2746 return pp2_init(&init_params);
2750 * Deinitialize packet processor.
2753 * 0 on success, negative error value otherwise.
2756 mrvl_deinit_pp2(void)
2762 * Create private device structure.
2765 * Pointer to the port name passed in the initialization parameters.
2768 * Pointer to the newly allocated private device structure.
2770 static struct mrvl_priv *
2771 mrvl_priv_create(const char *dev_name)
2773 struct pp2_bpool_params bpool_params;
2774 char match[MRVL_MATCH_LEN];
2775 struct mrvl_priv *priv;
2778 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2782 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2783 &priv->pp_id, &priv->ppio_id);
2787 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2788 PP2_BPOOL_NUM_POOLS);
2791 priv->bpool_bit = bpool_bit;
2793 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2795 memset(&bpool_params, 0, sizeof(bpool_params));
2796 bpool_params.match = match;
2797 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2798 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2800 goto out_clear_bpool_bit;
2802 priv->ppio_params.type = PP2_PPIO_T_NIC;
2803 rte_spinlock_init(&priv->lock);
2806 out_clear_bpool_bit:
2807 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2814 * Create device representing Ethernet port.
2817 * Pointer to the port's name.
2820 * 0 on success, negative error value otherwise.
2823 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2825 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2826 struct rte_eth_dev *eth_dev;
2827 struct mrvl_priv *priv;
2830 eth_dev = rte_eth_dev_allocate(name);
2834 priv = mrvl_priv_create(name);
2839 eth_dev->data->dev_private = priv;
2841 eth_dev->data->mac_addrs =
2842 rte_zmalloc("mac_addrs",
2843 RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2844 if (!eth_dev->data->mac_addrs) {
2845 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2850 memset(&req, 0, sizeof(req));
2851 strcpy(req.ifr_name, name);
2852 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2856 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2857 req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN);
2859 eth_dev->device = &vdev->device;
2860 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2861 mrvl_set_tx_function(eth_dev);
2862 eth_dev->dev_ops = &mrvl_ops;
2864 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2865 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2867 rte_eth_dev_probing_finish(eth_dev);
2870 rte_eth_dev_release_port(eth_dev);
2876 * Callback used by rte_kvargs_process() during argument parsing.
2879 * Pointer to the parsed key (unused).
2881 * Pointer to the parsed value.
2883 * Pointer to the extra arguments which contains address of the
2884 * table of pointers to parsed interface names.
2890 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2893 struct mrvl_ifnames *ifnames = extra_args;
2895 ifnames->names[ifnames->idx++] = value;
2901 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2904 mrvl_deinit_hifs(void)
2908 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2910 pp2_hif_deinit(hifs[i]);
2912 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2913 memset(hifs, 0, sizeof(hifs));
2917 * DPDK callback to register the virtual device.
2920 * Pointer to the virtual device.
2923 * 0 on success, negative error value otherwise.
2926 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2928 struct rte_kvargs *kvlist;
2929 struct mrvl_ifnames ifnames;
2931 uint32_t i, ifnum, cfgnum;
2934 params = rte_vdev_device_args(vdev);
2938 kvlist = rte_kvargs_parse(params, valid_args);
2942 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2943 if (ifnum > RTE_DIM(ifnames.names))
2944 goto out_free_kvlist;
2947 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2948 mrvl_get_ifnames, &ifnames);
2952 * The below system initialization should be done only once,
2953 * on the first provided configuration file
2955 if (!mrvl_qos_cfg) {
2956 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2957 MRVL_LOG(INFO, "Parsing config file!");
2959 MRVL_LOG(ERR, "Cannot handle more than one config file!");
2960 goto out_free_kvlist;
2961 } else if (cfgnum == 1) {
2962 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2963 mrvl_get_qoscfg, &mrvl_qos_cfg);
2970 MRVL_LOG(INFO, "Perform MUSDK initializations");
2972 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
2974 goto out_free_kvlist;
2976 ret = mrvl_init_pp2();
2978 MRVL_LOG(ERR, "Failed to init PP!");
2979 rte_mvep_deinit(MVEP_MOD_T_PP2);
2980 goto out_free_kvlist;
2983 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2984 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2986 mrvl_lcore_first = RTE_MAX_LCORE;
2987 mrvl_lcore_last = 0;
2990 for (i = 0; i < ifnum; i++) {
2991 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
2992 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2998 rte_kvargs_free(kvlist);
3002 rte_pmd_mrvl_remove(vdev);
3005 rte_kvargs_free(kvlist);
3011 * DPDK callback to remove virtual device.
3014 * Pointer to the removed virtual device.
3017 * 0 on success, negative error value otherwise.
3020 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
3024 RTE_ETH_FOREACH_DEV(port_id) {
3025 if (rte_eth_devices[port_id].device != &vdev->device)
3027 rte_eth_dev_close(port_id);
3033 static struct rte_vdev_driver pmd_mrvl_drv = {
3034 .probe = rte_pmd_mrvl_probe,
3035 .remove = rte_pmd_mrvl_remove,
3038 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
3039 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
3040 RTE_LOG_REGISTER(mrvl_logtype, pmd.net.mvpp2, NOTICE);