1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_string_fns.h>
8 #include <rte_ethdev_driver.h>
9 #include <rte_kvargs.h>
11 #include <rte_malloc.h>
12 #include <rte_bus_vdev.h>
15 #include <linux/ethtool.h>
16 #include <linux/sockios.h>
18 #include <net/if_arp.h>
19 #include <sys/ioctl.h>
20 #include <sys/socket.h>
22 #include <sys/types.h>
24 #include <rte_mvep_common.h>
25 #include "mrvl_ethdev.h"
27 #include "mrvl_flow.h"
31 /* bitmask with reserved hifs */
32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
33 /* bitmask with reserved bpools */
34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
35 /* bitmask with reserved kernel RSS tables */
36 #define MRVL_MUSDK_RSS_RESERVED 0x01
37 /* maximum number of available hifs */
38 #define MRVL_MUSDK_HIFS_MAX 9
41 #define MRVL_MUSDK_PREFETCH_SHIFT 2
43 /* TCAM has 25 entries reserved for uc/mc filter entries */
44 #define MRVL_MAC_ADDRS_MAX 25
45 #define MRVL_MATCH_LEN 16
46 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
47 /* Maximum allowable packet size */
48 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
50 #define MRVL_IFACE_NAME_ARG "iface"
51 #define MRVL_CFG_ARG "cfg"
53 #define MRVL_BURST_SIZE 64
55 #define MRVL_ARP_LENGTH 28
57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
60 /** Port Rx offload capabilities */
61 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
62 DEV_RX_OFFLOAD_JUMBO_FRAME | \
63 DEV_RX_OFFLOAD_CHECKSUM)
65 /** Port Tx offloads capabilities */
66 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
67 DEV_TX_OFFLOAD_UDP_CKSUM | \
68 DEV_TX_OFFLOAD_TCP_CKSUM | \
69 DEV_TX_OFFLOAD_MULTI_SEGS)
71 static const char * const valid_args[] = {
77 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
78 static struct pp2_hif *hifs[RTE_MAX_LCORE];
79 static int used_bpools[PP2_NUM_PKT_PROC] = {
80 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
83 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
84 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
85 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
90 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
95 * To use buffer harvesting based on loopback port shadow queue structure
96 * was introduced for buffers information bookkeeping.
98 * Before sending the packet, related buffer information (pp2_buff_inf) is
99 * stored in shadow queue. After packet is transmitted no longer used
100 * packet buffer is released back to it's original hardware pool,
101 * on condition it originated from interface.
102 * In case it was generated by application itself i.e: mbuf->port field is
103 * 0xff then its released to software mempool.
105 struct mrvl_shadow_txq {
106 int head; /* write index - used when sending buffers */
107 int tail; /* read index - used when releasing buffers */
108 u16 size; /* queue occupied size */
109 u16 num_to_release; /* number of descriptors sent, that can be
112 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
116 struct mrvl_priv *priv;
117 struct rte_mempool *mp;
126 struct mrvl_priv *priv;
130 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
131 int tx_deferred_start;
134 static int mrvl_lcore_first;
135 static int mrvl_lcore_last;
136 static int mrvl_dev_num;
138 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
139 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
140 struct pp2_hif *hif, unsigned int core_id,
141 struct mrvl_shadow_txq *sq, int qid, int force);
143 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
145 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
147 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev);
148 static void mrvl_deinit_pp2(void);
149 static void mrvl_deinit_hifs(void);
152 #define MRVL_XSTATS_TBL_ENTRY(name) { \
153 #name, offsetof(struct pp2_ppio_statistics, name), \
154 sizeof(((struct pp2_ppio_statistics *)0)->name) \
157 /* Table with xstats data */
162 } mrvl_xstats_tbl[] = {
163 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
164 MRVL_XSTATS_TBL_ENTRY(rx_packets),
165 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
166 MRVL_XSTATS_TBL_ENTRY(rx_errors),
167 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
168 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
169 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
170 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
171 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
172 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
173 MRVL_XSTATS_TBL_ENTRY(tx_packets),
174 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
175 MRVL_XSTATS_TBL_ENTRY(tx_errors)
179 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf)
181 sq->ent[sq->head].buff.cookie = (uint64_t)buf;
182 sq->ent[sq->head].buff.addr = buf ?
183 rte_mbuf_data_iova_default(buf) : 0;
185 sq->ent[sq->head].bpool =
186 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS ||
187 buf->refcnt > 1)) ? NULL :
188 mrvl_port_to_bpool_lookup[buf->port];
190 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
195 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf)
197 pp2_ppio_outq_desc_reset(desc);
198 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf));
199 pp2_ppio_outq_desc_set_pkt_offset(desc, 0);
200 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf));
204 mrvl_get_bpool_size(int pp2_id, int pool_id)
209 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
210 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
216 mrvl_reserve_bit(int *bitmap, int max)
218 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
229 mrvl_init_hif(int core_id)
231 struct pp2_hif_params params;
232 char match[MRVL_MATCH_LEN];
235 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
237 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
241 snprintf(match, sizeof(match), "hif-%d", ret);
242 memset(¶ms, 0, sizeof(params));
243 params.match = match;
244 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
245 ret = pp2_hif_init(¶ms, &hifs[core_id]);
247 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
254 static inline struct pp2_hif*
255 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
259 if (likely(hifs[core_id] != NULL))
260 return hifs[core_id];
262 rte_spinlock_lock(&priv->lock);
264 ret = mrvl_init_hif(core_id);
266 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
270 if (core_id < mrvl_lcore_first)
271 mrvl_lcore_first = core_id;
273 if (core_id > mrvl_lcore_last)
274 mrvl_lcore_last = core_id;
276 rte_spinlock_unlock(&priv->lock);
278 return hifs[core_id];
282 * Set tx burst function according to offload flag
285 * Pointer to Ethernet device structure.
288 mrvl_set_tx_function(struct rte_eth_dev *dev)
290 struct mrvl_priv *priv = dev->data->dev_private;
292 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
293 if (priv->multiseg) {
294 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n");
295 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst;
297 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n");
298 dev->tx_pkt_burst = mrvl_tx_pkt_burst;
303 * Configure rss based on dpdk rss configuration.
306 * Pointer to private structure.
308 * Pointer to RSS configuration.
311 * 0 on success, negative error value otherwise.
314 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
316 if (rss_conf->rss_key)
317 MRVL_LOG(WARNING, "Changing hash key is not supported");
319 if (rss_conf->rss_hf == 0) {
320 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
321 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
322 priv->ppio_params.inqs_params.hash_type =
323 PP2_PPIO_HASH_T_2_TUPLE;
324 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
325 priv->ppio_params.inqs_params.hash_type =
326 PP2_PPIO_HASH_T_5_TUPLE;
327 priv->rss_hf_tcp = 1;
328 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
329 priv->ppio_params.inqs_params.hash_type =
330 PP2_PPIO_HASH_T_5_TUPLE;
331 priv->rss_hf_tcp = 0;
340 * Ethernet device configuration.
342 * Prepare the driver for a given number of TX and RX queues and
346 * Pointer to Ethernet device structure.
349 * 0 on success, negative error value otherwise.
352 mrvl_dev_configure(struct rte_eth_dev *dev)
354 struct mrvl_priv *priv = dev->data->dev_private;
358 MRVL_LOG(INFO, "Device reconfiguration is not supported");
362 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
363 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
364 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
365 dev->data->dev_conf.rxmode.mq_mode);
369 if (dev->data->dev_conf.rxmode.split_hdr_size) {
370 MRVL_LOG(INFO, "Split headers not supported");
374 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
375 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
376 MRVL_PP2_ETH_HDRS_LEN;
378 if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
381 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
382 dev->data->nb_rx_queues);
386 ret = mrvl_configure_txqs(priv, dev->data->port_id,
387 dev->data->nb_tx_queues);
391 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
392 priv->ppio_params.maintain_stats = 1;
393 priv->nb_rx_queues = dev->data->nb_rx_queues;
395 ret = mrvl_tm_init(dev);
399 if (dev->data->nb_rx_queues == 1 &&
400 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
401 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
402 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
407 return mrvl_configure_rss(priv,
408 &dev->data->dev_conf.rx_adv_conf.rss_conf);
412 * DPDK callback to change the MTU.
414 * Setting the MTU affects hardware MRU (packets larger than the MRU
418 * Pointer to Ethernet device structure.
423 * 0 on success, negative error value otherwise.
426 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
428 struct mrvl_priv *priv = dev->data->dev_private;
430 uint16_t mbuf_data_size = 0; /* SW buffer size */
433 mru = MRVL_PP2_MTU_TO_MRU(mtu);
435 * min_rx_buf_size is equal to mbuf data size
436 * if pmd didn't set it differently
438 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
440 * - setting mru greater than the mbuf size resulting in
441 * hw and sw buffer size mismatch
442 * - setting mtu that requires the support of scattered packets
443 * when this feature has not been enabled/supported so far
444 * (TODO check scattered_rx flag here once scattered RX is supported).
446 if (mru + MRVL_PKT_OFFS > mbuf_data_size) {
447 mru = mbuf_data_size - MRVL_PKT_OFFS;
448 mtu = MRVL_PP2_MRU_TO_MTU(mru);
449 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted "
450 "by current mbuf size: %u. Set MTU to %u, MRU to %u",
451 mbuf_data_size, mtu, mru);
454 if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) {
455 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru);
459 dev->data->mtu = mtu;
460 dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE;
465 ret = pp2_ppio_set_mru(priv->ppio, mru);
467 MRVL_LOG(ERR, "Failed to change MRU");
471 ret = pp2_ppio_set_mtu(priv->ppio, mtu);
473 MRVL_LOG(ERR, "Failed to change MTU");
481 * DPDK callback to bring the link up.
484 * Pointer to Ethernet device structure.
487 * 0 on success, negative error value otherwise.
490 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
492 struct mrvl_priv *priv = dev->data->dev_private;
498 ret = pp2_ppio_enable(priv->ppio);
503 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
504 * as pp2_ppio_enable() changes port->t_mode from default 0 to
505 * PP2_TRAFFIC_INGRESS_EGRESS.
507 * Set mtu to default DPDK value here.
509 ret = mrvl_mtu_set(dev, dev->data->mtu);
511 pp2_ppio_disable(priv->ppio);
517 * DPDK callback to bring the link down.
520 * Pointer to Ethernet device structure.
523 * 0 on success, negative error value otherwise.
526 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
528 struct mrvl_priv *priv = dev->data->dev_private;
533 return pp2_ppio_disable(priv->ppio);
537 * DPDK callback to start tx queue.
540 * Pointer to Ethernet device structure.
542 * Transmit queue index.
545 * 0 on success, negative error value otherwise.
548 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
550 struct mrvl_priv *priv = dev->data->dev_private;
556 /* passing 1 enables given tx queue */
557 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
559 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
563 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
569 * DPDK callback to stop tx queue.
572 * Pointer to Ethernet device structure.
574 * Transmit queue index.
577 * 0 on success, negative error value otherwise.
580 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
582 struct mrvl_priv *priv = dev->data->dev_private;
588 /* passing 0 disables given tx queue */
589 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
591 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
595 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
601 * DPDK callback to start the device.
604 * Pointer to Ethernet device structure.
607 * 0 on success, negative errno value on failure.
610 mrvl_dev_start(struct rte_eth_dev *dev)
612 struct mrvl_priv *priv = dev->data->dev_private;
613 char match[MRVL_MATCH_LEN];
614 int ret = 0, i, def_init_size;
617 return mrvl_dev_set_link_up(dev);
619 snprintf(match, sizeof(match), "ppio-%d:%d",
620 priv->pp_id, priv->ppio_id);
621 priv->ppio_params.match = match;
624 * Calculate the minimum bpool size for refill feature as follows:
625 * 2 default burst sizes multiply by number of rx queues.
626 * If the bpool size will be below this value, new buffers will
627 * be added to the pool.
629 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
631 /* In case initial bpool size configured in queues setup is
632 * smaller than minimum size add more buffers
634 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
635 if (priv->bpool_init_size < def_init_size) {
636 int buffs_to_add = def_init_size - priv->bpool_init_size;
638 priv->bpool_init_size += buffs_to_add;
639 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
641 MRVL_LOG(ERR, "Failed to add buffers to bpool");
645 * Calculate the maximum bpool size for refill feature as follows:
646 * maximum number of descriptors in rx queue multiply by number
647 * of rx queues plus minimum bpool size.
648 * In case the bpool size will exceed this value, superfluous buffers
651 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
652 priv->bpool_min_size;
654 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
656 MRVL_LOG(ERR, "Failed to init ppio");
661 * In case there are some some stale uc/mc mac addresses flush them
662 * here. It cannot be done during mrvl_dev_close() as port information
663 * is already gone at that point (due to pp2_ppio_deinit() in
666 if (!priv->uc_mc_flushed) {
667 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
670 "Failed to flush uc/mc filter list");
673 priv->uc_mc_flushed = 1;
676 if (!priv->vlan_flushed) {
677 ret = pp2_ppio_flush_vlan(priv->ppio);
679 MRVL_LOG(ERR, "Failed to flush vlan list");
682 * once pp2_ppio_flush_vlan() is supported jump to out
686 priv->vlan_flushed = 1;
688 ret = mrvl_mtu_set(dev, dev->data->mtu);
690 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu);
692 /* For default QoS config, don't start classifier. */
694 mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) {
695 ret = mrvl_start_qos_mapping(priv);
697 MRVL_LOG(ERR, "Failed to setup QoS mapping");
702 ret = mrvl_dev_set_link_up(dev);
704 MRVL_LOG(ERR, "Failed to set link up");
708 /* start tx queues */
709 for (i = 0; i < dev->data->nb_tx_queues; i++) {
710 struct mrvl_txq *txq = dev->data->tx_queues[i];
712 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
714 if (!txq->tx_deferred_start)
718 * All txqs are started by default. Stop them
719 * so that tx_deferred_start works as expected.
721 ret = mrvl_tx_queue_stop(dev, i);
728 mrvl_set_tx_function(dev);
732 MRVL_LOG(ERR, "Failed to start device");
733 pp2_ppio_deinit(priv->ppio);
738 * Flush receive queues.
741 * Pointer to Ethernet device structure.
744 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
748 MRVL_LOG(INFO, "Flushing rx queues");
749 for (i = 0; i < dev->data->nb_rx_queues; i++) {
753 struct mrvl_rxq *q = dev->data->rx_queues[i];
754 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
756 num = MRVL_PP2_RXD_MAX;
757 ret = pp2_ppio_recv(q->priv->ppio,
758 q->priv->rxq_map[q->queue_id].tc,
759 q->priv->rxq_map[q->queue_id].inq,
760 descs, (uint16_t *)&num);
761 } while (ret == 0 && num);
766 * Flush transmit shadow queues.
769 * Pointer to Ethernet device structure.
772 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
775 struct mrvl_txq *txq;
777 MRVL_LOG(INFO, "Flushing tx shadow queues");
778 for (i = 0; i < dev->data->nb_tx_queues; i++) {
779 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
781 for (j = 0; j < RTE_MAX_LCORE; j++) {
782 struct mrvl_shadow_txq *sq;
787 sq = &txq->shadow_txqs[j];
788 mrvl_free_sent_buffers(txq->priv->ppio,
789 hifs[j], j, sq, txq->queue_id, 1);
790 while (sq->tail != sq->head) {
791 uint64_t addr = cookie_addr_high |
792 sq->ent[sq->tail].buff.cookie;
794 (struct rte_mbuf *)addr);
795 sq->tail = (sq->tail + 1) &
796 MRVL_PP2_TX_SHADOWQ_MASK;
798 memset(sq, 0, sizeof(*sq));
804 * Flush hardware bpool (buffer-pool).
807 * Pointer to Ethernet device structure.
810 mrvl_flush_bpool(struct rte_eth_dev *dev)
812 struct mrvl_priv *priv = dev->data->dev_private;
816 unsigned int core_id = rte_lcore_id();
818 if (core_id == LCORE_ID_ANY)
821 hif = mrvl_get_hif(priv, core_id);
823 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
825 MRVL_LOG(ERR, "Failed to get bpool buffers number");
830 struct pp2_buff_inf inf;
833 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
837 addr = cookie_addr_high | inf.cookie;
838 rte_pktmbuf_free((struct rte_mbuf *)addr);
843 * DPDK callback to stop the device.
846 * Pointer to Ethernet device structure.
849 mrvl_dev_stop(struct rte_eth_dev *dev)
851 mrvl_dev_set_link_down(dev);
855 * DPDK callback to close the device.
858 * Pointer to Ethernet device structure.
861 mrvl_dev_close(struct rte_eth_dev *dev)
863 struct mrvl_priv *priv = dev->data->dev_private;
866 mrvl_flush_rx_queues(dev);
867 mrvl_flush_tx_shadow_queues(dev);
868 mrvl_flow_deinit(dev);
869 mrvl_mtr_deinit(dev);
871 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
872 struct pp2_ppio_tc_params *tc_params =
873 &priv->ppio_params.inqs_params.tcs_params[i];
875 if (tc_params->inqs_params) {
876 rte_free(tc_params->inqs_params);
877 tc_params->inqs_params = NULL;
882 pp2_cls_tbl_deinit(priv->cls_tbl);
883 priv->cls_tbl = NULL;
887 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
888 priv->qos_tbl = NULL;
891 mrvl_flush_bpool(dev);
895 pp2_ppio_deinit(priv->ppio);
899 /* policer must be released after ppio deinitialization */
900 if (priv->default_policer) {
901 pp2_cls_plcr_deinit(priv->default_policer);
902 priv->default_policer = NULL;
907 pp2_bpool_deinit(priv->bpool);
908 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
914 if (mrvl_dev_num == 0) {
915 MRVL_LOG(INFO, "Perform MUSDK deinit");
918 rte_mvep_deinit(MVEP_MOD_T_PP2);
923 * DPDK callback to retrieve physical link information.
926 * Pointer to Ethernet device structure.
927 * @param wait_to_complete
928 * Wait for request completion (ignored).
931 * 0 on success, negative error value otherwise.
934 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
938 * once MUSDK provides necessary API use it here
940 struct mrvl_priv *priv = dev->data->dev_private;
941 struct ethtool_cmd edata;
943 int ret, fd, link_up;
948 edata.cmd = ETHTOOL_GSET;
950 strcpy(req.ifr_name, dev->data->name);
951 req.ifr_data = (void *)&edata;
953 fd = socket(AF_INET, SOCK_DGRAM, 0);
957 ret = ioctl(fd, SIOCETHTOOL, &req);
965 switch (ethtool_cmd_speed(&edata)) {
967 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
970 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
973 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
976 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
979 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
982 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
983 ETH_LINK_HALF_DUPLEX;
984 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
986 pp2_ppio_get_link_state(priv->ppio, &link_up);
987 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
993 * DPDK callback to enable promiscuous mode.
996 * Pointer to Ethernet device structure.
999 * 0 on success, negative error value otherwise.
1002 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
1004 struct mrvl_priv *priv = dev->data->dev_private;
1013 ret = pp2_ppio_set_promisc(priv->ppio, 1);
1015 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
1023 * DPDK callback to enable allmulti mode.
1026 * Pointer to Ethernet device structure.
1029 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
1031 struct mrvl_priv *priv = dev->data->dev_private;
1040 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
1042 MRVL_LOG(ERR, "Failed enable all-multicast mode");
1046 * DPDK callback to disable promiscuous mode.
1049 * Pointer to Ethernet device structure.
1052 * 0 on success, negative error value otherwise.
1055 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
1057 struct mrvl_priv *priv = dev->data->dev_private;
1063 ret = pp2_ppio_set_promisc(priv->ppio, 0);
1065 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
1073 * DPDK callback to disable allmulticast mode.
1076 * Pointer to Ethernet device structure.
1079 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
1081 struct mrvl_priv *priv = dev->data->dev_private;
1087 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
1089 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
1093 * DPDK callback to remove a MAC address.
1096 * Pointer to Ethernet device structure.
1098 * MAC address index.
1101 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
1103 struct mrvl_priv *priv = dev->data->dev_private;
1104 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1113 ret = pp2_ppio_remove_mac_addr(priv->ppio,
1114 dev->data->mac_addrs[index].addr_bytes);
1116 rte_ether_format_addr(buf, sizeof(buf),
1117 &dev->data->mac_addrs[index]);
1118 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
1123 * DPDK callback to add a MAC address.
1126 * Pointer to Ethernet device structure.
1128 * MAC address to register.
1130 * MAC address index.
1132 * VMDq pool index to associate address with (unused).
1135 * 0 on success, negative error value otherwise.
1138 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1139 uint32_t index, uint32_t vmdq __rte_unused)
1141 struct mrvl_priv *priv = dev->data->dev_private;
1142 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1149 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1156 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1157 * parameter uc_filter_max. Maximum number of mc addresses is then
1158 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1161 * If more than uc_filter_max uc addresses were added to filter list
1162 * then NIC will switch to promiscuous mode automatically.
1164 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1165 * were added to filter list then NIC will switch to all-multicast mode
1168 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1170 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1171 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1179 * DPDK callback to set the primary MAC address.
1182 * Pointer to Ethernet device structure.
1184 * MAC address to register.
1187 * 0 on success, negative error value otherwise.
1190 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1192 struct mrvl_priv *priv = dev->data->dev_private;
1201 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1203 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1204 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1205 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1212 * DPDK callback to get device statistics.
1215 * Pointer to Ethernet device structure.
1217 * Stats structure output buffer.
1220 * 0 on success, negative error value otherwise.
1223 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1225 struct mrvl_priv *priv = dev->data->dev_private;
1226 struct pp2_ppio_statistics ppio_stats;
1227 uint64_t drop_mac = 0;
1228 unsigned int i, idx, ret;
1233 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1234 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1235 struct pp2_ppio_inq_statistics rx_stats;
1240 idx = rxq->queue_id;
1241 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1243 "rx queue %d stats out of range (0 - %d)",
1244 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1248 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1249 priv->rxq_map[idx].tc,
1250 priv->rxq_map[idx].inq,
1252 if (unlikely(ret)) {
1254 "Failed to update rx queue %d stats", idx);
1258 stats->q_ibytes[idx] = rxq->bytes_recv;
1259 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1260 stats->q_errors[idx] = rx_stats.drop_early +
1261 rx_stats.drop_fullq +
1264 stats->ibytes += rxq->bytes_recv;
1265 drop_mac += rxq->drop_mac;
1268 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1269 struct mrvl_txq *txq = dev->data->tx_queues[i];
1270 struct pp2_ppio_outq_statistics tx_stats;
1275 idx = txq->queue_id;
1276 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1278 "tx queue %d stats out of range (0 - %d)",
1279 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1282 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1284 if (unlikely(ret)) {
1286 "Failed to update tx queue %d stats", idx);
1290 stats->q_opackets[idx] = tx_stats.deq_desc;
1291 stats->q_obytes[idx] = txq->bytes_sent;
1292 stats->obytes += txq->bytes_sent;
1295 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1296 if (unlikely(ret)) {
1297 MRVL_LOG(ERR, "Failed to update port statistics");
1301 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1302 stats->opackets += ppio_stats.tx_packets;
1303 stats->imissed += ppio_stats.rx_fullq_dropped +
1304 ppio_stats.rx_bm_dropped +
1305 ppio_stats.rx_early_dropped +
1306 ppio_stats.rx_fifo_dropped +
1307 ppio_stats.rx_cls_dropped;
1308 stats->ierrors = drop_mac;
1314 * DPDK callback to clear device statistics.
1317 * Pointer to Ethernet device structure.
1320 mrvl_stats_reset(struct rte_eth_dev *dev)
1322 struct mrvl_priv *priv = dev->data->dev_private;
1328 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1329 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1331 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1332 priv->rxq_map[i].inq, NULL, 1);
1333 rxq->bytes_recv = 0;
1337 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1338 struct mrvl_txq *txq = dev->data->tx_queues[i];
1340 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1341 txq->bytes_sent = 0;
1344 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1348 * DPDK callback to get extended statistics.
1351 * Pointer to Ethernet device structure.
1353 * Pointer to xstats table.
1355 * Number of entries in xstats table.
1357 * Negative value on error, number of read xstats otherwise.
1360 mrvl_xstats_get(struct rte_eth_dev *dev,
1361 struct rte_eth_xstat *stats, unsigned int n)
1363 struct mrvl_priv *priv = dev->data->dev_private;
1364 struct pp2_ppio_statistics ppio_stats;
1370 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1371 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1374 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1375 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1376 mrvl_xstats_tbl[i].offset);
1377 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1378 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1379 mrvl_xstats_tbl[i].offset);
1384 stats[i].value = val;
1391 * DPDK callback to reset extended statistics.
1394 * Pointer to Ethernet device structure.
1397 mrvl_xstats_reset(struct rte_eth_dev *dev)
1399 mrvl_stats_reset(dev);
1403 * DPDK callback to get extended statistics names.
1405 * @param dev (unused)
1406 * Pointer to Ethernet device structure.
1407 * @param xstats_names
1408 * Pointer to xstats names table.
1410 * Size of the xstats names table.
1412 * Number of read names.
1415 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1416 struct rte_eth_xstat_name *xstats_names,
1422 return RTE_DIM(mrvl_xstats_tbl);
1424 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1425 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name,
1426 RTE_ETH_XSTATS_NAME_SIZE);
1432 * DPDK callback to get information about the device.
1435 * Pointer to Ethernet device structure (unused).
1437 * Info structure output buffer.
1440 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1441 struct rte_eth_dev_info *info)
1443 info->speed_capa = ETH_LINK_SPEED_10M |
1444 ETH_LINK_SPEED_100M |
1448 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1449 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1450 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1452 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1453 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1454 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1456 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1457 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1458 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1460 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1461 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1463 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1464 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1466 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1467 ETH_RSS_NONFRAG_IPV4_TCP |
1468 ETH_RSS_NONFRAG_IPV4_UDP;
1470 /* By default packets are dropped if no descriptors are available */
1471 info->default_rxconf.rx_drop_en = 1;
1473 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1479 * Return supported packet types.
1482 * Pointer to Ethernet device structure (unused).
1485 * Const pointer to the table with supported packet types.
1487 static const uint32_t *
1488 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1490 static const uint32_t ptypes[] = {
1492 RTE_PTYPE_L2_ETHER_VLAN,
1493 RTE_PTYPE_L2_ETHER_QINQ,
1495 RTE_PTYPE_L3_IPV4_EXT,
1496 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1498 RTE_PTYPE_L3_IPV6_EXT,
1499 RTE_PTYPE_L2_ETHER_ARP,
1508 * DPDK callback to get information about specific receive queue.
1511 * Pointer to Ethernet device structure.
1512 * @param rx_queue_id
1513 * Receive queue index.
1515 * Receive queue information structure.
1517 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1518 struct rte_eth_rxq_info *qinfo)
1520 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1521 struct mrvl_priv *priv = dev->data->dev_private;
1522 int inq = priv->rxq_map[rx_queue_id].inq;
1523 int tc = priv->rxq_map[rx_queue_id].tc;
1524 struct pp2_ppio_tc_params *tc_params =
1525 &priv->ppio_params.inqs_params.tcs_params[tc];
1528 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1532 * DPDK callback to get information about specific transmit queue.
1535 * Pointer to Ethernet device structure.
1536 * @param tx_queue_id
1537 * Transmit queue index.
1539 * Transmit queue information structure.
1541 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1542 struct rte_eth_txq_info *qinfo)
1544 struct mrvl_priv *priv = dev->data->dev_private;
1545 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1548 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1549 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1553 * DPDK callback to Configure a VLAN filter.
1556 * Pointer to Ethernet device structure.
1558 * VLAN ID to filter.
1563 * 0 on success, negative error value otherwise.
1566 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1568 struct mrvl_priv *priv = dev->data->dev_private;
1576 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1577 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1581 * Release buffers to hardware bpool (buffer-pool)
1584 * Receive queue pointer.
1586 * Number of buffers to release to bpool.
1589 * 0 on success, negative error value otherwise.
1592 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1594 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1595 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1597 unsigned int core_id;
1598 struct pp2_hif *hif;
1599 struct pp2_bpool *bpool;
1601 core_id = rte_lcore_id();
1602 if (core_id == LCORE_ID_ANY)
1605 hif = mrvl_get_hif(rxq->priv, core_id);
1609 bpool = rxq->priv->bpool;
1611 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1615 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1617 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1619 for (i = 0; i < num; i++) {
1620 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1621 != cookie_addr_high) {
1623 "mbuf virtual addr high 0x%lx out of range",
1624 (uint64_t)mbufs[i] >> 32);
1628 entries[i].buff.addr =
1629 rte_mbuf_data_iova_default(mbufs[i]);
1630 entries[i].buff.cookie = (uint64_t)mbufs[i];
1631 entries[i].bpool = bpool;
1634 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1635 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1642 for (; i < num; i++)
1643 rte_pktmbuf_free(mbufs[i]);
1649 * DPDK callback to configure the receive queue.
1652 * Pointer to Ethernet device structure.
1656 * Number of descriptors to configure in queue.
1658 * NUMA socket on which memory must be allocated.
1660 * Thresholds parameters.
1662 * Memory pool for buffer allocations.
1665 * 0 on success, negative error value otherwise.
1668 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1669 unsigned int socket,
1670 const struct rte_eth_rxconf *conf,
1671 struct rte_mempool *mp)
1673 struct mrvl_priv *priv = dev->data->dev_private;
1674 struct mrvl_rxq *rxq;
1675 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp);
1676 uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1680 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1682 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1684 * Unknown TC mapping, mapping will not have a correct queue.
1686 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1687 idx, priv->ppio_id);
1691 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS;
1692 if (frame_size < max_rx_pkt_len) {
1694 "Mbuf size must be increased to %u bytes to hold up "
1695 "to %u bytes of data.",
1696 buf_size + max_rx_pkt_len - frame_size,
1698 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1699 MRVL_LOG(INFO, "Setting max rx pkt len to %u",
1700 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1703 if (dev->data->rx_queues[idx]) {
1704 rte_free(dev->data->rx_queues[idx]);
1705 dev->data->rx_queues[idx] = NULL;
1708 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1714 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1715 rxq->queue_id = idx;
1716 rxq->port_id = dev->data->port_id;
1717 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1719 tc = priv->rxq_map[rxq->queue_id].tc,
1720 inq = priv->rxq_map[rxq->queue_id].inq;
1721 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1724 ret = mrvl_fill_bpool(rxq, desc);
1730 priv->bpool_init_size += desc;
1732 dev->data->rx_queues[idx] = rxq;
1738 * DPDK callback to release the receive queue.
1741 * Generic receive queue pointer.
1744 mrvl_rx_queue_release(void *rxq)
1746 struct mrvl_rxq *q = rxq;
1747 struct pp2_ppio_tc_params *tc_params;
1748 int i, num, tc, inq;
1749 struct pp2_hif *hif;
1750 unsigned int core_id = rte_lcore_id();
1752 if (core_id == LCORE_ID_ANY)
1758 hif = mrvl_get_hif(q->priv, core_id);
1763 tc = q->priv->rxq_map[q->queue_id].tc;
1764 inq = q->priv->rxq_map[q->queue_id].inq;
1765 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1766 num = tc_params->inqs_params[inq].size;
1767 for (i = 0; i < num; i++) {
1768 struct pp2_buff_inf inf;
1771 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1772 addr = cookie_addr_high | inf.cookie;
1773 rte_pktmbuf_free((struct rte_mbuf *)addr);
1780 * DPDK callback to configure the transmit queue.
1783 * Pointer to Ethernet device structure.
1785 * Transmit queue index.
1787 * Number of descriptors to configure in the queue.
1789 * NUMA socket on which memory must be allocated.
1791 * Tx queue configuration parameters.
1794 * 0 on success, negative error value otherwise.
1797 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1798 unsigned int socket,
1799 const struct rte_eth_txconf *conf)
1801 struct mrvl_priv *priv = dev->data->dev_private;
1802 struct mrvl_txq *txq;
1804 if (dev->data->tx_queues[idx]) {
1805 rte_free(dev->data->tx_queues[idx]);
1806 dev->data->tx_queues[idx] = NULL;
1809 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1814 txq->queue_id = idx;
1815 txq->port_id = dev->data->port_id;
1816 txq->tx_deferred_start = conf->tx_deferred_start;
1817 dev->data->tx_queues[idx] = txq;
1819 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1825 * DPDK callback to release the transmit queue.
1828 * Generic transmit queue pointer.
1831 mrvl_tx_queue_release(void *txq)
1833 struct mrvl_txq *q = txq;
1842 * DPDK callback to get flow control configuration.
1845 * Pointer to Ethernet device structure.
1847 * Pointer to the flow control configuration.
1850 * 0 on success, negative error value otherwise.
1853 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1855 struct mrvl_priv *priv = dev->data->dev_private;
1861 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1863 MRVL_LOG(ERR, "Failed to read rx pause state");
1867 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1873 * DPDK callback to set flow control configuration.
1876 * Pointer to Ethernet device structure.
1878 * Pointer to the flow control configuration.
1881 * 0 on success, negative error value otherwise.
1884 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1886 struct mrvl_priv *priv = dev->data->dev_private;
1891 if (fc_conf->high_water ||
1892 fc_conf->low_water ||
1893 fc_conf->pause_time ||
1894 fc_conf->mac_ctrl_frame_fwd ||
1896 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1901 if (fc_conf->mode == RTE_FC_NONE ||
1902 fc_conf->mode == RTE_FC_RX_PAUSE) {
1905 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1906 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1909 "Failed to change flowctrl on RX side");
1918 * Update RSS hash configuration
1921 * Pointer to Ethernet device structure.
1923 * Pointer to RSS configuration.
1926 * 0 on success, negative error value otherwise.
1929 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1930 struct rte_eth_rss_conf *rss_conf)
1932 struct mrvl_priv *priv = dev->data->dev_private;
1937 return mrvl_configure_rss(priv, rss_conf);
1941 * DPDK callback to get RSS hash configuration.
1944 * Pointer to Ethernet device structure.
1946 * Pointer to RSS configuration.
1952 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1953 struct rte_eth_rss_conf *rss_conf)
1955 struct mrvl_priv *priv = dev->data->dev_private;
1956 enum pp2_ppio_hash_type hash_type =
1957 priv->ppio_params.inqs_params.hash_type;
1959 rss_conf->rss_key = NULL;
1961 if (hash_type == PP2_PPIO_HASH_T_NONE)
1962 rss_conf->rss_hf = 0;
1963 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1964 rss_conf->rss_hf = ETH_RSS_IPV4;
1965 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1966 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1967 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1968 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1974 * DPDK callback to get rte_flow callbacks.
1977 * Pointer to the device structure.
1981 * Flow filter operation.
1983 * Pointer to pass the flow ops.
1986 * 0 on success, negative error value otherwise.
1989 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1990 enum rte_filter_type filter_type,
1991 enum rte_filter_op filter_op, void *arg)
1993 switch (filter_type) {
1994 case RTE_ETH_FILTER_GENERIC:
1995 if (filter_op != RTE_ETH_FILTER_GET)
1997 *(const void **)arg = &mrvl_flow_ops;
2000 MRVL_LOG(WARNING, "Filter type (%d) not supported",
2007 * DPDK callback to get rte_mtr callbacks.
2010 * Pointer to the device structure.
2012 * Pointer to pass the mtr ops.
2018 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2020 *(const void **)ops = &mrvl_mtr_ops;
2026 * DPDK callback to get rte_tm callbacks.
2029 * Pointer to the device structure.
2031 * Pointer to pass the tm ops.
2037 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2039 *(const void **)ops = &mrvl_tm_ops;
2044 static const struct eth_dev_ops mrvl_ops = {
2045 .dev_configure = mrvl_dev_configure,
2046 .dev_start = mrvl_dev_start,
2047 .dev_stop = mrvl_dev_stop,
2048 .dev_set_link_up = mrvl_dev_set_link_up,
2049 .dev_set_link_down = mrvl_dev_set_link_down,
2050 .dev_close = mrvl_dev_close,
2051 .link_update = mrvl_link_update,
2052 .promiscuous_enable = mrvl_promiscuous_enable,
2053 .allmulticast_enable = mrvl_allmulticast_enable,
2054 .promiscuous_disable = mrvl_promiscuous_disable,
2055 .allmulticast_disable = mrvl_allmulticast_disable,
2056 .mac_addr_remove = mrvl_mac_addr_remove,
2057 .mac_addr_add = mrvl_mac_addr_add,
2058 .mac_addr_set = mrvl_mac_addr_set,
2059 .mtu_set = mrvl_mtu_set,
2060 .stats_get = mrvl_stats_get,
2061 .stats_reset = mrvl_stats_reset,
2062 .xstats_get = mrvl_xstats_get,
2063 .xstats_reset = mrvl_xstats_reset,
2064 .xstats_get_names = mrvl_xstats_get_names,
2065 .dev_infos_get = mrvl_dev_infos_get,
2066 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
2067 .rxq_info_get = mrvl_rxq_info_get,
2068 .txq_info_get = mrvl_txq_info_get,
2069 .vlan_filter_set = mrvl_vlan_filter_set,
2070 .tx_queue_start = mrvl_tx_queue_start,
2071 .tx_queue_stop = mrvl_tx_queue_stop,
2072 .rx_queue_setup = mrvl_rx_queue_setup,
2073 .rx_queue_release = mrvl_rx_queue_release,
2074 .tx_queue_setup = mrvl_tx_queue_setup,
2075 .tx_queue_release = mrvl_tx_queue_release,
2076 .flow_ctrl_get = mrvl_flow_ctrl_get,
2077 .flow_ctrl_set = mrvl_flow_ctrl_set,
2078 .rss_hash_update = mrvl_rss_hash_update,
2079 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
2080 .filter_ctrl = mrvl_eth_filter_ctrl,
2081 .mtr_ops_get = mrvl_mtr_ops_get,
2082 .tm_ops_get = mrvl_tm_ops_get,
2086 * Return packet type information and l3/l4 offsets.
2089 * Pointer to the received packet descriptor.
2096 * Packet type information.
2098 static inline uint64_t
2099 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2100 uint8_t *l3_offset, uint8_t *l4_offset)
2102 enum pp2_inq_l3_type l3_type;
2103 enum pp2_inq_l4_type l4_type;
2104 enum pp2_inq_vlan_tag vlan_tag;
2105 uint64_t packet_type;
2107 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2108 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2109 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
2111 packet_type = RTE_PTYPE_L2_ETHER;
2114 case PP2_INQ_VLAN_TAG_SINGLE:
2115 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
2117 case PP2_INQ_VLAN_TAG_DOUBLE:
2118 case PP2_INQ_VLAN_TAG_TRIPLE:
2119 packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
2126 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2127 packet_type |= RTE_PTYPE_L3_IPV4;
2129 case PP2_INQ_L3_TYPE_IPV4_OK:
2130 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2132 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2133 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2135 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2136 packet_type |= RTE_PTYPE_L3_IPV6;
2138 case PP2_INQ_L3_TYPE_IPV6_EXT:
2139 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2141 case PP2_INQ_L3_TYPE_ARP:
2142 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2144 * In case of ARP l4_offset is set to wrong value.
2145 * Set it to proper one so that later on mbuf->l3_len can be
2146 * calculated subtracting l4_offset and l3_offset.
2148 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2151 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
2156 case PP2_INQ_L4_TYPE_TCP:
2157 packet_type |= RTE_PTYPE_L4_TCP;
2159 case PP2_INQ_L4_TYPE_UDP:
2160 packet_type |= RTE_PTYPE_L4_UDP;
2163 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
2171 * Get offload information from the received packet descriptor.
2174 * Pointer to the received packet descriptor.
2177 * Mbuf offload flags.
2179 static inline uint64_t
2180 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
2183 enum pp2_inq_desc_status status;
2185 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2186 if (unlikely(status != PP2_DESC_ERR_OK))
2187 flags = PKT_RX_IP_CKSUM_BAD;
2189 flags = PKT_RX_IP_CKSUM_GOOD;
2191 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2192 if (unlikely(status != PP2_DESC_ERR_OK))
2193 flags |= PKT_RX_L4_CKSUM_BAD;
2195 flags |= PKT_RX_L4_CKSUM_GOOD;
2201 * DPDK callback for receive.
2204 * Generic pointer to the receive queue.
2206 * Array to store received packets.
2208 * Maximum number of packets in array.
2211 * Number of packets successfully received.
2214 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2216 struct mrvl_rxq *q = rxq;
2217 struct pp2_ppio_desc descs[nb_pkts];
2218 struct pp2_bpool *bpool;
2219 int i, ret, rx_done = 0;
2221 struct pp2_hif *hif;
2222 unsigned int core_id = rte_lcore_id();
2224 hif = mrvl_get_hif(q->priv, core_id);
2226 if (unlikely(!q->priv->ppio || !hif))
2229 bpool = q->priv->bpool;
2231 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2232 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2233 if (unlikely(ret < 0)) {
2234 MRVL_LOG(ERR, "Failed to receive packets");
2237 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2239 for (i = 0; i < nb_pkts; i++) {
2240 struct rte_mbuf *mbuf;
2241 uint8_t l3_offset, l4_offset;
2242 enum pp2_inq_desc_status status;
2245 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2246 struct pp2_ppio_desc *pref_desc;
2249 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2250 pref_addr = cookie_addr_high |
2251 pp2_ppio_inq_desc_get_cookie(pref_desc);
2252 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2253 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2256 addr = cookie_addr_high |
2257 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2258 mbuf = (struct rte_mbuf *)addr;
2259 rte_pktmbuf_reset(mbuf);
2261 /* drop packet in case of mac, overrun or resource error */
2262 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2263 if (unlikely(status != PP2_DESC_ERR_OK)) {
2264 struct pp2_buff_inf binf = {
2265 .addr = rte_mbuf_data_iova_default(mbuf),
2266 .cookie = (uint64_t)mbuf,
2269 pp2_bpool_put_buff(hif, bpool, &binf);
2270 mrvl_port_bpool_size
2271 [bpool->pp2_id][bpool->id][core_id]++;
2276 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2277 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2278 mbuf->data_len = mbuf->pkt_len;
2279 mbuf->port = q->port_id;
2281 mrvl_desc_to_packet_type_and_offset(&descs[i],
2284 mbuf->l2_len = l3_offset;
2285 mbuf->l3_len = l4_offset - l3_offset;
2287 if (likely(q->cksum_enabled))
2288 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2290 rx_pkts[rx_done++] = mbuf;
2291 q->bytes_recv += mbuf->pkt_len;
2294 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2295 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2297 if (unlikely(num <= q->priv->bpool_min_size ||
2298 (!rx_done && num < q->priv->bpool_init_size))) {
2299 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2301 MRVL_LOG(ERR, "Failed to fill bpool");
2302 } else if (unlikely(num > q->priv->bpool_max_size)) {
2304 int pkt_to_remove = num - q->priv->bpool_init_size;
2305 struct rte_mbuf *mbuf;
2306 struct pp2_buff_inf buff;
2309 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
2310 bpool->pp2_id, q->priv->ppio->port_id,
2311 bpool->id, pkt_to_remove, num,
2312 q->priv->bpool_init_size);
2314 for (i = 0; i < pkt_to_remove; i++) {
2315 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2318 mbuf = (struct rte_mbuf *)
2319 (cookie_addr_high | buff.cookie);
2320 rte_pktmbuf_free(mbuf);
2322 mrvl_port_bpool_size
2323 [bpool->pp2_id][bpool->id][core_id] -= i;
2325 rte_spinlock_unlock(&q->priv->lock);
2332 * Prepare offload information.
2336 * @param packet_type
2337 * Packet type bitfield.
2339 * Pointer to the pp2_ouq_l3_type structure.
2341 * Pointer to the pp2_outq_l4_type structure.
2342 * @param gen_l3_cksum
2343 * Will be set to 1 in case l3 checksum is computed.
2345 * Will be set to 1 in case l4 checksum is computed.
2348 * 0 on success, negative error value otherwise.
2351 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2352 enum pp2_outq_l3_type *l3_type,
2353 enum pp2_outq_l4_type *l4_type,
2358 * Based on ol_flags prepare information
2359 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2362 if (ol_flags & PKT_TX_IPV4) {
2363 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2364 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2365 } else if (ol_flags & PKT_TX_IPV6) {
2366 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2367 /* no checksum for ipv6 header */
2370 /* if something different then stop processing */
2374 ol_flags &= PKT_TX_L4_MASK;
2375 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2376 ol_flags == PKT_TX_TCP_CKSUM) {
2377 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2379 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2380 ol_flags == PKT_TX_UDP_CKSUM) {
2381 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2384 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2385 /* no checksum for other type */
2393 * Release already sent buffers to bpool (buffer-pool).
2396 * Pointer to the port structure.
2398 * Pointer to the MUSDK hardware interface.
2400 * Pointer to the shadow queue.
2404 * Force releasing packets.
2407 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2408 unsigned int core_id, struct mrvl_shadow_txq *sq,
2411 struct buff_release_entry *entry;
2412 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2415 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2417 sq->num_to_release += nb_done;
2419 if (likely(!force &&
2420 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2423 nb_done = sq->num_to_release;
2424 sq->num_to_release = 0;
2426 for (i = 0; i < nb_done; i++) {
2427 entry = &sq->ent[sq->tail + num];
2428 if (unlikely(!entry->buff.addr)) {
2430 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2431 sq->tail, (u64)entry->buff.cookie,
2432 (u64)entry->buff.addr);
2437 if (unlikely(!entry->bpool)) {
2438 struct rte_mbuf *mbuf;
2440 mbuf = (struct rte_mbuf *)
2441 (cookie_addr_high | entry->buff.cookie);
2442 rte_pktmbuf_free(mbuf);
2447 mrvl_port_bpool_size
2448 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2450 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2455 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2457 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2464 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2465 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2471 * DPDK callback for transmit.
2474 * Generic pointer transmit queue.
2476 * Packets to transmit.
2478 * Number of packets in array.
2481 * Number of packets successfully transmitted.
2484 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2486 struct mrvl_txq *q = txq;
2487 struct mrvl_shadow_txq *sq;
2488 struct pp2_hif *hif;
2489 struct pp2_ppio_desc descs[nb_pkts];
2490 unsigned int core_id = rte_lcore_id();
2491 int i, ret, bytes_sent = 0;
2492 uint16_t num, sq_free_size;
2495 hif = mrvl_get_hif(q->priv, core_id);
2496 sq = &q->shadow_txqs[core_id];
2498 if (unlikely(!q->priv->ppio || !hif))
2502 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2503 sq, q->queue_id, 0);
2505 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2506 if (unlikely(nb_pkts > sq_free_size)) {
2508 "No room in shadow queue for %d packets! %d packets will be sent.",
2509 nb_pkts, sq_free_size);
2510 nb_pkts = sq_free_size;
2513 for (i = 0; i < nb_pkts; i++) {
2514 struct rte_mbuf *mbuf = tx_pkts[i];
2515 int gen_l3_cksum, gen_l4_cksum;
2516 enum pp2_outq_l3_type l3_type;
2517 enum pp2_outq_l4_type l4_type;
2519 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2520 struct rte_mbuf *pref_pkt_hdr;
2522 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2523 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2524 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2527 mrvl_fill_shadowq(sq, mbuf);
2528 mrvl_fill_desc(&descs[i], mbuf);
2530 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2532 * in case unsupported ol_flags were passed
2533 * do not update descriptor offload information
2535 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2536 &l3_type, &l4_type, &gen_l3_cksum,
2541 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2543 mbuf->l2_len + mbuf->l3_len,
2544 gen_l3_cksum, gen_l4_cksum);
2548 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2549 /* number of packets that were not sent */
2550 if (unlikely(num > nb_pkts)) {
2551 for (i = nb_pkts; i < num; i++) {
2552 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2553 MRVL_PP2_TX_SHADOWQ_MASK;
2554 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2556 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2558 sq->size -= num - nb_pkts;
2561 q->bytes_sent += bytes_sent;
2566 /** DPDK callback for S/G transmit.
2569 * Generic pointer transmit queue.
2571 * Packets to transmit.
2573 * Number of packets in array.
2576 * Number of packets successfully transmitted.
2579 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
2582 struct mrvl_txq *q = txq;
2583 struct mrvl_shadow_txq *sq;
2584 struct pp2_hif *hif;
2585 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS];
2586 struct pp2_ppio_sg_pkts pkts;
2587 uint8_t frags[nb_pkts];
2588 unsigned int core_id = rte_lcore_id();
2589 int i, j, ret, bytes_sent = 0;
2590 int tail, tail_first;
2591 uint16_t num, sq_free_size;
2592 uint16_t nb_segs, total_descs = 0;
2595 hif = mrvl_get_hif(q->priv, core_id);
2596 sq = &q->shadow_txqs[core_id];
2600 if (unlikely(!q->priv->ppio || !hif))
2604 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2605 sq, q->queue_id, 0);
2607 /* Save shadow queue free size */
2608 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2611 for (i = 0; i < nb_pkts; i++) {
2612 struct rte_mbuf *mbuf = tx_pkts[i];
2613 struct rte_mbuf *seg = NULL;
2614 int gen_l3_cksum, gen_l4_cksum;
2615 enum pp2_outq_l3_type l3_type;
2616 enum pp2_outq_l4_type l4_type;
2618 nb_segs = mbuf->nb_segs;
2620 total_descs += nb_segs;
2623 * Check if total_descs does not exceed
2624 * shadow queue free size
2626 if (unlikely(total_descs > sq_free_size)) {
2627 total_descs -= nb_segs;
2629 "No room in shadow queue for %d packets! "
2630 "%d packets will be sent.\n",
2635 /* Check if nb_segs does not exceed the max nb of desc per
2638 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) {
2639 total_descs -= nb_segs;
2641 "Too many segments. Packet won't be sent.\n");
2645 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2646 struct rte_mbuf *pref_pkt_hdr;
2648 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2649 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2650 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2653 pkts.frags[pkts.num] = nb_segs;
2657 for (j = 0; j < nb_segs - 1; j++) {
2658 /* For the subsequent segments, set shadow queue
2661 mrvl_fill_shadowq(sq, NULL);
2662 mrvl_fill_desc(&descs[tail], seg);
2667 /* Put first mbuf info in last shadow queue entry */
2668 mrvl_fill_shadowq(sq, mbuf);
2669 /* Update descriptor with last segment */
2670 mrvl_fill_desc(&descs[tail++], seg);
2672 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2673 /* In case unsupported ol_flags were passed
2674 * do not update descriptor offload information
2676 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2677 &l3_type, &l4_type, &gen_l3_cksum,
2682 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type,
2683 l4_type, mbuf->l2_len,
2684 mbuf->l2_len + mbuf->l3_len,
2685 gen_l3_cksum, gen_l4_cksum);
2689 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs,
2690 &total_descs, &pkts);
2691 /* number of packets that were not sent */
2692 if (unlikely(num > total_descs)) {
2693 for (i = total_descs; i < num; i++) {
2694 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2695 MRVL_PP2_TX_SHADOWQ_MASK;
2697 addr = sq->ent[sq->head].buff.cookie;
2700 rte_pktmbuf_pkt_len((struct rte_mbuf *)
2701 (cookie_addr_high | addr));
2703 sq->size -= num - total_descs;
2707 q->bytes_sent += bytes_sent;
2713 * Initialize packet processor.
2716 * 0 on success, negative error value otherwise.
2721 struct pp2_init_params init_params;
2723 memset(&init_params, 0, sizeof(init_params));
2724 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2725 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2726 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2728 return pp2_init(&init_params);
2732 * Deinitialize packet processor.
2735 * 0 on success, negative error value otherwise.
2738 mrvl_deinit_pp2(void)
2744 * Create private device structure.
2747 * Pointer to the port name passed in the initialization parameters.
2750 * Pointer to the newly allocated private device structure.
2752 static struct mrvl_priv *
2753 mrvl_priv_create(const char *dev_name)
2755 struct pp2_bpool_params bpool_params;
2756 char match[MRVL_MATCH_LEN];
2757 struct mrvl_priv *priv;
2760 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2764 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2765 &priv->pp_id, &priv->ppio_id);
2769 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2770 PP2_BPOOL_NUM_POOLS);
2773 priv->bpool_bit = bpool_bit;
2775 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2777 memset(&bpool_params, 0, sizeof(bpool_params));
2778 bpool_params.match = match;
2779 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2780 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2782 goto out_clear_bpool_bit;
2784 priv->ppio_params.type = PP2_PPIO_T_NIC;
2785 rte_spinlock_init(&priv->lock);
2788 out_clear_bpool_bit:
2789 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2796 * Create device representing Ethernet port.
2799 * Pointer to the port's name.
2802 * 0 on success, negative error value otherwise.
2805 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2807 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2808 struct rte_eth_dev *eth_dev;
2809 struct mrvl_priv *priv;
2812 eth_dev = rte_eth_dev_allocate(name);
2816 priv = mrvl_priv_create(name);
2821 eth_dev->data->dev_private = priv;
2823 eth_dev->data->mac_addrs =
2824 rte_zmalloc("mac_addrs",
2825 RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2826 if (!eth_dev->data->mac_addrs) {
2827 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2832 memset(&req, 0, sizeof(req));
2833 strcpy(req.ifr_name, name);
2834 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2838 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2839 req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN);
2841 eth_dev->data->kdrv = RTE_KDRV_NONE;
2842 eth_dev->device = &vdev->device;
2843 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2844 mrvl_set_tx_function(eth_dev);
2845 eth_dev->dev_ops = &mrvl_ops;
2847 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2848 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2850 rte_eth_dev_probing_finish(eth_dev);
2853 rte_eth_dev_release_port(eth_dev);
2859 * Callback used by rte_kvargs_process() during argument parsing.
2862 * Pointer to the parsed key (unused).
2864 * Pointer to the parsed value.
2866 * Pointer to the extra arguments which contains address of the
2867 * table of pointers to parsed interface names.
2873 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2876 struct mrvl_ifnames *ifnames = extra_args;
2878 ifnames->names[ifnames->idx++] = value;
2884 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2887 mrvl_deinit_hifs(void)
2891 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2893 pp2_hif_deinit(hifs[i]);
2895 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2896 memset(hifs, 0, sizeof(hifs));
2900 * DPDK callback to register the virtual device.
2903 * Pointer to the virtual device.
2906 * 0 on success, negative error value otherwise.
2909 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2911 struct rte_kvargs *kvlist;
2912 struct mrvl_ifnames ifnames;
2914 uint32_t i, ifnum, cfgnum;
2917 params = rte_vdev_device_args(vdev);
2921 kvlist = rte_kvargs_parse(params, valid_args);
2925 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2926 if (ifnum > RTE_DIM(ifnames.names))
2927 goto out_free_kvlist;
2930 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2931 mrvl_get_ifnames, &ifnames);
2935 * The below system initialization should be done only once,
2936 * on the first provided configuration file
2938 if (!mrvl_qos_cfg) {
2939 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2940 MRVL_LOG(INFO, "Parsing config file!");
2942 MRVL_LOG(ERR, "Cannot handle more than one config file!");
2943 goto out_free_kvlist;
2944 } else if (cfgnum == 1) {
2945 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2946 mrvl_get_qoscfg, &mrvl_qos_cfg);
2953 MRVL_LOG(INFO, "Perform MUSDK initializations");
2955 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
2957 goto out_free_kvlist;
2959 ret = mrvl_init_pp2();
2961 MRVL_LOG(ERR, "Failed to init PP!");
2962 rte_mvep_deinit(MVEP_MOD_T_PP2);
2963 goto out_free_kvlist;
2966 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2967 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2969 mrvl_lcore_first = RTE_MAX_LCORE;
2970 mrvl_lcore_last = 0;
2973 for (i = 0; i < ifnum; i++) {
2974 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
2975 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2981 rte_kvargs_free(kvlist);
2985 rte_pmd_mrvl_remove(vdev);
2988 rte_kvargs_free(kvlist);
2994 * DPDK callback to remove virtual device.
2997 * Pointer to the removed virtual device.
3000 * 0 on success, negative error value otherwise.
3003 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
3007 RTE_ETH_FOREACH_DEV(port_id) {
3008 if (rte_eth_devices[port_id].device != &vdev->device)
3010 rte_eth_dev_close(port_id);
3016 static struct rte_vdev_driver pmd_mrvl_drv = {
3017 .probe = rte_pmd_mrvl_probe,
3018 .remove = rte_pmd_mrvl_remove,
3021 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
3022 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
3024 RTE_INIT(mrvl_init_log)
3026 mrvl_logtype = rte_log_register("pmd.net.mvpp2");
3027 if (mrvl_logtype >= 0)
3028 rte_log_set_level(mrvl_logtype, RTE_LOG_NOTICE);