1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #ifndef _MRVL_ETHDEV_H_
8 #define _MRVL_ETHDEV_H_
10 #include <rte_spinlock.h>
11 #include <rte_flow_driver.h>
12 #include <rte_mtr_driver.h>
13 #include <rte_tm_driver.h>
16 * container_of is defined by both DPDK and MUSDK,
17 * we'll declare only one version.
19 * Note that it is not used in this PMD anyway.
25 #include <env/mv_autogen_comp_flags.h>
26 #include <drivers/mv_pp2.h>
27 #include <drivers/mv_pp2_bpool.h>
28 #include <drivers/mv_pp2_cls.h>
29 #include <drivers/mv_pp2_hif.h>
30 #include <drivers/mv_pp2_ppio.h>
31 #include "env/mv_common.h" /* for BIT() */
33 /** Maximum number of rx queues per port */
34 #define MRVL_PP2_RXQ_MAX 32
36 /** Maximum number of tx queues per port */
37 #define MRVL_PP2_TXQ_MAX 8
39 /** Minimum number of descriptors in tx queue */
40 #define MRVL_PP2_TXD_MIN 16
42 /** Maximum number of descriptors in tx queue */
43 #define MRVL_PP2_TXD_MAX 2048
45 /** Tx queue descriptors alignment */
46 #define MRVL_PP2_TXD_ALIGN 16
48 /** Minimum number of descriptors in rx queue */
49 #define MRVL_PP2_RXD_MIN 16
51 /** Maximum number of descriptors in rx queue */
52 #define MRVL_PP2_RXD_MAX 2048
54 /** Rx queue descriptors alignment */
55 #define MRVL_PP2_RXD_ALIGN 16
57 /** Maximum number of descriptors in tx aggregated queue */
58 #define MRVL_PP2_AGGR_TXQD_MAX 2048
60 /** Maximum number of Traffic Classes. */
61 #define MRVL_PP2_TC_MAX 8
63 /** Packet offset inside RX buffer. */
64 #define MRVL_PKT_OFFS 64
66 /** Maximum number of descriptors in shadow queue. Must be power of 2 */
67 #define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX
69 /** Shadow queue size mask (since shadow queue size is power of 2) */
70 #define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1)
72 /** Minimum number of sent buffers to release from shadow queue to BM */
73 #define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64
75 /** Maximum length of a match string */
76 #define MRVL_MATCH_LEN 16
78 /** Parsed fields in processed rte_flow_item. */
79 enum mrvl_parsed_fields {
87 F_VLAN_TCI = BIT(5), /* not supported by MUSDK yet */
94 F_IP6_TC = BIT(10), /* not supported by MUSDK yet */
98 F_IP6_NEXT_HDR = BIT(14),
100 F_TCP_SPORT = BIT(15),
101 F_TCP_DPORT = BIT(16),
103 F_UDP_SPORT = BIT(17),
104 F_UDP_DPORT = BIT(18),
107 /** PMD-specific definition of a flow rule handle. */
110 LIST_ENTRY(rte_flow) next;
111 struct mrvl_mtr *mtr;
113 enum mrvl_parsed_fields pattern;
115 struct pp2_cls_tbl_rule rule;
116 struct pp2_cls_cos_desc cos;
117 struct pp2_cls_tbl_action action;
120 struct mrvl_mtr_profile {
121 LIST_ENTRY(mrvl_mtr_profile) next;
124 struct rte_mtr_meter_profile profile;
128 LIST_ENTRY(mrvl_mtr) next;
134 struct mrvl_mtr_profile *profile;
135 struct pp2_cls_plcr *plcr;
138 struct mrvl_tm_shaper_profile {
139 LIST_ENTRY(mrvl_tm_shaper_profile) next;
142 struct rte_tm_shaper_params params;
150 struct mrvl_tm_node {
151 LIST_ENTRY(mrvl_tm_node) next;
155 struct mrvl_tm_node *parent;
156 struct mrvl_tm_shaper_profile *profile;
162 /* Hot fields, used in fast path. */
163 struct pp2_bpool *bpool; /**< BPool pointer */
164 struct pp2_ppio *ppio; /**< Port handler pointer */
165 rte_spinlock_t lock; /**< Spinlock for checking bpool status */
166 uint16_t bpool_max_size; /**< BPool maximum size */
167 uint16_t bpool_min_size; /**< BPool minimum size */
168 uint16_t bpool_init_size; /**< Configured BPool size */
170 /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
172 uint8_t tc; /**< Traffic Class */
173 uint8_t inq; /**< Relative in-queue number */
174 } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
176 /* Configuration data, used sporadically. */
181 uint8_t uc_mc_flushed;
182 uint8_t vlan_flushed;
185 struct pp2_ppio_params ppio_params;
186 struct pp2_cls_qos_tbl_params qos_tbl_params;
187 struct pp2_cls_tbl *qos_tbl;
188 uint16_t nb_rx_queues;
190 struct pp2_cls_tbl_params cls_tbl_params;
191 struct pp2_cls_tbl *cls_tbl;
192 uint32_t cls_tbl_pattern;
193 LIST_HEAD(mrvl_flows, rte_flow) flows;
195 struct pp2_cls_plcr *default_policer;
197 LIST_HEAD(profiles, mrvl_mtr_profile) profiles;
198 LIST_HEAD(mtrs, mrvl_mtr) mtrs;
201 LIST_HEAD(shaper_profiles, mrvl_tm_shaper_profile) shaper_profiles;
202 LIST_HEAD(nodes, mrvl_tm_node) nodes;
206 /** Flow operations forward declaration. */
207 extern const struct rte_flow_ops mrvl_flow_ops;
209 /** Meter operations forward declaration. */
210 extern const struct rte_mtr_ops mrvl_mtr_ops;
212 /** Traffic manager operations forward declaration. */
213 extern const struct rte_tm_ops mrvl_tm_ops;
215 /** Current log type. */
216 extern int mrvl_logtype;
218 #define MRVL_LOG(level, fmt, args...) \
219 rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \
222 #endif /* _MRVL_ETHDEV_H_ */