1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
9 * vim:shiftwidth=8:noexpandtab
11 * @file dpdk/pmd/nfp_common.c
13 * Netronome vNIC DPDK Poll-Mode Driver: Common files
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
19 #include <rte_debug.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
23 #include <rte_ether.h>
24 #include <rte_malloc.h>
25 #include <rte_memzone.h>
26 #include <rte_mempool.h>
27 #include <rte_version.h>
28 #include <rte_string_fns.h>
29 #include <rte_alarm.h>
30 #include <rte_spinlock.h>
31 #include <rte_service_component.h>
33 #include "nfpcore/nfp_cpp.h"
34 #include "nfpcore/nfp_nffw.h"
35 #include "nfpcore/nfp_hwinfo.h"
36 #include "nfpcore/nfp_mip.h"
37 #include "nfpcore/nfp_rtsym.h"
38 #include "nfpcore/nfp_nsp.h"
40 #include "nfp_common.h"
44 #include "nfp_cpp_bridge.h"
46 #include <sys/types.h>
47 #include <sys/socket.h>
51 #include <sys/ioctl.h>
55 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
61 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
64 if (hw->qcp_cfg == NULL)
65 rte_panic("Bad configuration queue pointer\n");
67 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
70 wait.tv_nsec = 1000000;
72 PMD_DRV_LOG(DEBUG, "Polling for update ack...");
74 /* Poll update field, waiting for NFP to ack the config */
75 for (cnt = 0; ; cnt++) {
76 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
79 if (new & NFP_NET_CFG_UPDATE_ERR) {
80 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
83 if (cnt >= NFP_NET_POLL_TIMEOUT) {
84 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
85 " %dms", update, cnt);
86 rte_panic("Exiting\n");
88 nanosleep(&wait, 0); /* waiting for a 1ms */
90 PMD_DRV_LOG(DEBUG, "Ack DONE");
96 * @nn: device to reconfigure
97 * @ctrl: The value for the ctrl field in the BAR config
98 * @update: The value for the update field in the BAR config
100 * Write the update word to the BAR and ping the reconfig queue. Then poll
101 * until the firmware has acknowledged the update by zeroing the update word.
104 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
108 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
111 rte_spinlock_lock(&hw->reconfig_lock);
113 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
114 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
118 err = __nfp_net_reconfig(hw, update);
120 rte_spinlock_unlock(&hw->reconfig_lock);
126 * Reconfig errors imply situations where they can be handled.
127 * Otherwise, rte_panic is called inside __nfp_net_reconfig
129 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
135 * Configure an Ethernet device. This function must be invoked first
136 * before any other function in the Ethernet API. This function can
137 * also be re-invoked when a device is in the stopped state.
140 nfp_net_configure(struct rte_eth_dev *dev)
142 struct rte_eth_conf *dev_conf;
143 struct rte_eth_rxmode *rxmode;
144 struct rte_eth_txmode *txmode;
145 struct nfp_net_hw *hw;
147 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
150 * A DPDK app sends info about how many queues to use and how
151 * those queues need to be configured. This is used by the
152 * DPDK core and it makes sure no more queues than those
153 * advertised by the driver are requested. This function is
154 * called after that internal process
157 PMD_INIT_LOG(DEBUG, "Configure");
159 dev_conf = &dev->data->dev_conf;
160 rxmode = &dev_conf->rxmode;
161 txmode = &dev_conf->txmode;
163 if (rxmode->mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
164 rxmode->offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
166 /* Checking TX mode */
167 if (txmode->mq_mode) {
168 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
172 /* Checking RX mode */
173 if (rxmode->mq_mode & RTE_ETH_MQ_RX_RSS &&
174 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
175 PMD_INIT_LOG(INFO, "RSS not supported");
183 nfp_net_enable_queues(struct rte_eth_dev *dev)
185 struct nfp_net_hw *hw;
186 uint64_t enabled_queues = 0;
189 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
191 /* Enabling the required TX queues in the device */
192 for (i = 0; i < dev->data->nb_tx_queues; i++)
193 enabled_queues |= (1 << i);
195 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
199 /* Enabling the required RX queues in the device */
200 for (i = 0; i < dev->data->nb_rx_queues; i++)
201 enabled_queues |= (1 << i);
203 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
207 nfp_net_disable_queues(struct rte_eth_dev *dev)
209 struct nfp_net_hw *hw;
210 uint32_t new_ctrl, update = 0;
212 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
214 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
215 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
217 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
218 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
219 NFP_NET_CFG_UPDATE_MSIX;
221 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
222 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
224 /* If an error when reconfig we avoid to change hw state */
225 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
232 nfp_net_params_setup(struct nfp_net_hw *hw)
234 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
235 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
239 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
241 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
244 #define ETH_ADDR_LEN 6
247 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
251 for (i = 0; i < ETH_ADDR_LEN; i++)
256 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
258 uint32_t mac0 = *(uint32_t *)mac;
261 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
264 mac1 = *(uint16_t *)mac;
265 nn_writew(rte_cpu_to_be_16(mac1),
266 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
270 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
272 struct nfp_net_hw *hw;
273 uint32_t update, ctrl;
275 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
276 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
277 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
278 PMD_INIT_LOG(INFO, "MAC address unable to change when"
283 /* Writing new MAC to the specific port BAR address */
284 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
286 /* Signal the NIC about the change */
287 update = NFP_NET_CFG_UPDATE_MACADDR;
289 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
290 (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
291 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
292 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
293 PMD_INIT_LOG(INFO, "MAC address update failed");
300 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
301 struct rte_intr_handle *intr_handle)
303 struct nfp_net_hw *hw;
306 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
307 dev->data->nb_rx_queues)) {
308 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
309 " intr_vec", dev->data->nb_rx_queues);
313 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
315 if (rte_intr_type_get(intr_handle) == RTE_INTR_HANDLE_UIO) {
316 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
317 /* UIO just supports one queue and no LSC*/
318 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
319 if (rte_intr_vec_list_index_set(intr_handle, 0, 0))
322 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
323 for (i = 0; i < dev->data->nb_rx_queues; i++) {
325 * The first msix vector is reserved for non
328 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
329 if (rte_intr_vec_list_index_set(intr_handle, i,
332 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
333 rte_intr_vec_list_index_get(intr_handle,
338 /* Avoiding TX interrupts */
339 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
344 nfp_check_offloads(struct rte_eth_dev *dev)
346 struct nfp_net_hw *hw;
347 struct rte_eth_conf *dev_conf;
348 struct rte_eth_rxmode *rxmode;
349 struct rte_eth_txmode *txmode;
352 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
354 dev_conf = &dev->data->dev_conf;
355 rxmode = &dev_conf->rxmode;
356 txmode = &dev_conf->txmode;
358 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM) {
359 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
360 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
363 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {
364 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
365 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
368 hw->mtu = dev->data->mtu;
370 if (txmode->offloads & RTE_ETH_TX_OFFLOAD_VLAN_INSERT)
371 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
374 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
375 ctrl |= NFP_NET_CFG_CTRL_L2BC;
378 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
379 ctrl |= NFP_NET_CFG_CTRL_L2MC;
381 /* TX checksum offload */
382 if (txmode->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM ||
383 txmode->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM ||
384 txmode->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)
385 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
388 if (txmode->offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO) {
389 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
390 ctrl |= NFP_NET_CFG_CTRL_LSO;
392 ctrl |= NFP_NET_CFG_CTRL_LSO2;
396 if (txmode->offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
397 ctrl |= NFP_NET_CFG_CTRL_GATHER;
403 nfp_net_promisc_enable(struct rte_eth_dev *dev)
405 uint32_t new_ctrl, update = 0;
406 struct nfp_net_hw *hw;
409 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
411 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
413 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
414 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
418 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
419 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
423 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
424 update = NFP_NET_CFG_UPDATE_GEN;
427 * DPDK sets promiscuous mode on just after this call assuming
428 * it can not fail ...
430 ret = nfp_net_reconfig(hw, new_ctrl, update);
440 nfp_net_promisc_disable(struct rte_eth_dev *dev)
442 uint32_t new_ctrl, update = 0;
443 struct nfp_net_hw *hw;
446 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
448 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
449 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
453 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
454 update = NFP_NET_CFG_UPDATE_GEN;
457 * DPDK sets promiscuous mode off just before this call
458 * assuming it can not fail ...
460 ret = nfp_net_reconfig(hw, new_ctrl, update);
470 * return 0 means link status changed, -1 means not changed
472 * Wait to complete is needed as it can take up to 9 seconds to get the Link
476 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
478 struct nfp_net_hw *hw;
479 struct rte_eth_link link;
480 uint32_t nn_link_status;
483 static const uint32_t ls_to_ethtool[] = {
484 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = RTE_ETH_SPEED_NUM_NONE,
485 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = RTE_ETH_SPEED_NUM_NONE,
486 [NFP_NET_CFG_STS_LINK_RATE_1G] = RTE_ETH_SPEED_NUM_1G,
487 [NFP_NET_CFG_STS_LINK_RATE_10G] = RTE_ETH_SPEED_NUM_10G,
488 [NFP_NET_CFG_STS_LINK_RATE_25G] = RTE_ETH_SPEED_NUM_25G,
489 [NFP_NET_CFG_STS_LINK_RATE_40G] = RTE_ETH_SPEED_NUM_40G,
490 [NFP_NET_CFG_STS_LINK_RATE_50G] = RTE_ETH_SPEED_NUM_50G,
491 [NFP_NET_CFG_STS_LINK_RATE_100G] = RTE_ETH_SPEED_NUM_100G,
494 PMD_DRV_LOG(DEBUG, "Link update");
496 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
498 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
500 memset(&link, 0, sizeof(struct rte_eth_link));
502 if (nn_link_status & NFP_NET_CFG_STS_LINK)
503 link.link_status = RTE_ETH_LINK_UP;
505 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
507 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
508 NFP_NET_CFG_STS_LINK_RATE_MASK;
510 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
511 link.link_speed = RTE_ETH_SPEED_NUM_NONE;
513 link.link_speed = ls_to_ethtool[nn_link_status];
515 ret = rte_eth_linkstatus_set(dev, &link);
517 if (link.link_status)
518 PMD_DRV_LOG(INFO, "NIC Link is Up");
520 PMD_DRV_LOG(INFO, "NIC Link is Down");
526 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
529 struct nfp_net_hw *hw;
530 struct rte_eth_stats nfp_dev_stats;
532 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
534 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
536 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
538 /* reading per RX ring stats */
539 for (i = 0; i < dev->data->nb_rx_queues; i++) {
540 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
543 nfp_dev_stats.q_ipackets[i] =
544 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
546 nfp_dev_stats.q_ipackets[i] -=
547 hw->eth_stats_base.q_ipackets[i];
549 nfp_dev_stats.q_ibytes[i] =
550 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
552 nfp_dev_stats.q_ibytes[i] -=
553 hw->eth_stats_base.q_ibytes[i];
556 /* reading per TX ring stats */
557 for (i = 0; i < dev->data->nb_tx_queues; i++) {
558 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
561 nfp_dev_stats.q_opackets[i] =
562 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
564 nfp_dev_stats.q_opackets[i] -=
565 hw->eth_stats_base.q_opackets[i];
567 nfp_dev_stats.q_obytes[i] =
568 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
570 nfp_dev_stats.q_obytes[i] -=
571 hw->eth_stats_base.q_obytes[i];
574 nfp_dev_stats.ipackets =
575 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
577 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
579 nfp_dev_stats.ibytes =
580 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
582 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
584 nfp_dev_stats.opackets =
585 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
587 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
589 nfp_dev_stats.obytes =
590 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
592 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
594 /* reading general device stats */
595 nfp_dev_stats.ierrors =
596 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
598 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
600 nfp_dev_stats.oerrors =
601 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
603 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
605 /* RX ring mbuf allocation failures */
606 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
608 nfp_dev_stats.imissed =
609 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
611 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
614 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
621 nfp_net_stats_reset(struct rte_eth_dev *dev)
624 struct nfp_net_hw *hw;
626 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
629 * hw->eth_stats_base records the per counter starting point.
633 /* reading per RX ring stats */
634 for (i = 0; i < dev->data->nb_rx_queues; i++) {
635 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
638 hw->eth_stats_base.q_ipackets[i] =
639 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
641 hw->eth_stats_base.q_ibytes[i] =
642 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
645 /* reading per TX ring stats */
646 for (i = 0; i < dev->data->nb_tx_queues; i++) {
647 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
650 hw->eth_stats_base.q_opackets[i] =
651 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
653 hw->eth_stats_base.q_obytes[i] =
654 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
657 hw->eth_stats_base.ipackets =
658 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
660 hw->eth_stats_base.ibytes =
661 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
663 hw->eth_stats_base.opackets =
664 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
666 hw->eth_stats_base.obytes =
667 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
669 /* reading general device stats */
670 hw->eth_stats_base.ierrors =
671 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
673 hw->eth_stats_base.oerrors =
674 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
676 /* RX ring mbuf allocation failures */
677 dev->data->rx_mbuf_alloc_failed = 0;
679 hw->eth_stats_base.imissed =
680 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
686 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
688 struct nfp_net_hw *hw;
690 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
692 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
693 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
694 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
695 dev_info->max_rx_pktlen = hw->max_mtu;
696 /* Next should change when PF support is implemented */
697 dev_info->max_mac_addrs = 1;
699 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
700 dev_info->rx_offload_capa = RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
702 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
703 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
704 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
705 RTE_ETH_RX_OFFLOAD_TCP_CKSUM;
707 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
708 dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_VLAN_INSERT;
710 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
711 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
712 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
713 RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
715 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
716 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
718 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
719 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
721 dev_info->default_rxconf = (struct rte_eth_rxconf) {
723 .pthresh = DEFAULT_RX_PTHRESH,
724 .hthresh = DEFAULT_RX_HTHRESH,
725 .wthresh = DEFAULT_RX_WTHRESH,
727 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
731 dev_info->default_txconf = (struct rte_eth_txconf) {
733 .pthresh = DEFAULT_TX_PTHRESH,
734 .hthresh = DEFAULT_TX_HTHRESH,
735 .wthresh = DEFAULT_TX_WTHRESH,
737 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
738 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
741 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
742 .nb_max = NFP_NET_MAX_RX_DESC,
743 .nb_min = NFP_NET_MIN_RX_DESC,
744 .nb_align = NFP_ALIGN_RING_DESC,
747 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
748 .nb_max = NFP_NET_MAX_TX_DESC,
749 .nb_min = NFP_NET_MIN_TX_DESC,
750 .nb_align = NFP_ALIGN_RING_DESC,
751 .nb_seg_max = NFP_TX_MAX_SEG,
752 .nb_mtu_seg_max = NFP_TX_MAX_MTU_SEG,
755 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
756 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
758 dev_info->flow_type_rss_offloads = RTE_ETH_RSS_IPV4 |
759 RTE_ETH_RSS_NONFRAG_IPV4_TCP |
760 RTE_ETH_RSS_NONFRAG_IPV4_UDP |
762 RTE_ETH_RSS_NONFRAG_IPV6_TCP |
763 RTE_ETH_RSS_NONFRAG_IPV6_UDP;
765 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
766 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
769 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G |
770 RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G |
771 RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G;
777 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
779 static const uint32_t ptypes[] = {
780 /* refers to nfp_net_set_hash() */
781 RTE_PTYPE_INNER_L3_IPV4,
782 RTE_PTYPE_INNER_L3_IPV6,
783 RTE_PTYPE_INNER_L3_IPV6_EXT,
784 RTE_PTYPE_INNER_L4_MASK,
788 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
794 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
796 struct rte_pci_device *pci_dev;
797 struct nfp_net_hw *hw;
800 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
801 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
803 if (rte_intr_type_get(pci_dev->intr_handle) !=
807 /* Make sure all updates are written before un-masking */
809 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
810 NFP_NET_CFG_ICR_UNMASKED);
815 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
817 struct rte_pci_device *pci_dev;
818 struct nfp_net_hw *hw;
821 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
822 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
824 if (rte_intr_type_get(pci_dev->intr_handle) !=
828 /* Make sure all updates are written before un-masking */
830 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
835 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
837 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
838 struct rte_eth_link link;
840 rte_eth_linkstatus_get(dev, &link);
841 if (link.link_status)
842 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
843 dev->data->port_id, link.link_speed,
844 link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX
845 ? "full-duplex" : "half-duplex");
847 PMD_DRV_LOG(INFO, " Port %d: Link Down",
850 PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
851 pci_dev->addr.domain, pci_dev->addr.bus,
852 pci_dev->addr.devid, pci_dev->addr.function);
855 /* Interrupt configuration and handling */
858 * nfp_net_irq_unmask - Unmask an interrupt
860 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
861 * clear the ICR for the entry.
864 nfp_net_irq_unmask(struct rte_eth_dev *dev)
866 struct nfp_net_hw *hw;
867 struct rte_pci_device *pci_dev;
869 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
870 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
872 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
873 /* If MSI-X auto-masking is used, clear the entry */
875 rte_intr_ack(pci_dev->intr_handle);
877 /* Make sure all updates are written before un-masking */
879 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
880 NFP_NET_CFG_ICR_UNMASKED);
885 * Interrupt handler which shall be registered for alarm callback for delayed
886 * handling specific interrupt to wait for the stable nic state. As the NIC
887 * interrupt state is not stable for nfp after link is just down, it needs
888 * to wait 4 seconds to get the stable status.
890 * @param handle Pointer to interrupt handle.
891 * @param param The address of parameter (struct rte_eth_dev *)
896 nfp_net_dev_interrupt_delayed_handler(void *param)
898 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
900 nfp_net_link_update(dev, 0);
901 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
903 nfp_net_dev_link_status_print(dev);
906 nfp_net_irq_unmask(dev);
910 nfp_net_dev_interrupt_handler(void *param)
913 struct rte_eth_link link;
914 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
916 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
918 rte_eth_linkstatus_get(dev, &link);
920 nfp_net_link_update(dev, 0);
923 if (!link.link_status) {
924 /* handle it 1 sec later, wait it being stable */
925 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
928 /* handle it 4 sec later, wait it being stable */
929 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
932 if (rte_eal_alarm_set(timeout * 1000,
933 nfp_net_dev_interrupt_delayed_handler,
935 PMD_INIT_LOG(ERR, "Error setting alarm");
937 nfp_net_irq_unmask(dev);
942 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
944 struct nfp_net_hw *hw;
946 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
948 /* mtu setting is forbidden if port is started */
949 if (dev->data->dev_started) {
950 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
955 /* writing to configuration space */
956 nn_cfg_writel(hw, NFP_NET_CFG_MTU, mtu);
964 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
966 uint32_t new_ctrl, update;
967 struct nfp_net_hw *hw;
970 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
973 /* Enable vlan strip if it is not configured yet */
974 if ((mask & RTE_ETH_VLAN_STRIP_OFFLOAD) &&
975 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
976 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
978 /* Disable vlan strip just if it is configured */
979 if (!(mask & RTE_ETH_VLAN_STRIP_OFFLOAD) &&
980 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
981 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
986 update = NFP_NET_CFG_UPDATE_GEN;
988 ret = nfp_net_reconfig(hw, new_ctrl, update);
996 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
997 struct rte_eth_rss_reta_entry64 *reta_conf,
1000 uint32_t reta, mask;
1003 struct nfp_net_hw *hw =
1004 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
1007 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1008 "(%d) doesn't match the number hardware can supported "
1009 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
1014 * Update Redirection Table. There are 128 8bit-entries which can be
1015 * manage as 32 32bit-entries
1017 for (i = 0; i < reta_size; i += 4) {
1018 /* Handling 4 RSS entries per loop */
1019 idx = i / RTE_ETH_RETA_GROUP_SIZE;
1020 shift = i % RTE_ETH_RETA_GROUP_SIZE;
1021 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
1027 /* If all 4 entries were set, don't need read RETA register */
1029 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
1031 for (j = 0; j < 4; j++) {
1032 if (!(mask & (0x1 << j)))
1035 /* Clearing the entry bits */
1036 reta &= ~(0xFF << (8 * j));
1037 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
1039 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
1045 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
1047 nfp_net_reta_update(struct rte_eth_dev *dev,
1048 struct rte_eth_rss_reta_entry64 *reta_conf,
1051 struct nfp_net_hw *hw =
1052 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1059 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
1063 update = NFP_NET_CFG_UPDATE_RSS;
1065 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
1071 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
1073 nfp_net_reta_query(struct rte_eth_dev *dev,
1074 struct rte_eth_rss_reta_entry64 *reta_conf,
1080 struct nfp_net_hw *hw;
1082 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1087 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
1088 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1089 "(%d) doesn't match the number hardware can supported "
1090 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
1095 * Reading Redirection Table. There are 128 8bit-entries which can be
1096 * manage as 32 32bit-entries
1098 for (i = 0; i < reta_size; i += 4) {
1099 /* Handling 4 RSS entries per loop */
1100 idx = i / RTE_ETH_RETA_GROUP_SIZE;
1101 shift = i % RTE_ETH_RETA_GROUP_SIZE;
1102 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
1107 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
1109 for (j = 0; j < 4; j++) {
1110 if (!(mask & (0x1 << j)))
1112 reta_conf[idx].reta[shift + j] =
1113 (uint8_t)((reta >> (8 * j)) & 0xF);
1120 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
1121 struct rte_eth_rss_conf *rss_conf)
1123 struct nfp_net_hw *hw;
1125 uint32_t cfg_rss_ctrl = 0;
1129 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1131 /* Writing the key byte a byte */
1132 for (i = 0; i < rss_conf->rss_key_len; i++) {
1133 memcpy(&key, &rss_conf->rss_key[i], 1);
1134 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
1137 rss_hf = rss_conf->rss_hf;
1139 if (rss_hf & RTE_ETH_RSS_IPV4)
1140 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
1142 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP)
1143 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
1145 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP)
1146 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
1148 if (rss_hf & RTE_ETH_RSS_IPV6)
1149 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
1151 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP)
1152 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
1154 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP)
1155 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
1157 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
1158 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
1160 /* configuring where to apply the RSS hash */
1161 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
1163 /* Writing the key size */
1164 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
1170 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
1171 struct rte_eth_rss_conf *rss_conf)
1175 struct nfp_net_hw *hw;
1177 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1179 rss_hf = rss_conf->rss_hf;
1181 /* Checking if RSS is enabled */
1182 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
1183 if (rss_hf != 0) { /* Enable RSS? */
1184 PMD_DRV_LOG(ERR, "RSS unsupported");
1187 return 0; /* Nothing to do */
1190 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
1191 PMD_DRV_LOG(ERR, "hash key too long");
1195 nfp_net_rss_hash_write(dev, rss_conf);
1197 update = NFP_NET_CFG_UPDATE_RSS;
1199 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
1206 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
1207 struct rte_eth_rss_conf *rss_conf)
1210 uint32_t cfg_rss_ctrl;
1213 struct nfp_net_hw *hw;
1215 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1220 rss_hf = rss_conf->rss_hf;
1221 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
1223 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
1224 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP;
1226 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
1227 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP;
1229 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
1230 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP;
1232 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
1233 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP;
1235 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
1236 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP;
1238 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
1239 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV6_UDP;
1241 /* Propagate current RSS hash functions to caller */
1242 rss_conf->rss_hf = rss_hf;
1244 /* Reading the key size */
1245 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
1247 /* Reading the key byte a byte */
1248 for (i = 0; i < rss_conf->rss_key_len; i++) {
1249 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
1250 memcpy(&rss_conf->rss_key[i], &key, 1);
1257 nfp_net_rss_config_default(struct rte_eth_dev *dev)
1259 struct rte_eth_conf *dev_conf;
1260 struct rte_eth_rss_conf rss_conf;
1261 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
1262 uint16_t rx_queues = dev->data->nb_rx_queues;
1266 PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
1269 nfp_reta_conf[0].mask = ~0x0;
1270 nfp_reta_conf[1].mask = ~0x0;
1273 for (i = 0; i < 0x40; i += 8) {
1274 for (j = i; j < (i + 8); j++) {
1275 nfp_reta_conf[0].reta[j] = queue;
1276 nfp_reta_conf[1].reta[j] = queue++;
1280 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
1284 dev_conf = &dev->data->dev_conf;
1286 PMD_DRV_LOG(INFO, "wrong rss conf");
1289 rss_conf = dev_conf->rx_adv_conf.rss_conf;
1291 ret = nfp_net_rss_hash_write(dev, &rss_conf);
1296 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_init, init, NOTICE);
1297 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_driver, driver, NOTICE);
1300 * c-file-style: "Linux"
1301 * indent-tabs-mode: t