1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
9 * vim:shiftwidth=8:noexpandtab
11 * @file dpdk/pmd/nfp_common.c
13 * Netronome vNIC DPDK Poll-Mode Driver: Common files
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
19 #include <rte_debug.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
23 #include <rte_ether.h>
24 #include <rte_malloc.h>
25 #include <rte_memzone.h>
26 #include <rte_mempool.h>
27 #include <rte_version.h>
28 #include <rte_string_fns.h>
29 #include <rte_alarm.h>
30 #include <rte_spinlock.h>
31 #include <rte_service_component.h>
33 #include "nfpcore/nfp_cpp.h"
34 #include "nfpcore/nfp_nffw.h"
35 #include "nfpcore/nfp_hwinfo.h"
36 #include "nfpcore/nfp_mip.h"
37 #include "nfpcore/nfp_rtsym.h"
38 #include "nfpcore/nfp_nsp.h"
40 #include "nfp_common.h"
44 #include "nfp_cpp_bridge.h"
46 #include <sys/types.h>
47 #include <sys/socket.h>
51 #include <sys/ioctl.h>
55 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
61 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
64 if (hw->qcp_cfg == NULL)
65 rte_panic("Bad configuration queue pointer\n");
67 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
70 wait.tv_nsec = 1000000;
72 PMD_DRV_LOG(DEBUG, "Polling for update ack...");
74 /* Poll update field, waiting for NFP to ack the config */
75 for (cnt = 0; ; cnt++) {
76 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
79 if (new & NFP_NET_CFG_UPDATE_ERR) {
80 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
83 if (cnt >= NFP_NET_POLL_TIMEOUT) {
84 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
85 " %dms", update, cnt);
86 rte_panic("Exiting\n");
88 nanosleep(&wait, 0); /* waiting for a 1ms */
90 PMD_DRV_LOG(DEBUG, "Ack DONE");
96 * @nn: device to reconfigure
97 * @ctrl: The value for the ctrl field in the BAR config
98 * @update: The value for the update field in the BAR config
100 * Write the update word to the BAR and ping the reconfig queue. Then poll
101 * until the firmware has acknowledged the update by zeroing the update word.
104 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
108 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
111 rte_spinlock_lock(&hw->reconfig_lock);
113 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
114 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
118 err = __nfp_net_reconfig(hw, update);
120 rte_spinlock_unlock(&hw->reconfig_lock);
126 * Reconfig errors imply situations where they can be handled.
127 * Otherwise, rte_panic is called inside __nfp_net_reconfig
129 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
135 * Configure an Ethernet device. This function must be invoked first
136 * before any other function in the Ethernet API. This function can
137 * also be re-invoked when a device is in the stopped state.
140 nfp_net_configure(struct rte_eth_dev *dev)
142 struct rte_eth_conf *dev_conf;
143 struct rte_eth_rxmode *rxmode;
144 struct rte_eth_txmode *txmode;
145 struct nfp_net_hw *hw;
147 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
150 * A DPDK app sends info about how many queues to use and how
151 * those queues need to be configured. This is used by the
152 * DPDK core and it makes sure no more queues than those
153 * advertised by the driver are requested. This function is
154 * called after that internal process
157 PMD_INIT_LOG(DEBUG, "Configure");
159 dev_conf = &dev->data->dev_conf;
160 rxmode = &dev_conf->rxmode;
161 txmode = &dev_conf->txmode;
163 if (rxmode->mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
164 rxmode->offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
166 /* Checking TX mode */
167 if (txmode->mq_mode) {
168 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
172 /* Checking RX mode */
173 if (rxmode->mq_mode & RTE_ETH_MQ_RX_RSS &&
174 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
175 PMD_INIT_LOG(INFO, "RSS not supported");
183 nfp_net_enable_queues(struct rte_eth_dev *dev)
185 struct nfp_net_hw *hw;
186 uint64_t enabled_queues = 0;
189 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
191 /* Enabling the required TX queues in the device */
192 for (i = 0; i < dev->data->nb_tx_queues; i++)
193 enabled_queues |= (1 << i);
195 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
199 /* Enabling the required RX queues in the device */
200 for (i = 0; i < dev->data->nb_rx_queues; i++)
201 enabled_queues |= (1 << i);
203 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
207 nfp_net_disable_queues(struct rte_eth_dev *dev)
209 struct nfp_net_hw *hw;
210 uint32_t new_ctrl, update = 0;
212 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
214 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
215 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
217 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
218 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
219 NFP_NET_CFG_UPDATE_MSIX;
221 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
222 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
224 /* If an error when reconfig we avoid to change hw state */
225 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
232 nfp_net_params_setup(struct nfp_net_hw *hw)
234 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
235 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
239 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
241 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
244 #define ETH_ADDR_LEN 6
247 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
251 for (i = 0; i < ETH_ADDR_LEN; i++)
256 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
258 uint32_t mac0 = *(uint32_t *)mac;
261 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
264 mac1 = *(uint16_t *)mac;
265 nn_writew(rte_cpu_to_be_16(mac1),
266 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
270 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
272 struct nfp_net_hw *hw;
273 uint32_t update, ctrl;
275 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
276 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
277 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
278 PMD_INIT_LOG(INFO, "MAC address unable to change when"
283 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
284 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
287 /* Writing new MAC to the specific port BAR address */
288 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
290 /* Signal the NIC about the change */
291 update = NFP_NET_CFG_UPDATE_MACADDR;
293 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
294 (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
295 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
296 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
297 PMD_INIT_LOG(INFO, "MAC address update failed");
304 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
305 struct rte_intr_handle *intr_handle)
307 struct nfp_net_hw *hw;
310 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
311 dev->data->nb_rx_queues)) {
312 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
313 " intr_vec", dev->data->nb_rx_queues);
317 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
319 if (rte_intr_type_get(intr_handle) == RTE_INTR_HANDLE_UIO) {
320 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
321 /* UIO just supports one queue and no LSC*/
322 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
323 if (rte_intr_vec_list_index_set(intr_handle, 0, 0))
326 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
327 for (i = 0; i < dev->data->nb_rx_queues; i++) {
329 * The first msix vector is reserved for non
332 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
333 if (rte_intr_vec_list_index_set(intr_handle, i,
336 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
337 rte_intr_vec_list_index_get(intr_handle,
342 /* Avoiding TX interrupts */
343 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
348 nfp_check_offloads(struct rte_eth_dev *dev)
350 struct nfp_net_hw *hw;
351 struct rte_eth_conf *dev_conf;
352 struct rte_eth_rxmode *rxmode;
353 struct rte_eth_txmode *txmode;
356 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
358 dev_conf = &dev->data->dev_conf;
359 rxmode = &dev_conf->rxmode;
360 txmode = &dev_conf->txmode;
362 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM) {
363 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
364 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
367 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {
368 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
369 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
372 hw->mtu = dev->data->mtu;
374 if (txmode->offloads & RTE_ETH_TX_OFFLOAD_VLAN_INSERT)
375 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
378 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
379 ctrl |= NFP_NET_CFG_CTRL_L2BC;
382 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
383 ctrl |= NFP_NET_CFG_CTRL_L2MC;
385 /* TX checksum offload */
386 if (txmode->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM ||
387 txmode->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM ||
388 txmode->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)
389 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
392 if (txmode->offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO) {
393 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
394 ctrl |= NFP_NET_CFG_CTRL_LSO;
396 ctrl |= NFP_NET_CFG_CTRL_LSO2;
400 if (txmode->offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
401 ctrl |= NFP_NET_CFG_CTRL_GATHER;
407 nfp_net_promisc_enable(struct rte_eth_dev *dev)
409 uint32_t new_ctrl, update = 0;
410 struct nfp_net_hw *hw;
413 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
415 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
417 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
418 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
422 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
423 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
427 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
428 update = NFP_NET_CFG_UPDATE_GEN;
431 * DPDK sets promiscuous mode on just after this call assuming
432 * it can not fail ...
434 ret = nfp_net_reconfig(hw, new_ctrl, update);
444 nfp_net_promisc_disable(struct rte_eth_dev *dev)
446 uint32_t new_ctrl, update = 0;
447 struct nfp_net_hw *hw;
450 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
452 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
453 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
457 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
458 update = NFP_NET_CFG_UPDATE_GEN;
461 * DPDK sets promiscuous mode off just before this call
462 * assuming it can not fail ...
464 ret = nfp_net_reconfig(hw, new_ctrl, update);
474 * return 0 means link status changed, -1 means not changed
476 * Wait to complete is needed as it can take up to 9 seconds to get the Link
480 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
482 struct nfp_net_hw *hw;
483 struct rte_eth_link link;
484 uint32_t nn_link_status;
487 static const uint32_t ls_to_ethtool[] = {
488 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = RTE_ETH_SPEED_NUM_NONE,
489 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = RTE_ETH_SPEED_NUM_NONE,
490 [NFP_NET_CFG_STS_LINK_RATE_1G] = RTE_ETH_SPEED_NUM_1G,
491 [NFP_NET_CFG_STS_LINK_RATE_10G] = RTE_ETH_SPEED_NUM_10G,
492 [NFP_NET_CFG_STS_LINK_RATE_25G] = RTE_ETH_SPEED_NUM_25G,
493 [NFP_NET_CFG_STS_LINK_RATE_40G] = RTE_ETH_SPEED_NUM_40G,
494 [NFP_NET_CFG_STS_LINK_RATE_50G] = RTE_ETH_SPEED_NUM_50G,
495 [NFP_NET_CFG_STS_LINK_RATE_100G] = RTE_ETH_SPEED_NUM_100G,
498 PMD_DRV_LOG(DEBUG, "Link update");
500 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
502 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
504 memset(&link, 0, sizeof(struct rte_eth_link));
506 if (nn_link_status & NFP_NET_CFG_STS_LINK)
507 link.link_status = RTE_ETH_LINK_UP;
509 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
511 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
512 NFP_NET_CFG_STS_LINK_RATE_MASK;
514 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
515 link.link_speed = RTE_ETH_SPEED_NUM_NONE;
517 link.link_speed = ls_to_ethtool[nn_link_status];
519 ret = rte_eth_linkstatus_set(dev, &link);
521 if (link.link_status)
522 PMD_DRV_LOG(INFO, "NIC Link is Up");
524 PMD_DRV_LOG(INFO, "NIC Link is Down");
530 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
533 struct nfp_net_hw *hw;
534 struct rte_eth_stats nfp_dev_stats;
536 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
538 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
540 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
542 /* reading per RX ring stats */
543 for (i = 0; i < dev->data->nb_rx_queues; i++) {
544 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
547 nfp_dev_stats.q_ipackets[i] =
548 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
550 nfp_dev_stats.q_ipackets[i] -=
551 hw->eth_stats_base.q_ipackets[i];
553 nfp_dev_stats.q_ibytes[i] =
554 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
556 nfp_dev_stats.q_ibytes[i] -=
557 hw->eth_stats_base.q_ibytes[i];
560 /* reading per TX ring stats */
561 for (i = 0; i < dev->data->nb_tx_queues; i++) {
562 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
565 nfp_dev_stats.q_opackets[i] =
566 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
568 nfp_dev_stats.q_opackets[i] -=
569 hw->eth_stats_base.q_opackets[i];
571 nfp_dev_stats.q_obytes[i] =
572 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
574 nfp_dev_stats.q_obytes[i] -=
575 hw->eth_stats_base.q_obytes[i];
578 nfp_dev_stats.ipackets =
579 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
581 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
583 nfp_dev_stats.ibytes =
584 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
586 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
588 nfp_dev_stats.opackets =
589 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
591 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
593 nfp_dev_stats.obytes =
594 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
596 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
598 /* reading general device stats */
599 nfp_dev_stats.ierrors =
600 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
602 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
604 nfp_dev_stats.oerrors =
605 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
607 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
609 /* RX ring mbuf allocation failures */
610 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
612 nfp_dev_stats.imissed =
613 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
615 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
618 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
625 nfp_net_stats_reset(struct rte_eth_dev *dev)
628 struct nfp_net_hw *hw;
630 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 * hw->eth_stats_base records the per counter starting point.
637 /* reading per RX ring stats */
638 for (i = 0; i < dev->data->nb_rx_queues; i++) {
639 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
642 hw->eth_stats_base.q_ipackets[i] =
643 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
645 hw->eth_stats_base.q_ibytes[i] =
646 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
649 /* reading per TX ring stats */
650 for (i = 0; i < dev->data->nb_tx_queues; i++) {
651 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
654 hw->eth_stats_base.q_opackets[i] =
655 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
657 hw->eth_stats_base.q_obytes[i] =
658 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
661 hw->eth_stats_base.ipackets =
662 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
664 hw->eth_stats_base.ibytes =
665 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
667 hw->eth_stats_base.opackets =
668 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
670 hw->eth_stats_base.obytes =
671 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
673 /* reading general device stats */
674 hw->eth_stats_base.ierrors =
675 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
677 hw->eth_stats_base.oerrors =
678 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
680 /* RX ring mbuf allocation failures */
681 dev->data->rx_mbuf_alloc_failed = 0;
683 hw->eth_stats_base.imissed =
684 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
690 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
692 struct nfp_net_hw *hw;
694 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
696 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
697 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
698 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
699 dev_info->max_rx_pktlen = hw->max_mtu;
700 /* Next should change when PF support is implemented */
701 dev_info->max_mac_addrs = 1;
703 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
704 dev_info->rx_offload_capa = RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
706 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
707 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
708 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
709 RTE_ETH_RX_OFFLOAD_TCP_CKSUM;
711 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
712 dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_VLAN_INSERT;
714 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
715 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
716 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
717 RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
719 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
720 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
722 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
723 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
725 dev_info->default_rxconf = (struct rte_eth_rxconf) {
727 .pthresh = DEFAULT_RX_PTHRESH,
728 .hthresh = DEFAULT_RX_HTHRESH,
729 .wthresh = DEFAULT_RX_WTHRESH,
731 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
735 dev_info->default_txconf = (struct rte_eth_txconf) {
737 .pthresh = DEFAULT_TX_PTHRESH,
738 .hthresh = DEFAULT_TX_HTHRESH,
739 .wthresh = DEFAULT_TX_WTHRESH,
741 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
742 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
745 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
746 .nb_max = NFP_NET_MAX_RX_DESC,
747 .nb_min = NFP_NET_MIN_RX_DESC,
748 .nb_align = NFP_ALIGN_RING_DESC,
751 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
752 .nb_max = NFP_NET_MAX_TX_DESC,
753 .nb_min = NFP_NET_MIN_TX_DESC,
754 .nb_align = NFP_ALIGN_RING_DESC,
755 .nb_seg_max = NFP_TX_MAX_SEG,
756 .nb_mtu_seg_max = NFP_TX_MAX_MTU_SEG,
759 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
760 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
762 dev_info->flow_type_rss_offloads = RTE_ETH_RSS_IPV4 |
763 RTE_ETH_RSS_NONFRAG_IPV4_TCP |
764 RTE_ETH_RSS_NONFRAG_IPV4_UDP |
766 RTE_ETH_RSS_NONFRAG_IPV6_TCP |
767 RTE_ETH_RSS_NONFRAG_IPV6_UDP;
769 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
770 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
773 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G |
774 RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G |
775 RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G;
781 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
783 static const uint32_t ptypes[] = {
784 /* refers to nfp_net_set_hash() */
785 RTE_PTYPE_INNER_L3_IPV4,
786 RTE_PTYPE_INNER_L3_IPV6,
787 RTE_PTYPE_INNER_L3_IPV6_EXT,
788 RTE_PTYPE_INNER_L4_MASK,
792 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
798 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
800 struct rte_pci_device *pci_dev;
801 struct nfp_net_hw *hw;
804 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
805 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
807 if (rte_intr_type_get(pci_dev->intr_handle) !=
811 /* Make sure all updates are written before un-masking */
813 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
814 NFP_NET_CFG_ICR_UNMASKED);
819 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
821 struct rte_pci_device *pci_dev;
822 struct nfp_net_hw *hw;
825 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
826 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
828 if (rte_intr_type_get(pci_dev->intr_handle) !=
832 /* Make sure all updates are written before un-masking */
834 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
839 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
841 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
842 struct rte_eth_link link;
844 rte_eth_linkstatus_get(dev, &link);
845 if (link.link_status)
846 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
847 dev->data->port_id, link.link_speed,
848 link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX
849 ? "full-duplex" : "half-duplex");
851 PMD_DRV_LOG(INFO, " Port %d: Link Down",
854 PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
855 pci_dev->addr.domain, pci_dev->addr.bus,
856 pci_dev->addr.devid, pci_dev->addr.function);
859 /* Interrupt configuration and handling */
862 * nfp_net_irq_unmask - Unmask an interrupt
864 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
865 * clear the ICR for the entry.
868 nfp_net_irq_unmask(struct rte_eth_dev *dev)
870 struct nfp_net_hw *hw;
871 struct rte_pci_device *pci_dev;
873 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
874 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
876 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
877 /* If MSI-X auto-masking is used, clear the entry */
879 rte_intr_ack(pci_dev->intr_handle);
881 /* Make sure all updates are written before un-masking */
883 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
884 NFP_NET_CFG_ICR_UNMASKED);
889 * Interrupt handler which shall be registered for alarm callback for delayed
890 * handling specific interrupt to wait for the stable nic state. As the NIC
891 * interrupt state is not stable for nfp after link is just down, it needs
892 * to wait 4 seconds to get the stable status.
894 * @param handle Pointer to interrupt handle.
895 * @param param The address of parameter (struct rte_eth_dev *)
900 nfp_net_dev_interrupt_delayed_handler(void *param)
902 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
904 nfp_net_link_update(dev, 0);
905 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
907 nfp_net_dev_link_status_print(dev);
910 nfp_net_irq_unmask(dev);
914 nfp_net_dev_interrupt_handler(void *param)
917 struct rte_eth_link link;
918 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
920 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
922 rte_eth_linkstatus_get(dev, &link);
924 nfp_net_link_update(dev, 0);
927 if (!link.link_status) {
928 /* handle it 1 sec later, wait it being stable */
929 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
932 /* handle it 4 sec later, wait it being stable */
933 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
936 if (rte_eal_alarm_set(timeout * 1000,
937 nfp_net_dev_interrupt_delayed_handler,
939 PMD_INIT_LOG(ERR, "Error setting alarm");
941 nfp_net_irq_unmask(dev);
946 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
948 struct nfp_net_hw *hw;
950 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
952 /* mtu setting is forbidden if port is started */
953 if (dev->data->dev_started) {
954 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
959 /* writing to configuration space */
960 nn_cfg_writel(hw, NFP_NET_CFG_MTU, mtu);
968 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
970 uint32_t new_ctrl, update;
971 struct nfp_net_hw *hw;
974 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
977 /* Enable vlan strip if it is not configured yet */
978 if ((mask & RTE_ETH_VLAN_STRIP_OFFLOAD) &&
979 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
980 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
982 /* Disable vlan strip just if it is configured */
983 if (!(mask & RTE_ETH_VLAN_STRIP_OFFLOAD) &&
984 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
985 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
990 update = NFP_NET_CFG_UPDATE_GEN;
992 ret = nfp_net_reconfig(hw, new_ctrl, update);
1000 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
1001 struct rte_eth_rss_reta_entry64 *reta_conf,
1004 uint32_t reta, mask;
1007 struct nfp_net_hw *hw =
1008 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1010 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
1011 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1012 "(%d) doesn't match the number hardware can supported "
1013 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
1018 * Update Redirection Table. There are 128 8bit-entries which can be
1019 * manage as 32 32bit-entries
1021 for (i = 0; i < reta_size; i += 4) {
1022 /* Handling 4 RSS entries per loop */
1023 idx = i / RTE_ETH_RETA_GROUP_SIZE;
1024 shift = i % RTE_ETH_RETA_GROUP_SIZE;
1025 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
1031 /* If all 4 entries were set, don't need read RETA register */
1033 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
1035 for (j = 0; j < 4; j++) {
1036 if (!(mask & (0x1 << j)))
1039 /* Clearing the entry bits */
1040 reta &= ~(0xFF << (8 * j));
1041 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
1043 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
1049 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
1051 nfp_net_reta_update(struct rte_eth_dev *dev,
1052 struct rte_eth_rss_reta_entry64 *reta_conf,
1055 struct nfp_net_hw *hw =
1056 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1063 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
1067 update = NFP_NET_CFG_UPDATE_RSS;
1069 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
1075 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
1077 nfp_net_reta_query(struct rte_eth_dev *dev,
1078 struct rte_eth_rss_reta_entry64 *reta_conf,
1084 struct nfp_net_hw *hw;
1086 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1088 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1091 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
1092 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1093 "(%d) doesn't match the number hardware can supported "
1094 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
1099 * Reading Redirection Table. There are 128 8bit-entries which can be
1100 * manage as 32 32bit-entries
1102 for (i = 0; i < reta_size; i += 4) {
1103 /* Handling 4 RSS entries per loop */
1104 idx = i / RTE_ETH_RETA_GROUP_SIZE;
1105 shift = i % RTE_ETH_RETA_GROUP_SIZE;
1106 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
1111 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
1113 for (j = 0; j < 4; j++) {
1114 if (!(mask & (0x1 << j)))
1116 reta_conf[idx].reta[shift + j] =
1117 (uint8_t)((reta >> (8 * j)) & 0xF);
1124 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
1125 struct rte_eth_rss_conf *rss_conf)
1127 struct nfp_net_hw *hw;
1129 uint32_t cfg_rss_ctrl = 0;
1133 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1135 /* Writing the key byte a byte */
1136 for (i = 0; i < rss_conf->rss_key_len; i++) {
1137 memcpy(&key, &rss_conf->rss_key[i], 1);
1138 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
1141 rss_hf = rss_conf->rss_hf;
1143 if (rss_hf & RTE_ETH_RSS_IPV4)
1144 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
1146 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP)
1147 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
1149 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP)
1150 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
1152 if (rss_hf & RTE_ETH_RSS_IPV6)
1153 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
1155 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP)
1156 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
1158 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP)
1159 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
1161 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
1162 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
1164 /* configuring where to apply the RSS hash */
1165 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
1167 /* Writing the key size */
1168 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
1174 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
1175 struct rte_eth_rss_conf *rss_conf)
1179 struct nfp_net_hw *hw;
1181 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1183 rss_hf = rss_conf->rss_hf;
1185 /* Checking if RSS is enabled */
1186 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
1187 if (rss_hf != 0) { /* Enable RSS? */
1188 PMD_DRV_LOG(ERR, "RSS unsupported");
1191 return 0; /* Nothing to do */
1194 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
1195 PMD_DRV_LOG(ERR, "hash key too long");
1199 nfp_net_rss_hash_write(dev, rss_conf);
1201 update = NFP_NET_CFG_UPDATE_RSS;
1203 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
1210 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
1211 struct rte_eth_rss_conf *rss_conf)
1214 uint32_t cfg_rss_ctrl;
1217 struct nfp_net_hw *hw;
1219 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1221 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1224 rss_hf = rss_conf->rss_hf;
1225 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
1227 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
1228 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP;
1230 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
1231 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP;
1233 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
1234 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP;
1236 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
1237 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP;
1239 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
1240 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP;
1242 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
1243 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV6_UDP;
1245 /* Propagate current RSS hash functions to caller */
1246 rss_conf->rss_hf = rss_hf;
1248 /* Reading the key size */
1249 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
1251 /* Reading the key byte a byte */
1252 for (i = 0; i < rss_conf->rss_key_len; i++) {
1253 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
1254 memcpy(&rss_conf->rss_key[i], &key, 1);
1261 nfp_net_rss_config_default(struct rte_eth_dev *dev)
1263 struct rte_eth_conf *dev_conf;
1264 struct rte_eth_rss_conf rss_conf;
1265 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
1266 uint16_t rx_queues = dev->data->nb_rx_queues;
1270 PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
1273 nfp_reta_conf[0].mask = ~0x0;
1274 nfp_reta_conf[1].mask = ~0x0;
1277 for (i = 0; i < 0x40; i += 8) {
1278 for (j = i; j < (i + 8); j++) {
1279 nfp_reta_conf[0].reta[j] = queue;
1280 nfp_reta_conf[1].reta[j] = queue++;
1284 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
1288 dev_conf = &dev->data->dev_conf;
1290 PMD_DRV_LOG(INFO, "wrong rss conf");
1293 rss_conf = dev_conf->rx_adv_conf.rss_conf;
1295 ret = nfp_net_rss_hash_write(dev, &rss_conf);
1300 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_init, init, NOTICE);
1301 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_driver, driver, NOTICE);
1304 * c-file-style: "Linux"
1305 * indent-tabs-mode: t