1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
7 * vim:shiftwidth=8:noexpandtab
9 * @file dpdk/pmd/nfp_net_pmd.h
11 * Netronome NFP_NET PMD
14 #ifndef _NFP_COMMON_H_
15 #define _NFP_COMMON_H_
17 #define NFP_NET_PMD_VERSION "0.1"
18 #define PCI_VENDOR_ID_NETRONOME 0x19ee
19 #define PCI_DEVICE_ID_NFP4000_PF_NIC 0x4000
20 #define PCI_DEVICE_ID_NFP6000_PF_NIC 0x6000
21 #define PCI_DEVICE_ID_NFP6000_VF_NIC 0x6003
23 /* Forward declaration */
24 struct nfp_net_adapter;
26 #define NFP_TX_MAX_SEG UINT8_MAX
27 #define NFP_TX_MAX_MTU_SEG 8
30 #define NFP_NET_CRTL_BAR 0
31 #define NFP_NET_TX_BAR 2
32 #define NFP_NET_RX_BAR 2
33 #define NFP_QCP_QUEUE_AREA_SZ 0x80000
35 /* Macros for accessing the Queue Controller Peripheral 'CSRs' */
36 #define NFP_QCP_QUEUE_OFF(_x) ((_x) * 0x800)
37 #define NFP_QCP_QUEUE_ADD_RPTR 0x0000
38 #define NFP_QCP_QUEUE_ADD_WPTR 0x0004
39 #define NFP_QCP_QUEUE_STS_LO 0x0008
40 #define NFP_QCP_QUEUE_STS_LO_READPTR_mask (0x3ffff)
41 #define NFP_QCP_QUEUE_STS_HI 0x000c
42 #define NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask (0x3ffff)
44 /* The offset of the queue controller queues in the PCIe Target */
45 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
47 /* Maximum value which can be added to a queue with one transaction */
48 #define NFP_QCP_MAX_ADD 0x7f
50 /* Interrupt definitions */
51 #define NFP_NET_IRQ_LSC_IDX 0
53 /* Default values for RX/TX configuration */
54 #define DEFAULT_RX_FREE_THRESH 32
55 #define DEFAULT_RX_PTHRESH 8
56 #define DEFAULT_RX_HTHRESH 8
57 #define DEFAULT_RX_WTHRESH 0
59 #define DEFAULT_TX_RS_THRESH 32
60 #define DEFAULT_TX_FREE_THRESH 32
61 #define DEFAULT_TX_PTHRESH 32
62 #define DEFAULT_TX_HTHRESH 0
63 #define DEFAULT_TX_WTHRESH 0
64 #define DEFAULT_TX_RSBIT_THRESH 32
66 /* Alignment for dma zones */
67 #define NFP_MEMZONE_ALIGN 128
70 * This is used by the reconfig protocol. It sets the maximum time waiting in
71 * milliseconds before a reconfig timeout happens.
73 #define NFP_NET_POLL_TIMEOUT 5000
75 #define NFP_QCP_QUEUE_ADDR_SZ (0x800)
77 #define NFP_NET_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
78 #define NFP_NET_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
80 /* Version number helper defines */
81 #define NFD_CFG_CLASS_VER_msk 0xff
82 #define NFD_CFG_CLASS_VER_shf 24
83 #define NFD_CFG_CLASS_VER(x) (((x) & 0xff) << 24)
84 #define NFD_CFG_CLASS_VER_of(x) (((x) >> 24) & 0xff)
85 #define NFD_CFG_CLASS_TYPE_msk 0xff
86 #define NFD_CFG_CLASS_TYPE_shf 16
87 #define NFD_CFG_CLASS_TYPE(x) (((x) & 0xff) << 16)
88 #define NFD_CFG_CLASS_TYPE_of(x) (((x) >> 16) & 0xff)
89 #define NFD_CFG_MAJOR_VERSION_msk 0xff
90 #define NFD_CFG_MAJOR_VERSION_shf 8
91 #define NFD_CFG_MAJOR_VERSION(x) (((x) & 0xff) << 8)
92 #define NFD_CFG_MAJOR_VERSION_of(x) (((x) >> 8) & 0xff)
93 #define NFD_CFG_MINOR_VERSION_msk 0xff
94 #define NFD_CFG_MINOR_VERSION_shf 0
95 #define NFD_CFG_MINOR_VERSION(x) (((x) & 0xff) << 0)
96 #define NFD_CFG_MINOR_VERSION_of(x) (((x) >> 0) & 0xff)
98 /* Number of supported physical ports */
99 #define NFP_MAX_PHYPORTS 12
101 /* Maximum supported NFP frame size (MTU + layer 2 headers) */
102 #define NFP_FRAME_SIZE_MAX 10048
104 #include <linux/types.h>
107 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
109 NFP_QCP_READ_PTR = 0,
114 /* Backpointer to associated pci device */
115 struct rte_pci_device *pci_dev;
117 /* Array of physical ports belonging to this PF */
118 struct nfp_net_hw *ports[NFP_MAX_PHYPORTS];
120 /* Current values for control */
128 rte_spinlock_t reconfig_lock;
133 uint16_t subsystem_device_id;
134 uint16_t subsystem_vendor_id;
135 #if defined(DSTQ_SELECTION)
137 uint16_t device_function;
142 struct nfp_cpp_area *ctrl_area;
143 struct nfp_cpp_area *hwqueues_area;
144 struct nfp_cpp_area *msix_area;
147 uint8_t total_phyports;
150 union eth_table_entry *eth_table;
152 struct nfp_hwinfo *hwinfo;
153 struct nfp_rtsym_table *sym_tbl;
154 uint32_t nfp_cpp_service_id;
158 /* Backpointer to the PF this port belongs to */
159 struct nfp_pf_dev *pf_dev;
161 /* Backpointer to the eth_dev of this port*/
162 struct rte_eth_dev *eth_dev;
164 /* Info from the firmware */
171 /* Current values for control */
182 rte_spinlock_t reconfig_lock;
184 uint32_t max_tx_queues;
185 uint32_t max_rx_queues;
189 uint16_t subsystem_device_id;
190 uint16_t subsystem_vendor_id;
191 #if defined(DSTQ_SELECTION)
193 uint16_t device_function;
197 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
199 /* Records starting point for counters */
200 struct rte_eth_stats eth_stats_base;
203 struct nfp_cpp_area *ctrl_area;
204 struct nfp_cpp_area *hwqueues_area;
205 struct nfp_cpp_area *msix_area;
208 /* Sequential physical port number */
210 /* Internal port number as seen from NFP */
214 union eth_table_entry *eth_table;
216 uint32_t nfp_cpp_service_id;
219 struct nfp_net_adapter {
220 struct nfp_net_hw hw;
223 static inline uint8_t nn_readb(volatile const void *addr)
225 return rte_read8(addr);
228 static inline void nn_writeb(uint8_t val, volatile void *addr)
230 rte_write8(val, addr);
233 static inline uint32_t nn_readl(volatile const void *addr)
235 return rte_read32(addr);
238 static inline void nn_writel(uint32_t val, volatile void *addr)
240 rte_write32(val, addr);
243 static inline void nn_writew(uint16_t val, volatile void *addr)
245 rte_write16(val, addr);
248 static inline uint64_t nn_readq(volatile void *addr)
250 const volatile uint32_t *p = addr;
253 high = nn_readl((volatile const void *)(p + 1));
254 low = nn_readl((volatile const void *)p);
256 return low + ((uint64_t)high << 32);
259 static inline void nn_writeq(uint64_t val, volatile void *addr)
261 nn_writel(val >> 32, (volatile char *)addr + 4);
262 nn_writel(val, addr);
266 * Functions to read/write from/to Config BAR
267 * Performs any endian conversion necessary.
269 static inline uint8_t
270 nn_cfg_readb(struct nfp_net_hw *hw, int off)
272 return nn_readb(hw->ctrl_bar + off);
276 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
278 nn_writeb(val, hw->ctrl_bar + off);
281 static inline uint32_t
282 nn_cfg_readl(struct nfp_net_hw *hw, int off)
284 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
288 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
290 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
293 static inline uint64_t
294 nn_cfg_readq(struct nfp_net_hw *hw, int off)
296 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
300 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
302 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
306 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
307 * @q: Base address for queue structure
308 * @ptr: Add to the Read or Write pointer
309 * @val: Value to add to the queue pointer
311 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
314 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
318 if (ptr == NFP_QCP_READ_PTR)
319 off = NFP_QCP_QUEUE_ADD_RPTR;
321 off = NFP_QCP_QUEUE_ADD_WPTR;
323 while (val > NFP_QCP_MAX_ADD) {
324 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
325 val -= NFP_QCP_MAX_ADD;
328 nn_writel(rte_cpu_to_le_32(val), q + off);
332 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
333 * @q: Base address for queue structure
334 * @ptr: Read or Write pointer
336 static inline uint32_t
337 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
342 if (ptr == NFP_QCP_READ_PTR)
343 off = NFP_QCP_QUEUE_STS_LO;
345 off = NFP_QCP_QUEUE_STS_HI;
347 val = rte_cpu_to_le_32(nn_readl(q + off));
349 if (ptr == NFP_QCP_READ_PTR)
350 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
352 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
355 /* Prototypes for common NFP functions */
356 int nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update);
357 int nfp_net_configure(struct rte_eth_dev *dev);
358 void nfp_net_enable_queues(struct rte_eth_dev *dev);
359 void nfp_net_disable_queues(struct rte_eth_dev *dev);
360 void nfp_net_params_setup(struct nfp_net_hw *hw);
361 void nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src);
362 void nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac);
363 int nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
364 int nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
365 struct rte_intr_handle *intr_handle);
366 uint32_t nfp_check_offloads(struct rte_eth_dev *dev);
367 int nfp_net_promisc_enable(struct rte_eth_dev *dev);
368 int nfp_net_promisc_disable(struct rte_eth_dev *dev);
369 int nfp_net_link_update(struct rte_eth_dev *dev,
370 __rte_unused int wait_to_complete);
371 int nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
372 int nfp_net_stats_reset(struct rte_eth_dev *dev);
373 int nfp_net_infos_get(struct rte_eth_dev *dev,
374 struct rte_eth_dev_info *dev_info);
375 const uint32_t *nfp_net_supported_ptypes_get(struct rte_eth_dev *dev);
376 int nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
377 int nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
378 void nfp_net_params_setup(struct nfp_net_hw *hw);
379 void nfp_net_cfg_queue_setup(struct nfp_net_hw *hw);
380 void nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src);
381 void nfp_net_dev_interrupt_handler(void *param);
382 void nfp_net_dev_interrupt_delayed_handler(void *param);
383 int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
384 int nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask);
385 int nfp_net_reta_update(struct rte_eth_dev *dev,
386 struct rte_eth_rss_reta_entry64 *reta_conf,
388 int nfp_net_reta_query(struct rte_eth_dev *dev,
389 struct rte_eth_rss_reta_entry64 *reta_conf,
391 int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
392 struct rte_eth_rss_conf *rss_conf);
393 int nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
394 struct rte_eth_rss_conf *rss_conf);
395 int nfp_net_rss_config_default(struct rte_eth_dev *dev);
397 #define NFP_NET_DEV_PRIVATE_TO_HW(adapter)\
398 (&((struct nfp_net_adapter *)adapter)->hw)
400 #define NFP_NET_DEV_PRIVATE_TO_PF(dev_priv)\
401 (((struct nfp_net_hw *)dev_priv)->pf_dev)
403 #endif /* _NFP_COMMON_H_ */
406 * c-file-style: "Linux"
407 * indent-tabs-mode: t