drivers/net/nfp/nfp_net.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  */
   7
   8 /*
   9  * vim:shiftwidth=8:noexpandtab
  10  *
  11  * @file dpdk/pmd/nfp_net.c
  12  *
  13  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  14  */
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_log.h>
  19 #include <rte_debug.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_dev.h>
  23 #include <rte_ether.h>
  24 #include <rte_malloc.h>
  25 #include <rte_memzone.h>
  26 #include <rte_mempool.h>
  27 #include <rte_version.h>
  28 #include <rte_string_fns.h>
  29 #include <rte_alarm.h>
  30 #include <rte_spinlock.h>
  31 #include <rte_service_component.h>
  32
  33 #include "nfpcore/nfp_cpp.h"
  34 #include "nfpcore/nfp_nffw.h"
  35 #include "nfpcore/nfp_hwinfo.h"
  36 #include "nfpcore/nfp_mip.h"
  37 #include "nfpcore/nfp_rtsym.h"
  38 #include "nfpcore/nfp_nsp.h"
  39
  40 #include "nfp_net_pmd.h"
  41 #include "nfp_net_logs.h"
  42 #include "nfp_net_ctrl.h"
  43
  44 #include <sys/types.h>
  45 #include <sys/socket.h>
  46 #include <sys/un.h>
  47 #include <unistd.h>
  48 #include <stdio.h>
  49 #include <sys/ioctl.h>
  50 #include <errno.h>
  51
  52 /* Prototypes */
  53 static int nfp_net_close(struct rte_eth_dev *dev);
  54 static int nfp_net_configure(struct rte_eth_dev *dev);
  55 static void nfp_net_dev_interrupt_handler(void *param);
  56 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  57 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  58 static int nfp_net_infos_get(struct rte_eth_dev *dev,
  59                              struct rte_eth_dev_info *dev_info);
  60 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  61 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  62 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
  63 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
  64 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  65 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  66                                        uint16_t queue_idx);
  67 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  68                                   uint16_t nb_pkts);
  69 static void nfp_net_rx_queue_release(void *rxq);
  70 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  71                                   uint16_t nb_desc, unsigned int socket_id,
  72                                   const struct rte_eth_rxconf *rx_conf,
  73                                   struct rte_mempool *mp);
  74 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  75 static void nfp_net_tx_queue_release(void *txq);
  76 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  77                                   uint16_t nb_desc, unsigned int socket_id,
  78                                   const struct rte_eth_txconf *tx_conf);
  79 static int nfp_net_start(struct rte_eth_dev *dev);
  80 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  81                               struct rte_eth_stats *stats);
  82 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
  83 static int nfp_net_stop(struct rte_eth_dev *dev);
  84 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  85                                   uint16_t nb_pkts);
  86
  87 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
  88 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
  89                                    struct rte_eth_rss_conf *rss_conf);
  90 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
  91                     struct rte_eth_rss_reta_entry64 *reta_conf,
  92                     uint16_t reta_size);
  93 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
  94                         struct rte_eth_rss_conf *rss_conf);
  95 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
  96                              struct rte_ether_addr *mac_addr);
  97
  98 /* The offset of the queue controller queues in the PCIe Target */
  99 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 100
 101 /* Maximum value which can be added to a queue with one transaction */
 102 #define NFP_QCP_MAX_ADD 0x7f
 103
 104 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 105         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 106
 107 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 108 enum nfp_qcp_ptr {
 109         NFP_QCP_READ_PTR = 0,
 110         NFP_QCP_WRITE_PTR
 111 };
 112
 113 /*
 114  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 115  * @q: Base address for queue structure
 116  * @ptr: Add to the Read or Write pointer
 117  * @val: Value to add to the queue pointer
 118  *
 119  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 120  */
 121 static inline void
 122 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 123 {
 124         uint32_t off;
 125
 126         if (ptr == NFP_QCP_READ_PTR)
 127                 off = NFP_QCP_QUEUE_ADD_RPTR;
 128         else
 129                 off = NFP_QCP_QUEUE_ADD_WPTR;
 130
 131         while (val > NFP_QCP_MAX_ADD) {
 132                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 133                 val -= NFP_QCP_MAX_ADD;
 134         }
 135
 136         nn_writel(rte_cpu_to_le_32(val), q + off);
 137 }
 138
 139 /*
 140  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 141  * @q:  Base address for queue structure
 142  * @ptr: Read or Write pointer
 143  */
 144 static inline uint32_t
 145 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 146 {
 147         uint32_t off;
 148         uint32_t val;
 149
 150         if (ptr == NFP_QCP_READ_PTR)
 151                 off = NFP_QCP_QUEUE_STS_LO;
 152         else
 153                 off = NFP_QCP_QUEUE_STS_HI;
 154
 155         val = rte_cpu_to_le_32(nn_readl(q + off));
 156
 157         if (ptr == NFP_QCP_READ_PTR)
 158                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 159         else
 160                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 161 }
 162
 163 /*
 164  * Functions to read/write from/to Config BAR
 165  * Performs any endian conversion necessary.
 166  */
 167 static inline uint8_t
 168 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 169 {
 170         return nn_readb(hw->ctrl_bar + off);
 171 }
 172
 173 static inline void
 174 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 175 {
 176         nn_writeb(val, hw->ctrl_bar + off);
 177 }
 178
 179 static inline uint32_t
 180 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 181 {
 182         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 183 }
 184
 185 static inline void
 186 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 187 {
 188         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 189 }
 190
 191 static inline uint64_t
 192 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 193 {
 194         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 195 }
 196
 197 static inline void
 198 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 199 {
 200         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 201 }
 202
 203 static void
 204 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 205 {
 206         unsigned i;
 207
 208         if (rxq->rxbufs == NULL)
 209                 return;
 210
 211         for (i = 0; i < rxq->rx_count; i++) {
 212                 if (rxq->rxbufs[i].mbuf) {
 213                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 214                         rxq->rxbufs[i].mbuf = NULL;
 215                 }
 216         }
 217 }
 218
 219 static void
 220 nfp_net_rx_queue_release(void *rx_queue)
 221 {
 222         struct nfp_net_rxq *rxq = rx_queue;
 223
 224         if (rxq) {
 225                 nfp_net_rx_queue_release_mbufs(rxq);
 226                 rte_free(rxq->rxbufs);
 227                 rte_free(rxq);
 228         }
 229 }
 230
 231 static void
 232 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 233 {
 234         nfp_net_rx_queue_release_mbufs(rxq);
 235         rxq->rd_p = 0;
 236         rxq->nb_rx_hold = 0;
 237 }
 238
 239 static void
 240 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 241 {
 242         unsigned i;
 243
 244         if (txq->txbufs == NULL)
 245                 return;
 246
 247         for (i = 0; i < txq->tx_count; i++) {
 248                 if (txq->txbufs[i].mbuf) {
 249                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 250                         txq->txbufs[i].mbuf = NULL;
 251                 }
 252         }
 253 }
 254
 255 static void
 256 nfp_net_tx_queue_release(void *tx_queue)
 257 {
 258         struct nfp_net_txq *txq = tx_queue;
 259
 260         if (txq) {
 261                 nfp_net_tx_queue_release_mbufs(txq);
 262                 rte_free(txq->txbufs);
 263                 rte_free(txq);
 264         }
 265 }
 266
 267 static void
 268 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 269 {
 270         nfp_net_tx_queue_release_mbufs(txq);
 271         txq->wr_p = 0;
 272         txq->rd_p = 0;
 273 }
 274
 275 static int
 276 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 277 {
 278         int cnt;
 279         uint32_t new;
 280         struct timespec wait;
 281
 282         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 283                     hw->qcp_cfg);
 284
 285         if (hw->qcp_cfg == NULL)
 286                 rte_panic("Bad configuration queue pointer\n");
 287
 288         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 289
 290         wait.tv_sec = 0;
 291         wait.tv_nsec = 1000000;
 292
 293         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 294
 295         /* Poll update field, waiting for NFP to ack the config */
 296         for (cnt = 0; ; cnt++) {
 297                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 298                 if (new == 0)
 299                         break;
 300                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 301                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 302                         return -1;
 303                 }
 304                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 305                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 306                                           " %dms", update, cnt);
 307                         rte_panic("Exiting\n");
 308                 }
 309                 nanosleep(&wait, 0); /* waiting for a 1ms */
 310         }
 311         PMD_DRV_LOG(DEBUG, "Ack DONE");
 312         return 0;
 313 }
 314
 315 /*
 316  * Reconfigure the NIC
 317  * @nn:    device to reconfigure
 318  * @ctrl:    The value for the ctrl field in the BAR config
 319  * @update:  The value for the update field in the BAR config
 320  *
 321  * Write the update word to the BAR and ping the reconfig queue. Then poll
 322  * until the firmware has acknowledged the update by zeroing the update word.
 323  */
 324 static int
 325 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 326 {
 327         uint32_t err;
 328
 329         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 330                     ctrl, update);
 331
 332         rte_spinlock_lock(&hw->reconfig_lock);
 333
 334         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 335         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 336
 337         rte_wmb();
 338
 339         err = __nfp_net_reconfig(hw, update);
 340
 341         rte_spinlock_unlock(&hw->reconfig_lock);
 342
 343         if (!err)
 344                 return 0;
 345
 346         /*
 347          * Reconfig errors imply situations where they can be handled.
 348          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 349          */
 350         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 351                      ctrl, update);
 352         return -EIO;
 353 }
 354
 355 /*
 356  * Configure an Ethernet device. This function must be invoked first
 357  * before any other function in the Ethernet API. This function can
 358  * also be re-invoked when a device is in the stopped state.
 359  */
 360 static int
 361 nfp_net_configure(struct rte_eth_dev *dev)
 362 {
 363         struct rte_eth_conf *dev_conf;
 364         struct rte_eth_rxmode *rxmode;
 365         struct rte_eth_txmode *txmode;
 366         struct nfp_net_hw *hw;
 367
 368         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 369
 370         /*
 371          * A DPDK app sends info about how many queues to use and how
 372          * those queues need to be configured. This is used by the
 373          * DPDK core and it makes sure no more queues than those
 374          * advertised by the driver are requested. This function is
 375          * called after that internal process
 376          */
 377
 378         PMD_INIT_LOG(DEBUG, "Configure");
 379
 380         dev_conf = &dev->data->dev_conf;
 381         rxmode = &dev_conf->rxmode;
 382         txmode = &dev_conf->txmode;
 383
 384         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
 385                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 386
 387         /* Checking TX mode */
 388         if (txmode->mq_mode) {
 389                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 390                 return -EINVAL;
 391         }
 392
 393         /* Checking RX mode */
 394         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 395             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 396                 PMD_INIT_LOG(INFO, "RSS not supported");
 397                 return -EINVAL;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static void
 404 nfp_net_enable_queues(struct rte_eth_dev *dev)
 405 {
 406         struct nfp_net_hw *hw;
 407         uint64_t enabled_queues = 0;
 408         int i;
 409
 410         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 411
 412         /* Enabling the required TX queues in the device */
 413         for (i = 0; i < dev->data->nb_tx_queues; i++)
 414                 enabled_queues |= (1 << i);
 415
 416         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 417
 418         enabled_queues = 0;
 419
 420         /* Enabling the required RX queues in the device */
 421         for (i = 0; i < dev->data->nb_rx_queues; i++)
 422                 enabled_queues |= (1 << i);
 423
 424         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 425 }
 426
 427 static void
 428 nfp_net_disable_queues(struct rte_eth_dev *dev)
 429 {
 430         struct nfp_net_hw *hw;
 431         uint32_t new_ctrl, update = 0;
 432
 433         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 434
 435         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 436         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 437
 438         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 439         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 440                  NFP_NET_CFG_UPDATE_MSIX;
 441
 442         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 443                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 444
 445         /* If an error when reconfig we avoid to change hw state */
 446         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 447                 return;
 448
 449         hw->ctrl = new_ctrl;
 450 }
 451
 452 static int
 453 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 454 {
 455         int i;
 456
 457         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 458                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 459                         return -1;
 460         }
 461         return 0;
 462 }
 463
 464 static void
 465 nfp_net_params_setup(struct nfp_net_hw *hw)
 466 {
 467         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 468         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 469 }
 470
 471 static void
 472 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 473 {
 474         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 475 }
 476
 477 #define ETH_ADDR_LEN    6
 478
 479 static void
 480 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 481 {
 482         int i;
 483
 484         for (i = 0; i < ETH_ADDR_LEN; i++)
 485                 dst[i] = src[i];
 486 }
 487
 488 static int
 489 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 490 {
 491         struct nfp_eth_table *nfp_eth_table;
 492
 493         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 494         /*
 495          * hw points to port0 private data. We need hw now pointing to
 496          * right port.
 497          */
 498         hw += port;
 499         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 500                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 501
 502         free(nfp_eth_table);
 503         return 0;
 504 }
 505
 506 static void
 507 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 508 {
 509         uint32_t tmp;
 510
 511         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 512         memcpy(&hw->mac_addr[0], &tmp, 4);
 513
 514         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 515         memcpy(&hw->mac_addr[4], &tmp, 2);
 516 }
 517
 518 static void
 519 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 520 {
 521         uint32_t mac0 = *(uint32_t *)mac;
 522         uint16_t mac1;
 523
 524         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 525
 526         mac += 4;
 527         mac1 = *(uint16_t *)mac;
 528         nn_writew(rte_cpu_to_be_16(mac1),
 529                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 530 }
 531
 532 int
 533 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
 534 {
 535         struct nfp_net_hw *hw;
 536         uint32_t update, ctrl;
 537
 538         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 539         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 540             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 541                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 542                                   " port enabled");
 543                 return -EBUSY;
 544         }
 545
 546         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 547             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 548                 return -EBUSY;
 549
 550         /* Writing new MAC to the specific port BAR address */
 551         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 552
 553         /* Signal the NIC about the change */
 554         update = NFP_NET_CFG_UPDATE_MACADDR;
 555         ctrl = hw->ctrl;
 556         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 557             (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 558                 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
 559         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 560                 PMD_INIT_LOG(INFO, "MAC address update failed");
 561                 return -EIO;
 562         }
 563         return 0;
 564 }
 565
 566 static int
 567 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 568                            struct rte_intr_handle *intr_handle)
 569 {
 570         struct nfp_net_hw *hw;
 571         int i;
 572
 573         if (!intr_handle->intr_vec) {
 574                 intr_handle->intr_vec =
 575                         rte_zmalloc("intr_vec",
 576                                     dev->data->nb_rx_queues * sizeof(int), 0);
 577                 if (!intr_handle->intr_vec) {
 578                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 579                                      " intr_vec", dev->data->nb_rx_queues);
 580                         return -ENOMEM;
 581                 }
 582         }
 583
 584         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 585
 586         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 587                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 588                 /* UIO just supports one queue and no LSC*/
 589                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 590                 intr_handle->intr_vec[0] = 0;
 591         } else {
 592                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 593                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 594                         /*
 595                          * The first msix vector is reserved for non
 596                          * efd interrupts
 597                         */
 598                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 599                         intr_handle->intr_vec[i] = i + 1;
 600                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 601                                             intr_handle->intr_vec[i]);
 602                 }
 603         }
 604
 605         /* Avoiding TX interrupts */
 606         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 607         return 0;
 608 }
 609
 610 static uint32_t
 611 nfp_check_offloads(struct rte_eth_dev *dev)
 612 {
 613         struct nfp_net_hw *hw;
 614         struct rte_eth_conf *dev_conf;
 615         struct rte_eth_rxmode *rxmode;
 616         struct rte_eth_txmode *txmode;
 617         uint32_t ctrl = 0;
 618
 619         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 620
 621         dev_conf = &dev->data->dev_conf;
 622         rxmode = &dev_conf->rxmode;
 623         txmode = &dev_conf->txmode;
 624
 625         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 626                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 627                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 628         }
 629
 630         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 631                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 632                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 633         }
 634
 635         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 636                 hw->mtu = rxmode->max_rx_pkt_len;
 637
 638         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 639                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 640
 641         /* L2 broadcast */
 642         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 643                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 644
 645         /* L2 multicast */
 646         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 647                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 648
 649         /* TX checksum offload */
 650         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 651             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 652             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 653                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 654
 655         /* LSO offload */
 656         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 657                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 658                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 659                 else
 660                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 661         }
 662
 663         /* RX gather */
 664         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 665                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 666
 667         return ctrl;
 668 }
 669
 670 static int
 671 nfp_net_start(struct rte_eth_dev *dev)
 672 {
 673         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 674         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 675         uint32_t new_ctrl, update = 0;
 676         struct nfp_net_hw *hw;
 677         struct rte_eth_conf *dev_conf;
 678         struct rte_eth_rxmode *rxmode;
 679         uint32_t intr_vector;
 680         int ret;
 681
 682         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 683
 684         PMD_INIT_LOG(DEBUG, "Start");
 685
 686         /* Disabling queues just in case... */
 687         nfp_net_disable_queues(dev);
 688
 689         /* Enabling the required queues in the device */
 690         nfp_net_enable_queues(dev);
 691
 692         /* check and configure queue intr-vector mapping */
 693         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 694                 if (hw->pf_multiport_enabled) {
 695                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 696                                           "with NFP multiport PF");
 697                                 return -EINVAL;
 698                 }
 699                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 700                         /*
 701                          * Better not to share LSC with RX interrupts.
 702                          * Unregistering LSC interrupt handler
 703                          */
 704                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 705                                 nfp_net_dev_interrupt_handler, (void *)dev);
 706
 707                         if (dev->data->nb_rx_queues > 1) {
 708                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 709                                              "supports 1 queue with UIO");
 710                                 return -EIO;
 711                         }
 712                 }
 713                 intr_vector = dev->data->nb_rx_queues;
 714                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 715                         return -1;
 716
 717                 nfp_configure_rx_interrupt(dev, intr_handle);
 718                 update = NFP_NET_CFG_UPDATE_MSIX;
 719         }
 720
 721         rte_intr_enable(intr_handle);
 722
 723         new_ctrl = nfp_check_offloads(dev);
 724
 725         /* Writing configuration parameters in the device */
 726         nfp_net_params_setup(hw);
 727
 728         dev_conf = &dev->data->dev_conf;
 729         rxmode = &dev_conf->rxmode;
 730
 731         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 732                 nfp_net_rss_config_default(dev);
 733                 update |= NFP_NET_CFG_UPDATE_RSS;
 734                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 735         }
 736
 737         /* Enable device */
 738         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 739
 740         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 741
 742         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 743                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 744
 745         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 746         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 747                 return -EIO;
 748
 749         /*
 750          * Allocating rte mbufs for configured rx queues.
 751          * This requires queues being enabled before
 752          */
 753         if (nfp_net_rx_freelist_setup(dev) < 0) {
 754                 ret = -ENOMEM;
 755                 goto error;
 756         }
 757
 758         if (hw->is_pf) {
 759                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 760                         /* Configure the physical port up */
 761                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 762                 else
 763                         nfp_eth_set_configured(dev->process_private,
 764                                                hw->pf_port_idx, 1);
 765         }
 766
 767         hw->ctrl = new_ctrl;
 768
 769         return 0;
 770
 771 error:
 772         /*
 773          * An error returned by this function should mean the app
 774          * exiting and then the system releasing all the memory
 775          * allocated even memory coming from hugepages.
 776          *
 777          * The device could be enabled at this point with some queues
 778          * ready for getting packets. This is true if the call to
 779          * nfp_net_rx_freelist_setup() succeeds for some queues but
 780          * fails for subsequent queues.
 781          *
 782          * This should make the app exiting but better if we tell the
 783          * device first.
 784          */
 785         nfp_net_disable_queues(dev);
 786
 787         return ret;
 788 }
 789
 790 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 791 static int
 792 nfp_net_stop(struct rte_eth_dev *dev)
 793 {
 794         int i;
 795         struct nfp_net_hw *hw;
 796
 797         PMD_INIT_LOG(DEBUG, "Stop");
 798
 799         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 800
 801         nfp_net_disable_queues(dev);
 802
 803         /* Clear queues */
 804         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 805                 nfp_net_reset_tx_queue(
 806                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 807         }
 808
 809         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 810                 nfp_net_reset_rx_queue(
 811                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 812         }
 813
 814         if (hw->is_pf) {
 815                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 816                         /* Configure the physical port down */
 817                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 818                 else
 819                         nfp_eth_set_configured(dev->process_private,
 820                                                hw->pf_port_idx, 0);
 821         }
 822
 823         return 0;
 824 }
 825
 826 /* Set the link up. */
 827 static int
 828 nfp_net_set_link_up(struct rte_eth_dev *dev)
 829 {
 830         struct nfp_net_hw *hw;
 831
 832         PMD_DRV_LOG(DEBUG, "Set link up");
 833
 834         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 835
 836         if (!hw->is_pf)
 837                 return -ENOTSUP;
 838
 839         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 840                 /* Configure the physical port down */
 841                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 842         else
 843                 return nfp_eth_set_configured(dev->process_private,
 844                                               hw->pf_port_idx, 1);
 845 }
 846
 847 /* Set the link down. */
 848 static int
 849 nfp_net_set_link_down(struct rte_eth_dev *dev)
 850 {
 851         struct nfp_net_hw *hw;
 852
 853         PMD_DRV_LOG(DEBUG, "Set link down");
 854
 855         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 856
 857         if (!hw->is_pf)
 858                 return -ENOTSUP;
 859
 860         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 861                 /* Configure the physical port down */
 862                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 863         else
 864                 return nfp_eth_set_configured(dev->process_private,
 865                                               hw->pf_port_idx, 0);
 866 }
 867
 868 /* Reset and stop device. The device can not be restarted. */
 869 static int
 870 nfp_net_close(struct rte_eth_dev *dev)
 871 {
 872         struct nfp_net_hw *hw;
 873         struct rte_pci_device *pci_dev;
 874         int i;
 875
 876         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 877                 return 0;
 878
 879         PMD_INIT_LOG(DEBUG, "Close");
 880
 881         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 882         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 883
 884         /*
 885          * We assume that the DPDK application is stopping all the
 886          * threads/queues before calling the device close function.
 887          */
 888
 889         nfp_net_disable_queues(dev);
 890
 891         /* Clear queues */
 892         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 893                 nfp_net_reset_tx_queue(
 894                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 895         }
 896
 897         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 898                 nfp_net_reset_rx_queue(
 899                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 900         }
 901
 902         rte_intr_disable(&pci_dev->intr_handle);
 903         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 904
 905         /* unregister callback func from eal lib */
 906         rte_intr_callback_unregister(&pci_dev->intr_handle,
 907                                      nfp_net_dev_interrupt_handler,
 908                                      (void *)dev);
 909
 910         /*
 911          * The ixgbe PMD driver disables the pcie master on the
 912          * device. The i40e does not...
 913          */
 914
 915         return 0;
 916 }
 917
 918 static int
 919 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 920 {
 921         uint32_t new_ctrl, update = 0;
 922         struct nfp_net_hw *hw;
 923         int ret;
 924
 925         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 926
 927         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 928
 929         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 930                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 931                 return -ENOTSUP;
 932         }
 933
 934         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 935                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 936                 return 0;
 937         }
 938
 939         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 940         update = NFP_NET_CFG_UPDATE_GEN;
 941
 942         /*
 943          * DPDK sets promiscuous mode on just after this call assuming
 944          * it can not fail ...
 945          */
 946         ret = nfp_net_reconfig(hw, new_ctrl, update);
 947         if (ret < 0)
 948                 return ret;
 949
 950         hw->ctrl = new_ctrl;
 951
 952         return 0;
 953 }
 954
 955 static int
 956 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 957 {
 958         uint32_t new_ctrl, update = 0;
 959         struct nfp_net_hw *hw;
 960         int ret;
 961
 962         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 963
 964         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 965                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 966                 return 0;
 967         }
 968
 969         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 970         update = NFP_NET_CFG_UPDATE_GEN;
 971
 972         /*
 973          * DPDK sets promiscuous mode off just before this call
 974          * assuming it can not fail ...
 975          */
 976         ret = nfp_net_reconfig(hw, new_ctrl, update);
 977         if (ret < 0)
 978                 return ret;
 979
 980         hw->ctrl = new_ctrl;
 981
 982         return 0;
 983 }
 984
 985 /*
 986  * return 0 means link status changed, -1 means not changed
 987  *
 988  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 989  * status.
 990  */
 991 static int
 992 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 993 {
 994         struct nfp_net_hw *hw;
 995         struct rte_eth_link link;
 996         uint32_t nn_link_status;
 997         int ret;
 998
 999         static const uint32_t ls_to_ethtool[] = {
1000                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
1001                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
1002                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
1003                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
1004                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
1005                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
1006                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
1007                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
1008         };
1009
1010         PMD_DRV_LOG(DEBUG, "Link update");
1011
1012         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1013
1014         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1015
1016         memset(&link, 0, sizeof(struct rte_eth_link));
1017
1018         if (nn_link_status & NFP_NET_CFG_STS_LINK)
1019                 link.link_status = ETH_LINK_UP;
1020
1021         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1022
1023         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1024                          NFP_NET_CFG_STS_LINK_RATE_MASK;
1025
1026         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1027                 link.link_speed = ETH_SPEED_NUM_NONE;
1028         else
1029                 link.link_speed = ls_to_ethtool[nn_link_status];
1030
1031         ret = rte_eth_linkstatus_set(dev, &link);
1032         if (ret == 0) {
1033                 if (link.link_status)
1034                         PMD_DRV_LOG(INFO, "NIC Link is Up");
1035                 else
1036                         PMD_DRV_LOG(INFO, "NIC Link is Down");
1037         }
1038         return ret;
1039 }
1040
1041 static int
1042 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1043 {
1044         int i;
1045         struct nfp_net_hw *hw;
1046         struct rte_eth_stats nfp_dev_stats;
1047
1048         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049
1050         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1051
1052         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1053
1054         /* reading per RX ring stats */
1055         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1056                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1057                         break;
1058
1059                 nfp_dev_stats.q_ipackets[i] =
1060                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1061
1062                 nfp_dev_stats.q_ipackets[i] -=
1063                         hw->eth_stats_base.q_ipackets[i];
1064
1065                 nfp_dev_stats.q_ibytes[i] =
1066                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1067
1068                 nfp_dev_stats.q_ibytes[i] -=
1069                         hw->eth_stats_base.q_ibytes[i];
1070         }
1071
1072         /* reading per TX ring stats */
1073         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1074                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1075                         break;
1076
1077                 nfp_dev_stats.q_opackets[i] =
1078                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1079
1080                 nfp_dev_stats.q_opackets[i] -=
1081                         hw->eth_stats_base.q_opackets[i];
1082
1083                 nfp_dev_stats.q_obytes[i] =
1084                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1085
1086                 nfp_dev_stats.q_obytes[i] -=
1087                         hw->eth_stats_base.q_obytes[i];
1088         }
1089
1090         nfp_dev_stats.ipackets =
1091                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1092
1093         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1094
1095         nfp_dev_stats.ibytes =
1096                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1097
1098         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1099
1100         nfp_dev_stats.opackets =
1101                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1102
1103         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1104
1105         nfp_dev_stats.obytes =
1106                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1107
1108         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1109
1110         /* reading general device stats */
1111         nfp_dev_stats.ierrors =
1112                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1113
1114         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1115
1116         nfp_dev_stats.oerrors =
1117                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1118
1119         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1120
1121         /* RX ring mbuf allocation failures */
1122         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1123
1124         nfp_dev_stats.imissed =
1125                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1126
1127         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1128
1129         if (stats) {
1130                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1131                 return 0;
1132         }
1133         return -EINVAL;
1134 }
1135
1136 static int
1137 nfp_net_stats_reset(struct rte_eth_dev *dev)
1138 {
1139         int i;
1140         struct nfp_net_hw *hw;
1141
1142         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1143
1144         /*
1145          * hw->eth_stats_base records the per counter starting point.
1146          * Lets update it now
1147          */
1148
1149         /* reading per RX ring stats */
1150         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1151                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1152                         break;
1153
1154                 hw->eth_stats_base.q_ipackets[i] =
1155                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1156
1157                 hw->eth_stats_base.q_ibytes[i] =
1158                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1159         }
1160
1161         /* reading per TX ring stats */
1162         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1163                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1164                         break;
1165
1166                 hw->eth_stats_base.q_opackets[i] =
1167                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1168
1169                 hw->eth_stats_base.q_obytes[i] =
1170                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1171         }
1172
1173         hw->eth_stats_base.ipackets =
1174                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1175
1176         hw->eth_stats_base.ibytes =
1177                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1178
1179         hw->eth_stats_base.opackets =
1180                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1181
1182         hw->eth_stats_base.obytes =
1183                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1184
1185         /* reading general device stats */
1186         hw->eth_stats_base.ierrors =
1187                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1188
1189         hw->eth_stats_base.oerrors =
1190                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1191
1192         /* RX ring mbuf allocation failures */
1193         dev->data->rx_mbuf_alloc_failed = 0;
1194
1195         hw->eth_stats_base.imissed =
1196                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1197
1198         return 0;
1199 }
1200
1201 static int
1202 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1203 {
1204         struct nfp_net_hw *hw;
1205
1206         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207
1208         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1209         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1210         dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1211         dev_info->max_rx_pktlen = hw->max_mtu;
1212         /* Next should change when PF support is implemented */
1213         dev_info->max_mac_addrs = 1;
1214
1215         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1216                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1217
1218         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1219                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1220                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1221                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1222
1223         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME |
1224                                      DEV_RX_OFFLOAD_RSS_HASH;
1225
1226         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1227                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1228
1229         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1230                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1231                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1232                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1233
1234         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1235                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1236
1237         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1238                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1239
1240         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1241                 .rx_thresh = {
1242                         .pthresh = DEFAULT_RX_PTHRESH,
1243                         .hthresh = DEFAULT_RX_HTHRESH,
1244                         .wthresh = DEFAULT_RX_WTHRESH,
1245                 },
1246                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1247                 .rx_drop_en = 0,
1248         };
1249
1250         dev_info->default_txconf = (struct rte_eth_txconf) {
1251                 .tx_thresh = {
1252                         .pthresh = DEFAULT_TX_PTHRESH,
1253                         .hthresh = DEFAULT_TX_HTHRESH,
1254                         .wthresh = DEFAULT_TX_WTHRESH,
1255                 },
1256                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1257                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1258         };
1259
1260         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1261                 .nb_max = NFP_NET_MAX_RX_DESC,
1262                 .nb_min = NFP_NET_MIN_RX_DESC,
1263                 .nb_align = NFP_ALIGN_RING_DESC,
1264         };
1265
1266         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1267                 .nb_max = NFP_NET_MAX_TX_DESC,
1268                 .nb_min = NFP_NET_MIN_TX_DESC,
1269                 .nb_align = NFP_ALIGN_RING_DESC,
1270                 .nb_seg_max = NFP_TX_MAX_SEG,
1271                 .nb_mtu_seg_max = NFP_TX_MAX_MTU_SEG,
1272         };
1273
1274         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1275                                            ETH_RSS_NONFRAG_IPV4_TCP |
1276                                            ETH_RSS_NONFRAG_IPV4_UDP |
1277                                            ETH_RSS_IPV6 |
1278                                            ETH_RSS_NONFRAG_IPV6_TCP |
1279                                            ETH_RSS_NONFRAG_IPV6_UDP;
1280
1281         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1282         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1283
1284         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1285                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1286                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1287
1288         return 0;
1289 }
1290
1291 static const uint32_t *
1292 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1293 {
1294         static const uint32_t ptypes[] = {
1295                 /* refers to nfp_net_set_hash() */
1296                 RTE_PTYPE_INNER_L3_IPV4,
1297                 RTE_PTYPE_INNER_L3_IPV6,
1298                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1299                 RTE_PTYPE_INNER_L4_MASK,
1300                 RTE_PTYPE_UNKNOWN
1301         };
1302
1303         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1304                 return ptypes;
1305         return NULL;
1306 }
1307
1308 static uint32_t
1309 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1310 {
1311         struct nfp_net_rxq *rxq;
1312         struct nfp_net_rx_desc *rxds;
1313         uint32_t idx;
1314         uint32_t count;
1315
1316         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1317
1318         idx = rxq->rd_p;
1319
1320         count = 0;
1321
1322         /*
1323          * Other PMDs are just checking the DD bit in intervals of 4
1324          * descriptors and counting all four if the first has the DD
1325          * bit on. Of course, this is not accurate but can be good for
1326          * performance. But ideally that should be done in descriptors
1327          * chunks belonging to the same cache line
1328          */
1329
1330         while (count < rxq->rx_count) {
1331                 rxds = &rxq->rxds[idx];
1332                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1333                         break;
1334
1335                 count++;
1336                 idx++;
1337
1338                 /* Wrapping? */
1339                 if ((idx) == rxq->rx_count)
1340                         idx = 0;
1341         }
1342
1343         return count;
1344 }
1345
1346 static int
1347 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1348 {
1349         struct rte_pci_device *pci_dev;
1350         struct nfp_net_hw *hw;
1351         int base = 0;
1352
1353         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1355
1356         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1357                 base = 1;
1358
1359         /* Make sure all updates are written before un-masking */
1360         rte_wmb();
1361         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1362                       NFP_NET_CFG_ICR_UNMASKED);
1363         return 0;
1364 }
1365
1366 static int
1367 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1368 {
1369         struct rte_pci_device *pci_dev;
1370         struct nfp_net_hw *hw;
1371         int base = 0;
1372
1373         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1374         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1375
1376         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1377                 base = 1;
1378
1379         /* Make sure all updates are written before un-masking */
1380         rte_wmb();
1381         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1382         return 0;
1383 }
1384
1385 static void
1386 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1387 {
1388         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1389         struct rte_eth_link link;
1390
1391         rte_eth_linkstatus_get(dev, &link);
1392         if (link.link_status)
1393                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1394                             dev->data->port_id, link.link_speed,
1395                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1396                             ? "full-duplex" : "half-duplex");
1397         else
1398                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1399                             dev->data->port_id);
1400
1401         PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
1402                     pci_dev->addr.domain, pci_dev->addr.bus,
1403                     pci_dev->addr.devid, pci_dev->addr.function);
1404 }
1405
1406 /* Interrupt configuration and handling */
1407
1408 /*
1409  * nfp_net_irq_unmask - Unmask an interrupt
1410  *
1411  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1412  * clear the ICR for the entry.
1413  */
1414 static void
1415 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1416 {
1417         struct nfp_net_hw *hw;
1418         struct rte_pci_device *pci_dev;
1419
1420         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1422
1423         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1424                 /* If MSI-X auto-masking is used, clear the entry */
1425                 rte_wmb();
1426                 rte_intr_ack(&pci_dev->intr_handle);
1427         } else {
1428                 /* Make sure all updates are written before un-masking */
1429                 rte_wmb();
1430                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1431                               NFP_NET_CFG_ICR_UNMASKED);
1432         }
1433 }
1434
1435 static void
1436 nfp_net_dev_interrupt_handler(void *param)
1437 {
1438         int64_t timeout;
1439         struct rte_eth_link link;
1440         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1441
1442         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1443
1444         rte_eth_linkstatus_get(dev, &link);
1445
1446         nfp_net_link_update(dev, 0);
1447
1448         /* likely to up */
1449         if (!link.link_status) {
1450                 /* handle it 1 sec later, wait it being stable */
1451                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1452                 /* likely to down */
1453         } else {
1454                 /* handle it 4 sec later, wait it being stable */
1455                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1456         }
1457
1458         if (rte_eal_alarm_set(timeout * 1000,
1459                               nfp_net_dev_interrupt_delayed_handler,
1460                               (void *)dev) < 0) {
1461                 PMD_INIT_LOG(ERR, "Error setting alarm");
1462                 /* Unmasking */
1463                 nfp_net_irq_unmask(dev);
1464         }
1465 }
1466
1467 /*
1468  * Interrupt handler which shall be registered for alarm callback for delayed
1469  * handling specific interrupt to wait for the stable nic state. As the NIC
1470  * interrupt state is not stable for nfp after link is just down, it needs
1471  * to wait 4 seconds to get the stable status.
1472  *
1473  * @param handle   Pointer to interrupt handle.
1474  * @param param    The address of parameter (struct rte_eth_dev *)
1475  *
1476  * @return  void
1477  */
1478 static void
1479 nfp_net_dev_interrupt_delayed_handler(void *param)
1480 {
1481         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1482
1483         nfp_net_link_update(dev, 0);
1484         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1485
1486         nfp_net_dev_link_status_print(dev);
1487
1488         /* Unmasking */
1489         nfp_net_irq_unmask(dev);
1490 }
1491
1492 static int
1493 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1494 {
1495         struct nfp_net_hw *hw;
1496
1497         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1498
1499         /* check that mtu is within the allowed range */
1500         if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1501                 return -EINVAL;
1502
1503         /* mtu setting is forbidden if port is started */
1504         if (dev->data->dev_started) {
1505                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1506                             dev->data->port_id);
1507                 return -EBUSY;
1508         }
1509
1510         /* switch to jumbo mode if needed */
1511         if ((uint32_t)mtu > RTE_ETHER_MAX_LEN)
1512                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1513         else
1514                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1515
1516         /* update max frame size */
1517         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1518
1519         /* writing to configuration space */
1520         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1521
1522         hw->mtu = mtu;
1523
1524         return 0;
1525 }
1526
1527 static int
1528 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1529                        uint16_t queue_idx, uint16_t nb_desc,
1530                        unsigned int socket_id,
1531                        const struct rte_eth_rxconf *rx_conf,
1532                        struct rte_mempool *mp)
1533 {
1534         const struct rte_memzone *tz;
1535         struct nfp_net_rxq *rxq;
1536         struct nfp_net_hw *hw;
1537         uint32_t rx_desc_sz;
1538
1539         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540
1541         PMD_INIT_FUNC_TRACE();
1542
1543         /* Validating number of descriptors */
1544         rx_desc_sz = nb_desc * sizeof(struct nfp_net_rx_desc);
1545         if (rx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1546             nb_desc > NFP_NET_MAX_RX_DESC ||
1547             nb_desc < NFP_NET_MIN_RX_DESC) {
1548                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1549                 return -EINVAL;
1550         }
1551
1552         /*
1553          * Free memory prior to re-allocation if needed. This is the case after
1554          * calling nfp_net_stop
1555          */
1556         if (dev->data->rx_queues[queue_idx]) {
1557                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1558                 dev->data->rx_queues[queue_idx] = NULL;
1559         }
1560
1561         /* Allocating rx queue data structure */
1562         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1563                                  RTE_CACHE_LINE_SIZE, socket_id);
1564         if (rxq == NULL)
1565                 return -ENOMEM;
1566
1567         /* Hw queues mapping based on firmware configuration */
1568         rxq->qidx = queue_idx;
1569         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1570         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1571         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1572         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1573
1574         /*
1575          * Tracking mbuf size for detecting a potential mbuf overflow due to
1576          * RX offset
1577          */
1578         rxq->mem_pool = mp;
1579         rxq->mbuf_size = rxq->mem_pool->elt_size;
1580         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1581         hw->flbufsz = rxq->mbuf_size;
1582
1583         rxq->rx_count = nb_desc;
1584         rxq->port_id = dev->data->port_id;
1585         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1586         rxq->drop_en = rx_conf->rx_drop_en;
1587
1588         /*
1589          * Allocate RX ring hardware descriptors. A memzone large enough to
1590          * handle the maximum ring size is allocated in order to allow for
1591          * resizing in later calls to the queue setup function.
1592          */
1593         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1594                                    sizeof(struct nfp_net_rx_desc) *
1595                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1596                                    socket_id);
1597
1598         if (tz == NULL) {
1599                 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1600                 nfp_net_rx_queue_release(rxq);
1601                 return -ENOMEM;
1602         }
1603
1604         /* Saving physical and virtual addresses for the RX ring */
1605         rxq->dma = (uint64_t)tz->iova;
1606         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1607
1608         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1609         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1610                                          sizeof(*rxq->rxbufs) * nb_desc,
1611                                          RTE_CACHE_LINE_SIZE, socket_id);
1612         if (rxq->rxbufs == NULL) {
1613                 nfp_net_rx_queue_release(rxq);
1614                 return -ENOMEM;
1615         }
1616
1617         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1618                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1619
1620         nfp_net_reset_rx_queue(rxq);
1621
1622         dev->data->rx_queues[queue_idx] = rxq;
1623         rxq->hw = hw;
1624
1625         /*
1626          * Telling the HW about the physical address of the RX ring and number
1627          * of descriptors in log2 format
1628          */
1629         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1630         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1631
1632         return 0;
1633 }
1634
1635 static int
1636 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1637 {
1638         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1639         uint64_t dma_addr;
1640         unsigned i;
1641
1642         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1643                    rxq->rx_count);
1644
1645         for (i = 0; i < rxq->rx_count; i++) {
1646                 struct nfp_net_rx_desc *rxd;
1647                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1648
1649                 if (mbuf == NULL) {
1650                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1651                                 (unsigned)rxq->qidx);
1652                         return -ENOMEM;
1653                 }
1654
1655                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1656
1657                 rxd = &rxq->rxds[i];
1658                 rxd->fld.dd = 0;
1659                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1660                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1661                 rxe[i].mbuf = mbuf;
1662                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1663         }
1664
1665         /* Make sure all writes are flushed before telling the hardware */
1666         rte_wmb();
1667
1668         /* Not advertising the whole ring as the firmware gets confused if so */
1669         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1670                    rxq->rx_count - 1);
1671
1672         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1673
1674         return 0;
1675 }
1676
1677 static int
1678 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1679                        uint16_t nb_desc, unsigned int socket_id,
1680                        const struct rte_eth_txconf *tx_conf)
1681 {
1682         const struct rte_memzone *tz;
1683         struct nfp_net_txq *txq;
1684         uint16_t tx_free_thresh;
1685         struct nfp_net_hw *hw;
1686         uint32_t tx_desc_sz;
1687
1688         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1689
1690         PMD_INIT_FUNC_TRACE();
1691
1692         /* Validating number of descriptors */
1693         tx_desc_sz = nb_desc * sizeof(struct nfp_net_tx_desc);
1694         if (tx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1695             nb_desc > NFP_NET_MAX_TX_DESC ||
1696             nb_desc < NFP_NET_MIN_TX_DESC) {
1697                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1698                 return -EINVAL;
1699         }
1700
1701         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1702                                     tx_conf->tx_free_thresh :
1703                                     DEFAULT_TX_FREE_THRESH);
1704
1705         if (tx_free_thresh > (nb_desc)) {
1706                 PMD_DRV_LOG(ERR,
1707                         "tx_free_thresh must be less than the number of TX "
1708                         "descriptors. (tx_free_thresh=%u port=%d "
1709                         "queue=%d)", (unsigned int)tx_free_thresh,
1710                         dev->data->port_id, (int)queue_idx);
1711                 return -(EINVAL);
1712         }
1713
1714         /*
1715          * Free memory prior to re-allocation if needed. This is the case after
1716          * calling nfp_net_stop
1717          */
1718         if (dev->data->tx_queues[queue_idx]) {
1719                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1720                            queue_idx);
1721                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1722                 dev->data->tx_queues[queue_idx] = NULL;
1723         }
1724
1725         /* Allocating tx queue data structure */
1726         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1727                                  RTE_CACHE_LINE_SIZE, socket_id);
1728         if (txq == NULL) {
1729                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1730                 return -ENOMEM;
1731         }
1732
1733         /*
1734          * Allocate TX ring hardware descriptors. A memzone large enough to
1735          * handle the maximum ring size is allocated in order to allow for
1736          * resizing in later calls to the queue setup function.
1737          */
1738         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1739                                    sizeof(struct nfp_net_tx_desc) *
1740                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1741                                    socket_id);
1742         if (tz == NULL) {
1743                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1744                 nfp_net_tx_queue_release(txq);
1745                 return -ENOMEM;
1746         }
1747
1748         txq->tx_count = nb_desc;
1749         txq->tx_free_thresh = tx_free_thresh;
1750         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1751         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1752         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1753
1754         /* queue mapping based on firmware configuration */
1755         txq->qidx = queue_idx;
1756         txq->tx_qcidx = queue_idx * hw->stride_tx;
1757         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1758
1759         txq->port_id = dev->data->port_id;
1760
1761         /* Saving physical and virtual addresses for the TX ring */
1762         txq->dma = (uint64_t)tz->iova;
1763         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1764
1765         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1766         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1767                                          sizeof(*txq->txbufs) * nb_desc,
1768                                          RTE_CACHE_LINE_SIZE, socket_id);
1769         if (txq->txbufs == NULL) {
1770                 nfp_net_tx_queue_release(txq);
1771                 return -ENOMEM;
1772         }
1773         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1774                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1775
1776         nfp_net_reset_tx_queue(txq);
1777
1778         dev->data->tx_queues[queue_idx] = txq;
1779         txq->hw = hw;
1780
1781         /*
1782          * Telling the HW about the physical address of the TX ring and number
1783          * of descriptors in log2 format
1784          */
1785         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1786         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1787
1788         return 0;
1789 }
1790
1791 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1792 static inline void
1793 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1794                struct rte_mbuf *mb)
1795 {
1796         uint64_t ol_flags;
1797         struct nfp_net_hw *hw = txq->hw;
1798
1799         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1800                 goto clean_txd;
1801
1802         ol_flags = mb->ol_flags;
1803
1804         if (!(ol_flags & PKT_TX_TCP_SEG))
1805                 goto clean_txd;
1806
1807         txd->l3_offset = mb->l2_len;
1808         txd->l4_offset = mb->l2_len + mb->l3_len;
1809         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1810         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1811         txd->flags = PCIE_DESC_TX_LSO;
1812         return;
1813
1814 clean_txd:
1815         txd->flags = 0;
1816         txd->l3_offset = 0;
1817         txd->l4_offset = 0;
1818         txd->lso_hdrlen = 0;
1819         txd->mss = 0;
1820 }
1821
1822 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1823 static inline void
1824 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1825                  struct rte_mbuf *mb)
1826 {
1827         uint64_t ol_flags;
1828         struct nfp_net_hw *hw = txq->hw;
1829
1830         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1831                 return;
1832
1833         ol_flags = mb->ol_flags;
1834
1835         /* IPv6 does not need checksum */
1836         if (ol_flags & PKT_TX_IP_CKSUM)
1837                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1838
1839         switch (ol_flags & PKT_TX_L4_MASK) {
1840         case PKT_TX_UDP_CKSUM:
1841                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1842                 break;
1843         case PKT_TX_TCP_CKSUM:
1844                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1845                 break;
1846         }
1847
1848         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1849                 txd->flags |= PCIE_DESC_TX_CSUM;
1850 }
1851
1852 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1853 static inline void
1854 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1855                  struct rte_mbuf *mb)
1856 {
1857         struct nfp_net_hw *hw = rxq->hw;
1858
1859         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1860                 return;
1861
1862         /* If IPv4 and IP checksum error, fail */
1863         if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1864             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1865                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1866         else
1867                 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1868
1869         /* If neither UDP nor TCP return */
1870         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1871             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1872                 return;
1873
1874         if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1875                 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1876         else
1877                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1878 }
1879
1880 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1881 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1882
1883 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1884
1885 /*
1886  * nfp_net_set_hash - Set mbuf hash data
1887  *
1888  * The RSS hash and hash-type are pre-pended to the packet data.
1889  * Extract and decode it and set the mbuf fields.
1890  */
1891 static inline void
1892 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1893                  struct rte_mbuf *mbuf)
1894 {
1895         struct nfp_net_hw *hw = rxq->hw;
1896         uint8_t *meta_offset;
1897         uint32_t meta_info;
1898         uint32_t hash = 0;
1899         uint32_t hash_type = 0;
1900
1901         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1902                 return;
1903
1904         /* this is true for new firmwares */
1905         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1906             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1907              NFP_DESC_META_LEN(rxd))) {
1908                 /*
1909                  * new metadata api:
1910                  * <----  32 bit  ----->
1911                  * m    field type word
1912                  * e     data field #2
1913                  * t     data field #1
1914                  * a     data field #0
1915                  * ====================
1916                  *    packet data
1917                  *
1918                  * Field type word contains up to 8 4bit field types
1919                  * A 4bit field type refers to a data field word
1920                  * A data field word can have several 4bit field types
1921                  */
1922                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1923                 meta_offset -= NFP_DESC_META_LEN(rxd);
1924                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1925                 meta_offset += 4;
1926                 /* NFP PMD just supports metadata for hashing */
1927                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1928                 case NFP_NET_META_HASH:
1929                         /* next field type is about the hash type */
1930                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1931                         /* hash value is in the data field */
1932                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1933                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1934                         break;
1935                 default:
1936                         /* Unsupported metadata can be a performance issue */
1937                         return;
1938                 }
1939         } else {
1940                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1941                         return;
1942
1943                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1944                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1945         }
1946
1947         mbuf->hash.rss = hash;
1948         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1949
1950         switch (hash_type) {
1951         case NFP_NET_RSS_IPV4:
1952                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1953                 break;
1954         case NFP_NET_RSS_IPV6:
1955                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1956                 break;
1957         case NFP_NET_RSS_IPV6_EX:
1958                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1959                 break;
1960         case NFP_NET_RSS_IPV4_TCP:
1961                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1962                 break;
1963         case NFP_NET_RSS_IPV6_TCP:
1964                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1965                 break;
1966         case NFP_NET_RSS_IPV4_UDP:
1967                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1968                 break;
1969         case NFP_NET_RSS_IPV6_UDP:
1970                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1971                 break;
1972         default:
1973                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1974         }
1975 }
1976
1977 static inline void
1978 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1979 {
1980         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1981 }
1982
1983 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1984
1985 /*
1986  * RX path design:
1987  *
1988  * There are some decisions to take:
1989  * 1) How to check DD RX descriptors bit
1990  * 2) How and when to allocate new mbufs
1991  *
1992  * Current implementation checks just one single DD bit each loop. As each
1993  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1994  * a single cache line instead. Tests with this change have not shown any
1995  * performance improvement but it requires further investigation. For example,
1996  * depending on which descriptor is next, the number of descriptors could be
1997  * less than 8 for just checking those in the same cache line. This implies
1998  * extra work which could be counterproductive by itself. Indeed, last firmware
1999  * changes are just doing this: writing several descriptors with the DD bit
2000  * for saving PCIe bandwidth and DMA operations from the NFP.
2001  *
2002  * Mbuf allocation is done when a new packet is received. Then the descriptor
2003  * is automatically linked with the new mbuf and the old one is given to the
2004  * user. The main drawback with this design is mbuf allocation is heavier than
2005  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2006  * cache point of view it does not seem allocating the mbuf early on as we are
2007  * doing now have any benefit at all. Again, tests with this change have not
2008  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2009  * so looking at the implications of this type of allocation should be studied
2010  * deeply
2011  */
2012
2013 static uint16_t
2014 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2015 {
2016         struct nfp_net_rxq *rxq;
2017         struct nfp_net_rx_desc *rxds;
2018         struct nfp_net_rx_buff *rxb;
2019         struct nfp_net_hw *hw;
2020         struct rte_mbuf *mb;
2021         struct rte_mbuf *new_mb;
2022         uint16_t nb_hold;
2023         uint64_t dma_addr;
2024         int avail;
2025
2026         rxq = rx_queue;
2027         if (unlikely(rxq == NULL)) {
2028                 /*
2029                  * DPDK just checks the queue is lower than max queues
2030                  * enabled. But the queue needs to be configured
2031                  */
2032                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2033                 return -EINVAL;
2034         }
2035
2036         hw = rxq->hw;
2037         avail = 0;
2038         nb_hold = 0;
2039
2040         while (avail < nb_pkts) {
2041                 rxb = &rxq->rxbufs[rxq->rd_p];
2042                 if (unlikely(rxb == NULL)) {
2043                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2044                         break;
2045                 }
2046
2047                 rxds = &rxq->rxds[rxq->rd_p];
2048                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2049                         break;
2050
2051                 /*
2052                  * Memory barrier to ensure that we won't do other
2053                  * reads before the DD bit.
2054                  */
2055                 rte_rmb();
2056
2057                 /*
2058                  * We got a packet. Let's alloc a new mbuf for refilling the
2059                  * free descriptor ring as soon as possible
2060                  */
2061                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2062                 if (unlikely(new_mb == NULL)) {
2063                         RTE_LOG_DP(DEBUG, PMD,
2064                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2065                                 rxq->port_id, (unsigned int)rxq->qidx);
2066                         nfp_net_mbuf_alloc_failed(rxq);
2067                         break;
2068                 }
2069
2070                 nb_hold++;
2071
2072                 /*
2073                  * Grab the mbuf and refill the descriptor with the
2074                  * previously allocated mbuf
2075                  */
2076                 mb = rxb->mbuf;
2077                 rxb->mbuf = new_mb;
2078
2079                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2080                            rxds->rxd.data_len, rxq->mbuf_size);
2081
2082                 /* Size of this segment */
2083                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2084                 /* Size of the whole packet. We just support 1 segment */
2085                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2086
2087                 if (unlikely((mb->data_len + hw->rx_offset) >
2088                              rxq->mbuf_size)) {
2089                         /*
2090                          * This should not happen and the user has the
2091                          * responsibility of avoiding it. But we have
2092                          * to give some info about the error
2093                          */
2094                         RTE_LOG_DP(ERR, PMD,
2095                                 "mbuf overflow likely due to the RX offset.\n"
2096                                 "\t\tYour mbuf size should have extra space for"
2097                                 " RX offset=%u bytes.\n"
2098                                 "\t\tCurrently you just have %u bytes available"
2099                                 " but the received packet is %u bytes long",
2100                                 hw->rx_offset,
2101                                 rxq->mbuf_size - hw->rx_offset,
2102                                 mb->data_len);
2103                         return -EINVAL;
2104                 }
2105
2106                 /* Filling the received mbuf with packet info */
2107                 if (hw->rx_offset)
2108                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2109                 else
2110                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2111                                        NFP_DESC_META_LEN(rxds);
2112
2113                 /* No scatter mode supported */
2114                 mb->nb_segs = 1;
2115                 mb->next = NULL;
2116
2117                 mb->port = rxq->port_id;
2118
2119                 /* Checking the RSS flag */
2120                 nfp_net_set_hash(rxq, rxds, mb);
2121
2122                 /* Checking the checksum flag */
2123                 nfp_net_rx_cksum(rxq, rxds, mb);
2124
2125                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2126                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2127                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2128                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2129                 }
2130
2131                 /* Adding the mbuf to the mbuf array passed by the app */
2132                 rx_pkts[avail++] = mb;
2133
2134                 /* Now resetting and updating the descriptor */
2135                 rxds->vals[0] = 0;
2136                 rxds->vals[1] = 0;
2137                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2138                 rxds->fld.dd = 0;
2139                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2140                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2141
2142                 rxq->rd_p++;
2143                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2144                         rxq->rd_p = 0;
2145         }
2146
2147         if (nb_hold == 0)
2148                 return nb_hold;
2149
2150         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2151                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2152
2153         nb_hold += rxq->nb_rx_hold;
2154
2155         /*
2156          * FL descriptors needs to be written before incrementing the
2157          * FL queue WR pointer
2158          */
2159         rte_wmb();
2160         if (nb_hold > rxq->rx_free_thresh) {
2161                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2162                            rxq->port_id, (unsigned int)rxq->qidx,
2163                            (unsigned)nb_hold, (unsigned)avail);
2164                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2165                 nb_hold = 0;
2166         }
2167         rxq->nb_rx_hold = nb_hold;
2168
2169         return avail;
2170 }
2171
2172 /*
2173  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2174  * status
2175  * @txq: TX queue to work with
2176  * Returns number of descriptors freed
2177  */
2178 int
2179 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2180 {
2181         uint32_t qcp_rd_p;
2182         int todo;
2183
2184         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2185                    " status", txq->qidx);
2186
2187         /* Work out how many packets have been sent */
2188         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2189
2190         if (qcp_rd_p == txq->rd_p) {
2191                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2192                            "packets (%u, %u)", txq->qidx,
2193                            qcp_rd_p, txq->rd_p);
2194                 return 0;
2195         }
2196
2197         if (qcp_rd_p > txq->rd_p)
2198                 todo = qcp_rd_p - txq->rd_p;
2199         else
2200                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2201
2202         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2203                    qcp_rd_p, txq->rd_p, txq->rd_p);
2204
2205         if (todo == 0)
2206                 return todo;
2207
2208         txq->rd_p += todo;
2209         if (unlikely(txq->rd_p >= txq->tx_count))
2210                 txq->rd_p -= txq->tx_count;
2211
2212         return todo;
2213 }
2214
2215 /* Leaving always free descriptors for avoiding wrapping confusion */
2216 static inline
2217 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2218 {
2219         if (txq->wr_p >= txq->rd_p)
2220                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2221         else
2222                 return txq->rd_p - txq->wr_p - 8;
2223 }
2224
2225 /*
2226  * nfp_net_txq_full - Check if the TX queue free descriptors
2227  * is below tx_free_threshold
2228  *
2229  * @txq: TX queue to check
2230  *
2231  * This function uses the host copy* of read/write pointers
2232  */
2233 static inline
2234 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2235 {
2236         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2237 }
2238
2239 static uint16_t
2240 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2241 {
2242         struct nfp_net_txq *txq;
2243         struct nfp_net_hw *hw;
2244         struct nfp_net_tx_desc *txds, txd;
2245         struct rte_mbuf *pkt;
2246         uint64_t dma_addr;
2247         int pkt_size, dma_size;
2248         uint16_t free_descs, issued_descs;
2249         struct rte_mbuf **lmbuf;
2250         int i;
2251
2252         txq = tx_queue;
2253         hw = txq->hw;
2254         txds = &txq->txds[txq->wr_p];
2255
2256         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2257                    txq->qidx, txq->wr_p, nb_pkts);
2258
2259         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2260                 nfp_net_tx_free_bufs(txq);
2261
2262         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2263         if (unlikely(free_descs == 0))
2264                 return 0;
2265
2266         pkt = *tx_pkts;
2267
2268         i = 0;
2269         issued_descs = 0;
2270         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2271                    txq->qidx, nb_pkts);
2272         /* Sending packets */
2273         while ((i < nb_pkts) && free_descs) {
2274                 /* Grabbing the mbuf linked to the current descriptor */
2275                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2276                 /* Warming the cache for releasing the mbuf later on */
2277                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2278
2279                 pkt = *(tx_pkts + i);
2280
2281                 if (unlikely((pkt->nb_segs > 1) &&
2282                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2283                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2284                         rte_panic("Multisegment packet unsupported\n");
2285                 }
2286
2287                 /* Checking if we have enough descriptors */
2288                 if (unlikely(pkt->nb_segs > free_descs))
2289                         goto xmit_end;
2290
2291                 /*
2292                  * Checksum and VLAN flags just in the first descriptor for a
2293                  * multisegment packet, but TSO info needs to be in all of them.
2294                  */
2295                 txd.data_len = pkt->pkt_len;
2296                 nfp_net_tx_tso(txq, &txd, pkt);
2297                 nfp_net_tx_cksum(txq, &txd, pkt);
2298
2299                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2300                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2301                         txd.flags |= PCIE_DESC_TX_VLAN;
2302                         txd.vlan = pkt->vlan_tci;
2303                 }
2304
2305                 /*
2306                  * mbuf data_len is the data in one segment and pkt_len data
2307                  * in the whole packet. When the packet is just one segment,
2308                  * then data_len = pkt_len
2309                  */
2310                 pkt_size = pkt->pkt_len;
2311
2312                 while (pkt) {
2313                         /* Copying TSO, VLAN and cksum info */
2314                         *txds = txd;
2315
2316                         /* Releasing mbuf used by this descriptor previously*/
2317                         if (*lmbuf)
2318                                 rte_pktmbuf_free_seg(*lmbuf);
2319
2320                         /*
2321                          * Linking mbuf with descriptor for being released
2322                          * next time descriptor is used
2323                          */
2324                         *lmbuf = pkt;
2325
2326                         dma_size = pkt->data_len;
2327                         dma_addr = rte_mbuf_data_iova(pkt);
2328                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2329                                    "%" PRIx64 "", dma_addr);
2330
2331                         /* Filling descriptors fields */
2332                         txds->dma_len = dma_size;
2333                         txds->data_len = txd.data_len;
2334                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2335                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2336                         ASSERT(free_descs > 0);
2337                         free_descs--;
2338
2339                         txq->wr_p++;
2340                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2341                                 txq->wr_p = 0;
2342
2343                         pkt_size -= dma_size;
2344
2345                         /*
2346                          * Making the EOP, packets with just one segment
2347                          * the priority
2348                          */
2349                         if (likely(!pkt_size))
2350                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2351                         else
2352                                 txds->offset_eop = 0;
2353
2354                         pkt = pkt->next;
2355                         /* Referencing next free TX descriptor */
2356                         txds = &txq->txds[txq->wr_p];
2357                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2358                         issued_descs++;
2359                 }
2360                 i++;
2361         }
2362
2363 xmit_end:
2364         /* Increment write pointers. Force memory write before we let HW know */
2365         rte_wmb();
2366         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2367
2368         return i;
2369 }
2370
2371 static int
2372 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2373 {
2374         uint32_t new_ctrl, update;
2375         struct nfp_net_hw *hw;
2376         int ret;
2377
2378         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379         new_ctrl = 0;
2380
2381         /* Enable vlan strip if it is not configured yet */
2382         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2383             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2384                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2385
2386         /* Disable vlan strip just if it is configured */
2387         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2388             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2389                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2390
2391         if (new_ctrl == 0)
2392                 return 0;
2393
2394         update = NFP_NET_CFG_UPDATE_GEN;
2395
2396         ret = nfp_net_reconfig(hw, new_ctrl, update);
2397         if (!ret)
2398                 hw->ctrl = new_ctrl;
2399
2400         return ret;
2401 }
2402
2403 static int
2404 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2405                     struct rte_eth_rss_reta_entry64 *reta_conf,
2406                     uint16_t reta_size)
2407 {
2408         uint32_t reta, mask;
2409         int i, j;
2410         int idx, shift;
2411         struct nfp_net_hw *hw =
2412                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413
2414         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2415                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2416                         "(%d) doesn't match the number hardware can supported "
2417                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2418                 return -EINVAL;
2419         }
2420
2421         /*
2422          * Update Redirection Table. There are 128 8bit-entries which can be
2423          * manage as 32 32bit-entries
2424          */
2425         for (i = 0; i < reta_size; i += 4) {
2426                 /* Handling 4 RSS entries per loop */
2427                 idx = i / RTE_RETA_GROUP_SIZE;
2428                 shift = i % RTE_RETA_GROUP_SIZE;
2429                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2430
2431                 if (!mask)
2432                         continue;
2433
2434                 reta = 0;
2435                 /* If all 4 entries were set, don't need read RETA register */
2436                 if (mask != 0xF)
2437                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2438
2439                 for (j = 0; j < 4; j++) {
2440                         if (!(mask & (0x1 << j)))
2441                                 continue;
2442                         if (mask != 0xF)
2443                                 /* Clearing the entry bits */
2444                                 reta &= ~(0xFF << (8 * j));
2445                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2446                 }
2447                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2448                               reta);
2449         }
2450         return 0;
2451 }
2452
2453 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2454 static int
2455 nfp_net_reta_update(struct rte_eth_dev *dev,
2456                     struct rte_eth_rss_reta_entry64 *reta_conf,
2457                     uint16_t reta_size)
2458 {
2459         struct nfp_net_hw *hw =
2460                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2461         uint32_t update;
2462         int ret;
2463
2464         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2465                 return -EINVAL;
2466
2467         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2468         if (ret != 0)
2469                 return ret;
2470
2471         update = NFP_NET_CFG_UPDATE_RSS;
2472
2473         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2474                 return -EIO;
2475
2476         return 0;
2477 }
2478
2479  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2480 static int
2481 nfp_net_reta_query(struct rte_eth_dev *dev,
2482                    struct rte_eth_rss_reta_entry64 *reta_conf,
2483                    uint16_t reta_size)
2484 {
2485         uint8_t i, j, mask;
2486         int idx, shift;
2487         uint32_t reta;
2488         struct nfp_net_hw *hw;
2489
2490         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491
2492         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2493                 return -EINVAL;
2494
2495         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2496                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2497                         "(%d) doesn't match the number hardware can supported "
2498                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2499                 return -EINVAL;
2500         }
2501
2502         /*
2503          * Reading Redirection Table. There are 128 8bit-entries which can be
2504          * manage as 32 32bit-entries
2505          */
2506         for (i = 0; i < reta_size; i += 4) {
2507                 /* Handling 4 RSS entries per loop */
2508                 idx = i / RTE_RETA_GROUP_SIZE;
2509                 shift = i % RTE_RETA_GROUP_SIZE;
2510                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2511
2512                 if (!mask)
2513                         continue;
2514
2515                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2516                                     shift);
2517                 for (j = 0; j < 4; j++) {
2518                         if (!(mask & (0x1 << j)))
2519                                 continue;
2520                         reta_conf[idx].reta[shift + j] =
2521                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2522                 }
2523         }
2524         return 0;
2525 }
2526
2527 static int
2528 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2529                         struct rte_eth_rss_conf *rss_conf)
2530 {
2531         struct nfp_net_hw *hw;
2532         uint64_t rss_hf;
2533         uint32_t cfg_rss_ctrl = 0;
2534         uint8_t key;
2535         int i;
2536
2537         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538
2539         /* Writing the key byte a byte */
2540         for (i = 0; i < rss_conf->rss_key_len; i++) {
2541                 memcpy(&key, &rss_conf->rss_key[i], 1);
2542                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2543         }
2544
2545         rss_hf = rss_conf->rss_hf;
2546
2547         if (rss_hf & ETH_RSS_IPV4)
2548                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2549
2550         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2551                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2552
2553         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2554                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2555
2556         if (rss_hf & ETH_RSS_IPV6)
2557                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2558
2559         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2560                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2561
2562         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2563                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2564
2565         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2566         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2567
2568         /* configuring where to apply the RSS hash */
2569         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2570
2571         /* Writing the key size */
2572         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2573
2574         return 0;
2575 }
2576
2577 static int
2578 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2579                         struct rte_eth_rss_conf *rss_conf)
2580 {
2581         uint32_t update;
2582         uint64_t rss_hf;
2583         struct nfp_net_hw *hw;
2584
2585         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586
2587         rss_hf = rss_conf->rss_hf;
2588
2589         /* Checking if RSS is enabled */
2590         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2591                 if (rss_hf != 0) { /* Enable RSS? */
2592                         PMD_DRV_LOG(ERR, "RSS unsupported");
2593                         return -EINVAL;
2594                 }
2595                 return 0; /* Nothing to do */
2596         }
2597
2598         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2599                 PMD_DRV_LOG(ERR, "hash key too long");
2600                 return -EINVAL;
2601         }
2602
2603         nfp_net_rss_hash_write(dev, rss_conf);
2604
2605         update = NFP_NET_CFG_UPDATE_RSS;
2606
2607         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2608                 return -EIO;
2609
2610         return 0;
2611 }
2612
2613 static int
2614 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2615                           struct rte_eth_rss_conf *rss_conf)
2616 {
2617         uint64_t rss_hf;
2618         uint32_t cfg_rss_ctrl;
2619         uint8_t key;
2620         int i;
2621         struct nfp_net_hw *hw;
2622
2623         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2624
2625         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2626                 return -EINVAL;
2627
2628         rss_hf = rss_conf->rss_hf;
2629         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2630
2631         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2632                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2633
2634         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2635                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2636
2637         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2638                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2639
2640         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2641                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2642
2643         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2644                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2645
2646         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2647                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2648
2649         /* Propagate current RSS hash functions to caller */
2650         rss_conf->rss_hf = rss_hf;
2651
2652         /* Reading the key size */
2653         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2654
2655         /* Reading the key byte a byte */
2656         for (i = 0; i < rss_conf->rss_key_len; i++) {
2657                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2658                 memcpy(&rss_conf->rss_key[i], &key, 1);
2659         }
2660
2661         return 0;
2662 }
2663
2664 static int
2665 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2666 {
2667         struct rte_eth_conf *dev_conf;
2668         struct rte_eth_rss_conf rss_conf;
2669         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2670         uint16_t rx_queues = dev->data->nb_rx_queues;
2671         uint16_t queue;
2672         int i, j, ret;
2673
2674         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2675                 rx_queues);
2676
2677         nfp_reta_conf[0].mask = ~0x0;
2678         nfp_reta_conf[1].mask = ~0x0;
2679
2680         queue = 0;
2681         for (i = 0; i < 0x40; i += 8) {
2682                 for (j = i; j < (i + 8); j++) {
2683                         nfp_reta_conf[0].reta[j] = queue;
2684                         nfp_reta_conf[1].reta[j] = queue++;
2685                         queue %= rx_queues;
2686                 }
2687         }
2688         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2689         if (ret != 0)
2690                 return ret;
2691
2692         dev_conf = &dev->data->dev_conf;
2693         if (!dev_conf) {
2694                 PMD_DRV_LOG(INFO, "wrong rss conf");
2695                 return -EINVAL;
2696         }
2697         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2698
2699         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2700
2701         return ret;
2702 }
2703
2704
2705 /* Initialise and register driver with DPDK Application */
2706 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2707         .dev_configure          = nfp_net_configure,
2708         .dev_start              = nfp_net_start,
2709         .dev_stop               = nfp_net_stop,
2710         .dev_set_link_up        = nfp_net_set_link_up,
2711         .dev_set_link_down      = nfp_net_set_link_down,
2712         .dev_close              = nfp_net_close,
2713         .promiscuous_enable     = nfp_net_promisc_enable,
2714         .promiscuous_disable    = nfp_net_promisc_disable,
2715         .link_update            = nfp_net_link_update,
2716         .stats_get              = nfp_net_stats_get,
2717         .stats_reset            = nfp_net_stats_reset,
2718         .dev_infos_get          = nfp_net_infos_get,
2719         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2720         .mtu_set                = nfp_net_dev_mtu_set,
2721         .mac_addr_set           = nfp_set_mac_addr,
2722         .vlan_offload_set       = nfp_net_vlan_offload_set,
2723         .reta_update            = nfp_net_reta_update,
2724         .reta_query             = nfp_net_reta_query,
2725         .rss_hash_update        = nfp_net_rss_hash_update,
2726         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2727         .rx_queue_setup         = nfp_net_rx_queue_setup,
2728         .rx_queue_release       = nfp_net_rx_queue_release,
2729         .tx_queue_setup         = nfp_net_tx_queue_setup,
2730         .tx_queue_release       = nfp_net_tx_queue_release,
2731         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2732         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2733 };
2734
2735 /*
2736  * All eth_dev created got its private data, but before nfp_net_init, that
2737  * private data is referencing private data for all the PF ports. This is due
2738  * to how the vNIC bars are mapped based on first port, so all ports need info
2739  * about port 0 private data. Inside nfp_net_init the private data pointer is
2740  * changed to the right address for each port once the bars have been mapped.
2741  *
2742  * This functions helps to find out which port and therefore which offset
2743  * inside the private data array to use.
2744  */
2745 static int
2746 get_pf_port_number(char *name)
2747 {
2748         char *pf_str = name;
2749         int size = 0;
2750
2751         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2752                 pf_str++;
2753
2754         if (size == 30)
2755                 /*
2756                  * This should not happen at all and it would mean major
2757                  * implementation fault.
2758                  */
2759                 rte_panic("nfp_net: problem with pf device name\n");
2760
2761         /* Expecting _portX with X within [0,7] */
2762         pf_str += 5;
2763
2764         return (int)strtol(pf_str, NULL, 10);
2765 }
2766
2767 static int
2768 nfp_net_init(struct rte_eth_dev *eth_dev)
2769 {
2770         struct rte_pci_device *pci_dev;
2771         struct nfp_net_hw *hw, *hwport0;
2772
2773         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2774         uint32_t start_q;
2775         int stride = 4;
2776         int port = 0;
2777         int err;
2778
2779         PMD_INIT_FUNC_TRACE();
2780
2781         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2782
2783         /* NFP can not handle DMA addresses requiring more than 40 bits */
2784         if (rte_mem_check_dma_mask(40)) {
2785                 RTE_LOG(ERR, PMD, "device %s can not be used:",
2786                                    pci_dev->device.name);
2787                 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2788                 return -ENODEV;
2789         };
2790
2791         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2792             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2793                 port = get_pf_port_number(eth_dev->data->name);
2794                 if (port < 0 || port > 7) {
2795                         PMD_DRV_LOG(ERR, "Port value is wrong");
2796                         return -ENODEV;
2797                 }
2798
2799                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2800
2801                 /* This points to port 0 private data */
2802                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2803
2804                 /* This points to the specific port private data */
2805                 hw = &hwport0[port];
2806         } else {
2807                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2808                 hwport0 = 0;
2809         }
2810
2811         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2812         eth_dev->rx_queue_count = nfp_net_rx_queue_count;
2813         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2814         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2815
2816         /* For secondary processes, the primary has done all the work */
2817         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2818                 return 0;
2819
2820         rte_eth_copy_pci_info(eth_dev, pci_dev);
2821
2822         hw->device_id = pci_dev->id.device_id;
2823         hw->vendor_id = pci_dev->id.vendor_id;
2824         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2825         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2826
2827         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2828                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2829                      pci_dev->addr.domain, pci_dev->addr.bus,
2830                      pci_dev->addr.devid, pci_dev->addr.function);
2831
2832         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2833         if (hw->ctrl_bar == NULL) {
2834                 PMD_DRV_LOG(ERR,
2835                         "hw->ctrl_bar is NULL. BAR0 not configured");
2836                 return -ENODEV;
2837         }
2838
2839         if (hw->is_pf && port == 0) {
2840                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2841                                              hw->total_ports * 32768,
2842                                              &hw->ctrl_area);
2843                 if (!hw->ctrl_bar) {
2844                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2845                         return -EIO;
2846                 }
2847
2848                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2849         }
2850
2851         if (port > 0) {
2852                 if (!hwport0->ctrl_bar)
2853                         return -ENODEV;
2854
2855                 /* address based on port0 offset */
2856                 hw->ctrl_bar = hwport0->ctrl_bar +
2857                                (port * NFP_PF_CSR_SLICE_SIZE);
2858         }
2859
2860         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2861
2862         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2863         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2864
2865         /* Work out where in the BAR the queues start. */
2866         switch (pci_dev->id.device_id) {
2867         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2868         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2869         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2870                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2871                 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2872                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2873                 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2874                 break;
2875         default:
2876                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2877                 err = -ENODEV;
2878                 goto dev_err_ctrl_map;
2879         }
2880
2881         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2882         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2883
2884         if (hw->is_pf && port == 0) {
2885                 /* configure access to tx/rx vNIC BARs */
2886                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2887                                                       NFP_PCIE_QUEUE(0),
2888                                                       NFP_QCP_QUEUE_AREA_SZ,
2889                                                       &hw->hwqueues_area);
2890
2891                 if (!hwport0->hw_queues) {
2892                         printf("nfp_rtsym_map fails for net.qc");
2893                         err = -EIO;
2894                         goto dev_err_ctrl_map;
2895                 }
2896
2897                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2898                                     hwport0->hw_queues);
2899         }
2900
2901         if (hw->is_pf) {
2902                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2903                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2904                 eth_dev->data->dev_private = hw;
2905         } else {
2906                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2907                              tx_bar_off;
2908                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2909                              rx_bar_off;
2910         }
2911
2912         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2913                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2914
2915         nfp_net_cfg_queue_setup(hw);
2916
2917         /* Get some of the read-only fields from the config BAR */
2918         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2919         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2920         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2921         hw->mtu = RTE_ETHER_MTU;
2922
2923         /* VLAN insertion is incompatible with LSOv2 */
2924         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2925                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2926
2927         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2928                 hw->rx_offset = NFP_NET_RX_OFFSET;
2929         else
2930                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2931
2932         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2933                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2934                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2935
2936         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2937                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2938                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2939                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2940                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2941                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2942                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2943                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2944                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2945                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2946                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2947                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2948                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2949                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2950                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2951
2952         hw->ctrl = 0;
2953
2954         hw->stride_rx = stride;
2955         hw->stride_tx = stride;
2956
2957         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2958                      hw->max_rx_queues, hw->max_tx_queues);
2959
2960         /* Initializing spinlock for reconfigs */
2961         rte_spinlock_init(&hw->reconfig_lock);
2962
2963         /* Allocating memory for mac addr */
2964         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2965                                                RTE_ETHER_ADDR_LEN, 0);
2966         if (eth_dev->data->mac_addrs == NULL) {
2967                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2968                 err = -ENOMEM;
2969                 goto dev_err_queues_map;
2970         }
2971
2972         if (hw->is_pf) {
2973                 nfp_net_pf_read_mac(hwport0, port);
2974                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2975         } else {
2976                 nfp_net_vf_read_mac(hw);
2977         }
2978
2979         if (!rte_is_valid_assigned_ether_addr(
2980                     (struct rte_ether_addr *)&hw->mac_addr)) {
2981                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2982                                    port);
2983                 /* Using random mac addresses for VFs */
2984                 rte_eth_random_addr(&hw->mac_addr[0]);
2985                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2986         }
2987
2988         /* Copying mac address to DPDK eth_dev struct */
2989         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2990                         &eth_dev->data->mac_addrs[0]);
2991
2992         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2993                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2994
2995         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2996
2997         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2998                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2999                      eth_dev->data->port_id, pci_dev->id.vendor_id,
3000                      pci_dev->id.device_id,
3001                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
3002                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
3003
3004         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3005                 /* Registering LSC interrupt handler */
3006                 rte_intr_callback_register(&pci_dev->intr_handle,
3007                                            nfp_net_dev_interrupt_handler,
3008                                            (void *)eth_dev);
3009                 /* Telling the firmware about the LSC interrupt entry */
3010                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3011                 /* Recording current stats counters values */
3012                 nfp_net_stats_reset(eth_dev);
3013         }
3014
3015         return 0;
3016
3017 dev_err_queues_map:
3018                 nfp_cpp_area_free(hw->hwqueues_area);
3019 dev_err_ctrl_map:
3020                 nfp_cpp_area_free(hw->ctrl_area);
3021
3022         return err;
3023 }
3024
3025 #define NFP_CPP_MEMIO_BOUNDARY          (1 << 20)
3026
3027 /*
3028  * Serving a write request to NFP from host programs. The request
3029  * sends the write size and the CPP target. The bridge makes use
3030  * of CPP interface handler configured by the PMD setup.
3031  */
3032 static int
3033 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3034 {
3035         struct nfp_cpp_area *area;
3036         off_t offset, nfp_offset;
3037         uint32_t cpp_id, pos, len;
3038         uint32_t tmpbuf[16];
3039         size_t count, curlen, totlen = 0;
3040         int err = 0;
3041
3042         PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3043                 sizeof(off_t), sizeof(size_t));
3044
3045         /* Reading the count param */
3046         err = recv(sockfd, &count, sizeof(off_t), 0);
3047         if (err != sizeof(off_t))
3048                 return -EINVAL;
3049
3050         curlen = count;
3051
3052         /* Reading the offset param */
3053         err = recv(sockfd, &offset, sizeof(off_t), 0);
3054         if (err != sizeof(off_t))
3055                 return -EINVAL;
3056
3057         /* Obtain target's CPP ID and offset in target */
3058         cpp_id = (offset >> 40) << 8;
3059         nfp_offset = offset & ((1ull << 40) - 1);
3060
3061         PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3062                 offset);
3063         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3064                 cpp_id, nfp_offset);
3065
3066         /* Adjust length if not aligned */
3067         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3068             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3069                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3070                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3071         }
3072
3073         while (count > 0) {
3074                 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3075                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3076                                                     nfp_offset, curlen);
3077                 if (!area) {
3078                         RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3079                         return -EIO;
3080                 }
3081
3082                 /* mapping the target */
3083                 err = nfp_cpp_area_acquire(area);
3084                 if (err < 0) {
3085                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3086                         nfp_cpp_area_free(area);
3087                         return -EIO;
3088                 }
3089
3090                 for (pos = 0; pos < curlen; pos += len) {
3091                         len = curlen - pos;
3092                         if (len > sizeof(tmpbuf))
3093                                 len = sizeof(tmpbuf);
3094
3095                         PMD_CPP_LOG(DEBUG, "%s: Receive %u of %zu\n", __func__,
3096                                            len, count);
3097                         err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3098                         if (err != (int)len) {
3099                                 RTE_LOG(ERR, PMD,
3100                                         "%s: error when receiving, %d of %zu\n",
3101                                         __func__, err, count);
3102                                 nfp_cpp_area_release(area);
3103                                 nfp_cpp_area_free(area);
3104                                 return -EIO;
3105                         }
3106                         err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3107                         if (err < 0) {
3108                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3109                                 nfp_cpp_area_release(area);
3110                                 nfp_cpp_area_free(area);
3111                                 return -EIO;
3112                         }
3113                 }
3114
3115                 nfp_offset += pos;
3116                 totlen += pos;
3117                 nfp_cpp_area_release(area);
3118                 nfp_cpp_area_free(area);
3119
3120                 count -= pos;
3121                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3122                          NFP_CPP_MEMIO_BOUNDARY : count;
3123         }
3124
3125         return 0;
3126 }
3127
3128 /*
3129  * Serving a read request to NFP from host programs. The request
3130  * sends the read size and the CPP target. The bridge makes use
3131  * of CPP interface handler configured by the PMD setup. The read
3132  * data is sent to the requester using the same socket.
3133  */
3134 static int
3135 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3136 {
3137         struct nfp_cpp_area *area;
3138         off_t offset, nfp_offset;
3139         uint32_t cpp_id, pos, len;
3140         uint32_t tmpbuf[16];
3141         size_t count, curlen, totlen = 0;
3142         int err = 0;
3143
3144         PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3145                 sizeof(off_t), sizeof(size_t));
3146
3147         /* Reading the count param */
3148         err = recv(sockfd, &count, sizeof(off_t), 0);
3149         if (err != sizeof(off_t))
3150                 return -EINVAL;
3151
3152         curlen = count;
3153
3154         /* Reading the offset param */
3155         err = recv(sockfd, &offset, sizeof(off_t), 0);
3156         if (err != sizeof(off_t))
3157                 return -EINVAL;
3158
3159         /* Obtain target's CPP ID and offset in target */
3160         cpp_id = (offset >> 40) << 8;
3161         nfp_offset = offset & ((1ull << 40) - 1);
3162
3163         PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3164                            offset);
3165         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3166                            cpp_id, nfp_offset);
3167
3168         /* Adjust length if not aligned */
3169         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3170             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3171                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3172                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3173         }
3174
3175         while (count > 0) {
3176                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3177                                                     nfp_offset, curlen);
3178                 if (!area) {
3179                         RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3180                         return -EIO;
3181                 }
3182
3183                 err = nfp_cpp_area_acquire(area);
3184                 if (err < 0) {
3185                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3186                         nfp_cpp_area_free(area);
3187                         return -EIO;
3188                 }
3189
3190                 for (pos = 0; pos < curlen; pos += len) {
3191                         len = curlen - pos;
3192                         if (len > sizeof(tmpbuf))
3193                                 len = sizeof(tmpbuf);
3194
3195                         err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3196                         if (err < 0) {
3197                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3198                                 nfp_cpp_area_release(area);
3199                                 nfp_cpp_area_free(area);
3200                                 return -EIO;
3201                         }
3202                         PMD_CPP_LOG(DEBUG, "%s: sending %u of %zu\n", __func__,
3203                                            len, count);
3204
3205                         err = send(sockfd, tmpbuf, len, 0);
3206                         if (err != (int)len) {
3207                                 RTE_LOG(ERR, PMD,
3208                                         "%s: error when sending: %d of %zu\n",
3209                                         __func__, err, count);
3210                                 nfp_cpp_area_release(area);
3211                                 nfp_cpp_area_free(area);
3212                                 return -EIO;
3213                         }
3214                 }
3215
3216                 nfp_offset += pos;
3217                 totlen += pos;
3218                 nfp_cpp_area_release(area);
3219                 nfp_cpp_area_free(area);
3220
3221                 count -= pos;
3222                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3223                         NFP_CPP_MEMIO_BOUNDARY : count;
3224         }
3225         return 0;
3226 }
3227
3228 #define NFP_IOCTL 'n'
3229 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3230 /*
3231  * Serving a ioctl command from host NFP tools. This usually goes to
3232  * a kernel driver char driver but it is not available when the PF is
3233  * bound to the PMD. Currently just one ioctl command is served and it
3234  * does not require any CPP access at all.
3235  */
3236 static int
3237 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3238 {
3239         uint32_t cmd, ident_size, tmp;
3240         int err;
3241
3242         /* Reading now the IOCTL command */
3243         err = recv(sockfd, &cmd, 4, 0);
3244         if (err != 4) {
3245                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3246                 return -EIO;
3247         }
3248
3249         /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3250         if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3251                 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3252                 return -EINVAL;
3253         }
3254
3255         err = recv(sockfd, &ident_size, 4, 0);
3256         if (err != 4) {
3257                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3258                 return -EIO;
3259         }
3260
3261         tmp = nfp_cpp_model(cpp);
3262
3263         PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3264
3265         err = send(sockfd, &tmp, 4, 0);
3266         if (err != 4) {
3267                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3268                 return -EIO;
3269         }
3270
3271         tmp = cpp->interface;
3272
3273         PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3274
3275         err = send(sockfd, &tmp, 4, 0);
3276         if (err != 4) {
3277                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3278                 return -EIO;
3279         }
3280
3281         return 0;
3282 }
3283
3284 #define NFP_BRIDGE_OP_READ      20
3285 #define NFP_BRIDGE_OP_WRITE     30
3286 #define NFP_BRIDGE_OP_IOCTL     40
3287
3288 /*
3289  * This is the code to be executed by a service core. The CPP bridge interface
3290  * is based on a unix socket and requests usually received by a kernel char
3291  * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3292  * can be executed with a wrapper library and LD_LIBRARY being completely
3293  * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3294  * accesses.
3295  */
3296 static int32_t
3297 nfp_cpp_bridge_service_func(void *args)
3298 {
3299         struct sockaddr address;
3300         struct nfp_cpp *cpp = args;
3301         int sockfd, datafd, op, ret;
3302
3303         unlink("/tmp/nfp_cpp");
3304         sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3305         if (sockfd < 0) {
3306                 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3307                         __func__);
3308                 return -EIO;
3309         }
3310
3311         memset(&address, 0, sizeof(struct sockaddr));
3312
3313         address.sa_family = AF_UNIX;
3314         strcpy(address.sa_data, "/tmp/nfp_cpp");
3315
3316         ret = bind(sockfd, (const struct sockaddr *)&address,
3317                    sizeof(struct sockaddr));
3318         if (ret < 0) {
3319                 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3320                                   __func__, errno);
3321                 close(sockfd);
3322                 return ret;
3323         }
3324
3325         ret = listen(sockfd, 20);
3326         if (ret < 0) {
3327                 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3328                                   __func__, errno);
3329                 close(sockfd);
3330                 return ret;
3331         }
3332
3333         for (;;) {
3334                 datafd = accept(sockfd, NULL, NULL);
3335                 if (datafd < 0) {
3336                         RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3337                                           __func__, errno);
3338                         RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3339                         close(sockfd);
3340                         return -EIO;
3341                 }
3342
3343                 while (1) {
3344                         ret = recv(datafd, &op, 4, 0);
3345                         if (ret <= 0) {
3346                                 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3347                                                    __func__);
3348                                 break;
3349                         }
3350
3351                         PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3352
3353                         if (op == NFP_BRIDGE_OP_READ)
3354                                 nfp_cpp_bridge_serve_read(datafd, cpp);
3355
3356                         if (op == NFP_BRIDGE_OP_WRITE)
3357                                 nfp_cpp_bridge_serve_write(datafd, cpp);
3358
3359                         if (op == NFP_BRIDGE_OP_IOCTL)
3360                                 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3361
3362                         if (op == 0)
3363                                 break;
3364                 }
3365                 close(datafd);
3366         }
3367         close(sockfd);
3368
3369         return 0;
3370 }
3371
3372 static int
3373 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3374                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3375                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3376 {
3377         struct rte_eth_dev *eth_dev;
3378         struct nfp_net_hw *hw = NULL;
3379         char *port_name;
3380         struct rte_service_spec service;
3381         int retval;
3382
3383         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3384         if (!port_name)
3385                 return -ENOMEM;
3386
3387         if (ports > 1)
3388                 snprintf(port_name, 100, "%s_port%d", dev->device.name, port);
3389         else
3390                 strlcat(port_name, dev->device.name, 100);
3391
3392
3393         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3394                 eth_dev = rte_eth_dev_allocate(port_name);
3395                 if (!eth_dev) {
3396                         rte_free(port_name);
3397                         return -ENODEV;
3398                 }
3399                 if (port == 0) {
3400                         *priv = rte_zmalloc(port_name,
3401                                             sizeof(struct nfp_net_adapter) *
3402                                             ports, RTE_CACHE_LINE_SIZE);
3403                         if (!*priv) {
3404                                 rte_free(port_name);
3405                                 rte_eth_dev_release_port(eth_dev);
3406                                 return -ENOMEM;
3407                         }
3408                 }
3409                 eth_dev->data->dev_private = *priv;
3410
3411                 /*
3412                  * dev_private pointing to port0 dev_private because we need
3413                  * to configure vNIC bars based on port0 at nfp_net_init.
3414                  * Then dev_private is adjusted per port.
3415                  */
3416                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3417                 hw->cpp = cpp;
3418                 hw->hwinfo = hwinfo;
3419                 hw->sym_tbl = sym_tbl;
3420                 hw->pf_port_idx = phys_port;
3421                 hw->is_pf = 1;
3422                 if (ports > 1)
3423                         hw->pf_multiport_enabled = 1;
3424
3425                 hw->total_ports = ports;
3426         } else {
3427                 eth_dev = rte_eth_dev_attach_secondary(port_name);
3428                 if (!eth_dev) {
3429                         RTE_LOG(ERR, EAL, "secondary process attach failed, "
3430                                 "ethdev doesn't exist");
3431                         rte_free(port_name);
3432                         return -ENODEV;
3433                 }
3434                 eth_dev->process_private = cpp;
3435         }
3436
3437         eth_dev->device = &dev->device;
3438         rte_eth_copy_pci_info(eth_dev, dev);
3439
3440         retval = nfp_net_init(eth_dev);
3441
3442         if (retval) {
3443                 retval = -ENODEV;
3444                 goto probe_failed;
3445         } else {
3446                 rte_eth_dev_probing_finish(eth_dev);
3447         }
3448
3449         rte_free(port_name);
3450
3451         if (port == 0) {
3452                 /*
3453                  * The rte_service needs to be created just once per PMD.
3454                  * And the cpp handler needs to be linked to the service.
3455                  * Secondary processes will be used for debugging DPDK apps
3456                  * when requiring to use the CPP interface for accessing NFP
3457                  * components. And the cpp handler for secondary processes is
3458                  * available at this point.
3459                  */
3460                 memset(&service, 0, sizeof(struct rte_service_spec));
3461                 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3462                 service.callback = nfp_cpp_bridge_service_func;
3463                 service.callback_userdata = (void *)cpp;
3464
3465                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
3466
3467                 if (rte_service_component_register(&service,
3468                                                    &hw->nfp_cpp_service_id))
3469                         RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3470                 else
3471                         RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3472         }
3473
3474         return retval;
3475
3476 probe_failed:
3477         rte_free(port_name);
3478         /* free ports private data if primary process */
3479         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3480                 rte_free(eth_dev->data->dev_private);
3481                 eth_dev->data->dev_private = NULL;
3482         }
3483         rte_eth_dev_release_port(eth_dev);
3484
3485         return retval;
3486 }
3487
3488 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
3489
3490 static int
3491 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3492 {
3493         struct nfp_cpp *cpp = nsp->cpp;
3494         int fw_f;
3495         char *fw_buf;
3496         char fw_name[125];
3497         char serial[40];
3498         struct stat file_stat;
3499         off_t fsize, bytes;
3500
3501         /* Looking for firmware file in order of priority */
3502
3503         /* First try to find a firmware image specific for this device */
3504         snprintf(serial, sizeof(serial),
3505                         "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3506                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3507                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3508                 cpp->interface & 0xff);
3509
3510         snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3511                         serial);
3512
3513         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3514         fw_f = open(fw_name, O_RDONLY);
3515         if (fw_f >= 0)
3516                 goto read_fw;
3517
3518         /* Then try the PCI name */
3519         snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3520                         dev->device.name);
3521
3522         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3523         fw_f = open(fw_name, O_RDONLY);
3524         if (fw_f >= 0)
3525                 goto read_fw;
3526
3527         /* Finally try the card type and media */
3528         snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3529         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3530         fw_f = open(fw_name, O_RDONLY);
3531         if (fw_f < 0) {
3532                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3533                 return -ENOENT;
3534         }
3535
3536 read_fw:
3537         if (fstat(fw_f, &file_stat) < 0) {
3538                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3539                 close(fw_f);
3540                 return -ENOENT;
3541         }
3542
3543         fsize = file_stat.st_size;
3544         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3545                             fw_name, (uint64_t)fsize);
3546
3547         fw_buf = malloc((size_t)fsize);
3548         if (!fw_buf) {
3549                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3550                 close(fw_f);
3551                 return -ENOMEM;
3552         }
3553         memset(fw_buf, 0, fsize);
3554
3555         bytes = read(fw_f, fw_buf, fsize);
3556         if (bytes != fsize) {
3557                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3558                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3559                                    (uint64_t)bytes, (uint64_t)fsize);
3560                 free(fw_buf);
3561                 close(fw_f);
3562                 return -EIO;
3563         }
3564
3565         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3566         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3567         PMD_DRV_LOG(INFO, "Done");
3568
3569         free(fw_buf);
3570         close(fw_f);
3571
3572         return 0;
3573 }
3574
3575 static int
3576 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3577              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3578 {
3579         struct nfp_nsp *nsp;
3580         const char *nfp_fw_model;
3581         char card_desc[100];
3582         int err = 0;
3583
3584         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3585
3586         if (nfp_fw_model) {
3587                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3588         } else {
3589                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3590                 return -EIO;
3591         }
3592
3593         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3594                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3595                        nfp_eth_table->count);
3596                 return -EIO;
3597         }
3598
3599         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3600                            nfp_eth_table->count);
3601
3602         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3603
3604         snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3605                         nfp_fw_model, nfp_eth_table->count,
3606                         nfp_eth_table->ports[0].speed / 1000);
3607
3608         nsp = nfp_nsp_open(cpp);
3609         if (!nsp) {
3610                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3611                 return -EIO;
3612         }
3613
3614         nfp_nsp_device_soft_reset(nsp);
3615         err = nfp_fw_upload(dev, nsp, card_desc);
3616
3617         nfp_nsp_close(nsp);
3618         return err;
3619 }
3620
3621 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3622                             struct rte_pci_device *dev)
3623 {
3624         struct nfp_cpp *cpp;
3625         struct nfp_hwinfo *hwinfo;
3626         struct nfp_rtsym_table *sym_tbl;
3627         struct nfp_eth_table *nfp_eth_table = NULL;
3628         int total_ports;
3629         void *priv = 0;
3630         int ret = -ENODEV;
3631         int err;
3632         int i;
3633
3634         if (!dev)
3635                 return ret;
3636
3637         /*
3638          * When device bound to UIO, the device could be used, by mistake,
3639          * by two DPDK apps, and the UIO driver does not avoid it. This
3640          * could lead to a serious problem when configuring the NFP CPP
3641          * interface. Here we avoid this telling to the CPP init code to
3642          * use a lock file if UIO is being used.
3643          */
3644         if (dev->kdrv == RTE_PCI_KDRV_VFIO)
3645                 cpp = nfp_cpp_from_device_name(dev, 0);
3646         else
3647                 cpp = nfp_cpp_from_device_name(dev, 1);
3648
3649         if (!cpp) {
3650                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3651                 ret = -EIO;
3652                 goto error;
3653         }
3654
3655         hwinfo = nfp_hwinfo_read(cpp);
3656         if (!hwinfo) {
3657                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3658                 return -EIO;
3659         }
3660
3661         nfp_eth_table = nfp_eth_read_ports(cpp);
3662         if (!nfp_eth_table) {
3663                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3664                 return -EIO;
3665         }
3666
3667         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3668                 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3669                         PMD_DRV_LOG(INFO, "Error when uploading firmware");
3670                         ret = -EIO;
3671                         goto error;
3672                 }
3673         }
3674
3675         /* Now the symbol table should be there */
3676         sym_tbl = nfp_rtsym_table_read(cpp);
3677         if (!sym_tbl) {
3678                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3679                                 " symbol table");
3680                 ret = -EIO;
3681                 goto error;
3682         }
3683
3684         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3685         if (total_ports != (int)nfp_eth_table->count) {
3686                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3687                 ret = -EIO;
3688                 goto error;
3689         }
3690         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3691
3692         if (total_ports <= 0 || total_ports > 8) {
3693                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3694                 ret = -ENODEV;
3695                 goto error;
3696         }
3697
3698         for (i = 0; i < total_ports; i++) {
3699                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3700                                         nfp_eth_table->ports[i].index,
3701                                         sym_tbl, &priv);
3702                 if (ret)
3703                         break;
3704         }
3705
3706 error:
3707         free(nfp_eth_table);
3708         return ret;
3709 }
3710
3711 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3712         {
3713                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3714                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3715         },
3716         {
3717                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3718                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3719         },
3720         {
3721                 .vendor_id = 0,
3722         },
3723 };
3724
3725 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3726         {
3727                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3728                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3729         },
3730         {
3731                 .vendor_id = 0,
3732         },
3733 };
3734
3735 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3736         struct rte_pci_device *pci_dev)
3737 {
3738         return rte_eth_dev_pci_generic_probe(pci_dev,
3739                 sizeof(struct nfp_net_adapter), nfp_net_init);
3740 }
3741
3742 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3743 {
3744         struct rte_eth_dev *eth_dev;
3745         struct nfp_net_hw *hw, *hwport0;
3746         int port = 0;
3747
3748         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3749         if (eth_dev == NULL)
3750                 return 0; /* port already released */
3751         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3752             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3753                 port = get_pf_port_number(eth_dev->data->name);
3754                 /*
3755                  * hotplug is not possible with multiport PF although freeing
3756                  * data structures can be done for first port.
3757                  */
3758                 if (port != 0)
3759                         return -ENOTSUP;
3760                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3761                 hw = &hwport0[port];
3762                 nfp_cpp_area_free(hw->ctrl_area);
3763                 nfp_cpp_area_free(hw->hwqueues_area);
3764                 free(hw->hwinfo);
3765                 free(hw->sym_tbl);
3766                 nfp_cpp_free(hw->cpp);
3767         } else {
3768                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3769         }
3770         /* hotplug is not possible with multiport PF */
3771         if (hw->pf_multiport_enabled)
3772                 return -ENOTSUP;
3773         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3774 }
3775
3776 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3777         .id_table = pci_id_nfp_pf_net_map,
3778         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3779         .probe = nfp_pf_pci_probe,
3780         .remove = eth_nfp_pci_remove,
3781 };
3782
3783 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3784         .id_table = pci_id_nfp_vf_net_map,
3785         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3786         .probe = eth_nfp_pci_probe,
3787         .remove = eth_nfp_pci_remove,
3788 };
3789
3790 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3791 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3792 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3793 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3794 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3795 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3796 RTE_LOG_REGISTER(nfp_logtype_init, pmd.net.nfp.init, NOTICE);
3797 RTE_LOG_REGISTER(nfp_logtype_driver, pmd.net.nfp.driver, NOTICE);
3798 /*
3799  * Local variables:
3800  * c-file-style: "Linux"
3801  * indent-tabs-mode: t
3802  * End:
3803  */