1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
9 * vim:shiftwidth=8:noexpandtab
11 * @file dpdk/pmd/nfp_net.c
13 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
19 #include <rte_debug.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
23 #include <rte_ether.h>
24 #include <rte_malloc.h>
25 #include <rte_memzone.h>
26 #include <rte_mempool.h>
27 #include <rte_version.h>
28 #include <rte_string_fns.h>
29 #include <rte_alarm.h>
30 #include <rte_spinlock.h>
31 #include <rte_service_component.h>
33 #include "nfpcore/nfp_cpp.h"
34 #include "nfpcore/nfp_nffw.h"
35 #include "nfpcore/nfp_hwinfo.h"
36 #include "nfpcore/nfp_mip.h"
37 #include "nfpcore/nfp_rtsym.h"
38 #include "nfpcore/nfp_nsp.h"
40 #include "nfp_net_pmd.h"
41 #include "nfp_net_logs.h"
42 #include "nfp_net_ctrl.h"
44 #include <sys/types.h>
45 #include <sys/socket.h>
49 #include <sys/ioctl.h>
53 static void nfp_net_close(struct rte_eth_dev *dev);
54 static int nfp_net_configure(struct rte_eth_dev *dev);
55 static void nfp_net_dev_interrupt_handler(void *param);
56 static void nfp_net_dev_interrupt_delayed_handler(void *param);
57 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
58 static int nfp_net_infos_get(struct rte_eth_dev *dev,
59 struct rte_eth_dev_info *dev_info);
60 static int nfp_net_init(struct rte_eth_dev *eth_dev);
61 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
62 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
63 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
64 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
65 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
67 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
69 static void nfp_net_rx_queue_release(void *rxq);
70 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
71 uint16_t nb_desc, unsigned int socket_id,
72 const struct rte_eth_rxconf *rx_conf,
73 struct rte_mempool *mp);
74 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
75 static void nfp_net_tx_queue_release(void *txq);
76 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
77 uint16_t nb_desc, unsigned int socket_id,
78 const struct rte_eth_txconf *tx_conf);
79 static int nfp_net_start(struct rte_eth_dev *dev);
80 static int nfp_net_stats_get(struct rte_eth_dev *dev,
81 struct rte_eth_stats *stats);
82 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
83 static void nfp_net_stop(struct rte_eth_dev *dev);
84 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
87 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
88 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
89 struct rte_eth_rss_conf *rss_conf);
90 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
91 struct rte_eth_rss_reta_entry64 *reta_conf,
93 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
94 struct rte_eth_rss_conf *rss_conf);
95 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
96 struct rte_ether_addr *mac_addr);
98 /* The offset of the queue controller queues in the PCIe Target */
99 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
101 /* Maximum value which can be added to a queue with one transaction */
102 #define NFP_QCP_MAX_ADD 0x7f
104 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
105 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
107 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
109 NFP_QCP_READ_PTR = 0,
114 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
115 * @q: Base address for queue structure
116 * @ptr: Add to the Read or Write pointer
117 * @val: Value to add to the queue pointer
119 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
122 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
126 if (ptr == NFP_QCP_READ_PTR)
127 off = NFP_QCP_QUEUE_ADD_RPTR;
129 off = NFP_QCP_QUEUE_ADD_WPTR;
131 while (val > NFP_QCP_MAX_ADD) {
132 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
133 val -= NFP_QCP_MAX_ADD;
136 nn_writel(rte_cpu_to_le_32(val), q + off);
140 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
141 * @q: Base address for queue structure
142 * @ptr: Read or Write pointer
144 static inline uint32_t
145 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
150 if (ptr == NFP_QCP_READ_PTR)
151 off = NFP_QCP_QUEUE_STS_LO;
153 off = NFP_QCP_QUEUE_STS_HI;
155 val = rte_cpu_to_le_32(nn_readl(q + off));
157 if (ptr == NFP_QCP_READ_PTR)
158 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
160 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
164 * Functions to read/write from/to Config BAR
165 * Performs any endian conversion necessary.
167 static inline uint8_t
168 nn_cfg_readb(struct nfp_net_hw *hw, int off)
170 return nn_readb(hw->ctrl_bar + off);
174 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
176 nn_writeb(val, hw->ctrl_bar + off);
179 static inline uint32_t
180 nn_cfg_readl(struct nfp_net_hw *hw, int off)
182 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
186 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
188 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
191 static inline uint64_t
192 nn_cfg_readq(struct nfp_net_hw *hw, int off)
194 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
198 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
200 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
204 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
208 if (rxq->rxbufs == NULL)
211 for (i = 0; i < rxq->rx_count; i++) {
212 if (rxq->rxbufs[i].mbuf) {
213 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
214 rxq->rxbufs[i].mbuf = NULL;
220 nfp_net_rx_queue_release(void *rx_queue)
222 struct nfp_net_rxq *rxq = rx_queue;
225 nfp_net_rx_queue_release_mbufs(rxq);
226 rte_free(rxq->rxbufs);
232 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
234 nfp_net_rx_queue_release_mbufs(rxq);
240 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
244 if (txq->txbufs == NULL)
247 for (i = 0; i < txq->tx_count; i++) {
248 if (txq->txbufs[i].mbuf) {
249 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
250 txq->txbufs[i].mbuf = NULL;
256 nfp_net_tx_queue_release(void *tx_queue)
258 struct nfp_net_txq *txq = tx_queue;
261 nfp_net_tx_queue_release_mbufs(txq);
262 rte_free(txq->txbufs);
268 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
270 nfp_net_tx_queue_release_mbufs(txq);
276 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
280 struct timespec wait;
282 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
285 if (hw->qcp_cfg == NULL)
286 rte_panic("Bad configuration queue pointer\n");
288 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
291 wait.tv_nsec = 1000000;
293 PMD_DRV_LOG(DEBUG, "Polling for update ack...");
295 /* Poll update field, waiting for NFP to ack the config */
296 for (cnt = 0; ; cnt++) {
297 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
300 if (new & NFP_NET_CFG_UPDATE_ERR) {
301 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
304 if (cnt >= NFP_NET_POLL_TIMEOUT) {
305 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
306 " %dms", update, cnt);
307 rte_panic("Exiting\n");
309 nanosleep(&wait, 0); /* waiting for a 1ms */
311 PMD_DRV_LOG(DEBUG, "Ack DONE");
316 * Reconfigure the NIC
317 * @nn: device to reconfigure
318 * @ctrl: The value for the ctrl field in the BAR config
319 * @update: The value for the update field in the BAR config
321 * Write the update word to the BAR and ping the reconfig queue. Then poll
322 * until the firmware has acknowledged the update by zeroing the update word.
325 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
329 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
332 rte_spinlock_lock(&hw->reconfig_lock);
334 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
335 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
339 err = __nfp_net_reconfig(hw, update);
341 rte_spinlock_unlock(&hw->reconfig_lock);
347 * Reconfig errors imply situations where they can be handled.
348 * Otherwise, rte_panic is called inside __nfp_net_reconfig
350 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
356 * Configure an Ethernet device. This function must be invoked first
357 * before any other function in the Ethernet API. This function can
358 * also be re-invoked when a device is in the stopped state.
361 nfp_net_configure(struct rte_eth_dev *dev)
363 struct rte_eth_conf *dev_conf;
364 struct rte_eth_rxmode *rxmode;
365 struct rte_eth_txmode *txmode;
366 struct nfp_net_hw *hw;
368 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
371 * A DPDK app sends info about how many queues to use and how
372 * those queues need to be configured. This is used by the
373 * DPDK core and it makes sure no more queues than those
374 * advertised by the driver are requested. This function is
375 * called after that internal process
378 PMD_INIT_LOG(DEBUG, "Configure");
380 dev_conf = &dev->data->dev_conf;
381 rxmode = &dev_conf->rxmode;
382 txmode = &dev_conf->txmode;
384 if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
385 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
387 /* Checking TX mode */
388 if (txmode->mq_mode) {
389 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
393 /* Checking RX mode */
394 if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
395 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
396 PMD_INIT_LOG(INFO, "RSS not supported");
404 nfp_net_enable_queues(struct rte_eth_dev *dev)
406 struct nfp_net_hw *hw;
407 uint64_t enabled_queues = 0;
410 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
412 /* Enabling the required TX queues in the device */
413 for (i = 0; i < dev->data->nb_tx_queues; i++)
414 enabled_queues |= (1 << i);
416 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
420 /* Enabling the required RX queues in the device */
421 for (i = 0; i < dev->data->nb_rx_queues; i++)
422 enabled_queues |= (1 << i);
424 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
428 nfp_net_disable_queues(struct rte_eth_dev *dev)
430 struct nfp_net_hw *hw;
431 uint32_t new_ctrl, update = 0;
433 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
435 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
436 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
438 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
439 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
440 NFP_NET_CFG_UPDATE_MSIX;
442 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
443 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
445 /* If an error when reconfig we avoid to change hw state */
446 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
453 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
457 for (i = 0; i < dev->data->nb_rx_queues; i++) {
458 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
465 nfp_net_params_setup(struct nfp_net_hw *hw)
467 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
468 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
472 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
474 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
477 #define ETH_ADDR_LEN 6
480 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
484 for (i = 0; i < ETH_ADDR_LEN; i++)
489 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
491 struct nfp_eth_table *nfp_eth_table;
493 nfp_eth_table = nfp_eth_read_ports(hw->cpp);
495 * hw points to port0 private data. We need hw now pointing to
499 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
500 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
507 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
511 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
512 memcpy(&hw->mac_addr[0], &tmp, 4);
514 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
515 memcpy(&hw->mac_addr[4], &tmp, 2);
519 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
521 uint32_t mac0 = *(uint32_t *)mac;
524 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
527 mac1 = *(uint16_t *)mac;
528 nn_writew(rte_cpu_to_be_16(mac1),
529 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
533 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
535 struct nfp_net_hw *hw;
536 uint32_t update, ctrl;
538 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
539 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
540 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
541 PMD_INIT_LOG(INFO, "MAC address unable to change when"
546 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
547 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
550 /* Writing new MAC to the specific port BAR address */
551 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
553 /* Signal the NIC about the change */
554 update = NFP_NET_CFG_UPDATE_MACADDR;
556 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
557 (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
558 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
559 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
560 PMD_INIT_LOG(INFO, "MAC address update failed");
567 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
568 struct rte_intr_handle *intr_handle)
570 struct nfp_net_hw *hw;
573 if (!intr_handle->intr_vec) {
574 intr_handle->intr_vec =
575 rte_zmalloc("intr_vec",
576 dev->data->nb_rx_queues * sizeof(int), 0);
577 if (!intr_handle->intr_vec) {
578 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
579 " intr_vec", dev->data->nb_rx_queues);
584 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
586 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
587 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
588 /* UIO just supports one queue and no LSC*/
589 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
590 intr_handle->intr_vec[0] = 0;
592 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
593 for (i = 0; i < dev->data->nb_rx_queues; i++) {
595 * The first msix vector is reserved for non
598 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
599 intr_handle->intr_vec[i] = i + 1;
600 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
601 intr_handle->intr_vec[i]);
605 /* Avoiding TX interrupts */
606 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
611 nfp_check_offloads(struct rte_eth_dev *dev)
613 struct nfp_net_hw *hw;
614 struct rte_eth_conf *dev_conf;
615 struct rte_eth_rxmode *rxmode;
616 struct rte_eth_txmode *txmode;
619 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
621 dev_conf = &dev->data->dev_conf;
622 rxmode = &dev_conf->rxmode;
623 txmode = &dev_conf->txmode;
625 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
626 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
627 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
630 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
631 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
632 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
635 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
636 hw->mtu = rxmode->max_rx_pkt_len;
638 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
639 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
642 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
643 ctrl |= NFP_NET_CFG_CTRL_L2BC;
646 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
647 ctrl |= NFP_NET_CFG_CTRL_L2MC;
649 /* TX checksum offload */
650 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
651 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
652 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
653 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
656 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
657 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
658 ctrl |= NFP_NET_CFG_CTRL_LSO;
660 ctrl |= NFP_NET_CFG_CTRL_LSO2;
664 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
665 ctrl |= NFP_NET_CFG_CTRL_GATHER;
671 nfp_net_start(struct rte_eth_dev *dev)
673 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
674 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
675 uint32_t new_ctrl, update = 0;
676 struct nfp_net_hw *hw;
677 struct rte_eth_conf *dev_conf;
678 struct rte_eth_rxmode *rxmode;
679 uint32_t intr_vector;
682 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
684 PMD_INIT_LOG(DEBUG, "Start");
686 /* Disabling queues just in case... */
687 nfp_net_disable_queues(dev);
689 /* Enabling the required queues in the device */
690 nfp_net_enable_queues(dev);
692 /* check and configure queue intr-vector mapping */
693 if (dev->data->dev_conf.intr_conf.rxq != 0) {
694 if (hw->pf_multiport_enabled) {
695 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
696 "with NFP multiport PF");
699 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
701 * Better not to share LSC with RX interrupts.
702 * Unregistering LSC interrupt handler
704 rte_intr_callback_unregister(&pci_dev->intr_handle,
705 nfp_net_dev_interrupt_handler, (void *)dev);
707 if (dev->data->nb_rx_queues > 1) {
708 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
709 "supports 1 queue with UIO");
713 intr_vector = dev->data->nb_rx_queues;
714 if (rte_intr_efd_enable(intr_handle, intr_vector))
717 nfp_configure_rx_interrupt(dev, intr_handle);
718 update = NFP_NET_CFG_UPDATE_MSIX;
721 rte_intr_enable(intr_handle);
723 new_ctrl = nfp_check_offloads(dev);
725 /* Writing configuration parameters in the device */
726 nfp_net_params_setup(hw);
728 dev_conf = &dev->data->dev_conf;
729 rxmode = &dev_conf->rxmode;
731 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
732 nfp_net_rss_config_default(dev);
733 update |= NFP_NET_CFG_UPDATE_RSS;
734 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
738 new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
740 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
742 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
743 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
745 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
746 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
750 * Allocating rte mbufs for configured rx queues.
751 * This requires queues being enabled before
753 if (nfp_net_rx_freelist_setup(dev) < 0) {
759 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
760 /* Configure the physical port up */
761 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
763 nfp_eth_set_configured(dev->process_private,
773 * An error returned by this function should mean the app
774 * exiting and then the system releasing all the memory
775 * allocated even memory coming from hugepages.
777 * The device could be enabled at this point with some queues
778 * ready for getting packets. This is true if the call to
779 * nfp_net_rx_freelist_setup() succeeds for some queues but
780 * fails for subsequent queues.
782 * This should make the app exiting but better if we tell the
785 nfp_net_disable_queues(dev);
790 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
792 nfp_net_stop(struct rte_eth_dev *dev)
795 struct nfp_net_hw *hw;
797 PMD_INIT_LOG(DEBUG, "Stop");
799 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
801 nfp_net_disable_queues(dev);
804 for (i = 0; i < dev->data->nb_tx_queues; i++) {
805 nfp_net_reset_tx_queue(
806 (struct nfp_net_txq *)dev->data->tx_queues[i]);
809 for (i = 0; i < dev->data->nb_rx_queues; i++) {
810 nfp_net_reset_rx_queue(
811 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
815 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
816 /* Configure the physical port down */
817 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
819 nfp_eth_set_configured(dev->process_private,
824 /* Set the link up. */
826 nfp_net_set_link_up(struct rte_eth_dev *dev)
828 struct nfp_net_hw *hw;
830 PMD_DRV_LOG(DEBUG, "Set link up");
832 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
837 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
838 /* Configure the physical port down */
839 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
841 return nfp_eth_set_configured(dev->process_private,
845 /* Set the link down. */
847 nfp_net_set_link_down(struct rte_eth_dev *dev)
849 struct nfp_net_hw *hw;
851 PMD_DRV_LOG(DEBUG, "Set link down");
853 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
858 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
859 /* Configure the physical port down */
860 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
862 return nfp_eth_set_configured(dev->process_private,
866 /* Reset and stop device. The device can not be restarted. */
868 nfp_net_close(struct rte_eth_dev *dev)
870 struct nfp_net_hw *hw;
871 struct rte_pci_device *pci_dev;
874 PMD_INIT_LOG(DEBUG, "Close");
876 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
877 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
880 * We assume that the DPDK application is stopping all the
881 * threads/queues before calling the device close function.
884 nfp_net_disable_queues(dev);
887 for (i = 0; i < dev->data->nb_tx_queues; i++) {
888 nfp_net_reset_tx_queue(
889 (struct nfp_net_txq *)dev->data->tx_queues[i]);
892 for (i = 0; i < dev->data->nb_rx_queues; i++) {
893 nfp_net_reset_rx_queue(
894 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
897 rte_intr_disable(&pci_dev->intr_handle);
898 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
900 /* unregister callback func from eal lib */
901 rte_intr_callback_unregister(&pci_dev->intr_handle,
902 nfp_net_dev_interrupt_handler,
906 * The ixgbe PMD driver disables the pcie master on the
907 * device. The i40e does not...
912 nfp_net_promisc_enable(struct rte_eth_dev *dev)
914 uint32_t new_ctrl, update = 0;
915 struct nfp_net_hw *hw;
918 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
920 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
922 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
923 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
927 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
928 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
932 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
933 update = NFP_NET_CFG_UPDATE_GEN;
936 * DPDK sets promiscuous mode on just after this call assuming
937 * it can not fail ...
939 ret = nfp_net_reconfig(hw, new_ctrl, update);
949 nfp_net_promisc_disable(struct rte_eth_dev *dev)
951 uint32_t new_ctrl, update = 0;
952 struct nfp_net_hw *hw;
955 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
957 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
958 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
962 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
963 update = NFP_NET_CFG_UPDATE_GEN;
966 * DPDK sets promiscuous mode off just before this call
967 * assuming it can not fail ...
969 ret = nfp_net_reconfig(hw, new_ctrl, update);
979 * return 0 means link status changed, -1 means not changed
981 * Wait to complete is needed as it can take up to 9 seconds to get the Link
985 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
987 struct nfp_net_hw *hw;
988 struct rte_eth_link link;
989 uint32_t nn_link_status;
992 static const uint32_t ls_to_ethtool[] = {
993 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
994 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
995 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
996 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
997 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
998 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
999 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
1000 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
1003 PMD_DRV_LOG(DEBUG, "Link update");
1005 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1007 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1009 memset(&link, 0, sizeof(struct rte_eth_link));
1011 if (nn_link_status & NFP_NET_CFG_STS_LINK)
1012 link.link_status = ETH_LINK_UP;
1014 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1016 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1017 NFP_NET_CFG_STS_LINK_RATE_MASK;
1019 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1020 link.link_speed = ETH_SPEED_NUM_NONE;
1022 link.link_speed = ls_to_ethtool[nn_link_status];
1024 ret = rte_eth_linkstatus_set(dev, &link);
1026 if (link.link_status)
1027 PMD_DRV_LOG(INFO, "NIC Link is Up");
1029 PMD_DRV_LOG(INFO, "NIC Link is Down");
1035 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1038 struct nfp_net_hw *hw;
1039 struct rte_eth_stats nfp_dev_stats;
1041 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1045 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1047 /* reading per RX ring stats */
1048 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1049 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1052 nfp_dev_stats.q_ipackets[i] =
1053 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1055 nfp_dev_stats.q_ipackets[i] -=
1056 hw->eth_stats_base.q_ipackets[i];
1058 nfp_dev_stats.q_ibytes[i] =
1059 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1061 nfp_dev_stats.q_ibytes[i] -=
1062 hw->eth_stats_base.q_ibytes[i];
1065 /* reading per TX ring stats */
1066 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1067 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1070 nfp_dev_stats.q_opackets[i] =
1071 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1073 nfp_dev_stats.q_opackets[i] -=
1074 hw->eth_stats_base.q_opackets[i];
1076 nfp_dev_stats.q_obytes[i] =
1077 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1079 nfp_dev_stats.q_obytes[i] -=
1080 hw->eth_stats_base.q_obytes[i];
1083 nfp_dev_stats.ipackets =
1084 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1086 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1088 nfp_dev_stats.ibytes =
1089 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1091 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1093 nfp_dev_stats.opackets =
1094 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1096 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1098 nfp_dev_stats.obytes =
1099 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1101 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1103 /* reading general device stats */
1104 nfp_dev_stats.ierrors =
1105 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1107 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1109 nfp_dev_stats.oerrors =
1110 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1112 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1114 /* RX ring mbuf allocation failures */
1115 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1117 nfp_dev_stats.imissed =
1118 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1120 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1123 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1130 nfp_net_stats_reset(struct rte_eth_dev *dev)
1133 struct nfp_net_hw *hw;
1135 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1138 * hw->eth_stats_base records the per counter starting point.
1139 * Lets update it now
1142 /* reading per RX ring stats */
1143 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1144 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1147 hw->eth_stats_base.q_ipackets[i] =
1148 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1150 hw->eth_stats_base.q_ibytes[i] =
1151 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1154 /* reading per TX ring stats */
1155 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1156 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1159 hw->eth_stats_base.q_opackets[i] =
1160 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1162 hw->eth_stats_base.q_obytes[i] =
1163 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1166 hw->eth_stats_base.ipackets =
1167 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1169 hw->eth_stats_base.ibytes =
1170 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1172 hw->eth_stats_base.opackets =
1173 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1175 hw->eth_stats_base.obytes =
1176 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1178 /* reading general device stats */
1179 hw->eth_stats_base.ierrors =
1180 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1182 hw->eth_stats_base.oerrors =
1183 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1185 /* RX ring mbuf allocation failures */
1186 dev->data->rx_mbuf_alloc_failed = 0;
1188 hw->eth_stats_base.imissed =
1189 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1195 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1197 struct nfp_net_hw *hw;
1199 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1201 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1202 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1203 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1204 dev_info->max_rx_pktlen = hw->max_mtu;
1205 /* Next should change when PF support is implemented */
1206 dev_info->max_mac_addrs = 1;
1208 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1209 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1211 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1212 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1213 DEV_RX_OFFLOAD_UDP_CKSUM |
1214 DEV_RX_OFFLOAD_TCP_CKSUM;
1216 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME |
1217 DEV_RX_OFFLOAD_RSS_HASH;
1219 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1220 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1222 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1223 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1224 DEV_TX_OFFLOAD_UDP_CKSUM |
1225 DEV_TX_OFFLOAD_TCP_CKSUM;
1227 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1228 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1230 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1231 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1233 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1235 .pthresh = DEFAULT_RX_PTHRESH,
1236 .hthresh = DEFAULT_RX_HTHRESH,
1237 .wthresh = DEFAULT_RX_WTHRESH,
1239 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1243 dev_info->default_txconf = (struct rte_eth_txconf) {
1245 .pthresh = DEFAULT_TX_PTHRESH,
1246 .hthresh = DEFAULT_TX_HTHRESH,
1247 .wthresh = DEFAULT_TX_WTHRESH,
1249 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1250 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1253 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1254 ETH_RSS_NONFRAG_IPV4_TCP |
1255 ETH_RSS_NONFRAG_IPV4_UDP |
1257 ETH_RSS_NONFRAG_IPV6_TCP |
1258 ETH_RSS_NONFRAG_IPV6_UDP;
1260 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1261 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1263 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1264 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1265 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1270 static const uint32_t *
1271 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1273 static const uint32_t ptypes[] = {
1274 /* refers to nfp_net_set_hash() */
1275 RTE_PTYPE_INNER_L3_IPV4,
1276 RTE_PTYPE_INNER_L3_IPV6,
1277 RTE_PTYPE_INNER_L3_IPV6_EXT,
1278 RTE_PTYPE_INNER_L4_MASK,
1282 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1288 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1290 struct nfp_net_rxq *rxq;
1291 struct nfp_net_rx_desc *rxds;
1295 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1302 * Other PMDs are just checking the DD bit in intervals of 4
1303 * descriptors and counting all four if the first has the DD
1304 * bit on. Of course, this is not accurate but can be good for
1305 * performance. But ideally that should be done in descriptors
1306 * chunks belonging to the same cache line
1309 while (count < rxq->rx_count) {
1310 rxds = &rxq->rxds[idx];
1311 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1318 if ((idx) == rxq->rx_count)
1326 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1328 struct rte_pci_device *pci_dev;
1329 struct nfp_net_hw *hw;
1332 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1333 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1335 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1338 /* Make sure all updates are written before un-masking */
1340 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1341 NFP_NET_CFG_ICR_UNMASKED);
1346 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1348 struct rte_pci_device *pci_dev;
1349 struct nfp_net_hw *hw;
1352 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1353 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1355 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1358 /* Make sure all updates are written before un-masking */
1360 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1365 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1367 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1368 struct rte_eth_link link;
1370 rte_eth_linkstatus_get(dev, &link);
1371 if (link.link_status)
1372 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1373 dev->data->port_id, link.link_speed,
1374 link.link_duplex == ETH_LINK_FULL_DUPLEX
1375 ? "full-duplex" : "half-duplex");
1377 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1378 dev->data->port_id);
1380 PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
1381 pci_dev->addr.domain, pci_dev->addr.bus,
1382 pci_dev->addr.devid, pci_dev->addr.function);
1385 /* Interrupt configuration and handling */
1388 * nfp_net_irq_unmask - Unmask an interrupt
1390 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1391 * clear the ICR for the entry.
1394 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1396 struct nfp_net_hw *hw;
1397 struct rte_pci_device *pci_dev;
1399 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1402 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1403 /* If MSI-X auto-masking is used, clear the entry */
1405 rte_intr_ack(&pci_dev->intr_handle);
1407 /* Make sure all updates are written before un-masking */
1409 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1410 NFP_NET_CFG_ICR_UNMASKED);
1415 nfp_net_dev_interrupt_handler(void *param)
1418 struct rte_eth_link link;
1419 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1421 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1423 rte_eth_linkstatus_get(dev, &link);
1425 nfp_net_link_update(dev, 0);
1428 if (!link.link_status) {
1429 /* handle it 1 sec later, wait it being stable */
1430 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1431 /* likely to down */
1433 /* handle it 4 sec later, wait it being stable */
1434 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1437 if (rte_eal_alarm_set(timeout * 1000,
1438 nfp_net_dev_interrupt_delayed_handler,
1440 PMD_INIT_LOG(ERR, "Error setting alarm");
1442 nfp_net_irq_unmask(dev);
1447 * Interrupt handler which shall be registered for alarm callback for delayed
1448 * handling specific interrupt to wait for the stable nic state. As the NIC
1449 * interrupt state is not stable for nfp after link is just down, it needs
1450 * to wait 4 seconds to get the stable status.
1452 * @param handle Pointer to interrupt handle.
1453 * @param param The address of parameter (struct rte_eth_dev *)
1458 nfp_net_dev_interrupt_delayed_handler(void *param)
1460 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1462 nfp_net_link_update(dev, 0);
1463 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1465 nfp_net_dev_link_status_print(dev);
1468 nfp_net_irq_unmask(dev);
1472 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1474 struct nfp_net_hw *hw;
1476 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1478 /* check that mtu is within the allowed range */
1479 if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1482 /* mtu setting is forbidden if port is started */
1483 if (dev->data->dev_started) {
1484 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1485 dev->data->port_id);
1489 /* switch to jumbo mode if needed */
1490 if ((uint32_t)mtu > RTE_ETHER_MAX_LEN)
1491 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1493 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1495 /* update max frame size */
1496 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1498 /* writing to configuration space */
1499 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1507 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1508 uint16_t queue_idx, uint16_t nb_desc,
1509 unsigned int socket_id,
1510 const struct rte_eth_rxconf *rx_conf,
1511 struct rte_mempool *mp)
1513 const struct rte_memzone *tz;
1514 struct nfp_net_rxq *rxq;
1515 struct nfp_net_hw *hw;
1517 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1519 PMD_INIT_FUNC_TRACE();
1521 /* Validating number of descriptors */
1522 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1523 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1524 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1525 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1530 * Free memory prior to re-allocation if needed. This is the case after
1531 * calling nfp_net_stop
1533 if (dev->data->rx_queues[queue_idx]) {
1534 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1535 dev->data->rx_queues[queue_idx] = NULL;
1538 /* Allocating rx queue data structure */
1539 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1540 RTE_CACHE_LINE_SIZE, socket_id);
1544 /* Hw queues mapping based on firmware configuration */
1545 rxq->qidx = queue_idx;
1546 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1547 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1548 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1549 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1552 * Tracking mbuf size for detecting a potential mbuf overflow due to
1556 rxq->mbuf_size = rxq->mem_pool->elt_size;
1557 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1558 hw->flbufsz = rxq->mbuf_size;
1560 rxq->rx_count = nb_desc;
1561 rxq->port_id = dev->data->port_id;
1562 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1563 rxq->drop_en = rx_conf->rx_drop_en;
1566 * Allocate RX ring hardware descriptors. A memzone large enough to
1567 * handle the maximum ring size is allocated in order to allow for
1568 * resizing in later calls to the queue setup function.
1570 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1571 sizeof(struct nfp_net_rx_desc) *
1572 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1576 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1577 nfp_net_rx_queue_release(rxq);
1581 /* Saving physical and virtual addresses for the RX ring */
1582 rxq->dma = (uint64_t)tz->iova;
1583 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1585 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1586 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1587 sizeof(*rxq->rxbufs) * nb_desc,
1588 RTE_CACHE_LINE_SIZE, socket_id);
1589 if (rxq->rxbufs == NULL) {
1590 nfp_net_rx_queue_release(rxq);
1594 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1595 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1597 nfp_net_reset_rx_queue(rxq);
1599 dev->data->rx_queues[queue_idx] = rxq;
1603 * Telling the HW about the physical address of the RX ring and number
1604 * of descriptors in log2 format
1606 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1607 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1613 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1615 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1619 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1622 for (i = 0; i < rxq->rx_count; i++) {
1623 struct nfp_net_rx_desc *rxd;
1624 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1627 PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1628 (unsigned)rxq->qidx);
1632 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1634 rxd = &rxq->rxds[i];
1636 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1637 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1639 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1642 /* Make sure all writes are flushed before telling the hardware */
1645 /* Not advertising the whole ring as the firmware gets confused if so */
1646 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1649 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1655 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1656 uint16_t nb_desc, unsigned int socket_id,
1657 const struct rte_eth_txconf *tx_conf)
1659 const struct rte_memzone *tz;
1660 struct nfp_net_txq *txq;
1661 uint16_t tx_free_thresh;
1662 struct nfp_net_hw *hw;
1664 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666 PMD_INIT_FUNC_TRACE();
1668 /* Validating number of descriptors */
1669 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1670 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1671 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1672 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1676 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1677 tx_conf->tx_free_thresh :
1678 DEFAULT_TX_FREE_THRESH);
1680 if (tx_free_thresh > (nb_desc)) {
1682 "tx_free_thresh must be less than the number of TX "
1683 "descriptors. (tx_free_thresh=%u port=%d "
1684 "queue=%d)", (unsigned int)tx_free_thresh,
1685 dev->data->port_id, (int)queue_idx);
1690 * Free memory prior to re-allocation if needed. This is the case after
1691 * calling nfp_net_stop
1693 if (dev->data->tx_queues[queue_idx]) {
1694 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1696 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1697 dev->data->tx_queues[queue_idx] = NULL;
1700 /* Allocating tx queue data structure */
1701 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1702 RTE_CACHE_LINE_SIZE, socket_id);
1704 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1709 * Allocate TX ring hardware descriptors. A memzone large enough to
1710 * handle the maximum ring size is allocated in order to allow for
1711 * resizing in later calls to the queue setup function.
1713 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1714 sizeof(struct nfp_net_tx_desc) *
1715 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1718 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1719 nfp_net_tx_queue_release(txq);
1723 txq->tx_count = nb_desc;
1724 txq->tx_free_thresh = tx_free_thresh;
1725 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1726 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1727 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1729 /* queue mapping based on firmware configuration */
1730 txq->qidx = queue_idx;
1731 txq->tx_qcidx = queue_idx * hw->stride_tx;
1732 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1734 txq->port_id = dev->data->port_id;
1736 /* Saving physical and virtual addresses for the TX ring */
1737 txq->dma = (uint64_t)tz->iova;
1738 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1740 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1741 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1742 sizeof(*txq->txbufs) * nb_desc,
1743 RTE_CACHE_LINE_SIZE, socket_id);
1744 if (txq->txbufs == NULL) {
1745 nfp_net_tx_queue_release(txq);
1748 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1749 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1751 nfp_net_reset_tx_queue(txq);
1753 dev->data->tx_queues[queue_idx] = txq;
1757 * Telling the HW about the physical address of the TX ring and number
1758 * of descriptors in log2 format
1760 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1761 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1766 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1768 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1769 struct rte_mbuf *mb)
1772 struct nfp_net_hw *hw = txq->hw;
1774 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1777 ol_flags = mb->ol_flags;
1779 if (!(ol_flags & PKT_TX_TCP_SEG))
1782 txd->l3_offset = mb->l2_len;
1783 txd->l4_offset = mb->l2_len + mb->l3_len;
1784 txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1785 txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1786 txd->flags = PCIE_DESC_TX_LSO;
1793 txd->lso_hdrlen = 0;
1797 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1799 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1800 struct rte_mbuf *mb)
1803 struct nfp_net_hw *hw = txq->hw;
1805 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1808 ol_flags = mb->ol_flags;
1810 /* IPv6 does not need checksum */
1811 if (ol_flags & PKT_TX_IP_CKSUM)
1812 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1814 switch (ol_flags & PKT_TX_L4_MASK) {
1815 case PKT_TX_UDP_CKSUM:
1816 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1818 case PKT_TX_TCP_CKSUM:
1819 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1823 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1824 txd->flags |= PCIE_DESC_TX_CSUM;
1827 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1829 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1830 struct rte_mbuf *mb)
1832 struct nfp_net_hw *hw = rxq->hw;
1834 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1837 /* If IPv4 and IP checksum error, fail */
1838 if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1839 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1840 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1842 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1844 /* If neither UDP nor TCP return */
1845 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1846 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1849 if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1850 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1852 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1855 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1856 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1858 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1861 * nfp_net_set_hash - Set mbuf hash data
1863 * The RSS hash and hash-type are pre-pended to the packet data.
1864 * Extract and decode it and set the mbuf fields.
1867 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1868 struct rte_mbuf *mbuf)
1870 struct nfp_net_hw *hw = rxq->hw;
1871 uint8_t *meta_offset;
1874 uint32_t hash_type = 0;
1876 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1879 /* this is true for new firmwares */
1880 if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1881 (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1882 NFP_DESC_META_LEN(rxd))) {
1885 * <---- 32 bit ----->
1890 * ====================
1893 * Field type word contains up to 8 4bit field types
1894 * A 4bit field type refers to a data field word
1895 * A data field word can have several 4bit field types
1897 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1898 meta_offset -= NFP_DESC_META_LEN(rxd);
1899 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1901 /* NFP PMD just supports metadata for hashing */
1902 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1903 case NFP_NET_META_HASH:
1904 /* next field type is about the hash type */
1905 meta_info >>= NFP_NET_META_FIELD_SIZE;
1906 /* hash value is in the data field */
1907 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1908 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1911 /* Unsupported metadata can be a performance issue */
1915 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1918 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1919 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1922 mbuf->hash.rss = hash;
1923 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1925 switch (hash_type) {
1926 case NFP_NET_RSS_IPV4:
1927 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1929 case NFP_NET_RSS_IPV6:
1930 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1932 case NFP_NET_RSS_IPV6_EX:
1933 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1935 case NFP_NET_RSS_IPV4_TCP:
1936 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1938 case NFP_NET_RSS_IPV6_TCP:
1939 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1941 case NFP_NET_RSS_IPV4_UDP:
1942 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1944 case NFP_NET_RSS_IPV6_UDP:
1945 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1948 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1953 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1955 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1958 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1963 * There are some decisions to take:
1964 * 1) How to check DD RX descriptors bit
1965 * 2) How and when to allocate new mbufs
1967 * Current implementation checks just one single DD bit each loop. As each
1968 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1969 * a single cache line instead. Tests with this change have not shown any
1970 * performance improvement but it requires further investigation. For example,
1971 * depending on which descriptor is next, the number of descriptors could be
1972 * less than 8 for just checking those in the same cache line. This implies
1973 * extra work which could be counterproductive by itself. Indeed, last firmware
1974 * changes are just doing this: writing several descriptors with the DD bit
1975 * for saving PCIe bandwidth and DMA operations from the NFP.
1977 * Mbuf allocation is done when a new packet is received. Then the descriptor
1978 * is automatically linked with the new mbuf and the old one is given to the
1979 * user. The main drawback with this design is mbuf allocation is heavier than
1980 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1981 * cache point of view it does not seem allocating the mbuf early on as we are
1982 * doing now have any benefit at all. Again, tests with this change have not
1983 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1984 * so looking at the implications of this type of allocation should be studied
1989 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1991 struct nfp_net_rxq *rxq;
1992 struct nfp_net_rx_desc *rxds;
1993 struct nfp_net_rx_buff *rxb;
1994 struct nfp_net_hw *hw;
1995 struct rte_mbuf *mb;
1996 struct rte_mbuf *new_mb;
2002 if (unlikely(rxq == NULL)) {
2004 * DPDK just checks the queue is lower than max queues
2005 * enabled. But the queue needs to be configured
2007 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2015 while (avail < nb_pkts) {
2016 rxb = &rxq->rxbufs[rxq->rd_p];
2017 if (unlikely(rxb == NULL)) {
2018 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2022 rxds = &rxq->rxds[rxq->rd_p];
2023 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2027 * Memory barrier to ensure that we won't do other
2028 * reads before the DD bit.
2033 * We got a packet. Let's alloc a new mbuf for refilling the
2034 * free descriptor ring as soon as possible
2036 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2037 if (unlikely(new_mb == NULL)) {
2038 RTE_LOG_DP(DEBUG, PMD,
2039 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2040 rxq->port_id, (unsigned int)rxq->qidx);
2041 nfp_net_mbuf_alloc_failed(rxq);
2048 * Grab the mbuf and refill the descriptor with the
2049 * previously allocated mbuf
2054 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2055 rxds->rxd.data_len, rxq->mbuf_size);
2057 /* Size of this segment */
2058 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2059 /* Size of the whole packet. We just support 1 segment */
2060 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2062 if (unlikely((mb->data_len + hw->rx_offset) >
2065 * This should not happen and the user has the
2066 * responsibility of avoiding it. But we have
2067 * to give some info about the error
2069 RTE_LOG_DP(ERR, PMD,
2070 "mbuf overflow likely due to the RX offset.\n"
2071 "\t\tYour mbuf size should have extra space for"
2072 " RX offset=%u bytes.\n"
2073 "\t\tCurrently you just have %u bytes available"
2074 " but the received packet is %u bytes long",
2076 rxq->mbuf_size - hw->rx_offset,
2081 /* Filling the received mbuf with packet info */
2083 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2085 mb->data_off = RTE_PKTMBUF_HEADROOM +
2086 NFP_DESC_META_LEN(rxds);
2088 /* No scatter mode supported */
2092 mb->port = rxq->port_id;
2094 /* Checking the RSS flag */
2095 nfp_net_set_hash(rxq, rxds, mb);
2097 /* Checking the checksum flag */
2098 nfp_net_rx_cksum(rxq, rxds, mb);
2100 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2101 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2102 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2103 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2106 /* Adding the mbuf to the mbuf array passed by the app */
2107 rx_pkts[avail++] = mb;
2109 /* Now resetting and updating the descriptor */
2112 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2114 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2115 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2118 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2125 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received",
2126 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2128 nb_hold += rxq->nb_rx_hold;
2131 * FL descriptors needs to be written before incrementing the
2132 * FL queue WR pointer
2135 if (nb_hold > rxq->rx_free_thresh) {
2136 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2137 rxq->port_id, (unsigned int)rxq->qidx,
2138 (unsigned)nb_hold, (unsigned)avail);
2139 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2142 rxq->nb_rx_hold = nb_hold;
2148 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2150 * @txq: TX queue to work with
2151 * Returns number of descriptors freed
2154 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2159 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2160 " status", txq->qidx);
2162 /* Work out how many packets have been sent */
2163 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2165 if (qcp_rd_p == txq->rd_p) {
2166 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2167 "packets (%u, %u)", txq->qidx,
2168 qcp_rd_p, txq->rd_p);
2172 if (qcp_rd_p > txq->rd_p)
2173 todo = qcp_rd_p - txq->rd_p;
2175 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2177 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2178 qcp_rd_p, txq->rd_p, txq->rd_p);
2184 if (unlikely(txq->rd_p >= txq->tx_count))
2185 txq->rd_p -= txq->tx_count;
2190 /* Leaving always free descriptors for avoiding wrapping confusion */
2192 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2194 if (txq->wr_p >= txq->rd_p)
2195 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2197 return txq->rd_p - txq->wr_p - 8;
2201 * nfp_net_txq_full - Check if the TX queue free descriptors
2202 * is below tx_free_threshold
2204 * @txq: TX queue to check
2206 * This function uses the host copy* of read/write pointers
2209 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2211 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2215 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2217 struct nfp_net_txq *txq;
2218 struct nfp_net_hw *hw;
2219 struct nfp_net_tx_desc *txds, txd;
2220 struct rte_mbuf *pkt;
2222 int pkt_size, dma_size;
2223 uint16_t free_descs, issued_descs;
2224 struct rte_mbuf **lmbuf;
2229 txds = &txq->txds[txq->wr_p];
2231 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2232 txq->qidx, txq->wr_p, nb_pkts);
2234 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2235 nfp_net_tx_free_bufs(txq);
2237 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2238 if (unlikely(free_descs == 0))
2245 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2246 txq->qidx, nb_pkts);
2247 /* Sending packets */
2248 while ((i < nb_pkts) && free_descs) {
2249 /* Grabbing the mbuf linked to the current descriptor */
2250 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2251 /* Warming the cache for releasing the mbuf later on */
2252 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2254 pkt = *(tx_pkts + i);
2256 if (unlikely((pkt->nb_segs > 1) &&
2257 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2258 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2259 rte_panic("Multisegment packet unsupported\n");
2262 /* Checking if we have enough descriptors */
2263 if (unlikely(pkt->nb_segs > free_descs))
2267 * Checksum and VLAN flags just in the first descriptor for a
2268 * multisegment packet, but TSO info needs to be in all of them.
2270 txd.data_len = pkt->pkt_len;
2271 nfp_net_tx_tso(txq, &txd, pkt);
2272 nfp_net_tx_cksum(txq, &txd, pkt);
2274 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2275 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2276 txd.flags |= PCIE_DESC_TX_VLAN;
2277 txd.vlan = pkt->vlan_tci;
2281 * mbuf data_len is the data in one segment and pkt_len data
2282 * in the whole packet. When the packet is just one segment,
2283 * then data_len = pkt_len
2285 pkt_size = pkt->pkt_len;
2288 /* Copying TSO, VLAN and cksum info */
2291 /* Releasing mbuf used by this descriptor previously*/
2293 rte_pktmbuf_free_seg(*lmbuf);
2296 * Linking mbuf with descriptor for being released
2297 * next time descriptor is used
2301 dma_size = pkt->data_len;
2302 dma_addr = rte_mbuf_data_iova(pkt);
2303 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2304 "%" PRIx64 "", dma_addr);
2306 /* Filling descriptors fields */
2307 txds->dma_len = dma_size;
2308 txds->data_len = txd.data_len;
2309 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2310 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2311 ASSERT(free_descs > 0);
2315 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2318 pkt_size -= dma_size;
2321 * Making the EOP, packets with just one segment
2324 if (likely(!pkt_size))
2325 txds->offset_eop = PCIE_DESC_TX_EOP;
2327 txds->offset_eop = 0;
2330 /* Referencing next free TX descriptor */
2331 txds = &txq->txds[txq->wr_p];
2332 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2339 /* Increment write pointers. Force memory write before we let HW know */
2341 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2347 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2349 uint32_t new_ctrl, update;
2350 struct nfp_net_hw *hw;
2353 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356 /* Enable vlan strip if it is not configured yet */
2357 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2358 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2359 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2361 /* Disable vlan strip just if it is configured */
2362 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2363 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2364 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2369 update = NFP_NET_CFG_UPDATE_GEN;
2371 ret = nfp_net_reconfig(hw, new_ctrl, update);
2373 hw->ctrl = new_ctrl;
2379 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2380 struct rte_eth_rss_reta_entry64 *reta_conf,
2383 uint32_t reta, mask;
2386 struct nfp_net_hw *hw =
2387 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2390 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2391 "(%d) doesn't match the number hardware can supported "
2392 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2397 * Update Redirection Table. There are 128 8bit-entries which can be
2398 * manage as 32 32bit-entries
2400 for (i = 0; i < reta_size; i += 4) {
2401 /* Handling 4 RSS entries per loop */
2402 idx = i / RTE_RETA_GROUP_SIZE;
2403 shift = i % RTE_RETA_GROUP_SIZE;
2404 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2410 /* If all 4 entries were set, don't need read RETA register */
2412 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2414 for (j = 0; j < 4; j++) {
2415 if (!(mask & (0x1 << j)))
2418 /* Clearing the entry bits */
2419 reta &= ~(0xFF << (8 * j));
2420 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2422 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2428 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2430 nfp_net_reta_update(struct rte_eth_dev *dev,
2431 struct rte_eth_rss_reta_entry64 *reta_conf,
2434 struct nfp_net_hw *hw =
2435 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2442 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2446 update = NFP_NET_CFG_UPDATE_RSS;
2448 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2454 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2456 nfp_net_reta_query(struct rte_eth_dev *dev,
2457 struct rte_eth_rss_reta_entry64 *reta_conf,
2463 struct nfp_net_hw *hw;
2465 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2467 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2470 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2471 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2472 "(%d) doesn't match the number hardware can supported "
2473 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2478 * Reading Redirection Table. There are 128 8bit-entries which can be
2479 * manage as 32 32bit-entries
2481 for (i = 0; i < reta_size; i += 4) {
2482 /* Handling 4 RSS entries per loop */
2483 idx = i / RTE_RETA_GROUP_SIZE;
2484 shift = i % RTE_RETA_GROUP_SIZE;
2485 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2490 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2492 for (j = 0; j < 4; j++) {
2493 if (!(mask & (0x1 << j)))
2495 reta_conf[idx].reta[shift + j] =
2496 (uint8_t)((reta >> (8 * j)) & 0xF);
2503 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2504 struct rte_eth_rss_conf *rss_conf)
2506 struct nfp_net_hw *hw;
2508 uint32_t cfg_rss_ctrl = 0;
2512 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2514 /* Writing the key byte a byte */
2515 for (i = 0; i < rss_conf->rss_key_len; i++) {
2516 memcpy(&key, &rss_conf->rss_key[i], 1);
2517 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2520 rss_hf = rss_conf->rss_hf;
2522 if (rss_hf & ETH_RSS_IPV4)
2523 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2525 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2526 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2528 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2529 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2531 if (rss_hf & ETH_RSS_IPV6)
2532 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2534 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2535 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2537 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2538 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2540 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2541 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2543 /* configuring where to apply the RSS hash */
2544 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2546 /* Writing the key size */
2547 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2553 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2554 struct rte_eth_rss_conf *rss_conf)
2558 struct nfp_net_hw *hw;
2560 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562 rss_hf = rss_conf->rss_hf;
2564 /* Checking if RSS is enabled */
2565 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2566 if (rss_hf != 0) { /* Enable RSS? */
2567 PMD_DRV_LOG(ERR, "RSS unsupported");
2570 return 0; /* Nothing to do */
2573 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2574 PMD_DRV_LOG(ERR, "hash key too long");
2578 nfp_net_rss_hash_write(dev, rss_conf);
2580 update = NFP_NET_CFG_UPDATE_RSS;
2582 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2589 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2590 struct rte_eth_rss_conf *rss_conf)
2593 uint32_t cfg_rss_ctrl;
2596 struct nfp_net_hw *hw;
2598 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2600 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2603 rss_hf = rss_conf->rss_hf;
2604 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2606 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2607 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2609 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2610 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2612 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2613 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2615 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2616 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2618 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2619 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2621 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2622 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2624 /* Propagate current RSS hash functions to caller */
2625 rss_conf->rss_hf = rss_hf;
2627 /* Reading the key size */
2628 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2630 /* Reading the key byte a byte */
2631 for (i = 0; i < rss_conf->rss_key_len; i++) {
2632 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2633 memcpy(&rss_conf->rss_key[i], &key, 1);
2640 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2642 struct rte_eth_conf *dev_conf;
2643 struct rte_eth_rss_conf rss_conf;
2644 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2645 uint16_t rx_queues = dev->data->nb_rx_queues;
2649 PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2652 nfp_reta_conf[0].mask = ~0x0;
2653 nfp_reta_conf[1].mask = ~0x0;
2656 for (i = 0; i < 0x40; i += 8) {
2657 for (j = i; j < (i + 8); j++) {
2658 nfp_reta_conf[0].reta[j] = queue;
2659 nfp_reta_conf[1].reta[j] = queue++;
2663 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2667 dev_conf = &dev->data->dev_conf;
2669 PMD_DRV_LOG(INFO, "wrong rss conf");
2672 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2674 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2680 /* Initialise and register driver with DPDK Application */
2681 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2682 .dev_configure = nfp_net_configure,
2683 .dev_start = nfp_net_start,
2684 .dev_stop = nfp_net_stop,
2685 .dev_set_link_up = nfp_net_set_link_up,
2686 .dev_set_link_down = nfp_net_set_link_down,
2687 .dev_close = nfp_net_close,
2688 .promiscuous_enable = nfp_net_promisc_enable,
2689 .promiscuous_disable = nfp_net_promisc_disable,
2690 .link_update = nfp_net_link_update,
2691 .stats_get = nfp_net_stats_get,
2692 .stats_reset = nfp_net_stats_reset,
2693 .dev_infos_get = nfp_net_infos_get,
2694 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2695 .mtu_set = nfp_net_dev_mtu_set,
2696 .mac_addr_set = nfp_set_mac_addr,
2697 .vlan_offload_set = nfp_net_vlan_offload_set,
2698 .reta_update = nfp_net_reta_update,
2699 .reta_query = nfp_net_reta_query,
2700 .rss_hash_update = nfp_net_rss_hash_update,
2701 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2702 .rx_queue_setup = nfp_net_rx_queue_setup,
2703 .rx_queue_release = nfp_net_rx_queue_release,
2704 .rx_queue_count = nfp_net_rx_queue_count,
2705 .tx_queue_setup = nfp_net_tx_queue_setup,
2706 .tx_queue_release = nfp_net_tx_queue_release,
2707 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2708 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2712 * All eth_dev created got its private data, but before nfp_net_init, that
2713 * private data is referencing private data for all the PF ports. This is due
2714 * to how the vNIC bars are mapped based on first port, so all ports need info
2715 * about port 0 private data. Inside nfp_net_init the private data pointer is
2716 * changed to the right address for each port once the bars have been mapped.
2718 * This functions helps to find out which port and therefore which offset
2719 * inside the private data array to use.
2722 get_pf_port_number(char *name)
2724 char *pf_str = name;
2727 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2732 * This should not happen at all and it would mean major
2733 * implementation fault.
2735 rte_panic("nfp_net: problem with pf device name\n");
2737 /* Expecting _portX with X within [0,7] */
2740 return (int)strtol(pf_str, NULL, 10);
2744 nfp_net_init(struct rte_eth_dev *eth_dev)
2746 struct rte_pci_device *pci_dev;
2747 struct nfp_net_hw *hw, *hwport0;
2749 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2755 PMD_INIT_FUNC_TRACE();
2757 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2759 /* NFP can not handle DMA addresses requiring more than 40 bits */
2760 if (rte_mem_check_dma_mask(40)) {
2761 RTE_LOG(ERR, PMD, "device %s can not be used:",
2762 pci_dev->device.name);
2763 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2767 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2768 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2769 port = get_pf_port_number(eth_dev->data->name);
2770 if (port < 0 || port > 7) {
2771 PMD_DRV_LOG(ERR, "Port value is wrong");
2775 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2777 /* This points to port 0 private data */
2778 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2780 /* This points to the specific port private data */
2781 hw = &hwport0[port];
2783 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2787 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2788 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2789 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2791 /* For secondary processes, the primary has done all the work */
2792 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2795 rte_eth_copy_pci_info(eth_dev, pci_dev);
2797 hw->device_id = pci_dev->id.device_id;
2798 hw->vendor_id = pci_dev->id.vendor_id;
2799 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2800 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2802 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2803 pci_dev->id.vendor_id, pci_dev->id.device_id,
2804 pci_dev->addr.domain, pci_dev->addr.bus,
2805 pci_dev->addr.devid, pci_dev->addr.function);
2807 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2808 if (hw->ctrl_bar == NULL) {
2810 "hw->ctrl_bar is NULL. BAR0 not configured");
2814 if (hw->is_pf && port == 0) {
2815 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2816 hw->total_ports * 32768,
2818 if (!hw->ctrl_bar) {
2819 printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2823 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2827 if (!hwport0->ctrl_bar)
2830 /* address based on port0 offset */
2831 hw->ctrl_bar = hwport0->ctrl_bar +
2832 (port * NFP_PF_CSR_SLICE_SIZE);
2835 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2837 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2838 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2840 /* Work out where in the BAR the queues start. */
2841 switch (pci_dev->id.device_id) {
2842 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2843 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2844 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2845 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2846 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2847 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2848 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2851 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2853 goto dev_err_ctrl_map;
2856 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2857 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2859 if (hw->is_pf && port == 0) {
2860 /* configure access to tx/rx vNIC BARs */
2861 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2863 NFP_QCP_QUEUE_AREA_SZ,
2864 &hw->hwqueues_area);
2866 if (!hwport0->hw_queues) {
2867 printf("nfp_rtsym_map fails for net.qc");
2869 goto dev_err_ctrl_map;
2872 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2873 hwport0->hw_queues);
2877 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2878 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2879 eth_dev->data->dev_private = hw;
2881 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2883 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2887 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2888 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2890 nfp_net_cfg_queue_setup(hw);
2892 /* Get some of the read-only fields from the config BAR */
2893 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2894 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2895 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2896 hw->mtu = RTE_ETHER_MTU;
2898 /* VLAN insertion is incompatible with LSOv2 */
2899 if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2900 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2902 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2903 hw->rx_offset = NFP_NET_RX_OFFSET;
2905 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2907 PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2908 NFD_CFG_MAJOR_VERSION_of(hw->ver),
2909 NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2911 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2912 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2913 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2914 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2915 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2916 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2917 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2918 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2919 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2920 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2921 hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "",
2922 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2923 hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "",
2924 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "",
2925 hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : "");
2929 hw->stride_rx = stride;
2930 hw->stride_tx = stride;
2932 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2933 hw->max_rx_queues, hw->max_tx_queues);
2935 /* Initializing spinlock for reconfigs */
2936 rte_spinlock_init(&hw->reconfig_lock);
2938 /* Allocating memory for mac addr */
2939 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2940 RTE_ETHER_ADDR_LEN, 0);
2941 if (eth_dev->data->mac_addrs == NULL) {
2942 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2944 goto dev_err_queues_map;
2948 nfp_net_pf_read_mac(hwport0, port);
2949 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2951 nfp_net_vf_read_mac(hw);
2954 if (!rte_is_valid_assigned_ether_addr(
2955 (struct rte_ether_addr *)&hw->mac_addr)) {
2956 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2958 /* Using random mac addresses for VFs */
2959 rte_eth_random_addr(&hw->mac_addr[0]);
2960 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2963 /* Copying mac address to DPDK eth_dev struct */
2964 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2965 ð_dev->data->mac_addrs[0]);
2967 if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2968 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2970 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2971 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2972 eth_dev->data->port_id, pci_dev->id.vendor_id,
2973 pci_dev->id.device_id,
2974 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2975 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2977 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2978 /* Registering LSC interrupt handler */
2979 rte_intr_callback_register(&pci_dev->intr_handle,
2980 nfp_net_dev_interrupt_handler,
2982 /* Telling the firmware about the LSC interrupt entry */
2983 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2984 /* Recording current stats counters values */
2985 nfp_net_stats_reset(eth_dev);
2991 nfp_cpp_area_free(hw->hwqueues_area);
2993 nfp_cpp_area_free(hw->ctrl_area);
2998 #define NFP_CPP_MEMIO_BOUNDARY (1 << 20)
3001 * Serving a write request to NFP from host programs. The request
3002 * sends the write size and the CPP target. The bridge makes use
3003 * of CPP interface handler configured by the PMD setup.
3006 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3008 struct nfp_cpp_area *area;
3009 off_t offset, nfp_offset;
3010 uint32_t cpp_id, pos, len;
3011 uint32_t tmpbuf[16];
3012 size_t count, curlen, totlen = 0;
3015 PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3016 sizeof(off_t), sizeof(size_t));
3018 /* Reading the count param */
3019 err = recv(sockfd, &count, sizeof(off_t), 0);
3020 if (err != sizeof(off_t))
3025 /* Reading the offset param */
3026 err = recv(sockfd, &offset, sizeof(off_t), 0);
3027 if (err != sizeof(off_t))
3030 /* Obtain target's CPP ID and offset in target */
3031 cpp_id = (offset >> 40) << 8;
3032 nfp_offset = offset & ((1ull << 40) - 1);
3034 PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3036 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3037 cpp_id, nfp_offset);
3039 /* Adjust length if not aligned */
3040 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3041 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3042 curlen = NFP_CPP_MEMIO_BOUNDARY -
3043 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3047 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3048 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3049 nfp_offset, curlen);
3051 RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3055 /* mapping the target */
3056 err = nfp_cpp_area_acquire(area);
3058 RTE_LOG(ERR, PMD, "area acquire failed\n");
3059 nfp_cpp_area_free(area);
3063 for (pos = 0; pos < curlen; pos += len) {
3065 if (len > sizeof(tmpbuf))
3066 len = sizeof(tmpbuf);
3068 PMD_CPP_LOG(DEBUG, "%s: Receive %u of %zu\n", __func__,
3070 err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3071 if (err != (int)len) {
3073 "%s: error when receiving, %d of %zu\n",
3074 __func__, err, count);
3075 nfp_cpp_area_release(area);
3076 nfp_cpp_area_free(area);
3079 err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3081 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3082 nfp_cpp_area_release(area);
3083 nfp_cpp_area_free(area);
3090 nfp_cpp_area_release(area);
3091 nfp_cpp_area_free(area);
3094 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3095 NFP_CPP_MEMIO_BOUNDARY : count;
3102 * Serving a read request to NFP from host programs. The request
3103 * sends the read size and the CPP target. The bridge makes use
3104 * of CPP interface handler configured by the PMD setup. The read
3105 * data is sent to the requester using the same socket.
3108 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3110 struct nfp_cpp_area *area;
3111 off_t offset, nfp_offset;
3112 uint32_t cpp_id, pos, len;
3113 uint32_t tmpbuf[16];
3114 size_t count, curlen, totlen = 0;
3117 PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3118 sizeof(off_t), sizeof(size_t));
3120 /* Reading the count param */
3121 err = recv(sockfd, &count, sizeof(off_t), 0);
3122 if (err != sizeof(off_t))
3127 /* Reading the offset param */
3128 err = recv(sockfd, &offset, sizeof(off_t), 0);
3129 if (err != sizeof(off_t))
3132 /* Obtain target's CPP ID and offset in target */
3133 cpp_id = (offset >> 40) << 8;
3134 nfp_offset = offset & ((1ull << 40) - 1);
3136 PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3138 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3139 cpp_id, nfp_offset);
3141 /* Adjust length if not aligned */
3142 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3143 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3144 curlen = NFP_CPP_MEMIO_BOUNDARY -
3145 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3149 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3150 nfp_offset, curlen);
3152 RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3156 err = nfp_cpp_area_acquire(area);
3158 RTE_LOG(ERR, PMD, "area acquire failed\n");
3159 nfp_cpp_area_free(area);
3163 for (pos = 0; pos < curlen; pos += len) {
3165 if (len > sizeof(tmpbuf))
3166 len = sizeof(tmpbuf);
3168 err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3170 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3171 nfp_cpp_area_release(area);
3172 nfp_cpp_area_free(area);
3175 PMD_CPP_LOG(DEBUG, "%s: sending %u of %zu\n", __func__,
3178 err = send(sockfd, tmpbuf, len, 0);
3179 if (err != (int)len) {
3181 "%s: error when sending: %d of %zu\n",
3182 __func__, err, count);
3183 nfp_cpp_area_release(area);
3184 nfp_cpp_area_free(area);
3191 nfp_cpp_area_release(area);
3192 nfp_cpp_area_free(area);
3195 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3196 NFP_CPP_MEMIO_BOUNDARY : count;
3201 #define NFP_IOCTL 'n'
3202 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3204 * Serving a ioctl command from host NFP tools. This usually goes to
3205 * a kernel driver char driver but it is not available when the PF is
3206 * bound to the PMD. Currently just one ioctl command is served and it
3207 * does not require any CPP access at all.
3210 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3212 uint32_t cmd, ident_size, tmp;
3215 /* Reading now the IOCTL command */
3216 err = recv(sockfd, &cmd, 4, 0);
3218 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3222 /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3223 if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3224 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3228 err = recv(sockfd, &ident_size, 4, 0);
3230 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3234 tmp = nfp_cpp_model(cpp);
3236 PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3238 err = send(sockfd, &tmp, 4, 0);
3240 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3244 tmp = cpp->interface;
3246 PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3248 err = send(sockfd, &tmp, 4, 0);
3250 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3257 #define NFP_BRIDGE_OP_READ 20
3258 #define NFP_BRIDGE_OP_WRITE 30
3259 #define NFP_BRIDGE_OP_IOCTL 40
3262 * This is the code to be executed by a service core. The CPP bridge interface
3263 * is based on a unix socket and requests usually received by a kernel char
3264 * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3265 * can be executed with a wrapper library and LD_LIBRARY being completely
3266 * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3270 nfp_cpp_bridge_service_func(void *args)
3272 struct sockaddr address;
3273 struct nfp_cpp *cpp = args;
3274 int sockfd, datafd, op, ret;
3276 unlink("/tmp/nfp_cpp");
3277 sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3279 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3284 memset(&address, 0, sizeof(struct sockaddr));
3286 address.sa_family = AF_UNIX;
3287 strcpy(address.sa_data, "/tmp/nfp_cpp");
3289 ret = bind(sockfd, (const struct sockaddr *)&address,
3290 sizeof(struct sockaddr));
3292 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3298 ret = listen(sockfd, 20);
3300 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3307 datafd = accept(sockfd, NULL, NULL);
3309 RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3311 RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3317 ret = recv(datafd, &op, 4, 0);
3319 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3324 PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3326 if (op == NFP_BRIDGE_OP_READ)
3327 nfp_cpp_bridge_serve_read(datafd, cpp);
3329 if (op == NFP_BRIDGE_OP_WRITE)
3330 nfp_cpp_bridge_serve_write(datafd, cpp);
3332 if (op == NFP_BRIDGE_OP_IOCTL)
3333 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3346 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3347 struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3348 int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3350 struct rte_eth_dev *eth_dev;
3351 struct nfp_net_hw *hw = NULL;
3353 struct rte_service_spec service;
3356 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3361 snprintf(port_name, 100, "%s_port%d", dev->device.name, port);
3363 strlcat(port_name, dev->device.name, 100);
3366 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3367 eth_dev = rte_eth_dev_allocate(port_name);
3369 rte_free(port_name);
3373 *priv = rte_zmalloc(port_name,
3374 sizeof(struct nfp_net_adapter) *
3375 ports, RTE_CACHE_LINE_SIZE);
3377 rte_free(port_name);
3378 rte_eth_dev_release_port(eth_dev);
3382 eth_dev->data->dev_private = *priv;
3385 * dev_private pointing to port0 dev_private because we need
3386 * to configure vNIC bars based on port0 at nfp_net_init.
3387 * Then dev_private is adjusted per port.
3389 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3391 hw->hwinfo = hwinfo;
3392 hw->sym_tbl = sym_tbl;
3393 hw->pf_port_idx = phys_port;
3396 hw->pf_multiport_enabled = 1;
3398 hw->total_ports = ports;
3400 eth_dev = rte_eth_dev_attach_secondary(port_name);
3402 RTE_LOG(ERR, EAL, "secondary process attach failed, "
3403 "ethdev doesn't exist");
3404 rte_free(port_name);
3407 eth_dev->process_private = cpp;
3410 eth_dev->device = &dev->device;
3411 rte_eth_copy_pci_info(eth_dev, dev);
3413 retval = nfp_net_init(eth_dev);
3419 rte_eth_dev_probing_finish(eth_dev);
3422 rte_free(port_name);
3426 * The rte_service needs to be created just once per PMD.
3427 * And the cpp handler needs to be linked to the service.
3428 * Secondary processes will be used for debugging DPDK apps
3429 * when requiring to use the CPP interface for accessing NFP
3430 * components. And the cpp handler for secondary processes is
3431 * available at this point.
3433 memset(&service, 0, sizeof(struct rte_service_spec));
3434 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3435 service.callback = nfp_cpp_bridge_service_func;
3436 service.callback_userdata = (void *)cpp;
3438 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
3440 if (rte_service_component_register(&service,
3441 &hw->nfp_cpp_service_id))
3442 RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3444 RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3450 rte_free(port_name);
3451 /* free ports private data if primary process */
3452 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3453 rte_free(eth_dev->data->dev_private);
3454 eth_dev->data->dev_private = NULL;
3456 rte_eth_dev_release_port(eth_dev);
3461 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
3464 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3466 struct nfp_cpp *cpp = nsp->cpp;
3471 struct stat file_stat;
3474 /* Looking for firmware file in order of priority */
3476 /* First try to find a firmware image specific for this device */
3477 snprintf(serial, sizeof(serial),
3478 "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3479 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3480 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3481 cpp->interface & 0xff);
3483 snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3486 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3487 fw_f = open(fw_name, O_RDONLY);
3491 /* Then try the PCI name */
3492 snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3495 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3496 fw_f = open(fw_name, O_RDONLY);
3500 /* Finally try the card type and media */
3501 snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3502 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3503 fw_f = open(fw_name, O_RDONLY);
3505 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3510 if (fstat(fw_f, &file_stat) < 0) {
3511 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3516 fsize = file_stat.st_size;
3517 PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3518 fw_name, (uint64_t)fsize);
3520 fw_buf = malloc((size_t)fsize);
3522 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3526 memset(fw_buf, 0, fsize);
3528 bytes = read(fw_f, fw_buf, fsize);
3529 if (bytes != fsize) {
3530 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3531 "Just %" PRIu64 " of %" PRIu64 " bytes read",
3532 (uint64_t)bytes, (uint64_t)fsize);
3538 PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3539 nfp_nsp_load_fw(nsp, fw_buf, bytes);
3540 PMD_DRV_LOG(INFO, "Done");
3549 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3550 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3552 struct nfp_nsp *nsp;
3553 const char *nfp_fw_model;
3554 char card_desc[100];
3557 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3560 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3562 PMD_DRV_LOG(ERR, "firmware model NOT found");
3566 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3567 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3568 nfp_eth_table->count);
3572 PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3573 nfp_eth_table->count);
3575 PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3577 snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3578 nfp_fw_model, nfp_eth_table->count,
3579 nfp_eth_table->ports[0].speed / 1000);
3581 nsp = nfp_nsp_open(cpp);
3583 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3587 nfp_nsp_device_soft_reset(nsp);
3588 err = nfp_fw_upload(dev, nsp, card_desc);
3594 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3595 struct rte_pci_device *dev)
3597 struct nfp_cpp *cpp;
3598 struct nfp_hwinfo *hwinfo;
3599 struct nfp_rtsym_table *sym_tbl;
3600 struct nfp_eth_table *nfp_eth_table = NULL;
3611 * When device bound to UIO, the device could be used, by mistake,
3612 * by two DPDK apps, and the UIO driver does not avoid it. This
3613 * could lead to a serious problem when configuring the NFP CPP
3614 * interface. Here we avoid this telling to the CPP init code to
3615 * use a lock file if UIO is being used.
3617 if (dev->kdrv == RTE_PCI_KDRV_VFIO)
3618 cpp = nfp_cpp_from_device_name(dev, 0);
3620 cpp = nfp_cpp_from_device_name(dev, 1);
3623 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3628 hwinfo = nfp_hwinfo_read(cpp);
3630 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3634 nfp_eth_table = nfp_eth_read_ports(cpp);
3635 if (!nfp_eth_table) {
3636 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3640 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3641 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3642 PMD_DRV_LOG(INFO, "Error when uploading firmware");
3648 /* Now the symbol table should be there */
3649 sym_tbl = nfp_rtsym_table_read(cpp);
3651 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3657 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3658 if (total_ports != (int)nfp_eth_table->count) {
3659 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3663 PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3665 if (total_ports <= 0 || total_ports > 8) {
3666 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3671 for (i = 0; i < total_ports; i++) {
3672 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3673 nfp_eth_table->ports[i].index,
3680 free(nfp_eth_table);
3684 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3686 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3687 PCI_DEVICE_ID_NFP4000_PF_NIC)
3690 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3691 PCI_DEVICE_ID_NFP6000_PF_NIC)
3698 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3700 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3701 PCI_DEVICE_ID_NFP6000_VF_NIC)
3708 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3709 struct rte_pci_device *pci_dev)
3711 return rte_eth_dev_pci_generic_probe(pci_dev,
3712 sizeof(struct nfp_net_adapter), nfp_net_init);
3715 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3717 struct rte_eth_dev *eth_dev;
3718 struct nfp_net_hw *hw, *hwport0;
3721 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3722 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3723 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3724 port = get_pf_port_number(eth_dev->data->name);
3726 * hotplug is not possible with multiport PF although freeing
3727 * data structures can be done for first port.
3731 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3732 hw = &hwport0[port];
3733 nfp_cpp_area_free(hw->ctrl_area);
3734 nfp_cpp_area_free(hw->hwqueues_area);
3737 nfp_cpp_free(hw->cpp);
3739 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3741 /* hotplug is not possible with multiport PF */
3742 if (hw->pf_multiport_enabled)
3744 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3747 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3748 .id_table = pci_id_nfp_pf_net_map,
3749 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3750 .probe = nfp_pf_pci_probe,
3751 .remove = eth_nfp_pci_remove,
3754 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3755 .id_table = pci_id_nfp_vf_net_map,
3756 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3757 .probe = eth_nfp_pci_probe,
3758 .remove = eth_nfp_pci_remove,
3761 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3762 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3763 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3764 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3765 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3766 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3767 RTE_LOG_REGISTER(nfp_logtype_init, pmd.net.nfp.init, NOTICE);
3768 RTE_LOG_REGISTER(nfp_logtype_driver, pmd.net.nfp.driver, NOTICE);
3771 * c-file-style: "Linux"
3772 * indent-tabs-mode: t