2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev_driver.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
57 #include <rte_service_component.h>
59 #include "nfpcore/nfp_cpp.h"
60 #include "nfpcore/nfp_nffw.h"
61 #include "nfpcore/nfp_hwinfo.h"
62 #include "nfpcore/nfp_mip.h"
63 #include "nfpcore/nfp_rtsym.h"
64 #include "nfpcore/nfp_nsp.h"
66 #include "nfp_net_pmd.h"
67 #include "nfp_net_logs.h"
68 #include "nfp_net_ctrl.h"
70 #include <sys/types.h>
71 #include <sys/socket.h>
75 #include <sys/ioctl.h>
79 static void nfp_net_close(struct rte_eth_dev *dev);
80 static int nfp_net_configure(struct rte_eth_dev *dev);
81 static void nfp_net_dev_interrupt_handler(void *param);
82 static void nfp_net_dev_interrupt_delayed_handler(void *param);
83 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
84 static int nfp_net_infos_get(struct rte_eth_dev *dev,
85 struct rte_eth_dev_info *dev_info);
86 static int nfp_net_init(struct rte_eth_dev *eth_dev);
87 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
88 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
89 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
90 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
91 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
93 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
95 static void nfp_net_rx_queue_release(void *rxq);
96 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
97 uint16_t nb_desc, unsigned int socket_id,
98 const struct rte_eth_rxconf *rx_conf,
99 struct rte_mempool *mp);
100 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
101 static void nfp_net_tx_queue_release(void *txq);
102 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
103 uint16_t nb_desc, unsigned int socket_id,
104 const struct rte_eth_txconf *tx_conf);
105 static int nfp_net_start(struct rte_eth_dev *dev);
106 static int nfp_net_stats_get(struct rte_eth_dev *dev,
107 struct rte_eth_stats *stats);
108 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
109 static void nfp_net_stop(struct rte_eth_dev *dev);
110 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
113 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
114 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
115 struct rte_eth_rss_conf *rss_conf);
116 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
117 struct rte_eth_rss_reta_entry64 *reta_conf,
119 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
120 struct rte_eth_rss_conf *rss_conf);
121 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
122 struct rte_ether_addr *mac_addr);
124 /* The offset of the queue controller queues in the PCIe Target */
125 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
127 /* Maximum value which can be added to a queue with one transaction */
128 #define NFP_QCP_MAX_ADD 0x7f
130 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
131 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
133 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
135 NFP_QCP_READ_PTR = 0,
140 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
141 * @q: Base address for queue structure
142 * @ptr: Add to the Read or Write pointer
143 * @val: Value to add to the queue pointer
145 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
148 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
152 if (ptr == NFP_QCP_READ_PTR)
153 off = NFP_QCP_QUEUE_ADD_RPTR;
155 off = NFP_QCP_QUEUE_ADD_WPTR;
157 while (val > NFP_QCP_MAX_ADD) {
158 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
159 val -= NFP_QCP_MAX_ADD;
162 nn_writel(rte_cpu_to_le_32(val), q + off);
166 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
167 * @q: Base address for queue structure
168 * @ptr: Read or Write pointer
170 static inline uint32_t
171 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
176 if (ptr == NFP_QCP_READ_PTR)
177 off = NFP_QCP_QUEUE_STS_LO;
179 off = NFP_QCP_QUEUE_STS_HI;
181 val = rte_cpu_to_le_32(nn_readl(q + off));
183 if (ptr == NFP_QCP_READ_PTR)
184 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
186 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
190 * Functions to read/write from/to Config BAR
191 * Performs any endian conversion necessary.
193 static inline uint8_t
194 nn_cfg_readb(struct nfp_net_hw *hw, int off)
196 return nn_readb(hw->ctrl_bar + off);
200 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
202 nn_writeb(val, hw->ctrl_bar + off);
205 static inline uint32_t
206 nn_cfg_readl(struct nfp_net_hw *hw, int off)
208 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
212 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
214 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
217 static inline uint64_t
218 nn_cfg_readq(struct nfp_net_hw *hw, int off)
220 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
224 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
226 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
230 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
234 if (rxq->rxbufs == NULL)
237 for (i = 0; i < rxq->rx_count; i++) {
238 if (rxq->rxbufs[i].mbuf) {
239 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
240 rxq->rxbufs[i].mbuf = NULL;
246 nfp_net_rx_queue_release(void *rx_queue)
248 struct nfp_net_rxq *rxq = rx_queue;
251 nfp_net_rx_queue_release_mbufs(rxq);
252 rte_free(rxq->rxbufs);
258 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
260 nfp_net_rx_queue_release_mbufs(rxq);
266 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
270 if (txq->txbufs == NULL)
273 for (i = 0; i < txq->tx_count; i++) {
274 if (txq->txbufs[i].mbuf) {
275 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
276 txq->txbufs[i].mbuf = NULL;
282 nfp_net_tx_queue_release(void *tx_queue)
284 struct nfp_net_txq *txq = tx_queue;
287 nfp_net_tx_queue_release_mbufs(txq);
288 rte_free(txq->txbufs);
294 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
296 nfp_net_tx_queue_release_mbufs(txq);
302 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
306 struct timespec wait;
308 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
311 if (hw->qcp_cfg == NULL)
312 rte_panic("Bad configuration queue pointer\n");
314 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
317 wait.tv_nsec = 1000000;
319 PMD_DRV_LOG(DEBUG, "Polling for update ack...");
321 /* Poll update field, waiting for NFP to ack the config */
322 for (cnt = 0; ; cnt++) {
323 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
326 if (new & NFP_NET_CFG_UPDATE_ERR) {
327 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
330 if (cnt >= NFP_NET_POLL_TIMEOUT) {
331 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
332 " %dms", update, cnt);
333 rte_panic("Exiting\n");
335 nanosleep(&wait, 0); /* waiting for a 1ms */
337 PMD_DRV_LOG(DEBUG, "Ack DONE");
342 * Reconfigure the NIC
343 * @nn: device to reconfigure
344 * @ctrl: The value for the ctrl field in the BAR config
345 * @update: The value for the update field in the BAR config
347 * Write the update word to the BAR and ping the reconfig queue. Then poll
348 * until the firmware has acknowledged the update by zeroing the update word.
351 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
355 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
358 rte_spinlock_lock(&hw->reconfig_lock);
360 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
361 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
365 err = __nfp_net_reconfig(hw, update);
367 rte_spinlock_unlock(&hw->reconfig_lock);
373 * Reconfig errors imply situations where they can be handled.
374 * Otherwise, rte_panic is called inside __nfp_net_reconfig
376 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
382 * Configure an Ethernet device. This function must be invoked first
383 * before any other function in the Ethernet API. This function can
384 * also be re-invoked when a device is in the stopped state.
387 nfp_net_configure(struct rte_eth_dev *dev)
389 struct rte_eth_conf *dev_conf;
390 struct rte_eth_rxmode *rxmode;
391 struct rte_eth_txmode *txmode;
392 struct nfp_net_hw *hw;
394 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
397 * A DPDK app sends info about how many queues to use and how
398 * those queues need to be configured. This is used by the
399 * DPDK core and it makes sure no more queues than those
400 * advertised by the driver are requested. This function is
401 * called after that internal process
404 PMD_INIT_LOG(DEBUG, "Configure");
406 dev_conf = &dev->data->dev_conf;
407 rxmode = &dev_conf->rxmode;
408 txmode = &dev_conf->txmode;
410 /* Checking TX mode */
411 if (txmode->mq_mode) {
412 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
416 /* Checking RX mode */
417 if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
418 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
419 PMD_INIT_LOG(INFO, "RSS not supported");
427 nfp_net_enable_queues(struct rte_eth_dev *dev)
429 struct nfp_net_hw *hw;
430 uint64_t enabled_queues = 0;
433 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
435 /* Enabling the required TX queues in the device */
436 for (i = 0; i < dev->data->nb_tx_queues; i++)
437 enabled_queues |= (1 << i);
439 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
443 /* Enabling the required RX queues in the device */
444 for (i = 0; i < dev->data->nb_rx_queues; i++)
445 enabled_queues |= (1 << i);
447 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
451 nfp_net_disable_queues(struct rte_eth_dev *dev)
453 struct nfp_net_hw *hw;
454 uint32_t new_ctrl, update = 0;
456 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
458 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
459 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
461 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
462 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
463 NFP_NET_CFG_UPDATE_MSIX;
465 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
466 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
468 /* If an error when reconfig we avoid to change hw state */
469 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
476 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
480 for (i = 0; i < dev->data->nb_rx_queues; i++) {
481 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
488 nfp_net_params_setup(struct nfp_net_hw *hw)
490 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
491 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
495 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
497 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
500 #define ETH_ADDR_LEN 6
503 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
507 for (i = 0; i < ETH_ADDR_LEN; i++)
512 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
514 struct nfp_eth_table *nfp_eth_table;
516 nfp_eth_table = nfp_eth_read_ports(hw->cpp);
518 * hw points to port0 private data. We need hw now pointing to
522 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
523 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
530 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
534 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
535 memcpy(&hw->mac_addr[0], &tmp, 4);
537 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
538 memcpy(&hw->mac_addr[4], &tmp, 2);
542 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
544 uint32_t mac0 = *(uint32_t *)mac;
547 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
550 mac1 = *(uint16_t *)mac;
551 nn_writew(rte_cpu_to_be_16(mac1),
552 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
556 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
558 struct nfp_net_hw *hw;
559 uint32_t update, ctrl;
561 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
562 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
563 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
564 PMD_INIT_LOG(INFO, "MAC address unable to change when"
569 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
570 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
573 /* Writing new MAC to the specific port BAR address */
574 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
576 /* Signal the NIC about the change */
577 update = NFP_NET_CFG_UPDATE_MACADDR;
579 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
580 (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
581 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
582 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
583 PMD_INIT_LOG(INFO, "MAC address update failed");
590 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
591 struct rte_intr_handle *intr_handle)
593 struct nfp_net_hw *hw;
596 if (!intr_handle->intr_vec) {
597 intr_handle->intr_vec =
598 rte_zmalloc("intr_vec",
599 dev->data->nb_rx_queues * sizeof(int), 0);
600 if (!intr_handle->intr_vec) {
601 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
602 " intr_vec", dev->data->nb_rx_queues);
607 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
609 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
610 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
611 /* UIO just supports one queue and no LSC*/
612 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
613 intr_handle->intr_vec[0] = 0;
615 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
616 for (i = 0; i < dev->data->nb_rx_queues; i++) {
618 * The first msix vector is reserved for non
621 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
622 intr_handle->intr_vec[i] = i + 1;
623 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
624 intr_handle->intr_vec[i]);
628 /* Avoiding TX interrupts */
629 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
634 nfp_check_offloads(struct rte_eth_dev *dev)
636 struct nfp_net_hw *hw;
637 struct rte_eth_conf *dev_conf;
638 struct rte_eth_rxmode *rxmode;
639 struct rte_eth_txmode *txmode;
642 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
644 dev_conf = &dev->data->dev_conf;
645 rxmode = &dev_conf->rxmode;
646 txmode = &dev_conf->txmode;
648 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
649 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
650 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
653 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
654 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
655 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
658 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
659 hw->mtu = rxmode->max_rx_pkt_len;
661 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
662 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
665 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
666 ctrl |= NFP_NET_CFG_CTRL_L2BC;
669 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
670 ctrl |= NFP_NET_CFG_CTRL_L2MC;
672 /* TX checksum offload */
673 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
674 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
675 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
676 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
679 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
680 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
681 ctrl |= NFP_NET_CFG_CTRL_LSO;
683 ctrl |= NFP_NET_CFG_CTRL_LSO2;
687 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
688 ctrl |= NFP_NET_CFG_CTRL_GATHER;
694 nfp_net_start(struct rte_eth_dev *dev)
696 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
697 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
698 uint32_t new_ctrl, update = 0;
699 struct nfp_net_hw *hw;
700 struct rte_eth_conf *dev_conf;
701 struct rte_eth_rxmode *rxmode;
702 uint32_t intr_vector;
705 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
707 PMD_INIT_LOG(DEBUG, "Start");
709 /* Disabling queues just in case... */
710 nfp_net_disable_queues(dev);
712 /* Enabling the required queues in the device */
713 nfp_net_enable_queues(dev);
715 /* check and configure queue intr-vector mapping */
716 if (dev->data->dev_conf.intr_conf.rxq != 0) {
717 if (hw->pf_multiport_enabled) {
718 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
719 "with NFP multiport PF");
722 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
724 * Better not to share LSC with RX interrupts.
725 * Unregistering LSC interrupt handler
727 rte_intr_callback_unregister(&pci_dev->intr_handle,
728 nfp_net_dev_interrupt_handler, (void *)dev);
730 if (dev->data->nb_rx_queues > 1) {
731 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
732 "supports 1 queue with UIO");
736 intr_vector = dev->data->nb_rx_queues;
737 if (rte_intr_efd_enable(intr_handle, intr_vector))
740 nfp_configure_rx_interrupt(dev, intr_handle);
741 update = NFP_NET_CFG_UPDATE_MSIX;
744 rte_intr_enable(intr_handle);
746 new_ctrl = nfp_check_offloads(dev);
748 /* Writing configuration parameters in the device */
749 nfp_net_params_setup(hw);
751 dev_conf = &dev->data->dev_conf;
752 rxmode = &dev_conf->rxmode;
754 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
755 nfp_net_rss_config_default(dev);
756 update |= NFP_NET_CFG_UPDATE_RSS;
757 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
761 new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
763 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
765 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
766 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
768 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
769 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
773 * Allocating rte mbufs for configured rx queues.
774 * This requires queues being enabled before
776 if (nfp_net_rx_freelist_setup(dev) < 0) {
782 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
783 /* Configure the physical port up */
784 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
786 nfp_eth_set_configured(dev->process_private,
796 * An error returned by this function should mean the app
797 * exiting and then the system releasing all the memory
798 * allocated even memory coming from hugepages.
800 * The device could be enabled at this point with some queues
801 * ready for getting packets. This is true if the call to
802 * nfp_net_rx_freelist_setup() succeeds for some queues but
803 * fails for subsequent queues.
805 * This should make the app exiting but better if we tell the
808 nfp_net_disable_queues(dev);
813 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
815 nfp_net_stop(struct rte_eth_dev *dev)
818 struct nfp_net_hw *hw;
820 PMD_INIT_LOG(DEBUG, "Stop");
822 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
824 nfp_net_disable_queues(dev);
827 for (i = 0; i < dev->data->nb_tx_queues; i++) {
828 nfp_net_reset_tx_queue(
829 (struct nfp_net_txq *)dev->data->tx_queues[i]);
832 for (i = 0; i < dev->data->nb_rx_queues; i++) {
833 nfp_net_reset_rx_queue(
834 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
838 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
839 /* Configure the physical port down */
840 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
842 nfp_eth_set_configured(dev->process_private,
847 /* Set the link up. */
849 nfp_net_set_link_up(struct rte_eth_dev *dev)
851 struct nfp_net_hw *hw;
853 PMD_DRV_LOG(DEBUG, "Set link up");
855 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
860 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
861 /* Configure the physical port down */
862 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
864 return nfp_eth_set_configured(dev->process_private,
868 /* Set the link down. */
870 nfp_net_set_link_down(struct rte_eth_dev *dev)
872 struct nfp_net_hw *hw;
874 PMD_DRV_LOG(DEBUG, "Set link down");
876 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
881 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
882 /* Configure the physical port down */
883 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
885 return nfp_eth_set_configured(dev->process_private,
889 /* Reset and stop device. The device can not be restarted. */
891 nfp_net_close(struct rte_eth_dev *dev)
893 struct nfp_net_hw *hw;
894 struct rte_pci_device *pci_dev;
897 PMD_INIT_LOG(DEBUG, "Close");
899 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
900 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
903 * We assume that the DPDK application is stopping all the
904 * threads/queues before calling the device close function.
907 nfp_net_disable_queues(dev);
910 for (i = 0; i < dev->data->nb_tx_queues; i++) {
911 nfp_net_reset_tx_queue(
912 (struct nfp_net_txq *)dev->data->tx_queues[i]);
915 for (i = 0; i < dev->data->nb_rx_queues; i++) {
916 nfp_net_reset_rx_queue(
917 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
920 rte_intr_disable(&pci_dev->intr_handle);
921 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
923 /* unregister callback func from eal lib */
924 rte_intr_callback_unregister(&pci_dev->intr_handle,
925 nfp_net_dev_interrupt_handler,
929 * The ixgbe PMD driver disables the pcie master on the
930 * device. The i40e does not...
935 nfp_net_promisc_enable(struct rte_eth_dev *dev)
937 uint32_t new_ctrl, update = 0;
938 struct nfp_net_hw *hw;
941 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
943 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
945 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
946 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
950 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
951 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
955 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
956 update = NFP_NET_CFG_UPDATE_GEN;
959 * DPDK sets promiscuous mode on just after this call assuming
960 * it can not fail ...
962 ret = nfp_net_reconfig(hw, new_ctrl, update);
972 nfp_net_promisc_disable(struct rte_eth_dev *dev)
974 uint32_t new_ctrl, update = 0;
975 struct nfp_net_hw *hw;
978 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
980 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
981 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
985 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
986 update = NFP_NET_CFG_UPDATE_GEN;
989 * DPDK sets promiscuous mode off just before this call
990 * assuming it can not fail ...
992 ret = nfp_net_reconfig(hw, new_ctrl, update);
1002 * return 0 means link status changed, -1 means not changed
1004 * Wait to complete is needed as it can take up to 9 seconds to get the Link
1008 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1010 struct nfp_net_hw *hw;
1011 struct rte_eth_link link;
1012 uint32_t nn_link_status;
1015 static const uint32_t ls_to_ethtool[] = {
1016 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
1017 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
1018 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
1019 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
1020 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
1021 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
1022 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
1023 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
1026 PMD_DRV_LOG(DEBUG, "Link update");
1028 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1032 memset(&link, 0, sizeof(struct rte_eth_link));
1034 if (nn_link_status & NFP_NET_CFG_STS_LINK)
1035 link.link_status = ETH_LINK_UP;
1037 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1039 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1040 NFP_NET_CFG_STS_LINK_RATE_MASK;
1042 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1043 link.link_speed = ETH_SPEED_NUM_NONE;
1045 link.link_speed = ls_to_ethtool[nn_link_status];
1047 ret = rte_eth_linkstatus_set(dev, &link);
1049 if (link.link_status)
1050 PMD_DRV_LOG(INFO, "NIC Link is Up");
1052 PMD_DRV_LOG(INFO, "NIC Link is Down");
1058 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1061 struct nfp_net_hw *hw;
1062 struct rte_eth_stats nfp_dev_stats;
1064 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1066 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1068 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1070 /* reading per RX ring stats */
1071 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1072 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1075 nfp_dev_stats.q_ipackets[i] =
1076 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1078 nfp_dev_stats.q_ipackets[i] -=
1079 hw->eth_stats_base.q_ipackets[i];
1081 nfp_dev_stats.q_ibytes[i] =
1082 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1084 nfp_dev_stats.q_ibytes[i] -=
1085 hw->eth_stats_base.q_ibytes[i];
1088 /* reading per TX ring stats */
1089 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1090 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1093 nfp_dev_stats.q_opackets[i] =
1094 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1096 nfp_dev_stats.q_opackets[i] -=
1097 hw->eth_stats_base.q_opackets[i];
1099 nfp_dev_stats.q_obytes[i] =
1100 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1102 nfp_dev_stats.q_obytes[i] -=
1103 hw->eth_stats_base.q_obytes[i];
1106 nfp_dev_stats.ipackets =
1107 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1109 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1111 nfp_dev_stats.ibytes =
1112 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1114 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1116 nfp_dev_stats.opackets =
1117 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1119 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1121 nfp_dev_stats.obytes =
1122 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1124 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1126 /* reading general device stats */
1127 nfp_dev_stats.ierrors =
1128 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1130 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1132 nfp_dev_stats.oerrors =
1133 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1135 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1137 /* RX ring mbuf allocation failures */
1138 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1140 nfp_dev_stats.imissed =
1141 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1143 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1146 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1153 nfp_net_stats_reset(struct rte_eth_dev *dev)
1156 struct nfp_net_hw *hw;
1158 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1161 * hw->eth_stats_base records the per counter starting point.
1162 * Lets update it now
1165 /* reading per RX ring stats */
1166 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1167 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1170 hw->eth_stats_base.q_ipackets[i] =
1171 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1173 hw->eth_stats_base.q_ibytes[i] =
1174 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1177 /* reading per TX ring stats */
1178 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1179 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1182 hw->eth_stats_base.q_opackets[i] =
1183 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1185 hw->eth_stats_base.q_obytes[i] =
1186 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1189 hw->eth_stats_base.ipackets =
1190 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1192 hw->eth_stats_base.ibytes =
1193 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1195 hw->eth_stats_base.opackets =
1196 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1198 hw->eth_stats_base.obytes =
1199 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1201 /* reading general device stats */
1202 hw->eth_stats_base.ierrors =
1203 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1205 hw->eth_stats_base.oerrors =
1206 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1208 /* RX ring mbuf allocation failures */
1209 dev->data->rx_mbuf_alloc_failed = 0;
1211 hw->eth_stats_base.imissed =
1212 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1218 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1220 struct nfp_net_hw *hw;
1222 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1225 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1226 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1227 dev_info->max_rx_pktlen = hw->max_mtu;
1228 /* Next should change when PF support is implemented */
1229 dev_info->max_mac_addrs = 1;
1231 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1232 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1234 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1235 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1236 DEV_RX_OFFLOAD_UDP_CKSUM |
1237 DEV_RX_OFFLOAD_TCP_CKSUM;
1239 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1241 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1242 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1244 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1245 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1246 DEV_TX_OFFLOAD_UDP_CKSUM |
1247 DEV_TX_OFFLOAD_TCP_CKSUM;
1249 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1250 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1252 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1253 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1255 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1257 .pthresh = DEFAULT_RX_PTHRESH,
1258 .hthresh = DEFAULT_RX_HTHRESH,
1259 .wthresh = DEFAULT_RX_WTHRESH,
1261 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1265 dev_info->default_txconf = (struct rte_eth_txconf) {
1267 .pthresh = DEFAULT_TX_PTHRESH,
1268 .hthresh = DEFAULT_TX_HTHRESH,
1269 .wthresh = DEFAULT_TX_WTHRESH,
1271 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1272 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1275 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1276 ETH_RSS_NONFRAG_IPV4_TCP |
1277 ETH_RSS_NONFRAG_IPV4_UDP |
1279 ETH_RSS_NONFRAG_IPV6_TCP |
1280 ETH_RSS_NONFRAG_IPV6_UDP;
1282 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1283 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1285 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1286 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1287 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1292 static const uint32_t *
1293 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1295 static const uint32_t ptypes[] = {
1296 /* refers to nfp_net_set_hash() */
1297 RTE_PTYPE_INNER_L3_IPV4,
1298 RTE_PTYPE_INNER_L3_IPV6,
1299 RTE_PTYPE_INNER_L3_IPV6_EXT,
1300 RTE_PTYPE_INNER_L4_MASK,
1304 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1310 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1312 struct nfp_net_rxq *rxq;
1313 struct nfp_net_rx_desc *rxds;
1317 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1324 * Other PMDs are just checking the DD bit in intervals of 4
1325 * descriptors and counting all four if the first has the DD
1326 * bit on. Of course, this is not accurate but can be good for
1327 * performance. But ideally that should be done in descriptors
1328 * chunks belonging to the same cache line
1331 while (count < rxq->rx_count) {
1332 rxds = &rxq->rxds[idx];
1333 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1340 if ((idx) == rxq->rx_count)
1348 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1350 struct rte_pci_device *pci_dev;
1351 struct nfp_net_hw *hw;
1354 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1355 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1357 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1360 /* Make sure all updates are written before un-masking */
1362 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1363 NFP_NET_CFG_ICR_UNMASKED);
1368 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1370 struct rte_pci_device *pci_dev;
1371 struct nfp_net_hw *hw;
1374 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1377 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1380 /* Make sure all updates are written before un-masking */
1382 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1387 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1389 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1390 struct rte_eth_link link;
1392 rte_eth_linkstatus_get(dev, &link);
1393 if (link.link_status)
1394 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1395 dev->data->port_id, link.link_speed,
1396 link.link_duplex == ETH_LINK_FULL_DUPLEX
1397 ? "full-duplex" : "half-duplex");
1399 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1400 dev->data->port_id);
1402 PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1403 pci_dev->addr.domain, pci_dev->addr.bus,
1404 pci_dev->addr.devid, pci_dev->addr.function);
1407 /* Interrupt configuration and handling */
1410 * nfp_net_irq_unmask - Unmask an interrupt
1412 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1413 * clear the ICR for the entry.
1416 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1418 struct nfp_net_hw *hw;
1419 struct rte_pci_device *pci_dev;
1421 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1424 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1425 /* If MSI-X auto-masking is used, clear the entry */
1427 rte_intr_ack(&pci_dev->intr_handle);
1429 /* Make sure all updates are written before un-masking */
1431 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1432 NFP_NET_CFG_ICR_UNMASKED);
1437 nfp_net_dev_interrupt_handler(void *param)
1440 struct rte_eth_link link;
1441 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1443 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1445 rte_eth_linkstatus_get(dev, &link);
1447 nfp_net_link_update(dev, 0);
1450 if (!link.link_status) {
1451 /* handle it 1 sec later, wait it being stable */
1452 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1453 /* likely to down */
1455 /* handle it 4 sec later, wait it being stable */
1456 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1459 if (rte_eal_alarm_set(timeout * 1000,
1460 nfp_net_dev_interrupt_delayed_handler,
1462 PMD_INIT_LOG(ERR, "Error setting alarm");
1464 nfp_net_irq_unmask(dev);
1469 * Interrupt handler which shall be registered for alarm callback for delayed
1470 * handling specific interrupt to wait for the stable nic state. As the NIC
1471 * interrupt state is not stable for nfp after link is just down, it needs
1472 * to wait 4 seconds to get the stable status.
1474 * @param handle Pointer to interrupt handle.
1475 * @param param The address of parameter (struct rte_eth_dev *)
1480 nfp_net_dev_interrupt_delayed_handler(void *param)
1482 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1484 nfp_net_link_update(dev, 0);
1485 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1487 nfp_net_dev_link_status_print(dev);
1490 nfp_net_irq_unmask(dev);
1494 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1496 struct nfp_net_hw *hw;
1498 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1500 /* check that mtu is within the allowed range */
1501 if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1504 /* mtu setting is forbidden if port is started */
1505 if (dev->data->dev_started) {
1506 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1507 dev->data->port_id);
1511 /* switch to jumbo mode if needed */
1512 if ((uint32_t)mtu > RTE_ETHER_MAX_LEN)
1513 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1515 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1517 /* update max frame size */
1518 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1520 /* writing to configuration space */
1521 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1529 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1530 uint16_t queue_idx, uint16_t nb_desc,
1531 unsigned int socket_id,
1532 const struct rte_eth_rxconf *rx_conf,
1533 struct rte_mempool *mp)
1535 const struct rte_memzone *tz;
1536 struct nfp_net_rxq *rxq;
1537 struct nfp_net_hw *hw;
1539 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1541 PMD_INIT_FUNC_TRACE();
1543 /* Validating number of descriptors */
1544 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1545 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1546 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1547 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1552 * Free memory prior to re-allocation if needed. This is the case after
1553 * calling nfp_net_stop
1555 if (dev->data->rx_queues[queue_idx]) {
1556 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1557 dev->data->rx_queues[queue_idx] = NULL;
1560 /* Allocating rx queue data structure */
1561 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1562 RTE_CACHE_LINE_SIZE, socket_id);
1566 /* Hw queues mapping based on firmware configuration */
1567 rxq->qidx = queue_idx;
1568 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1569 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1570 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1571 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1574 * Tracking mbuf size for detecting a potential mbuf overflow due to
1578 rxq->mbuf_size = rxq->mem_pool->elt_size;
1579 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1580 hw->flbufsz = rxq->mbuf_size;
1582 rxq->rx_count = nb_desc;
1583 rxq->port_id = dev->data->port_id;
1584 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1585 rxq->drop_en = rx_conf->rx_drop_en;
1588 * Allocate RX ring hardware descriptors. A memzone large enough to
1589 * handle the maximum ring size is allocated in order to allow for
1590 * resizing in later calls to the queue setup function.
1592 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1593 sizeof(struct nfp_net_rx_desc) *
1594 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1598 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1599 nfp_net_rx_queue_release(rxq);
1603 /* Saving physical and virtual addresses for the RX ring */
1604 rxq->dma = (uint64_t)tz->iova;
1605 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1607 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1608 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1609 sizeof(*rxq->rxbufs) * nb_desc,
1610 RTE_CACHE_LINE_SIZE, socket_id);
1611 if (rxq->rxbufs == NULL) {
1612 nfp_net_rx_queue_release(rxq);
1616 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1617 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1619 nfp_net_reset_rx_queue(rxq);
1621 dev->data->rx_queues[queue_idx] = rxq;
1625 * Telling the HW about the physical address of the RX ring and number
1626 * of descriptors in log2 format
1628 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1629 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1635 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1637 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1641 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1644 for (i = 0; i < rxq->rx_count; i++) {
1645 struct nfp_net_rx_desc *rxd;
1646 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1649 PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1650 (unsigned)rxq->qidx);
1654 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1656 rxd = &rxq->rxds[i];
1658 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1659 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1661 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1664 /* Make sure all writes are flushed before telling the hardware */
1667 /* Not advertising the whole ring as the firmware gets confused if so */
1668 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1671 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1677 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1678 uint16_t nb_desc, unsigned int socket_id,
1679 const struct rte_eth_txconf *tx_conf)
1681 const struct rte_memzone *tz;
1682 struct nfp_net_txq *txq;
1683 uint16_t tx_free_thresh;
1684 struct nfp_net_hw *hw;
1686 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1688 PMD_INIT_FUNC_TRACE();
1690 /* Validating number of descriptors */
1691 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1692 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1693 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1694 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1698 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1699 tx_conf->tx_free_thresh :
1700 DEFAULT_TX_FREE_THRESH);
1702 if (tx_free_thresh > (nb_desc)) {
1704 "tx_free_thresh must be less than the number of TX "
1705 "descriptors. (tx_free_thresh=%u port=%d "
1706 "queue=%d)", (unsigned int)tx_free_thresh,
1707 dev->data->port_id, (int)queue_idx);
1712 * Free memory prior to re-allocation if needed. This is the case after
1713 * calling nfp_net_stop
1715 if (dev->data->tx_queues[queue_idx]) {
1716 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1718 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1719 dev->data->tx_queues[queue_idx] = NULL;
1722 /* Allocating tx queue data structure */
1723 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1724 RTE_CACHE_LINE_SIZE, socket_id);
1726 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1731 * Allocate TX ring hardware descriptors. A memzone large enough to
1732 * handle the maximum ring size is allocated in order to allow for
1733 * resizing in later calls to the queue setup function.
1735 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1736 sizeof(struct nfp_net_tx_desc) *
1737 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1740 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1741 nfp_net_tx_queue_release(txq);
1745 txq->tx_count = nb_desc;
1746 txq->tx_free_thresh = tx_free_thresh;
1747 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1748 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1749 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1751 /* queue mapping based on firmware configuration */
1752 txq->qidx = queue_idx;
1753 txq->tx_qcidx = queue_idx * hw->stride_tx;
1754 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1756 txq->port_id = dev->data->port_id;
1758 /* Saving physical and virtual addresses for the TX ring */
1759 txq->dma = (uint64_t)tz->iova;
1760 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1762 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1763 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1764 sizeof(*txq->txbufs) * nb_desc,
1765 RTE_CACHE_LINE_SIZE, socket_id);
1766 if (txq->txbufs == NULL) {
1767 nfp_net_tx_queue_release(txq);
1770 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1771 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1773 nfp_net_reset_tx_queue(txq);
1775 dev->data->tx_queues[queue_idx] = txq;
1779 * Telling the HW about the physical address of the TX ring and number
1780 * of descriptors in log2 format
1782 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1783 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1788 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1790 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1791 struct rte_mbuf *mb)
1794 struct nfp_net_hw *hw = txq->hw;
1796 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1799 ol_flags = mb->ol_flags;
1801 if (!(ol_flags & PKT_TX_TCP_SEG))
1804 txd->l3_offset = mb->l2_len;
1805 txd->l4_offset = mb->l2_len + mb->l3_len;
1806 txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1807 txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1808 txd->flags = PCIE_DESC_TX_LSO;
1815 txd->lso_hdrlen = 0;
1819 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1821 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1822 struct rte_mbuf *mb)
1825 struct nfp_net_hw *hw = txq->hw;
1827 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1830 ol_flags = mb->ol_flags;
1832 /* IPv6 does not need checksum */
1833 if (ol_flags & PKT_TX_IP_CKSUM)
1834 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1836 switch (ol_flags & PKT_TX_L4_MASK) {
1837 case PKT_TX_UDP_CKSUM:
1838 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1840 case PKT_TX_TCP_CKSUM:
1841 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1845 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1846 txd->flags |= PCIE_DESC_TX_CSUM;
1849 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1851 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1852 struct rte_mbuf *mb)
1854 struct nfp_net_hw *hw = rxq->hw;
1856 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1859 /* If IPv4 and IP checksum error, fail */
1860 if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1861 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1862 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1864 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1866 /* If neither UDP nor TCP return */
1867 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1868 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1871 if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1872 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1874 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1877 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1878 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1880 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1883 * nfp_net_set_hash - Set mbuf hash data
1885 * The RSS hash and hash-type are pre-pended to the packet data.
1886 * Extract and decode it and set the mbuf fields.
1889 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1890 struct rte_mbuf *mbuf)
1892 struct nfp_net_hw *hw = rxq->hw;
1893 uint8_t *meta_offset;
1896 uint32_t hash_type = 0;
1898 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1901 /* this is true for new firmwares */
1902 if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1903 (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1904 NFP_DESC_META_LEN(rxd))) {
1907 * <---- 32 bit ----->
1912 * ====================
1915 * Field type word contains up to 8 4bit field types
1916 * A 4bit field type refers to a data field word
1917 * A data field word can have several 4bit field types
1919 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1920 meta_offset -= NFP_DESC_META_LEN(rxd);
1921 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1923 /* NFP PMD just supports metadata for hashing */
1924 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1925 case NFP_NET_META_HASH:
1926 /* next field type is about the hash type */
1927 meta_info >>= NFP_NET_META_FIELD_SIZE;
1928 /* hash value is in the data field */
1929 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1930 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1933 /* Unsupported metadata can be a performance issue */
1937 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1940 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1941 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1944 mbuf->hash.rss = hash;
1945 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1947 switch (hash_type) {
1948 case NFP_NET_RSS_IPV4:
1949 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1951 case NFP_NET_RSS_IPV6:
1952 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1954 case NFP_NET_RSS_IPV6_EX:
1955 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1957 case NFP_NET_RSS_IPV4_TCP:
1958 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1960 case NFP_NET_RSS_IPV6_TCP:
1961 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1963 case NFP_NET_RSS_IPV4_UDP:
1964 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1966 case NFP_NET_RSS_IPV6_UDP:
1967 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1970 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1975 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1977 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1980 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1985 * There are some decisions to take:
1986 * 1) How to check DD RX descriptors bit
1987 * 2) How and when to allocate new mbufs
1989 * Current implementation checks just one single DD bit each loop. As each
1990 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1991 * a single cache line instead. Tests with this change have not shown any
1992 * performance improvement but it requires further investigation. For example,
1993 * depending on which descriptor is next, the number of descriptors could be
1994 * less than 8 for just checking those in the same cache line. This implies
1995 * extra work which could be counterproductive by itself. Indeed, last firmware
1996 * changes are just doing this: writing several descriptors with the DD bit
1997 * for saving PCIe bandwidth and DMA operations from the NFP.
1999 * Mbuf allocation is done when a new packet is received. Then the descriptor
2000 * is automatically linked with the new mbuf and the old one is given to the
2001 * user. The main drawback with this design is mbuf allocation is heavier than
2002 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2003 * cache point of view it does not seem allocating the mbuf early on as we are
2004 * doing now have any benefit at all. Again, tests with this change have not
2005 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2006 * so looking at the implications of this type of allocation should be studied
2011 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2013 struct nfp_net_rxq *rxq;
2014 struct nfp_net_rx_desc *rxds;
2015 struct nfp_net_rx_buff *rxb;
2016 struct nfp_net_hw *hw;
2017 struct rte_mbuf *mb;
2018 struct rte_mbuf *new_mb;
2024 if (unlikely(rxq == NULL)) {
2026 * DPDK just checks the queue is lower than max queues
2027 * enabled. But the queue needs to be configured
2029 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2037 while (avail < nb_pkts) {
2038 rxb = &rxq->rxbufs[rxq->rd_p];
2039 if (unlikely(rxb == NULL)) {
2040 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2044 rxds = &rxq->rxds[rxq->rd_p];
2045 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2049 * Memory barrier to ensure that we won't do other
2050 * reads before the DD bit.
2055 * We got a packet. Let's alloc a new mbuf for refilling the
2056 * free descriptor ring as soon as possible
2058 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2059 if (unlikely(new_mb == NULL)) {
2060 RTE_LOG_DP(DEBUG, PMD,
2061 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2062 rxq->port_id, (unsigned int)rxq->qidx);
2063 nfp_net_mbuf_alloc_failed(rxq);
2070 * Grab the mbuf and refill the descriptor with the
2071 * previously allocated mbuf
2076 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2077 rxds->rxd.data_len, rxq->mbuf_size);
2079 /* Size of this segment */
2080 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2081 /* Size of the whole packet. We just support 1 segment */
2082 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2084 if (unlikely((mb->data_len + hw->rx_offset) >
2087 * This should not happen and the user has the
2088 * responsibility of avoiding it. But we have
2089 * to give some info about the error
2091 RTE_LOG_DP(ERR, PMD,
2092 "mbuf overflow likely due to the RX offset.\n"
2093 "\t\tYour mbuf size should have extra space for"
2094 " RX offset=%u bytes.\n"
2095 "\t\tCurrently you just have %u bytes available"
2096 " but the received packet is %u bytes long",
2098 rxq->mbuf_size - hw->rx_offset,
2103 /* Filling the received mbuf with packet info */
2105 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2107 mb->data_off = RTE_PKTMBUF_HEADROOM +
2108 NFP_DESC_META_LEN(rxds);
2110 /* No scatter mode supported */
2114 mb->port = rxq->port_id;
2116 /* Checking the RSS flag */
2117 nfp_net_set_hash(rxq, rxds, mb);
2119 /* Checking the checksum flag */
2120 nfp_net_rx_cksum(rxq, rxds, mb);
2122 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2123 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2124 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2125 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2128 /* Adding the mbuf to the mbuf array passed by the app */
2129 rx_pkts[avail++] = mb;
2131 /* Now resetting and updating the descriptor */
2134 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2136 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2137 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2140 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2147 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received",
2148 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2150 nb_hold += rxq->nb_rx_hold;
2153 * FL descriptors needs to be written before incrementing the
2154 * FL queue WR pointer
2157 if (nb_hold > rxq->rx_free_thresh) {
2158 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2159 rxq->port_id, (unsigned int)rxq->qidx,
2160 (unsigned)nb_hold, (unsigned)avail);
2161 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2164 rxq->nb_rx_hold = nb_hold;
2170 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2172 * @txq: TX queue to work with
2173 * Returns number of descriptors freed
2176 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2181 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2182 " status", txq->qidx);
2184 /* Work out how many packets have been sent */
2185 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2187 if (qcp_rd_p == txq->rd_p) {
2188 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2189 "packets (%u, %u)", txq->qidx,
2190 qcp_rd_p, txq->rd_p);
2194 if (qcp_rd_p > txq->rd_p)
2195 todo = qcp_rd_p - txq->rd_p;
2197 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2199 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2200 qcp_rd_p, txq->rd_p, txq->rd_p);
2206 if (unlikely(txq->rd_p >= txq->tx_count))
2207 txq->rd_p -= txq->tx_count;
2212 /* Leaving always free descriptors for avoiding wrapping confusion */
2214 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2216 if (txq->wr_p >= txq->rd_p)
2217 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2219 return txq->rd_p - txq->wr_p - 8;
2223 * nfp_net_txq_full - Check if the TX queue free descriptors
2224 * is below tx_free_threshold
2226 * @txq: TX queue to check
2228 * This function uses the host copy* of read/write pointers
2231 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2233 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2237 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2239 struct nfp_net_txq *txq;
2240 struct nfp_net_hw *hw;
2241 struct nfp_net_tx_desc *txds, txd;
2242 struct rte_mbuf *pkt;
2244 int pkt_size, dma_size;
2245 uint16_t free_descs, issued_descs;
2246 struct rte_mbuf **lmbuf;
2251 txds = &txq->txds[txq->wr_p];
2253 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2254 txq->qidx, txq->wr_p, nb_pkts);
2256 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2257 nfp_net_tx_free_bufs(txq);
2259 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2260 if (unlikely(free_descs == 0))
2267 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2268 txq->qidx, nb_pkts);
2269 /* Sending packets */
2270 while ((i < nb_pkts) && free_descs) {
2271 /* Grabbing the mbuf linked to the current descriptor */
2272 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2273 /* Warming the cache for releasing the mbuf later on */
2274 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2276 pkt = *(tx_pkts + i);
2278 if (unlikely((pkt->nb_segs > 1) &&
2279 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2280 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2281 rte_panic("Multisegment packet unsupported\n");
2284 /* Checking if we have enough descriptors */
2285 if (unlikely(pkt->nb_segs > free_descs))
2289 * Checksum and VLAN flags just in the first descriptor for a
2290 * multisegment packet, but TSO info needs to be in all of them.
2292 txd.data_len = pkt->pkt_len;
2293 nfp_net_tx_tso(txq, &txd, pkt);
2294 nfp_net_tx_cksum(txq, &txd, pkt);
2296 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2297 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2298 txd.flags |= PCIE_DESC_TX_VLAN;
2299 txd.vlan = pkt->vlan_tci;
2303 * mbuf data_len is the data in one segment and pkt_len data
2304 * in the whole packet. When the packet is just one segment,
2305 * then data_len = pkt_len
2307 pkt_size = pkt->pkt_len;
2310 /* Copying TSO, VLAN and cksum info */
2313 /* Releasing mbuf used by this descriptor previously*/
2315 rte_pktmbuf_free_seg(*lmbuf);
2318 * Linking mbuf with descriptor for being released
2319 * next time descriptor is used
2323 dma_size = pkt->data_len;
2324 dma_addr = rte_mbuf_data_iova(pkt);
2325 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2326 "%" PRIx64 "", dma_addr);
2328 /* Filling descriptors fields */
2329 txds->dma_len = dma_size;
2330 txds->data_len = txd.data_len;
2331 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2332 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2333 ASSERT(free_descs > 0);
2337 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2340 pkt_size -= dma_size;
2343 * Making the EOP, packets with just one segment
2346 if (likely(!pkt_size))
2347 txds->offset_eop = PCIE_DESC_TX_EOP;
2349 txds->offset_eop = 0;
2352 /* Referencing next free TX descriptor */
2353 txds = &txq->txds[txq->wr_p];
2354 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2361 /* Increment write pointers. Force memory write before we let HW know */
2363 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2369 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2371 uint32_t new_ctrl, update;
2372 struct nfp_net_hw *hw;
2375 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2378 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2379 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2380 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2381 " ETH_VLAN_EXTEND_OFFLOAD");
2383 /* Enable vlan strip if it is not configured yet */
2384 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2385 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2386 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2388 /* Disable vlan strip just if it is configured */
2389 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2390 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2391 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2396 update = NFP_NET_CFG_UPDATE_GEN;
2398 ret = nfp_net_reconfig(hw, new_ctrl, update);
2400 hw->ctrl = new_ctrl;
2406 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2407 struct rte_eth_rss_reta_entry64 *reta_conf,
2410 uint32_t reta, mask;
2413 struct nfp_net_hw *hw =
2414 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2416 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2417 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2418 "(%d) doesn't match the number hardware can supported "
2419 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2424 * Update Redirection Table. There are 128 8bit-entries which can be
2425 * manage as 32 32bit-entries
2427 for (i = 0; i < reta_size; i += 4) {
2428 /* Handling 4 RSS entries per loop */
2429 idx = i / RTE_RETA_GROUP_SIZE;
2430 shift = i % RTE_RETA_GROUP_SIZE;
2431 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2437 /* If all 4 entries were set, don't need read RETA register */
2439 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2441 for (j = 0; j < 4; j++) {
2442 if (!(mask & (0x1 << j)))
2445 /* Clearing the entry bits */
2446 reta &= ~(0xFF << (8 * j));
2447 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2449 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2455 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2457 nfp_net_reta_update(struct rte_eth_dev *dev,
2458 struct rte_eth_rss_reta_entry64 *reta_conf,
2461 struct nfp_net_hw *hw =
2462 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2469 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2473 update = NFP_NET_CFG_UPDATE_RSS;
2475 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2481 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2483 nfp_net_reta_query(struct rte_eth_dev *dev,
2484 struct rte_eth_rss_reta_entry64 *reta_conf,
2490 struct nfp_net_hw *hw;
2492 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2497 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2498 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2499 "(%d) doesn't match the number hardware can supported "
2500 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2505 * Reading Redirection Table. There are 128 8bit-entries which can be
2506 * manage as 32 32bit-entries
2508 for (i = 0; i < reta_size; i += 4) {
2509 /* Handling 4 RSS entries per loop */
2510 idx = i / RTE_RETA_GROUP_SIZE;
2511 shift = i % RTE_RETA_GROUP_SIZE;
2512 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2517 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2519 for (j = 0; j < 4; j++) {
2520 if (!(mask & (0x1 << j)))
2522 reta_conf[idx].reta[shift + j] =
2523 (uint8_t)((reta >> (8 * j)) & 0xF);
2530 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2531 struct rte_eth_rss_conf *rss_conf)
2533 struct nfp_net_hw *hw;
2535 uint32_t cfg_rss_ctrl = 0;
2539 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541 /* Writing the key byte a byte */
2542 for (i = 0; i < rss_conf->rss_key_len; i++) {
2543 memcpy(&key, &rss_conf->rss_key[i], 1);
2544 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2547 rss_hf = rss_conf->rss_hf;
2549 if (rss_hf & ETH_RSS_IPV4)
2550 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2552 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2553 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2555 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2556 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2558 if (rss_hf & ETH_RSS_IPV6)
2559 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2561 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2562 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2564 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2565 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2567 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2568 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2570 /* configuring where to apply the RSS hash */
2571 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2573 /* Writing the key size */
2574 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2580 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2581 struct rte_eth_rss_conf *rss_conf)
2585 struct nfp_net_hw *hw;
2587 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2589 rss_hf = rss_conf->rss_hf;
2591 /* Checking if RSS is enabled */
2592 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2593 if (rss_hf != 0) { /* Enable RSS? */
2594 PMD_DRV_LOG(ERR, "RSS unsupported");
2597 return 0; /* Nothing to do */
2600 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2601 PMD_DRV_LOG(ERR, "hash key too long");
2605 nfp_net_rss_hash_write(dev, rss_conf);
2607 update = NFP_NET_CFG_UPDATE_RSS;
2609 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2616 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2617 struct rte_eth_rss_conf *rss_conf)
2620 uint32_t cfg_rss_ctrl;
2623 struct nfp_net_hw *hw;
2625 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2627 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2630 rss_hf = rss_conf->rss_hf;
2631 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2633 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2634 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2636 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2637 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2639 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2640 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2642 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2643 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2645 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2646 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2648 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2649 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2651 /* Reading the key size */
2652 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2654 /* Reading the key byte a byte */
2655 for (i = 0; i < rss_conf->rss_key_len; i++) {
2656 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2657 memcpy(&rss_conf->rss_key[i], &key, 1);
2664 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2666 struct rte_eth_conf *dev_conf;
2667 struct rte_eth_rss_conf rss_conf;
2668 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2669 uint16_t rx_queues = dev->data->nb_rx_queues;
2673 PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2676 nfp_reta_conf[0].mask = ~0x0;
2677 nfp_reta_conf[1].mask = ~0x0;
2680 for (i = 0; i < 0x40; i += 8) {
2681 for (j = i; j < (i + 8); j++) {
2682 nfp_reta_conf[0].reta[j] = queue;
2683 nfp_reta_conf[1].reta[j] = queue++;
2687 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2691 dev_conf = &dev->data->dev_conf;
2693 PMD_DRV_LOG(INFO, "wrong rss conf");
2696 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2698 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2704 /* Initialise and register driver with DPDK Application */
2705 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2706 .dev_configure = nfp_net_configure,
2707 .dev_start = nfp_net_start,
2708 .dev_stop = nfp_net_stop,
2709 .dev_set_link_up = nfp_net_set_link_up,
2710 .dev_set_link_down = nfp_net_set_link_down,
2711 .dev_close = nfp_net_close,
2712 .promiscuous_enable = nfp_net_promisc_enable,
2713 .promiscuous_disable = nfp_net_promisc_disable,
2714 .link_update = nfp_net_link_update,
2715 .stats_get = nfp_net_stats_get,
2716 .stats_reset = nfp_net_stats_reset,
2717 .dev_infos_get = nfp_net_infos_get,
2718 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2719 .mtu_set = nfp_net_dev_mtu_set,
2720 .mac_addr_set = nfp_set_mac_addr,
2721 .vlan_offload_set = nfp_net_vlan_offload_set,
2722 .reta_update = nfp_net_reta_update,
2723 .reta_query = nfp_net_reta_query,
2724 .rss_hash_update = nfp_net_rss_hash_update,
2725 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2726 .rx_queue_setup = nfp_net_rx_queue_setup,
2727 .rx_queue_release = nfp_net_rx_queue_release,
2728 .rx_queue_count = nfp_net_rx_queue_count,
2729 .tx_queue_setup = nfp_net_tx_queue_setup,
2730 .tx_queue_release = nfp_net_tx_queue_release,
2731 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2732 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2736 * All eth_dev created got its private data, but before nfp_net_init, that
2737 * private data is referencing private data for all the PF ports. This is due
2738 * to how the vNIC bars are mapped based on first port, so all ports need info
2739 * about port 0 private data. Inside nfp_net_init the private data pointer is
2740 * changed to the right address for each port once the bars have been mapped.
2742 * This functions helps to find out which port and therefore which offset
2743 * inside the private data array to use.
2746 get_pf_port_number(char *name)
2748 char *pf_str = name;
2751 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2756 * This should not happen at all and it would mean major
2757 * implementation fault.
2759 rte_panic("nfp_net: problem with pf device name\n");
2761 /* Expecting _portX with X within [0,7] */
2764 return (int)strtol(pf_str, NULL, 10);
2768 nfp_net_init(struct rte_eth_dev *eth_dev)
2770 struct rte_pci_device *pci_dev;
2771 struct nfp_net_hw *hw, *hwport0;
2773 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2779 PMD_INIT_FUNC_TRACE();
2781 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2783 /* NFP can not handle DMA addresses requiring more than 40 bits */
2784 if (rte_mem_check_dma_mask(40)) {
2785 RTE_LOG(ERR, PMD, "device %s can not be used:",
2786 pci_dev->device.name);
2787 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2791 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2792 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2793 port = get_pf_port_number(eth_dev->data->name);
2794 if (port < 0 || port > 7) {
2795 PMD_DRV_LOG(ERR, "Port value is wrong");
2799 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2801 /* This points to port 0 private data */
2802 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2804 /* This points to the specific port private data */
2805 hw = &hwport0[port];
2807 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2811 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2812 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2813 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2815 /* For secondary processes, the primary has done all the work */
2816 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2819 rte_eth_copy_pci_info(eth_dev, pci_dev);
2821 hw->device_id = pci_dev->id.device_id;
2822 hw->vendor_id = pci_dev->id.vendor_id;
2823 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2824 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2826 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2827 pci_dev->id.vendor_id, pci_dev->id.device_id,
2828 pci_dev->addr.domain, pci_dev->addr.bus,
2829 pci_dev->addr.devid, pci_dev->addr.function);
2831 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2832 if (hw->ctrl_bar == NULL) {
2834 "hw->ctrl_bar is NULL. BAR0 not configured");
2838 if (hw->is_pf && port == 0) {
2839 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2840 hw->total_ports * 32768,
2842 if (!hw->ctrl_bar) {
2843 printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2847 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2851 if (!hwport0->ctrl_bar)
2854 /* address based on port0 offset */
2855 hw->ctrl_bar = hwport0->ctrl_bar +
2856 (port * NFP_PF_CSR_SLICE_SIZE);
2859 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2861 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2862 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2864 /* Work out where in the BAR the queues start. */
2865 switch (pci_dev->id.device_id) {
2866 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2867 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2868 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2869 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2870 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2871 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2872 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2875 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2877 goto dev_err_ctrl_map;
2880 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2881 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2883 if (hw->is_pf && port == 0) {
2884 /* configure access to tx/rx vNIC BARs */
2885 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2887 NFP_QCP_QUEUE_AREA_SZ,
2888 &hw->hwqueues_area);
2890 if (!hwport0->hw_queues) {
2891 printf("nfp_rtsym_map fails for net.qc");
2893 goto dev_err_ctrl_map;
2896 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2897 hwport0->hw_queues);
2901 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2902 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2903 eth_dev->data->dev_private = hw;
2905 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2907 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2911 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2912 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2914 nfp_net_cfg_queue_setup(hw);
2916 /* Get some of the read-only fields from the config BAR */
2917 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2918 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2919 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2920 hw->mtu = RTE_ETHER_MTU;
2922 /* VLAN insertion is incompatible with LSOv2 */
2923 if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2924 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2926 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2927 hw->rx_offset = NFP_NET_RX_OFFSET;
2929 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2931 PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2932 NFD_CFG_MAJOR_VERSION_of(hw->ver),
2933 NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2935 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2936 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2937 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2938 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2939 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2940 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2941 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2942 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2943 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2944 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2945 hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "",
2946 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2947 hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "",
2948 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "",
2949 hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : "");
2953 hw->stride_rx = stride;
2954 hw->stride_tx = stride;
2956 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2957 hw->max_rx_queues, hw->max_tx_queues);
2959 /* Initializing spinlock for reconfigs */
2960 rte_spinlock_init(&hw->reconfig_lock);
2962 /* Allocating memory for mac addr */
2963 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2964 RTE_ETHER_ADDR_LEN, 0);
2965 if (eth_dev->data->mac_addrs == NULL) {
2966 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2968 goto dev_err_queues_map;
2972 nfp_net_pf_read_mac(hwport0, port);
2973 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2975 nfp_net_vf_read_mac(hw);
2978 if (!rte_is_valid_assigned_ether_addr(
2979 (struct rte_ether_addr *)&hw->mac_addr)) {
2980 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2982 /* Using random mac addresses for VFs */
2983 rte_eth_random_addr(&hw->mac_addr[0]);
2984 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2987 /* Copying mac address to DPDK eth_dev struct */
2988 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2989 ð_dev->data->mac_addrs[0]);
2991 if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2992 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2994 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2995 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2996 eth_dev->data->port_id, pci_dev->id.vendor_id,
2997 pci_dev->id.device_id,
2998 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2999 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
3001 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3002 /* Registering LSC interrupt handler */
3003 rte_intr_callback_register(&pci_dev->intr_handle,
3004 nfp_net_dev_interrupt_handler,
3006 /* Telling the firmware about the LSC interrupt entry */
3007 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3008 /* Recording current stats counters values */
3009 nfp_net_stats_reset(eth_dev);
3015 nfp_cpp_area_free(hw->hwqueues_area);
3017 nfp_cpp_area_free(hw->ctrl_area);
3022 #define NFP_CPP_MEMIO_BOUNDARY (1 << 20)
3025 * Serving a write request to NFP from host programs. The request
3026 * sends the write size and the CPP target. The bridge makes use
3027 * of CPP interface handler configured by the PMD setup.
3030 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3032 struct nfp_cpp_area *area;
3033 off_t offset, nfp_offset;
3034 uint32_t cpp_id, pos, len;
3035 uint32_t tmpbuf[16];
3036 size_t count, curlen, totlen = 0;
3039 PMD_CPP_LOG(DEBUG, "%s: offset size %lu, count_size: %lu\n", __func__,
3040 sizeof(off_t), sizeof(size_t));
3042 /* Reading the count param */
3043 err = recv(sockfd, &count, sizeof(off_t), 0);
3044 if (err != sizeof(off_t))
3049 /* Reading the offset param */
3050 err = recv(sockfd, &offset, sizeof(off_t), 0);
3051 if (err != sizeof(off_t))
3054 /* Obtain target's CPP ID and offset in target */
3055 cpp_id = (offset >> 40) << 8;
3056 nfp_offset = offset & ((1ull << 40) - 1);
3058 PMD_CPP_LOG(DEBUG, "%s: count %lu and offset %ld\n", __func__, count,
3060 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %ld\n", __func__,
3061 cpp_id, nfp_offset);
3063 /* Adjust length if not aligned */
3064 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3065 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3066 curlen = NFP_CPP_MEMIO_BOUNDARY -
3067 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3071 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3072 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3073 nfp_offset, curlen);
3075 RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3079 /* mapping the target */
3080 err = nfp_cpp_area_acquire(area);
3082 RTE_LOG(ERR, PMD, "area acquire failed\n");
3083 nfp_cpp_area_free(area);
3087 for (pos = 0; pos < curlen; pos += len) {
3089 if (len > sizeof(tmpbuf))
3090 len = sizeof(tmpbuf);
3092 PMD_CPP_LOG(DEBUG, "%s: Receive %u of %lu\n", __func__,
3094 err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3095 if (err != (int)len) {
3097 "%s: error when receiving, %d of %lu\n",
3098 __func__, err, count);
3099 nfp_cpp_area_release(area);
3100 nfp_cpp_area_free(area);
3103 err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3105 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3106 nfp_cpp_area_release(area);
3107 nfp_cpp_area_free(area);
3114 nfp_cpp_area_release(area);
3115 nfp_cpp_area_free(area);
3118 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3119 NFP_CPP_MEMIO_BOUNDARY : count;
3126 * Serving a read request to NFP from host programs. The request
3127 * sends the read size and the CPP target. The bridge makes use
3128 * of CPP interface handler configured by the PMD setup. The read
3129 * data is sent to the requester using the same socket.
3132 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3134 struct nfp_cpp_area *area;
3135 off_t offset, nfp_offset;
3136 uint32_t cpp_id, pos, len;
3137 uint32_t tmpbuf[16];
3138 size_t count, curlen, totlen = 0;
3141 PMD_CPP_LOG(DEBUG, "%s: offset size %lu, count_size: %lu\n", __func__,
3142 sizeof(off_t), sizeof(size_t));
3144 /* Reading the count param */
3145 err = recv(sockfd, &count, sizeof(off_t), 0);
3146 if (err != sizeof(off_t))
3151 /* Reading the offset param */
3152 err = recv(sockfd, &offset, sizeof(off_t), 0);
3153 if (err != sizeof(off_t))
3156 /* Obtain target's CPP ID and offset in target */
3157 cpp_id = (offset >> 40) << 8;
3158 nfp_offset = offset & ((1ull << 40) - 1);
3160 PMD_CPP_LOG(DEBUG, "%s: count %lu and offset %ld\n", __func__, count,
3162 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %ld\n", __func__,
3163 cpp_id, nfp_offset);
3165 /* Adjust length if not aligned */
3166 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3167 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3168 curlen = NFP_CPP_MEMIO_BOUNDARY -
3169 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3173 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3174 nfp_offset, curlen);
3176 RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3180 err = nfp_cpp_area_acquire(area);
3182 RTE_LOG(ERR, PMD, "area acquire failed\n");
3183 nfp_cpp_area_free(area);
3187 for (pos = 0; pos < curlen; pos += len) {
3189 if (len > sizeof(tmpbuf))
3190 len = sizeof(tmpbuf);
3192 err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3194 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3195 nfp_cpp_area_release(area);
3196 nfp_cpp_area_free(area);
3199 PMD_CPP_LOG(DEBUG, "%s: sending %u of %lu\n", __func__,
3202 err = send(sockfd, tmpbuf, len, 0);
3203 if (err != (int)len) {
3205 "%s: error when sending: %d of %lu\n",
3206 __func__, err, count);
3207 nfp_cpp_area_release(area);
3208 nfp_cpp_area_free(area);
3215 nfp_cpp_area_release(area);
3216 nfp_cpp_area_free(area);
3219 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3220 NFP_CPP_MEMIO_BOUNDARY : count;
3225 #define NFP_IOCTL 'n'
3226 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3228 * Serving a ioctl command from host NFP tools. This usually goes to
3229 * a kernel driver char driver but it is not available when the PF is
3230 * bound to the PMD. Currently just one ioctl command is served and it
3231 * does not require any CPP access at all.
3234 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3236 uint32_t cmd, ident_size, tmp;
3239 /* Reading now the IOCTL command */
3240 err = recv(sockfd, &cmd, 4, 0);
3242 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3246 /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3247 if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3248 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3252 err = recv(sockfd, &ident_size, 4, 0);
3254 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3258 tmp = nfp_cpp_model(cpp);
3260 PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3262 err = send(sockfd, &tmp, 4, 0);
3264 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3268 tmp = cpp->interface;
3270 PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3272 err = send(sockfd, &tmp, 4, 0);
3274 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3281 #define NFP_BRIDGE_OP_READ 20
3282 #define NFP_BRIDGE_OP_WRITE 30
3283 #define NFP_BRIDGE_OP_IOCTL 40
3286 * This is the code to be executed by a service core. The CPP bridge interface
3287 * is based on a unix socket and requests usually received by a kernel char
3288 * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3289 * can be executed with a wrapper library and LD_LIBRARY being completely
3290 * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3294 nfp_cpp_bridge_service_func(void *args)
3296 struct sockaddr address;
3297 struct nfp_cpp *cpp = args;
3298 int sockfd, datafd, op, ret;
3300 unlink("/tmp/nfp_cpp");
3301 sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3303 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3308 memset(&address, 0, sizeof(struct sockaddr));
3310 address.sa_family = AF_UNIX;
3311 strcpy(address.sa_data, "/tmp/nfp_cpp");
3313 ret = bind(sockfd, (const struct sockaddr *)&address,
3314 sizeof(struct sockaddr));
3316 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3322 ret = listen(sockfd, 20);
3324 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3331 datafd = accept(sockfd, NULL, NULL);
3333 RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3335 RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3341 ret = recv(datafd, &op, 4, 0);
3343 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3348 PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3350 if (op == NFP_BRIDGE_OP_READ)
3351 nfp_cpp_bridge_serve_read(datafd, cpp);
3353 if (op == NFP_BRIDGE_OP_WRITE)
3354 nfp_cpp_bridge_serve_write(datafd, cpp);
3356 if (op == NFP_BRIDGE_OP_IOCTL)
3357 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3370 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3371 struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3372 int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3374 struct rte_eth_dev *eth_dev;
3375 struct nfp_net_hw *hw = NULL;
3377 struct rte_service_spec service;
3380 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3385 snprintf(port_name, 100, "%s_port%d", dev->device.name, port);
3387 strlcat(port_name, dev->device.name, 100);
3390 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3391 eth_dev = rte_eth_dev_allocate(port_name);
3393 rte_free(port_name);
3397 *priv = rte_zmalloc(port_name,
3398 sizeof(struct nfp_net_adapter) *
3399 ports, RTE_CACHE_LINE_SIZE);
3401 rte_free(port_name);
3402 rte_eth_dev_release_port(eth_dev);
3406 eth_dev->data->dev_private = *priv;
3409 * dev_private pointing to port0 dev_private because we need
3410 * to configure vNIC bars based on port0 at nfp_net_init.
3411 * Then dev_private is adjusted per port.
3413 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3415 hw->hwinfo = hwinfo;
3416 hw->sym_tbl = sym_tbl;
3417 hw->pf_port_idx = phys_port;
3420 hw->pf_multiport_enabled = 1;
3422 hw->total_ports = ports;
3424 eth_dev = rte_eth_dev_attach_secondary(port_name);
3426 RTE_LOG(ERR, EAL, "secondary process attach failed, "
3427 "ethdev doesn't exist");
3428 rte_free(port_name);
3431 eth_dev->process_private = cpp;
3434 eth_dev->device = &dev->device;
3435 rte_eth_copy_pci_info(eth_dev, dev);
3437 retval = nfp_net_init(eth_dev);
3443 rte_eth_dev_probing_finish(eth_dev);
3446 rte_free(port_name);
3450 * The rte_service needs to be created just once per PMD.
3451 * And the cpp handler needs to be linked to the service.
3452 * Secondary processes will be used for debugging DPDK apps
3453 * when requiring to use the CPP interface for accessing NFP
3454 * components. And the cpp handler for secondary processes is
3455 * available at this point.
3457 memset(&service, 0, sizeof(struct rte_service_spec));
3458 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3459 service.callback = nfp_cpp_bridge_service_func;
3460 service.callback_userdata = (void *)cpp;
3462 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
3464 if (rte_service_component_register(&service,
3465 &hw->nfp_cpp_service_id))
3466 RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3468 RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3474 rte_free(port_name);
3475 /* free ports private data if primary process */
3476 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3477 rte_free(eth_dev->data->dev_private);
3479 rte_eth_dev_release_port(eth_dev);
3484 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
3487 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3489 struct nfp_cpp *cpp = nsp->cpp;
3494 struct stat file_stat;
3497 /* Looking for firmware file in order of priority */
3499 /* First try to find a firmware image specific for this device */
3500 snprintf(serial, sizeof(serial),
3501 "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3502 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3503 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3504 cpp->interface & 0xff);
3506 snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3509 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3510 fw_f = open(fw_name, O_RDONLY);
3514 /* Then try the PCI name */
3515 snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3518 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3519 fw_f = open(fw_name, O_RDONLY);
3523 /* Finally try the card type and media */
3524 snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3525 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3526 fw_f = open(fw_name, O_RDONLY);
3528 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3533 if (fstat(fw_f, &file_stat) < 0) {
3534 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3539 fsize = file_stat.st_size;
3540 PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3541 fw_name, (uint64_t)fsize);
3543 fw_buf = malloc((size_t)fsize);
3545 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3549 memset(fw_buf, 0, fsize);
3551 bytes = read(fw_f, fw_buf, fsize);
3552 if (bytes != fsize) {
3553 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3554 "Just %" PRIu64 " of %" PRIu64 " bytes read",
3555 (uint64_t)bytes, (uint64_t)fsize);
3561 PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3562 nfp_nsp_load_fw(nsp, fw_buf, bytes);
3563 PMD_DRV_LOG(INFO, "Done");
3572 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3573 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3575 struct nfp_nsp *nsp;
3576 const char *nfp_fw_model;
3577 char card_desc[100];
3580 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3583 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3585 PMD_DRV_LOG(ERR, "firmware model NOT found");
3589 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3590 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3591 nfp_eth_table->count);
3595 PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3596 nfp_eth_table->count);
3598 PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3600 snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3601 nfp_fw_model, nfp_eth_table->count,
3602 nfp_eth_table->ports[0].speed / 1000);
3604 nsp = nfp_nsp_open(cpp);
3606 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3610 nfp_nsp_device_soft_reset(nsp);
3611 err = nfp_fw_upload(dev, nsp, card_desc);
3617 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3618 struct rte_pci_device *dev)
3620 struct nfp_cpp *cpp;
3621 struct nfp_hwinfo *hwinfo;
3622 struct nfp_rtsym_table *sym_tbl;
3623 struct nfp_eth_table *nfp_eth_table = NULL;
3634 * When device bound to UIO, the device could be used, by mistake,
3635 * by two DPDK apps, and the UIO driver does not avoid it. This
3636 * could lead to a serious problem when configuring the NFP CPP
3637 * interface. Here we avoid this telling to the CPP init code to
3638 * use a lock file if UIO is being used.
3640 if (dev->kdrv == RTE_KDRV_VFIO)
3641 cpp = nfp_cpp_from_device_name(dev, 0);
3643 cpp = nfp_cpp_from_device_name(dev, 1);
3646 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3651 hwinfo = nfp_hwinfo_read(cpp);
3653 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3657 nfp_eth_table = nfp_eth_read_ports(cpp);
3658 if (!nfp_eth_table) {
3659 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3663 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3664 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3665 PMD_DRV_LOG(INFO, "Error when uploading firmware");
3671 /* Now the symbol table should be there */
3672 sym_tbl = nfp_rtsym_table_read(cpp);
3674 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3680 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3681 if (total_ports != (int)nfp_eth_table->count) {
3682 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3686 PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3688 if (total_ports <= 0 || total_ports > 8) {
3689 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3694 for (i = 0; i < total_ports; i++) {
3695 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3696 nfp_eth_table->ports[i].index,
3703 free(nfp_eth_table);
3707 int nfp_logtype_init;
3708 int nfp_logtype_driver;
3710 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3712 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3713 PCI_DEVICE_ID_NFP4000_PF_NIC)
3716 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3717 PCI_DEVICE_ID_NFP6000_PF_NIC)
3724 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3726 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3727 PCI_DEVICE_ID_NFP6000_VF_NIC)
3734 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3735 struct rte_pci_device *pci_dev)
3737 return rte_eth_dev_pci_generic_probe(pci_dev,
3738 sizeof(struct nfp_net_adapter), nfp_net_init);
3741 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3743 struct rte_eth_dev *eth_dev;
3744 struct nfp_net_hw *hw, *hwport0;
3747 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3748 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3749 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3750 port = get_pf_port_number(eth_dev->data->name);
3752 * hotplug is not possible with multiport PF although freeing
3753 * data structures can be done for first port.
3757 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3758 hw = &hwport0[port];
3759 nfp_cpp_area_free(hw->ctrl_area);
3760 nfp_cpp_area_free(hw->hwqueues_area);
3763 nfp_cpp_free(hw->cpp);
3765 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3767 /* hotplug is not possible with multiport PF */
3768 if (hw->pf_multiport_enabled)
3770 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3773 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3774 .id_table = pci_id_nfp_pf_net_map,
3775 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3776 .probe = nfp_pf_pci_probe,
3777 .remove = eth_nfp_pci_remove,
3780 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3781 .id_table = pci_id_nfp_vf_net_map,
3782 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3783 .probe = eth_nfp_pci_probe,
3784 .remove = eth_nfp_pci_remove,
3787 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3788 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3789 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3790 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3791 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3792 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3794 RTE_INIT(nfp_init_log)
3796 nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3797 if (nfp_logtype_init >= 0)
3798 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3799 nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3800 if (nfp_logtype_driver >= 0)
3801 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3805 * c-file-style: "Linux"
3806 * indent-tabs-mode: t