drivers/net/nfp/nfp_net.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  */
   7
   8 /*
   9  * vim:shiftwidth=8:noexpandtab
  10  *
  11  * @file dpdk/pmd/nfp_net.c
  12  *
  13  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  14  */
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_log.h>
  19 #include <rte_debug.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_dev.h>
  23 #include <rte_ether.h>
  24 #include <rte_malloc.h>
  25 #include <rte_memzone.h>
  26 #include <rte_mempool.h>
  27 #include <rte_version.h>
  28 #include <rte_string_fns.h>
  29 #include <rte_alarm.h>
  30 #include <rte_spinlock.h>
  31 #include <rte_service_component.h>
  32
  33 #include "nfpcore/nfp_cpp.h"
  34 #include "nfpcore/nfp_nffw.h"
  35 #include "nfpcore/nfp_hwinfo.h"
  36 #include "nfpcore/nfp_mip.h"
  37 #include "nfpcore/nfp_rtsym.h"
  38 #include "nfpcore/nfp_nsp.h"
  39
  40 #include "nfp_net_pmd.h"
  41 #include "nfp_net_logs.h"
  42 #include "nfp_net_ctrl.h"
  43
  44 #include <sys/types.h>
  45 #include <sys/socket.h>
  46 #include <sys/un.h>
  47 #include <unistd.h>
  48 #include <stdio.h>
  49 #include <sys/ioctl.h>
  50 #include <errno.h>
  51
  52 /* Prototypes */
  53 static void nfp_net_close(struct rte_eth_dev *dev);
  54 static int nfp_net_configure(struct rte_eth_dev *dev);
  55 static void nfp_net_dev_interrupt_handler(void *param);
  56 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  57 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  58 static int nfp_net_infos_get(struct rte_eth_dev *dev,
  59                              struct rte_eth_dev_info *dev_info);
  60 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  61 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  62 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
  63 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
  64 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  65 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  66                                        uint16_t queue_idx);
  67 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  68                                   uint16_t nb_pkts);
  69 static void nfp_net_rx_queue_release(void *rxq);
  70 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  71                                   uint16_t nb_desc, unsigned int socket_id,
  72                                   const struct rte_eth_rxconf *rx_conf,
  73                                   struct rte_mempool *mp);
  74 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  75 static void nfp_net_tx_queue_release(void *txq);
  76 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  77                                   uint16_t nb_desc, unsigned int socket_id,
  78                                   const struct rte_eth_txconf *tx_conf);
  79 static int nfp_net_start(struct rte_eth_dev *dev);
  80 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  81                               struct rte_eth_stats *stats);
  82 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
  83 static void nfp_net_stop(struct rte_eth_dev *dev);
  84 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  85                                   uint16_t nb_pkts);
  86
  87 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
  88 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
  89                                    struct rte_eth_rss_conf *rss_conf);
  90 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
  91                     struct rte_eth_rss_reta_entry64 *reta_conf,
  92                     uint16_t reta_size);
  93 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
  94                         struct rte_eth_rss_conf *rss_conf);
  95 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
  96                              struct rte_ether_addr *mac_addr);
  97
  98 /* The offset of the queue controller queues in the PCIe Target */
  99 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 100
 101 /* Maximum value which can be added to a queue with one transaction */
 102 #define NFP_QCP_MAX_ADD 0x7f
 103
 104 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 105         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 106
 107 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 108 enum nfp_qcp_ptr {
 109         NFP_QCP_READ_PTR = 0,
 110         NFP_QCP_WRITE_PTR
 111 };
 112
 113 /*
 114  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 115  * @q: Base address for queue structure
 116  * @ptr: Add to the Read or Write pointer
 117  * @val: Value to add to the queue pointer
 118  *
 119  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 120  */
 121 static inline void
 122 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 123 {
 124         uint32_t off;
 125
 126         if (ptr == NFP_QCP_READ_PTR)
 127                 off = NFP_QCP_QUEUE_ADD_RPTR;
 128         else
 129                 off = NFP_QCP_QUEUE_ADD_WPTR;
 130
 131         while (val > NFP_QCP_MAX_ADD) {
 132                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 133                 val -= NFP_QCP_MAX_ADD;
 134         }
 135
 136         nn_writel(rte_cpu_to_le_32(val), q + off);
 137 }
 138
 139 /*
 140  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 141  * @q:  Base address for queue structure
 142  * @ptr: Read or Write pointer
 143  */
 144 static inline uint32_t
 145 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 146 {
 147         uint32_t off;
 148         uint32_t val;
 149
 150         if (ptr == NFP_QCP_READ_PTR)
 151                 off = NFP_QCP_QUEUE_STS_LO;
 152         else
 153                 off = NFP_QCP_QUEUE_STS_HI;
 154
 155         val = rte_cpu_to_le_32(nn_readl(q + off));
 156
 157         if (ptr == NFP_QCP_READ_PTR)
 158                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 159         else
 160                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 161 }
 162
 163 /*
 164  * Functions to read/write from/to Config BAR
 165  * Performs any endian conversion necessary.
 166  */
 167 static inline uint8_t
 168 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 169 {
 170         return nn_readb(hw->ctrl_bar + off);
 171 }
 172
 173 static inline void
 174 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 175 {
 176         nn_writeb(val, hw->ctrl_bar + off);
 177 }
 178
 179 static inline uint32_t
 180 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 181 {
 182         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 183 }
 184
 185 static inline void
 186 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 187 {
 188         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 189 }
 190
 191 static inline uint64_t
 192 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 193 {
 194         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 195 }
 196
 197 static inline void
 198 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 199 {
 200         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 201 }
 202
 203 static void
 204 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 205 {
 206         unsigned i;
 207
 208         if (rxq->rxbufs == NULL)
 209                 return;
 210
 211         for (i = 0; i < rxq->rx_count; i++) {
 212                 if (rxq->rxbufs[i].mbuf) {
 213                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 214                         rxq->rxbufs[i].mbuf = NULL;
 215                 }
 216         }
 217 }
 218
 219 static void
 220 nfp_net_rx_queue_release(void *rx_queue)
 221 {
 222         struct nfp_net_rxq *rxq = rx_queue;
 223
 224         if (rxq) {
 225                 nfp_net_rx_queue_release_mbufs(rxq);
 226                 rte_free(rxq->rxbufs);
 227                 rte_free(rxq);
 228         }
 229 }
 230
 231 static void
 232 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 233 {
 234         nfp_net_rx_queue_release_mbufs(rxq);
 235         rxq->rd_p = 0;
 236         rxq->nb_rx_hold = 0;
 237 }
 238
 239 static void
 240 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 241 {
 242         unsigned i;
 243
 244         if (txq->txbufs == NULL)
 245                 return;
 246
 247         for (i = 0; i < txq->tx_count; i++) {
 248                 if (txq->txbufs[i].mbuf) {
 249                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 250                         txq->txbufs[i].mbuf = NULL;
 251                 }
 252         }
 253 }
 254
 255 static void
 256 nfp_net_tx_queue_release(void *tx_queue)
 257 {
 258         struct nfp_net_txq *txq = tx_queue;
 259
 260         if (txq) {
 261                 nfp_net_tx_queue_release_mbufs(txq);
 262                 rte_free(txq->txbufs);
 263                 rte_free(txq);
 264         }
 265 }
 266
 267 static void
 268 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 269 {
 270         nfp_net_tx_queue_release_mbufs(txq);
 271         txq->wr_p = 0;
 272         txq->rd_p = 0;
 273 }
 274
 275 static int
 276 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 277 {
 278         int cnt;
 279         uint32_t new;
 280         struct timespec wait;
 281
 282         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 283                     hw->qcp_cfg);
 284
 285         if (hw->qcp_cfg == NULL)
 286                 rte_panic("Bad configuration queue pointer\n");
 287
 288         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 289
 290         wait.tv_sec = 0;
 291         wait.tv_nsec = 1000000;
 292
 293         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 294
 295         /* Poll update field, waiting for NFP to ack the config */
 296         for (cnt = 0; ; cnt++) {
 297                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 298                 if (new == 0)
 299                         break;
 300                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 301                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 302                         return -1;
 303                 }
 304                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 305                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 306                                           " %dms", update, cnt);
 307                         rte_panic("Exiting\n");
 308                 }
 309                 nanosleep(&wait, 0); /* waiting for a 1ms */
 310         }
 311         PMD_DRV_LOG(DEBUG, "Ack DONE");
 312         return 0;
 313 }
 314
 315 /*
 316  * Reconfigure the NIC
 317  * @nn:    device to reconfigure
 318  * @ctrl:    The value for the ctrl field in the BAR config
 319  * @update:  The value for the update field in the BAR config
 320  *
 321  * Write the update word to the BAR and ping the reconfig queue. Then poll
 322  * until the firmware has acknowledged the update by zeroing the update word.
 323  */
 324 static int
 325 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 326 {
 327         uint32_t err;
 328
 329         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 330                     ctrl, update);
 331
 332         rte_spinlock_lock(&hw->reconfig_lock);
 333
 334         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 335         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 336
 337         rte_wmb();
 338
 339         err = __nfp_net_reconfig(hw, update);
 340
 341         rte_spinlock_unlock(&hw->reconfig_lock);
 342
 343         if (!err)
 344                 return 0;
 345
 346         /*
 347          * Reconfig errors imply situations where they can be handled.
 348          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 349          */
 350         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 351                      ctrl, update);
 352         return -EIO;
 353 }
 354
 355 /*
 356  * Configure an Ethernet device. This function must be invoked first
 357  * before any other function in the Ethernet API. This function can
 358  * also be re-invoked when a device is in the stopped state.
 359  */
 360 static int
 361 nfp_net_configure(struct rte_eth_dev *dev)
 362 {
 363         struct rte_eth_conf *dev_conf;
 364         struct rte_eth_rxmode *rxmode;
 365         struct rte_eth_txmode *txmode;
 366         struct nfp_net_hw *hw;
 367
 368         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 369
 370         /*
 371          * A DPDK app sends info about how many queues to use and how
 372          * those queues need to be configured. This is used by the
 373          * DPDK core and it makes sure no more queues than those
 374          * advertised by the driver are requested. This function is
 375          * called after that internal process
 376          */
 377
 378         PMD_INIT_LOG(DEBUG, "Configure");
 379
 380         dev_conf = &dev->data->dev_conf;
 381         rxmode = &dev_conf->rxmode;
 382         txmode = &dev_conf->txmode;
 383
 384         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
 385                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 386
 387         /* Checking TX mode */
 388         if (txmode->mq_mode) {
 389                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 390                 return -EINVAL;
 391         }
 392
 393         /* Checking RX mode */
 394         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 395             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 396                 PMD_INIT_LOG(INFO, "RSS not supported");
 397                 return -EINVAL;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static void
 404 nfp_net_enable_queues(struct rte_eth_dev *dev)
 405 {
 406         struct nfp_net_hw *hw;
 407         uint64_t enabled_queues = 0;
 408         int i;
 409
 410         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 411
 412         /* Enabling the required TX queues in the device */
 413         for (i = 0; i < dev->data->nb_tx_queues; i++)
 414                 enabled_queues |= (1 << i);
 415
 416         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 417
 418         enabled_queues = 0;
 419
 420         /* Enabling the required RX queues in the device */
 421         for (i = 0; i < dev->data->nb_rx_queues; i++)
 422                 enabled_queues |= (1 << i);
 423
 424         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 425 }
 426
 427 static void
 428 nfp_net_disable_queues(struct rte_eth_dev *dev)
 429 {
 430         struct nfp_net_hw *hw;
 431         uint32_t new_ctrl, update = 0;
 432
 433         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 434
 435         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 436         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 437
 438         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 439         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 440                  NFP_NET_CFG_UPDATE_MSIX;
 441
 442         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 443                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 444
 445         /* If an error when reconfig we avoid to change hw state */
 446         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 447                 return;
 448
 449         hw->ctrl = new_ctrl;
 450 }
 451
 452 static int
 453 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 454 {
 455         int i;
 456
 457         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 458                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 459                         return -1;
 460         }
 461         return 0;
 462 }
 463
 464 static void
 465 nfp_net_params_setup(struct nfp_net_hw *hw)
 466 {
 467         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 468         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 469 }
 470
 471 static void
 472 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 473 {
 474         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 475 }
 476
 477 #define ETH_ADDR_LEN    6
 478
 479 static void
 480 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 481 {
 482         int i;
 483
 484         for (i = 0; i < ETH_ADDR_LEN; i++)
 485                 dst[i] = src[i];
 486 }
 487
 488 static int
 489 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 490 {
 491         struct nfp_eth_table *nfp_eth_table;
 492
 493         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 494         /*
 495          * hw points to port0 private data. We need hw now pointing to
 496          * right port.
 497          */
 498         hw += port;
 499         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 500                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 501
 502         free(nfp_eth_table);
 503         return 0;
 504 }
 505
 506 static void
 507 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 508 {
 509         uint32_t tmp;
 510
 511         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 512         memcpy(&hw->mac_addr[0], &tmp, 4);
 513
 514         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 515         memcpy(&hw->mac_addr[4], &tmp, 2);
 516 }
 517
 518 static void
 519 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 520 {
 521         uint32_t mac0 = *(uint32_t *)mac;
 522         uint16_t mac1;
 523
 524         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 525
 526         mac += 4;
 527         mac1 = *(uint16_t *)mac;
 528         nn_writew(rte_cpu_to_be_16(mac1),
 529                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 530 }
 531
 532 int
 533 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
 534 {
 535         struct nfp_net_hw *hw;
 536         uint32_t update, ctrl;
 537
 538         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 539         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 540             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 541                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 542                                   " port enabled");
 543                 return -EBUSY;
 544         }
 545
 546         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 547             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 548                 return -EBUSY;
 549
 550         /* Writing new MAC to the specific port BAR address */
 551         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 552
 553         /* Signal the NIC about the change */
 554         update = NFP_NET_CFG_UPDATE_MACADDR;
 555         ctrl = hw->ctrl;
 556         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 557             (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 558                 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
 559         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 560                 PMD_INIT_LOG(INFO, "MAC address update failed");
 561                 return -EIO;
 562         }
 563         return 0;
 564 }
 565
 566 static int
 567 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 568                            struct rte_intr_handle *intr_handle)
 569 {
 570         struct nfp_net_hw *hw;
 571         int i;
 572
 573         if (!intr_handle->intr_vec) {
 574                 intr_handle->intr_vec =
 575                         rte_zmalloc("intr_vec",
 576                                     dev->data->nb_rx_queues * sizeof(int), 0);
 577                 if (!intr_handle->intr_vec) {
 578                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 579                                      " intr_vec", dev->data->nb_rx_queues);
 580                         return -ENOMEM;
 581                 }
 582         }
 583
 584         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 585
 586         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 587                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 588                 /* UIO just supports one queue and no LSC*/
 589                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 590                 intr_handle->intr_vec[0] = 0;
 591         } else {
 592                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 593                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 594                         /*
 595                          * The first msix vector is reserved for non
 596                          * efd interrupts
 597                         */
 598                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 599                         intr_handle->intr_vec[i] = i + 1;
 600                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 601                                             intr_handle->intr_vec[i]);
 602                 }
 603         }
 604
 605         /* Avoiding TX interrupts */
 606         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 607         return 0;
 608 }
 609
 610 static uint32_t
 611 nfp_check_offloads(struct rte_eth_dev *dev)
 612 {
 613         struct nfp_net_hw *hw;
 614         struct rte_eth_conf *dev_conf;
 615         struct rte_eth_rxmode *rxmode;
 616         struct rte_eth_txmode *txmode;
 617         uint32_t ctrl = 0;
 618
 619         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 620
 621         dev_conf = &dev->data->dev_conf;
 622         rxmode = &dev_conf->rxmode;
 623         txmode = &dev_conf->txmode;
 624
 625         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 626                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 627                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 628         }
 629
 630         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 631                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 632                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 633         }
 634
 635         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 636                 hw->mtu = rxmode->max_rx_pkt_len;
 637
 638         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 639                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 640
 641         /* L2 broadcast */
 642         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 643                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 644
 645         /* L2 multicast */
 646         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 647                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 648
 649         /* TX checksum offload */
 650         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 651             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 652             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 653                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 654
 655         /* LSO offload */
 656         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 657                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 658                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 659                 else
 660                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 661         }
 662
 663         /* RX gather */
 664         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 665                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 666
 667         return ctrl;
 668 }
 669
 670 static int
 671 nfp_net_start(struct rte_eth_dev *dev)
 672 {
 673         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 674         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 675         uint32_t new_ctrl, update = 0;
 676         struct nfp_net_hw *hw;
 677         struct rte_eth_conf *dev_conf;
 678         struct rte_eth_rxmode *rxmode;
 679         uint32_t intr_vector;
 680         int ret;
 681
 682         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 683
 684         PMD_INIT_LOG(DEBUG, "Start");
 685
 686         /* Disabling queues just in case... */
 687         nfp_net_disable_queues(dev);
 688
 689         /* Enabling the required queues in the device */
 690         nfp_net_enable_queues(dev);
 691
 692         /* check and configure queue intr-vector mapping */
 693         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 694                 if (hw->pf_multiport_enabled) {
 695                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 696                                           "with NFP multiport PF");
 697                                 return -EINVAL;
 698                 }
 699                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 700                         /*
 701                          * Better not to share LSC with RX interrupts.
 702                          * Unregistering LSC interrupt handler
 703                          */
 704                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 705                                 nfp_net_dev_interrupt_handler, (void *)dev);
 706
 707                         if (dev->data->nb_rx_queues > 1) {
 708                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 709                                              "supports 1 queue with UIO");
 710                                 return -EIO;
 711                         }
 712                 }
 713                 intr_vector = dev->data->nb_rx_queues;
 714                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 715                         return -1;
 716
 717                 nfp_configure_rx_interrupt(dev, intr_handle);
 718                 update = NFP_NET_CFG_UPDATE_MSIX;
 719         }
 720
 721         rte_intr_enable(intr_handle);
 722
 723         new_ctrl = nfp_check_offloads(dev);
 724
 725         /* Writing configuration parameters in the device */
 726         nfp_net_params_setup(hw);
 727
 728         dev_conf = &dev->data->dev_conf;
 729         rxmode = &dev_conf->rxmode;
 730
 731         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 732                 nfp_net_rss_config_default(dev);
 733                 update |= NFP_NET_CFG_UPDATE_RSS;
 734                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 735         }
 736
 737         /* Enable device */
 738         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 739
 740         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 741
 742         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 743                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 744
 745         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 746         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 747                 return -EIO;
 748
 749         /*
 750          * Allocating rte mbufs for configured rx queues.
 751          * This requires queues being enabled before
 752          */
 753         if (nfp_net_rx_freelist_setup(dev) < 0) {
 754                 ret = -ENOMEM;
 755                 goto error;
 756         }
 757
 758         if (hw->is_pf) {
 759                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 760                         /* Configure the physical port up */
 761                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 762                 else
 763                         nfp_eth_set_configured(dev->process_private,
 764                                                hw->pf_port_idx, 1);
 765         }
 766
 767         hw->ctrl = new_ctrl;
 768
 769         return 0;
 770
 771 error:
 772         /*
 773          * An error returned by this function should mean the app
 774          * exiting and then the system releasing all the memory
 775          * allocated even memory coming from hugepages.
 776          *
 777          * The device could be enabled at this point with some queues
 778          * ready for getting packets. This is true if the call to
 779          * nfp_net_rx_freelist_setup() succeeds for some queues but
 780          * fails for subsequent queues.
 781          *
 782          * This should make the app exiting but better if we tell the
 783          * device first.
 784          */
 785         nfp_net_disable_queues(dev);
 786
 787         return ret;
 788 }
 789
 790 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 791 static void
 792 nfp_net_stop(struct rte_eth_dev *dev)
 793 {
 794         int i;
 795         struct nfp_net_hw *hw;
 796
 797         PMD_INIT_LOG(DEBUG, "Stop");
 798
 799         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 800
 801         nfp_net_disable_queues(dev);
 802
 803         /* Clear queues */
 804         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 805                 nfp_net_reset_tx_queue(
 806                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 807         }
 808
 809         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 810                 nfp_net_reset_rx_queue(
 811                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 812         }
 813
 814         if (hw->is_pf) {
 815                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 816                         /* Configure the physical port down */
 817                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 818                 else
 819                         nfp_eth_set_configured(dev->process_private,
 820                                                hw->pf_port_idx, 0);
 821         }
 822 }
 823
 824 /* Set the link up. */
 825 static int
 826 nfp_net_set_link_up(struct rte_eth_dev *dev)
 827 {
 828         struct nfp_net_hw *hw;
 829
 830         PMD_DRV_LOG(DEBUG, "Set link up");
 831
 832         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 833
 834         if (!hw->is_pf)
 835                 return -ENOTSUP;
 836
 837         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 838                 /* Configure the physical port down */
 839                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 840         else
 841                 return nfp_eth_set_configured(dev->process_private,
 842                                               hw->pf_port_idx, 1);
 843 }
 844
 845 /* Set the link down. */
 846 static int
 847 nfp_net_set_link_down(struct rte_eth_dev *dev)
 848 {
 849         struct nfp_net_hw *hw;
 850
 851         PMD_DRV_LOG(DEBUG, "Set link down");
 852
 853         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854
 855         if (!hw->is_pf)
 856                 return -ENOTSUP;
 857
 858         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 859                 /* Configure the physical port down */
 860                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 861         else
 862                 return nfp_eth_set_configured(dev->process_private,
 863                                               hw->pf_port_idx, 0);
 864 }
 865
 866 /* Reset and stop device. The device can not be restarted. */
 867 static void
 868 nfp_net_close(struct rte_eth_dev *dev)
 869 {
 870         struct nfp_net_hw *hw;
 871         struct rte_pci_device *pci_dev;
 872         int i;
 873
 874         PMD_INIT_LOG(DEBUG, "Close");
 875
 876         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 878
 879         /*
 880          * We assume that the DPDK application is stopping all the
 881          * threads/queues before calling the device close function.
 882          */
 883
 884         nfp_net_disable_queues(dev);
 885
 886         /* Clear queues */
 887         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 888                 nfp_net_reset_tx_queue(
 889                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 890         }
 891
 892         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 893                 nfp_net_reset_rx_queue(
 894                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 895         }
 896
 897         rte_intr_disable(&pci_dev->intr_handle);
 898         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 899
 900         /* unregister callback func from eal lib */
 901         rte_intr_callback_unregister(&pci_dev->intr_handle,
 902                                      nfp_net_dev_interrupt_handler,
 903                                      (void *)dev);
 904
 905         /*
 906          * The ixgbe PMD driver disables the pcie master on the
 907          * device. The i40e does not...
 908          */
 909 }
 910
 911 static int
 912 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 913 {
 914         uint32_t new_ctrl, update = 0;
 915         struct nfp_net_hw *hw;
 916         int ret;
 917
 918         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 919
 920         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 921
 922         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 923                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 924                 return -ENOTSUP;
 925         }
 926
 927         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 928                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 929                 return 0;
 930         }
 931
 932         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 933         update = NFP_NET_CFG_UPDATE_GEN;
 934
 935         /*
 936          * DPDK sets promiscuous mode on just after this call assuming
 937          * it can not fail ...
 938          */
 939         ret = nfp_net_reconfig(hw, new_ctrl, update);
 940         if (ret < 0)
 941                 return ret;
 942
 943         hw->ctrl = new_ctrl;
 944
 945         return 0;
 946 }
 947
 948 static int
 949 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 950 {
 951         uint32_t new_ctrl, update = 0;
 952         struct nfp_net_hw *hw;
 953         int ret;
 954
 955         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956
 957         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 958                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 959                 return 0;
 960         }
 961
 962         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 963         update = NFP_NET_CFG_UPDATE_GEN;
 964
 965         /*
 966          * DPDK sets promiscuous mode off just before this call
 967          * assuming it can not fail ...
 968          */
 969         ret = nfp_net_reconfig(hw, new_ctrl, update);
 970         if (ret < 0)
 971                 return ret;
 972
 973         hw->ctrl = new_ctrl;
 974
 975         return 0;
 976 }
 977
 978 /*
 979  * return 0 means link status changed, -1 means not changed
 980  *
 981  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 982  * status.
 983  */
 984 static int
 985 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 986 {
 987         struct nfp_net_hw *hw;
 988         struct rte_eth_link link;
 989         uint32_t nn_link_status;
 990         int ret;
 991
 992         static const uint32_t ls_to_ethtool[] = {
 993                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 994                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 995                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 996                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 997                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 998                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 999                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
1000                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
1001         };
1002
1003         PMD_DRV_LOG(DEBUG, "Link update");
1004
1005         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006
1007         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1008
1009         memset(&link, 0, sizeof(struct rte_eth_link));
1010
1011         if (nn_link_status & NFP_NET_CFG_STS_LINK)
1012                 link.link_status = ETH_LINK_UP;
1013
1014         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1015
1016         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1017                          NFP_NET_CFG_STS_LINK_RATE_MASK;
1018
1019         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1020                 link.link_speed = ETH_SPEED_NUM_NONE;
1021         else
1022                 link.link_speed = ls_to_ethtool[nn_link_status];
1023
1024         ret = rte_eth_linkstatus_set(dev, &link);
1025         if (ret == 0) {
1026                 if (link.link_status)
1027                         PMD_DRV_LOG(INFO, "NIC Link is Up");
1028                 else
1029                         PMD_DRV_LOG(INFO, "NIC Link is Down");
1030         }
1031         return ret;
1032 }
1033
1034 static int
1035 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1036 {
1037         int i;
1038         struct nfp_net_hw *hw;
1039         struct rte_eth_stats nfp_dev_stats;
1040
1041         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1042
1043         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1044
1045         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1046
1047         /* reading per RX ring stats */
1048         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1049                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1050                         break;
1051
1052                 nfp_dev_stats.q_ipackets[i] =
1053                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1054
1055                 nfp_dev_stats.q_ipackets[i] -=
1056                         hw->eth_stats_base.q_ipackets[i];
1057
1058                 nfp_dev_stats.q_ibytes[i] =
1059                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1060
1061                 nfp_dev_stats.q_ibytes[i] -=
1062                         hw->eth_stats_base.q_ibytes[i];
1063         }
1064
1065         /* reading per TX ring stats */
1066         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1067                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1068                         break;
1069
1070                 nfp_dev_stats.q_opackets[i] =
1071                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1072
1073                 nfp_dev_stats.q_opackets[i] -=
1074                         hw->eth_stats_base.q_opackets[i];
1075
1076                 nfp_dev_stats.q_obytes[i] =
1077                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1078
1079                 nfp_dev_stats.q_obytes[i] -=
1080                         hw->eth_stats_base.q_obytes[i];
1081         }
1082
1083         nfp_dev_stats.ipackets =
1084                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1085
1086         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1087
1088         nfp_dev_stats.ibytes =
1089                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1090
1091         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1092
1093         nfp_dev_stats.opackets =
1094                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1095
1096         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1097
1098         nfp_dev_stats.obytes =
1099                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1100
1101         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1102
1103         /* reading general device stats */
1104         nfp_dev_stats.ierrors =
1105                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1106
1107         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1108
1109         nfp_dev_stats.oerrors =
1110                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1111
1112         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1113
1114         /* RX ring mbuf allocation failures */
1115         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1116
1117         nfp_dev_stats.imissed =
1118                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1119
1120         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1121
1122         if (stats) {
1123                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1124                 return 0;
1125         }
1126         return -EINVAL;
1127 }
1128
1129 static int
1130 nfp_net_stats_reset(struct rte_eth_dev *dev)
1131 {
1132         int i;
1133         struct nfp_net_hw *hw;
1134
1135         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1136
1137         /*
1138          * hw->eth_stats_base records the per counter starting point.
1139          * Lets update it now
1140          */
1141
1142         /* reading per RX ring stats */
1143         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1144                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1145                         break;
1146
1147                 hw->eth_stats_base.q_ipackets[i] =
1148                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1149
1150                 hw->eth_stats_base.q_ibytes[i] =
1151                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1152         }
1153
1154         /* reading per TX ring stats */
1155         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1156                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1157                         break;
1158
1159                 hw->eth_stats_base.q_opackets[i] =
1160                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1161
1162                 hw->eth_stats_base.q_obytes[i] =
1163                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1164         }
1165
1166         hw->eth_stats_base.ipackets =
1167                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1168
1169         hw->eth_stats_base.ibytes =
1170                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1171
1172         hw->eth_stats_base.opackets =
1173                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1174
1175         hw->eth_stats_base.obytes =
1176                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1177
1178         /* reading general device stats */
1179         hw->eth_stats_base.ierrors =
1180                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1181
1182         hw->eth_stats_base.oerrors =
1183                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1184
1185         /* RX ring mbuf allocation failures */
1186         dev->data->rx_mbuf_alloc_failed = 0;
1187
1188         hw->eth_stats_base.imissed =
1189                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1190
1191         return 0;
1192 }
1193
1194 static int
1195 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1196 {
1197         struct nfp_net_hw *hw;
1198
1199         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200
1201         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1202         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1203         dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1204         dev_info->max_rx_pktlen = hw->max_mtu;
1205         /* Next should change when PF support is implemented */
1206         dev_info->max_mac_addrs = 1;
1207
1208         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1209                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1210
1211         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1212                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1213                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1214                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1215
1216         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME |
1217                                      DEV_RX_OFFLOAD_RSS_HASH;
1218
1219         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1220                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1221
1222         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1223                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1224                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1225                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1226
1227         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1228                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1229
1230         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1231                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1232
1233         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1234                 .rx_thresh = {
1235                         .pthresh = DEFAULT_RX_PTHRESH,
1236                         .hthresh = DEFAULT_RX_HTHRESH,
1237                         .wthresh = DEFAULT_RX_WTHRESH,
1238                 },
1239                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1240                 .rx_drop_en = 0,
1241         };
1242
1243         dev_info->default_txconf = (struct rte_eth_txconf) {
1244                 .tx_thresh = {
1245                         .pthresh = DEFAULT_TX_PTHRESH,
1246                         .hthresh = DEFAULT_TX_HTHRESH,
1247                         .wthresh = DEFAULT_TX_WTHRESH,
1248                 },
1249                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1250                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1251         };
1252
1253         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1254                                            ETH_RSS_NONFRAG_IPV4_TCP |
1255                                            ETH_RSS_NONFRAG_IPV4_UDP |
1256                                            ETH_RSS_IPV6 |
1257                                            ETH_RSS_NONFRAG_IPV6_TCP |
1258                                            ETH_RSS_NONFRAG_IPV6_UDP;
1259
1260         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1261         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1262
1263         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1264                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1265                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1266
1267         return 0;
1268 }
1269
1270 static const uint32_t *
1271 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1272 {
1273         static const uint32_t ptypes[] = {
1274                 /* refers to nfp_net_set_hash() */
1275                 RTE_PTYPE_INNER_L3_IPV4,
1276                 RTE_PTYPE_INNER_L3_IPV6,
1277                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1278                 RTE_PTYPE_INNER_L4_MASK,
1279                 RTE_PTYPE_UNKNOWN
1280         };
1281
1282         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1283                 return ptypes;
1284         return NULL;
1285 }
1286
1287 static uint32_t
1288 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1289 {
1290         struct nfp_net_rxq *rxq;
1291         struct nfp_net_rx_desc *rxds;
1292         uint32_t idx;
1293         uint32_t count;
1294
1295         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1296
1297         idx = rxq->rd_p;
1298
1299         count = 0;
1300
1301         /*
1302          * Other PMDs are just checking the DD bit in intervals of 4
1303          * descriptors and counting all four if the first has the DD
1304          * bit on. Of course, this is not accurate but can be good for
1305          * performance. But ideally that should be done in descriptors
1306          * chunks belonging to the same cache line
1307          */
1308
1309         while (count < rxq->rx_count) {
1310                 rxds = &rxq->rxds[idx];
1311                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1312                         break;
1313
1314                 count++;
1315                 idx++;
1316
1317                 /* Wrapping? */
1318                 if ((idx) == rxq->rx_count)
1319                         idx = 0;
1320         }
1321
1322         return count;
1323 }
1324
1325 static int
1326 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1327 {
1328         struct rte_pci_device *pci_dev;
1329         struct nfp_net_hw *hw;
1330         int base = 0;
1331
1332         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1333         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1334
1335         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1336                 base = 1;
1337
1338         /* Make sure all updates are written before un-masking */
1339         rte_wmb();
1340         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1341                       NFP_NET_CFG_ICR_UNMASKED);
1342         return 0;
1343 }
1344
1345 static int
1346 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1347 {
1348         struct rte_pci_device *pci_dev;
1349         struct nfp_net_hw *hw;
1350         int base = 0;
1351
1352         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1353         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1354
1355         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1356                 base = 1;
1357
1358         /* Make sure all updates are written before un-masking */
1359         rte_wmb();
1360         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1361         return 0;
1362 }
1363
1364 static void
1365 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1366 {
1367         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1368         struct rte_eth_link link;
1369
1370         rte_eth_linkstatus_get(dev, &link);
1371         if (link.link_status)
1372                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1373                             dev->data->port_id, link.link_speed,
1374                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1375                             ? "full-duplex" : "half-duplex");
1376         else
1377                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1378                             dev->data->port_id);
1379
1380         PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
1381                     pci_dev->addr.domain, pci_dev->addr.bus,
1382                     pci_dev->addr.devid, pci_dev->addr.function);
1383 }
1384
1385 /* Interrupt configuration and handling */
1386
1387 /*
1388  * nfp_net_irq_unmask - Unmask an interrupt
1389  *
1390  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1391  * clear the ICR for the entry.
1392  */
1393 static void
1394 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1395 {
1396         struct nfp_net_hw *hw;
1397         struct rte_pci_device *pci_dev;
1398
1399         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1401
1402         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1403                 /* If MSI-X auto-masking is used, clear the entry */
1404                 rte_wmb();
1405                 rte_intr_ack(&pci_dev->intr_handle);
1406         } else {
1407                 /* Make sure all updates are written before un-masking */
1408                 rte_wmb();
1409                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1410                               NFP_NET_CFG_ICR_UNMASKED);
1411         }
1412 }
1413
1414 static void
1415 nfp_net_dev_interrupt_handler(void *param)
1416 {
1417         int64_t timeout;
1418         struct rte_eth_link link;
1419         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1420
1421         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1422
1423         rte_eth_linkstatus_get(dev, &link);
1424
1425         nfp_net_link_update(dev, 0);
1426
1427         /* likely to up */
1428         if (!link.link_status) {
1429                 /* handle it 1 sec later, wait it being stable */
1430                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1431                 /* likely to down */
1432         } else {
1433                 /* handle it 4 sec later, wait it being stable */
1434                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1435         }
1436
1437         if (rte_eal_alarm_set(timeout * 1000,
1438                               nfp_net_dev_interrupt_delayed_handler,
1439                               (void *)dev) < 0) {
1440                 PMD_INIT_LOG(ERR, "Error setting alarm");
1441                 /* Unmasking */
1442                 nfp_net_irq_unmask(dev);
1443         }
1444 }
1445
1446 /*
1447  * Interrupt handler which shall be registered for alarm callback for delayed
1448  * handling specific interrupt to wait for the stable nic state. As the NIC
1449  * interrupt state is not stable for nfp after link is just down, it needs
1450  * to wait 4 seconds to get the stable status.
1451  *
1452  * @param handle   Pointer to interrupt handle.
1453  * @param param    The address of parameter (struct rte_eth_dev *)
1454  *
1455  * @return  void
1456  */
1457 static void
1458 nfp_net_dev_interrupt_delayed_handler(void *param)
1459 {
1460         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1461
1462         nfp_net_link_update(dev, 0);
1463         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1464
1465         nfp_net_dev_link_status_print(dev);
1466
1467         /* Unmasking */
1468         nfp_net_irq_unmask(dev);
1469 }
1470
1471 static int
1472 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1473 {
1474         struct nfp_net_hw *hw;
1475
1476         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477
1478         /* check that mtu is within the allowed range */
1479         if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1480                 return -EINVAL;
1481
1482         /* mtu setting is forbidden if port is started */
1483         if (dev->data->dev_started) {
1484                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1485                             dev->data->port_id);
1486                 return -EBUSY;
1487         }
1488
1489         /* switch to jumbo mode if needed */
1490         if ((uint32_t)mtu > RTE_ETHER_MAX_LEN)
1491                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1492         else
1493                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1494
1495         /* update max frame size */
1496         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1497
1498         /* writing to configuration space */
1499         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1500
1501         hw->mtu = mtu;
1502
1503         return 0;
1504 }
1505
1506 static int
1507 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1508                        uint16_t queue_idx, uint16_t nb_desc,
1509                        unsigned int socket_id,
1510                        const struct rte_eth_rxconf *rx_conf,
1511                        struct rte_mempool *mp)
1512 {
1513         const struct rte_memzone *tz;
1514         struct nfp_net_rxq *rxq;
1515         struct nfp_net_hw *hw;
1516
1517         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518
1519         PMD_INIT_FUNC_TRACE();
1520
1521         /* Validating number of descriptors */
1522         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1523             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1524             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1525                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1526                 return -EINVAL;
1527         }
1528
1529         /*
1530          * Free memory prior to re-allocation if needed. This is the case after
1531          * calling nfp_net_stop
1532          */
1533         if (dev->data->rx_queues[queue_idx]) {
1534                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1535                 dev->data->rx_queues[queue_idx] = NULL;
1536         }
1537
1538         /* Allocating rx queue data structure */
1539         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1540                                  RTE_CACHE_LINE_SIZE, socket_id);
1541         if (rxq == NULL)
1542                 return -ENOMEM;
1543
1544         /* Hw queues mapping based on firmware configuration */
1545         rxq->qidx = queue_idx;
1546         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1547         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1548         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1549         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1550
1551         /*
1552          * Tracking mbuf size for detecting a potential mbuf overflow due to
1553          * RX offset
1554          */
1555         rxq->mem_pool = mp;
1556         rxq->mbuf_size = rxq->mem_pool->elt_size;
1557         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1558         hw->flbufsz = rxq->mbuf_size;
1559
1560         rxq->rx_count = nb_desc;
1561         rxq->port_id = dev->data->port_id;
1562         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1563         rxq->drop_en = rx_conf->rx_drop_en;
1564
1565         /*
1566          * Allocate RX ring hardware descriptors. A memzone large enough to
1567          * handle the maximum ring size is allocated in order to allow for
1568          * resizing in later calls to the queue setup function.
1569          */
1570         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1571                                    sizeof(struct nfp_net_rx_desc) *
1572                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1573                                    socket_id);
1574
1575         if (tz == NULL) {
1576                 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1577                 nfp_net_rx_queue_release(rxq);
1578                 return -ENOMEM;
1579         }
1580
1581         /* Saving physical and virtual addresses for the RX ring */
1582         rxq->dma = (uint64_t)tz->iova;
1583         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1584
1585         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1586         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1587                                          sizeof(*rxq->rxbufs) * nb_desc,
1588                                          RTE_CACHE_LINE_SIZE, socket_id);
1589         if (rxq->rxbufs == NULL) {
1590                 nfp_net_rx_queue_release(rxq);
1591                 return -ENOMEM;
1592         }
1593
1594         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1595                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1596
1597         nfp_net_reset_rx_queue(rxq);
1598
1599         dev->data->rx_queues[queue_idx] = rxq;
1600         rxq->hw = hw;
1601
1602         /*
1603          * Telling the HW about the physical address of the RX ring and number
1604          * of descriptors in log2 format
1605          */
1606         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1607         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1608
1609         return 0;
1610 }
1611
1612 static int
1613 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1614 {
1615         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1616         uint64_t dma_addr;
1617         unsigned i;
1618
1619         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1620                    rxq->rx_count);
1621
1622         for (i = 0; i < rxq->rx_count; i++) {
1623                 struct nfp_net_rx_desc *rxd;
1624                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1625
1626                 if (mbuf == NULL) {
1627                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1628                                 (unsigned)rxq->qidx);
1629                         return -ENOMEM;
1630                 }
1631
1632                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1633
1634                 rxd = &rxq->rxds[i];
1635                 rxd->fld.dd = 0;
1636                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1637                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1638                 rxe[i].mbuf = mbuf;
1639                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1640         }
1641
1642         /* Make sure all writes are flushed before telling the hardware */
1643         rte_wmb();
1644
1645         /* Not advertising the whole ring as the firmware gets confused if so */
1646         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1647                    rxq->rx_count - 1);
1648
1649         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1650
1651         return 0;
1652 }
1653
1654 static int
1655 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1656                        uint16_t nb_desc, unsigned int socket_id,
1657                        const struct rte_eth_txconf *tx_conf)
1658 {
1659         const struct rte_memzone *tz;
1660         struct nfp_net_txq *txq;
1661         uint16_t tx_free_thresh;
1662         struct nfp_net_hw *hw;
1663
1664         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665
1666         PMD_INIT_FUNC_TRACE();
1667
1668         /* Validating number of descriptors */
1669         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1670             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1671             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1672                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1673                 return -EINVAL;
1674         }
1675
1676         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1677                                     tx_conf->tx_free_thresh :
1678                                     DEFAULT_TX_FREE_THRESH);
1679
1680         if (tx_free_thresh > (nb_desc)) {
1681                 PMD_DRV_LOG(ERR,
1682                         "tx_free_thresh must be less than the number of TX "
1683                         "descriptors. (tx_free_thresh=%u port=%d "
1684                         "queue=%d)", (unsigned int)tx_free_thresh,
1685                         dev->data->port_id, (int)queue_idx);
1686                 return -(EINVAL);
1687         }
1688
1689         /*
1690          * Free memory prior to re-allocation if needed. This is the case after
1691          * calling nfp_net_stop
1692          */
1693         if (dev->data->tx_queues[queue_idx]) {
1694                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1695                            queue_idx);
1696                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1697                 dev->data->tx_queues[queue_idx] = NULL;
1698         }
1699
1700         /* Allocating tx queue data structure */
1701         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1702                                  RTE_CACHE_LINE_SIZE, socket_id);
1703         if (txq == NULL) {
1704                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1705                 return -ENOMEM;
1706         }
1707
1708         /*
1709          * Allocate TX ring hardware descriptors. A memzone large enough to
1710          * handle the maximum ring size is allocated in order to allow for
1711          * resizing in later calls to the queue setup function.
1712          */
1713         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1714                                    sizeof(struct nfp_net_tx_desc) *
1715                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1716                                    socket_id);
1717         if (tz == NULL) {
1718                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1719                 nfp_net_tx_queue_release(txq);
1720                 return -ENOMEM;
1721         }
1722
1723         txq->tx_count = nb_desc;
1724         txq->tx_free_thresh = tx_free_thresh;
1725         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1726         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1727         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1728
1729         /* queue mapping based on firmware configuration */
1730         txq->qidx = queue_idx;
1731         txq->tx_qcidx = queue_idx * hw->stride_tx;
1732         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1733
1734         txq->port_id = dev->data->port_id;
1735
1736         /* Saving physical and virtual addresses for the TX ring */
1737         txq->dma = (uint64_t)tz->iova;
1738         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1739
1740         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1741         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1742                                          sizeof(*txq->txbufs) * nb_desc,
1743                                          RTE_CACHE_LINE_SIZE, socket_id);
1744         if (txq->txbufs == NULL) {
1745                 nfp_net_tx_queue_release(txq);
1746                 return -ENOMEM;
1747         }
1748         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1749                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1750
1751         nfp_net_reset_tx_queue(txq);
1752
1753         dev->data->tx_queues[queue_idx] = txq;
1754         txq->hw = hw;
1755
1756         /*
1757          * Telling the HW about the physical address of the TX ring and number
1758          * of descriptors in log2 format
1759          */
1760         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1761         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1762
1763         return 0;
1764 }
1765
1766 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1767 static inline void
1768 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1769                struct rte_mbuf *mb)
1770 {
1771         uint64_t ol_flags;
1772         struct nfp_net_hw *hw = txq->hw;
1773
1774         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1775                 goto clean_txd;
1776
1777         ol_flags = mb->ol_flags;
1778
1779         if (!(ol_flags & PKT_TX_TCP_SEG))
1780                 goto clean_txd;
1781
1782         txd->l3_offset = mb->l2_len;
1783         txd->l4_offset = mb->l2_len + mb->l3_len;
1784         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1785         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1786         txd->flags = PCIE_DESC_TX_LSO;
1787         return;
1788
1789 clean_txd:
1790         txd->flags = 0;
1791         txd->l3_offset = 0;
1792         txd->l4_offset = 0;
1793         txd->lso_hdrlen = 0;
1794         txd->mss = 0;
1795 }
1796
1797 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1798 static inline void
1799 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1800                  struct rte_mbuf *mb)
1801 {
1802         uint64_t ol_flags;
1803         struct nfp_net_hw *hw = txq->hw;
1804
1805         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1806                 return;
1807
1808         ol_flags = mb->ol_flags;
1809
1810         /* IPv6 does not need checksum */
1811         if (ol_flags & PKT_TX_IP_CKSUM)
1812                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1813
1814         switch (ol_flags & PKT_TX_L4_MASK) {
1815         case PKT_TX_UDP_CKSUM:
1816                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1817                 break;
1818         case PKT_TX_TCP_CKSUM:
1819                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1820                 break;
1821         }
1822
1823         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1824                 txd->flags |= PCIE_DESC_TX_CSUM;
1825 }
1826
1827 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1828 static inline void
1829 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1830                  struct rte_mbuf *mb)
1831 {
1832         struct nfp_net_hw *hw = rxq->hw;
1833
1834         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1835                 return;
1836
1837         /* If IPv4 and IP checksum error, fail */
1838         if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1839             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1840                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1841         else
1842                 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1843
1844         /* If neither UDP nor TCP return */
1845         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1846             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1847                 return;
1848
1849         if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1850                 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1851         else
1852                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1853 }
1854
1855 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1856 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1857
1858 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1859
1860 /*
1861  * nfp_net_set_hash - Set mbuf hash data
1862  *
1863  * The RSS hash and hash-type are pre-pended to the packet data.
1864  * Extract and decode it and set the mbuf fields.
1865  */
1866 static inline void
1867 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1868                  struct rte_mbuf *mbuf)
1869 {
1870         struct nfp_net_hw *hw = rxq->hw;
1871         uint8_t *meta_offset;
1872         uint32_t meta_info;
1873         uint32_t hash = 0;
1874         uint32_t hash_type = 0;
1875
1876         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1877                 return;
1878
1879         /* this is true for new firmwares */
1880         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1881             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1882              NFP_DESC_META_LEN(rxd))) {
1883                 /*
1884                  * new metadata api:
1885                  * <----  32 bit  ----->
1886                  * m    field type word
1887                  * e     data field #2
1888                  * t     data field #1
1889                  * a     data field #0
1890                  * ====================
1891                  *    packet data
1892                  *
1893                  * Field type word contains up to 8 4bit field types
1894                  * A 4bit field type refers to a data field word
1895                  * A data field word can have several 4bit field types
1896                  */
1897                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1898                 meta_offset -= NFP_DESC_META_LEN(rxd);
1899                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1900                 meta_offset += 4;
1901                 /* NFP PMD just supports metadata for hashing */
1902                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1903                 case NFP_NET_META_HASH:
1904                         /* next field type is about the hash type */
1905                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1906                         /* hash value is in the data field */
1907                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1908                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1909                         break;
1910                 default:
1911                         /* Unsupported metadata can be a performance issue */
1912                         return;
1913                 }
1914         } else {
1915                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1916                         return;
1917
1918                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1919                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1920         }
1921
1922         mbuf->hash.rss = hash;
1923         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1924
1925         switch (hash_type) {
1926         case NFP_NET_RSS_IPV4:
1927                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1928                 break;
1929         case NFP_NET_RSS_IPV6:
1930                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1931                 break;
1932         case NFP_NET_RSS_IPV6_EX:
1933                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1934                 break;
1935         case NFP_NET_RSS_IPV4_TCP:
1936                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1937                 break;
1938         case NFP_NET_RSS_IPV6_TCP:
1939                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1940                 break;
1941         case NFP_NET_RSS_IPV4_UDP:
1942                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1943                 break;
1944         case NFP_NET_RSS_IPV6_UDP:
1945                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1946                 break;
1947         default:
1948                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1949         }
1950 }
1951
1952 static inline void
1953 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1954 {
1955         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1956 }
1957
1958 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1959
1960 /*
1961  * RX path design:
1962  *
1963  * There are some decisions to take:
1964  * 1) How to check DD RX descriptors bit
1965  * 2) How and when to allocate new mbufs
1966  *
1967  * Current implementation checks just one single DD bit each loop. As each
1968  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1969  * a single cache line instead. Tests with this change have not shown any
1970  * performance improvement but it requires further investigation. For example,
1971  * depending on which descriptor is next, the number of descriptors could be
1972  * less than 8 for just checking those in the same cache line. This implies
1973  * extra work which could be counterproductive by itself. Indeed, last firmware
1974  * changes are just doing this: writing several descriptors with the DD bit
1975  * for saving PCIe bandwidth and DMA operations from the NFP.
1976  *
1977  * Mbuf allocation is done when a new packet is received. Then the descriptor
1978  * is automatically linked with the new mbuf and the old one is given to the
1979  * user. The main drawback with this design is mbuf allocation is heavier than
1980  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1981  * cache point of view it does not seem allocating the mbuf early on as we are
1982  * doing now have any benefit at all. Again, tests with this change have not
1983  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1984  * so looking at the implications of this type of allocation should be studied
1985  * deeply
1986  */
1987
1988 static uint16_t
1989 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1990 {
1991         struct nfp_net_rxq *rxq;
1992         struct nfp_net_rx_desc *rxds;
1993         struct nfp_net_rx_buff *rxb;
1994         struct nfp_net_hw *hw;
1995         struct rte_mbuf *mb;
1996         struct rte_mbuf *new_mb;
1997         uint16_t nb_hold;
1998         uint64_t dma_addr;
1999         int avail;
2000
2001         rxq = rx_queue;
2002         if (unlikely(rxq == NULL)) {
2003                 /*
2004                  * DPDK just checks the queue is lower than max queues
2005                  * enabled. But the queue needs to be configured
2006                  */
2007                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2008                 return -EINVAL;
2009         }
2010
2011         hw = rxq->hw;
2012         avail = 0;
2013         nb_hold = 0;
2014
2015         while (avail < nb_pkts) {
2016                 rxb = &rxq->rxbufs[rxq->rd_p];
2017                 if (unlikely(rxb == NULL)) {
2018                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2019                         break;
2020                 }
2021
2022                 rxds = &rxq->rxds[rxq->rd_p];
2023                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2024                         break;
2025
2026                 /*
2027                  * Memory barrier to ensure that we won't do other
2028                  * reads before the DD bit.
2029                  */
2030                 rte_rmb();
2031
2032                 /*
2033                  * We got a packet. Let's alloc a new mbuf for refilling the
2034                  * free descriptor ring as soon as possible
2035                  */
2036                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2037                 if (unlikely(new_mb == NULL)) {
2038                         RTE_LOG_DP(DEBUG, PMD,
2039                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2040                                 rxq->port_id, (unsigned int)rxq->qidx);
2041                         nfp_net_mbuf_alloc_failed(rxq);
2042                         break;
2043                 }
2044
2045                 nb_hold++;
2046
2047                 /*
2048                  * Grab the mbuf and refill the descriptor with the
2049                  * previously allocated mbuf
2050                  */
2051                 mb = rxb->mbuf;
2052                 rxb->mbuf = new_mb;
2053
2054                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2055                            rxds->rxd.data_len, rxq->mbuf_size);
2056
2057                 /* Size of this segment */
2058                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2059                 /* Size of the whole packet. We just support 1 segment */
2060                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2061
2062                 if (unlikely((mb->data_len + hw->rx_offset) >
2063                              rxq->mbuf_size)) {
2064                         /*
2065                          * This should not happen and the user has the
2066                          * responsibility of avoiding it. But we have
2067                          * to give some info about the error
2068                          */
2069                         RTE_LOG_DP(ERR, PMD,
2070                                 "mbuf overflow likely due to the RX offset.\n"
2071                                 "\t\tYour mbuf size should have extra space for"
2072                                 " RX offset=%u bytes.\n"
2073                                 "\t\tCurrently you just have %u bytes available"
2074                                 " but the received packet is %u bytes long",
2075                                 hw->rx_offset,
2076                                 rxq->mbuf_size - hw->rx_offset,
2077                                 mb->data_len);
2078                         return -EINVAL;
2079                 }
2080
2081                 /* Filling the received mbuf with packet info */
2082                 if (hw->rx_offset)
2083                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2084                 else
2085                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2086                                        NFP_DESC_META_LEN(rxds);
2087
2088                 /* No scatter mode supported */
2089                 mb->nb_segs = 1;
2090                 mb->next = NULL;
2091
2092                 mb->port = rxq->port_id;
2093
2094                 /* Checking the RSS flag */
2095                 nfp_net_set_hash(rxq, rxds, mb);
2096
2097                 /* Checking the checksum flag */
2098                 nfp_net_rx_cksum(rxq, rxds, mb);
2099
2100                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2101                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2102                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2103                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2104                 }
2105
2106                 /* Adding the mbuf to the mbuf array passed by the app */
2107                 rx_pkts[avail++] = mb;
2108
2109                 /* Now resetting and updating the descriptor */
2110                 rxds->vals[0] = 0;
2111                 rxds->vals[1] = 0;
2112                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2113                 rxds->fld.dd = 0;
2114                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2115                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2116
2117                 rxq->rd_p++;
2118                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2119                         rxq->rd_p = 0;
2120         }
2121
2122         if (nb_hold == 0)
2123                 return nb_hold;
2124
2125         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2126                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2127
2128         nb_hold += rxq->nb_rx_hold;
2129
2130         /*
2131          * FL descriptors needs to be written before incrementing the
2132          * FL queue WR pointer
2133          */
2134         rte_wmb();
2135         if (nb_hold > rxq->rx_free_thresh) {
2136                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2137                            rxq->port_id, (unsigned int)rxq->qidx,
2138                            (unsigned)nb_hold, (unsigned)avail);
2139                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2140                 nb_hold = 0;
2141         }
2142         rxq->nb_rx_hold = nb_hold;
2143
2144         return avail;
2145 }
2146
2147 /*
2148  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2149  * status
2150  * @txq: TX queue to work with
2151  * Returns number of descriptors freed
2152  */
2153 int
2154 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2155 {
2156         uint32_t qcp_rd_p;
2157         int todo;
2158
2159         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2160                    " status", txq->qidx);
2161
2162         /* Work out how many packets have been sent */
2163         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2164
2165         if (qcp_rd_p == txq->rd_p) {
2166                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2167                            "packets (%u, %u)", txq->qidx,
2168                            qcp_rd_p, txq->rd_p);
2169                 return 0;
2170         }
2171
2172         if (qcp_rd_p > txq->rd_p)
2173                 todo = qcp_rd_p - txq->rd_p;
2174         else
2175                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2176
2177         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2178                    qcp_rd_p, txq->rd_p, txq->rd_p);
2179
2180         if (todo == 0)
2181                 return todo;
2182
2183         txq->rd_p += todo;
2184         if (unlikely(txq->rd_p >= txq->tx_count))
2185                 txq->rd_p -= txq->tx_count;
2186
2187         return todo;
2188 }
2189
2190 /* Leaving always free descriptors for avoiding wrapping confusion */
2191 static inline
2192 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2193 {
2194         if (txq->wr_p >= txq->rd_p)
2195                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2196         else
2197                 return txq->rd_p - txq->wr_p - 8;
2198 }
2199
2200 /*
2201  * nfp_net_txq_full - Check if the TX queue free descriptors
2202  * is below tx_free_threshold
2203  *
2204  * @txq: TX queue to check
2205  *
2206  * This function uses the host copy* of read/write pointers
2207  */
2208 static inline
2209 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2210 {
2211         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2212 }
2213
2214 static uint16_t
2215 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2216 {
2217         struct nfp_net_txq *txq;
2218         struct nfp_net_hw *hw;
2219         struct nfp_net_tx_desc *txds, txd;
2220         struct rte_mbuf *pkt;
2221         uint64_t dma_addr;
2222         int pkt_size, dma_size;
2223         uint16_t free_descs, issued_descs;
2224         struct rte_mbuf **lmbuf;
2225         int i;
2226
2227         txq = tx_queue;
2228         hw = txq->hw;
2229         txds = &txq->txds[txq->wr_p];
2230
2231         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2232                    txq->qidx, txq->wr_p, nb_pkts);
2233
2234         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2235                 nfp_net_tx_free_bufs(txq);
2236
2237         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2238         if (unlikely(free_descs == 0))
2239                 return 0;
2240
2241         pkt = *tx_pkts;
2242
2243         i = 0;
2244         issued_descs = 0;
2245         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2246                    txq->qidx, nb_pkts);
2247         /* Sending packets */
2248         while ((i < nb_pkts) && free_descs) {
2249                 /* Grabbing the mbuf linked to the current descriptor */
2250                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2251                 /* Warming the cache for releasing the mbuf later on */
2252                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2253
2254                 pkt = *(tx_pkts + i);
2255
2256                 if (unlikely((pkt->nb_segs > 1) &&
2257                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2258                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2259                         rte_panic("Multisegment packet unsupported\n");
2260                 }
2261
2262                 /* Checking if we have enough descriptors */
2263                 if (unlikely(pkt->nb_segs > free_descs))
2264                         goto xmit_end;
2265
2266                 /*
2267                  * Checksum and VLAN flags just in the first descriptor for a
2268                  * multisegment packet, but TSO info needs to be in all of them.
2269                  */
2270                 txd.data_len = pkt->pkt_len;
2271                 nfp_net_tx_tso(txq, &txd, pkt);
2272                 nfp_net_tx_cksum(txq, &txd, pkt);
2273
2274                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2275                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2276                         txd.flags |= PCIE_DESC_TX_VLAN;
2277                         txd.vlan = pkt->vlan_tci;
2278                 }
2279
2280                 /*
2281                  * mbuf data_len is the data in one segment and pkt_len data
2282                  * in the whole packet. When the packet is just one segment,
2283                  * then data_len = pkt_len
2284                  */
2285                 pkt_size = pkt->pkt_len;
2286
2287                 while (pkt) {
2288                         /* Copying TSO, VLAN and cksum info */
2289                         *txds = txd;
2290
2291                         /* Releasing mbuf used by this descriptor previously*/
2292                         if (*lmbuf)
2293                                 rte_pktmbuf_free_seg(*lmbuf);
2294
2295                         /*
2296                          * Linking mbuf with descriptor for being released
2297                          * next time descriptor is used
2298                          */
2299                         *lmbuf = pkt;
2300
2301                         dma_size = pkt->data_len;
2302                         dma_addr = rte_mbuf_data_iova(pkt);
2303                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2304                                    "%" PRIx64 "", dma_addr);
2305
2306                         /* Filling descriptors fields */
2307                         txds->dma_len = dma_size;
2308                         txds->data_len = txd.data_len;
2309                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2310                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2311                         ASSERT(free_descs > 0);
2312                         free_descs--;
2313
2314                         txq->wr_p++;
2315                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2316                                 txq->wr_p = 0;
2317
2318                         pkt_size -= dma_size;
2319
2320                         /*
2321                          * Making the EOP, packets with just one segment
2322                          * the priority
2323                          */
2324                         if (likely(!pkt_size))
2325                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2326                         else
2327                                 txds->offset_eop = 0;
2328
2329                         pkt = pkt->next;
2330                         /* Referencing next free TX descriptor */
2331                         txds = &txq->txds[txq->wr_p];
2332                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2333                         issued_descs++;
2334                 }
2335                 i++;
2336         }
2337
2338 xmit_end:
2339         /* Increment write pointers. Force memory write before we let HW know */
2340         rte_wmb();
2341         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2342
2343         return i;
2344 }
2345
2346 static int
2347 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2348 {
2349         uint32_t new_ctrl, update;
2350         struct nfp_net_hw *hw;
2351         int ret;
2352
2353         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         new_ctrl = 0;
2355
2356         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2357             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2358                 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2359                         " ETH_VLAN_EXTEND_OFFLOAD");
2360
2361         /* Enable vlan strip if it is not configured yet */
2362         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2363             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2364                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2365
2366         /* Disable vlan strip just if it is configured */
2367         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2368             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2369                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2370
2371         if (new_ctrl == 0)
2372                 return 0;
2373
2374         update = NFP_NET_CFG_UPDATE_GEN;
2375
2376         ret = nfp_net_reconfig(hw, new_ctrl, update);
2377         if (!ret)
2378                 hw->ctrl = new_ctrl;
2379
2380         return ret;
2381 }
2382
2383 static int
2384 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2385                     struct rte_eth_rss_reta_entry64 *reta_conf,
2386                     uint16_t reta_size)
2387 {
2388         uint32_t reta, mask;
2389         int i, j;
2390         int idx, shift;
2391         struct nfp_net_hw *hw =
2392                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393
2394         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2395                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2396                         "(%d) doesn't match the number hardware can supported "
2397                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2398                 return -EINVAL;
2399         }
2400
2401         /*
2402          * Update Redirection Table. There are 128 8bit-entries which can be
2403          * manage as 32 32bit-entries
2404          */
2405         for (i = 0; i < reta_size; i += 4) {
2406                 /* Handling 4 RSS entries per loop */
2407                 idx = i / RTE_RETA_GROUP_SIZE;
2408                 shift = i % RTE_RETA_GROUP_SIZE;
2409                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2410
2411                 if (!mask)
2412                         continue;
2413
2414                 reta = 0;
2415                 /* If all 4 entries were set, don't need read RETA register */
2416                 if (mask != 0xF)
2417                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2418
2419                 for (j = 0; j < 4; j++) {
2420                         if (!(mask & (0x1 << j)))
2421                                 continue;
2422                         if (mask != 0xF)
2423                                 /* Clearing the entry bits */
2424                                 reta &= ~(0xFF << (8 * j));
2425                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2426                 }
2427                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2428                               reta);
2429         }
2430         return 0;
2431 }
2432
2433 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2434 static int
2435 nfp_net_reta_update(struct rte_eth_dev *dev,
2436                     struct rte_eth_rss_reta_entry64 *reta_conf,
2437                     uint16_t reta_size)
2438 {
2439         struct nfp_net_hw *hw =
2440                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441         uint32_t update;
2442         int ret;
2443
2444         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2445                 return -EINVAL;
2446
2447         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2448         if (ret != 0)
2449                 return ret;
2450
2451         update = NFP_NET_CFG_UPDATE_RSS;
2452
2453         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2454                 return -EIO;
2455
2456         return 0;
2457 }
2458
2459  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2460 static int
2461 nfp_net_reta_query(struct rte_eth_dev *dev,
2462                    struct rte_eth_rss_reta_entry64 *reta_conf,
2463                    uint16_t reta_size)
2464 {
2465         uint8_t i, j, mask;
2466         int idx, shift;
2467         uint32_t reta;
2468         struct nfp_net_hw *hw;
2469
2470         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471
2472         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2473                 return -EINVAL;
2474
2475         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2476                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2477                         "(%d) doesn't match the number hardware can supported "
2478                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2479                 return -EINVAL;
2480         }
2481
2482         /*
2483          * Reading Redirection Table. There are 128 8bit-entries which can be
2484          * manage as 32 32bit-entries
2485          */
2486         for (i = 0; i < reta_size; i += 4) {
2487                 /* Handling 4 RSS entries per loop */
2488                 idx = i / RTE_RETA_GROUP_SIZE;
2489                 shift = i % RTE_RETA_GROUP_SIZE;
2490                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2491
2492                 if (!mask)
2493                         continue;
2494
2495                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2496                                     shift);
2497                 for (j = 0; j < 4; j++) {
2498                         if (!(mask & (0x1 << j)))
2499                                 continue;
2500                         reta_conf[idx].reta[shift + j] =
2501                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2502                 }
2503         }
2504         return 0;
2505 }
2506
2507 static int
2508 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2509                         struct rte_eth_rss_conf *rss_conf)
2510 {
2511         struct nfp_net_hw *hw;
2512         uint64_t rss_hf;
2513         uint32_t cfg_rss_ctrl = 0;
2514         uint8_t key;
2515         int i;
2516
2517         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518
2519         /* Writing the key byte a byte */
2520         for (i = 0; i < rss_conf->rss_key_len; i++) {
2521                 memcpy(&key, &rss_conf->rss_key[i], 1);
2522                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2523         }
2524
2525         rss_hf = rss_conf->rss_hf;
2526
2527         if (rss_hf & ETH_RSS_IPV4)
2528                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2529
2530         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2531                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2532
2533         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2534                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2535
2536         if (rss_hf & ETH_RSS_IPV6)
2537                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2538
2539         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2540                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2541
2542         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2543                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2544
2545         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2546         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2547
2548         /* configuring where to apply the RSS hash */
2549         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2550
2551         /* Writing the key size */
2552         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2553
2554         return 0;
2555 }
2556
2557 static int
2558 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2559                         struct rte_eth_rss_conf *rss_conf)
2560 {
2561         uint32_t update;
2562         uint64_t rss_hf;
2563         struct nfp_net_hw *hw;
2564
2565         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2566
2567         rss_hf = rss_conf->rss_hf;
2568
2569         /* Checking if RSS is enabled */
2570         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2571                 if (rss_hf != 0) { /* Enable RSS? */
2572                         PMD_DRV_LOG(ERR, "RSS unsupported");
2573                         return -EINVAL;
2574                 }
2575                 return 0; /* Nothing to do */
2576         }
2577
2578         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2579                 PMD_DRV_LOG(ERR, "hash key too long");
2580                 return -EINVAL;
2581         }
2582
2583         nfp_net_rss_hash_write(dev, rss_conf);
2584
2585         update = NFP_NET_CFG_UPDATE_RSS;
2586
2587         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2588                 return -EIO;
2589
2590         return 0;
2591 }
2592
2593 static int
2594 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2595                           struct rte_eth_rss_conf *rss_conf)
2596 {
2597         uint64_t rss_hf;
2598         uint32_t cfg_rss_ctrl;
2599         uint8_t key;
2600         int i;
2601         struct nfp_net_hw *hw;
2602
2603         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2604
2605         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2606                 return -EINVAL;
2607
2608         rss_hf = rss_conf->rss_hf;
2609         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2610
2611         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2612                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2613
2614         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2615                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2616
2617         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2618                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2619
2620         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2621                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2622
2623         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2624                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2625
2626         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2627                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2628
2629         /* Reading the key size */
2630         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2631
2632         /* Reading the key byte a byte */
2633         for (i = 0; i < rss_conf->rss_key_len; i++) {
2634                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2635                 memcpy(&rss_conf->rss_key[i], &key, 1);
2636         }
2637
2638         return 0;
2639 }
2640
2641 static int
2642 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2643 {
2644         struct rte_eth_conf *dev_conf;
2645         struct rte_eth_rss_conf rss_conf;
2646         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2647         uint16_t rx_queues = dev->data->nb_rx_queues;
2648         uint16_t queue;
2649         int i, j, ret;
2650
2651         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2652                 rx_queues);
2653
2654         nfp_reta_conf[0].mask = ~0x0;
2655         nfp_reta_conf[1].mask = ~0x0;
2656
2657         queue = 0;
2658         for (i = 0; i < 0x40; i += 8) {
2659                 for (j = i; j < (i + 8); j++) {
2660                         nfp_reta_conf[0].reta[j] = queue;
2661                         nfp_reta_conf[1].reta[j] = queue++;
2662                         queue %= rx_queues;
2663                 }
2664         }
2665         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2666         if (ret != 0)
2667                 return ret;
2668
2669         dev_conf = &dev->data->dev_conf;
2670         if (!dev_conf) {
2671                 PMD_DRV_LOG(INFO, "wrong rss conf");
2672                 return -EINVAL;
2673         }
2674         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2675
2676         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2677
2678         return ret;
2679 }
2680
2681
2682 /* Initialise and register driver with DPDK Application */
2683 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2684         .dev_configure          = nfp_net_configure,
2685         .dev_start              = nfp_net_start,
2686         .dev_stop               = nfp_net_stop,
2687         .dev_set_link_up        = nfp_net_set_link_up,
2688         .dev_set_link_down      = nfp_net_set_link_down,
2689         .dev_close              = nfp_net_close,
2690         .promiscuous_enable     = nfp_net_promisc_enable,
2691         .promiscuous_disable    = nfp_net_promisc_disable,
2692         .link_update            = nfp_net_link_update,
2693         .stats_get              = nfp_net_stats_get,
2694         .stats_reset            = nfp_net_stats_reset,
2695         .dev_infos_get          = nfp_net_infos_get,
2696         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2697         .mtu_set                = nfp_net_dev_mtu_set,
2698         .mac_addr_set           = nfp_set_mac_addr,
2699         .vlan_offload_set       = nfp_net_vlan_offload_set,
2700         .reta_update            = nfp_net_reta_update,
2701         .reta_query             = nfp_net_reta_query,
2702         .rss_hash_update        = nfp_net_rss_hash_update,
2703         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2704         .rx_queue_setup         = nfp_net_rx_queue_setup,
2705         .rx_queue_release       = nfp_net_rx_queue_release,
2706         .rx_queue_count         = nfp_net_rx_queue_count,
2707         .tx_queue_setup         = nfp_net_tx_queue_setup,
2708         .tx_queue_release       = nfp_net_tx_queue_release,
2709         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2710         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2711 };
2712
2713 /*
2714  * All eth_dev created got its private data, but before nfp_net_init, that
2715  * private data is referencing private data for all the PF ports. This is due
2716  * to how the vNIC bars are mapped based on first port, so all ports need info
2717  * about port 0 private data. Inside nfp_net_init the private data pointer is
2718  * changed to the right address for each port once the bars have been mapped.
2719  *
2720  * This functions helps to find out which port and therefore which offset
2721  * inside the private data array to use.
2722  */
2723 static int
2724 get_pf_port_number(char *name)
2725 {
2726         char *pf_str = name;
2727         int size = 0;
2728
2729         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2730                 pf_str++;
2731
2732         if (size == 30)
2733                 /*
2734                  * This should not happen at all and it would mean major
2735                  * implementation fault.
2736                  */
2737                 rte_panic("nfp_net: problem with pf device name\n");
2738
2739         /* Expecting _portX with X within [0,7] */
2740         pf_str += 5;
2741
2742         return (int)strtol(pf_str, NULL, 10);
2743 }
2744
2745 static int
2746 nfp_net_init(struct rte_eth_dev *eth_dev)
2747 {
2748         struct rte_pci_device *pci_dev;
2749         struct nfp_net_hw *hw, *hwport0;
2750
2751         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2752         uint32_t start_q;
2753         int stride = 4;
2754         int port = 0;
2755         int err;
2756
2757         PMD_INIT_FUNC_TRACE();
2758
2759         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2760
2761         /* NFP can not handle DMA addresses requiring more than 40 bits */
2762         if (rte_mem_check_dma_mask(40)) {
2763                 RTE_LOG(ERR, PMD, "device %s can not be used:",
2764                                    pci_dev->device.name);
2765                 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2766                 return -ENODEV;
2767         };
2768
2769         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2770             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2771                 port = get_pf_port_number(eth_dev->data->name);
2772                 if (port < 0 || port > 7) {
2773                         PMD_DRV_LOG(ERR, "Port value is wrong");
2774                         return -ENODEV;
2775                 }
2776
2777                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2778
2779                 /* This points to port 0 private data */
2780                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2781
2782                 /* This points to the specific port private data */
2783                 hw = &hwport0[port];
2784         } else {
2785                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2786                 hwport0 = 0;
2787         }
2788
2789         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2790         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2791         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2792
2793         /* For secondary processes, the primary has done all the work */
2794         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2795                 return 0;
2796
2797         rte_eth_copy_pci_info(eth_dev, pci_dev);
2798
2799         hw->device_id = pci_dev->id.device_id;
2800         hw->vendor_id = pci_dev->id.vendor_id;
2801         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2802         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2803
2804         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2805                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2806                      pci_dev->addr.domain, pci_dev->addr.bus,
2807                      pci_dev->addr.devid, pci_dev->addr.function);
2808
2809         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2810         if (hw->ctrl_bar == NULL) {
2811                 PMD_DRV_LOG(ERR,
2812                         "hw->ctrl_bar is NULL. BAR0 not configured");
2813                 return -ENODEV;
2814         }
2815
2816         if (hw->is_pf && port == 0) {
2817                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2818                                              hw->total_ports * 32768,
2819                                              &hw->ctrl_area);
2820                 if (!hw->ctrl_bar) {
2821                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2822                         return -EIO;
2823                 }
2824
2825                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2826         }
2827
2828         if (port > 0) {
2829                 if (!hwport0->ctrl_bar)
2830                         return -ENODEV;
2831
2832                 /* address based on port0 offset */
2833                 hw->ctrl_bar = hwport0->ctrl_bar +
2834                                (port * NFP_PF_CSR_SLICE_SIZE);
2835         }
2836
2837         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2838
2839         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2840         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2841
2842         /* Work out where in the BAR the queues start. */
2843         switch (pci_dev->id.device_id) {
2844         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2845         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2846         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2847                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2848                 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2849                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2850                 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2851                 break;
2852         default:
2853                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2854                 err = -ENODEV;
2855                 goto dev_err_ctrl_map;
2856         }
2857
2858         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2859         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2860
2861         if (hw->is_pf && port == 0) {
2862                 /* configure access to tx/rx vNIC BARs */
2863                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2864                                                       NFP_PCIE_QUEUE(0),
2865                                                       NFP_QCP_QUEUE_AREA_SZ,
2866                                                       &hw->hwqueues_area);
2867
2868                 if (!hwport0->hw_queues) {
2869                         printf("nfp_rtsym_map fails for net.qc");
2870                         err = -EIO;
2871                         goto dev_err_ctrl_map;
2872                 }
2873
2874                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2875                                     hwport0->hw_queues);
2876         }
2877
2878         if (hw->is_pf) {
2879                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2880                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2881                 eth_dev->data->dev_private = hw;
2882         } else {
2883                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2884                              tx_bar_off;
2885                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2886                              rx_bar_off;
2887         }
2888
2889         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2890                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2891
2892         nfp_net_cfg_queue_setup(hw);
2893
2894         /* Get some of the read-only fields from the config BAR */
2895         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2896         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2897         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2898         hw->mtu = RTE_ETHER_MTU;
2899
2900         /* VLAN insertion is incompatible with LSOv2 */
2901         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2902                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2903
2904         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2905                 hw->rx_offset = NFP_NET_RX_OFFSET;
2906         else
2907                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2908
2909         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2910                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2911                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2912
2913         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2914                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2915                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2916                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2917                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2918                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2919                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2920                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2921                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2922                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2923                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2924                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2925                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2926                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2927                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2928
2929         hw->ctrl = 0;
2930
2931         hw->stride_rx = stride;
2932         hw->stride_tx = stride;
2933
2934         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2935                      hw->max_rx_queues, hw->max_tx_queues);
2936
2937         /* Initializing spinlock for reconfigs */
2938         rte_spinlock_init(&hw->reconfig_lock);
2939
2940         /* Allocating memory for mac addr */
2941         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2942                                                RTE_ETHER_ADDR_LEN, 0);
2943         if (eth_dev->data->mac_addrs == NULL) {
2944                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2945                 err = -ENOMEM;
2946                 goto dev_err_queues_map;
2947         }
2948
2949         if (hw->is_pf) {
2950                 nfp_net_pf_read_mac(hwport0, port);
2951                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2952         } else {
2953                 nfp_net_vf_read_mac(hw);
2954         }
2955
2956         if (!rte_is_valid_assigned_ether_addr(
2957                     (struct rte_ether_addr *)&hw->mac_addr)) {
2958                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2959                                    port);
2960                 /* Using random mac addresses for VFs */
2961                 rte_eth_random_addr(&hw->mac_addr[0]);
2962                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2963         }
2964
2965         /* Copying mac address to DPDK eth_dev struct */
2966         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2967                         &eth_dev->data->mac_addrs[0]);
2968
2969         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2970                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2971
2972         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2973                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2974                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2975                      pci_dev->id.device_id,
2976                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2977                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2978
2979         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2980                 /* Registering LSC interrupt handler */
2981                 rte_intr_callback_register(&pci_dev->intr_handle,
2982                                            nfp_net_dev_interrupt_handler,
2983                                            (void *)eth_dev);
2984                 /* Telling the firmware about the LSC interrupt entry */
2985                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2986                 /* Recording current stats counters values */
2987                 nfp_net_stats_reset(eth_dev);
2988         }
2989
2990         return 0;
2991
2992 dev_err_queues_map:
2993                 nfp_cpp_area_free(hw->hwqueues_area);
2994 dev_err_ctrl_map:
2995                 nfp_cpp_area_free(hw->ctrl_area);
2996
2997         return err;
2998 }
2999
3000 #define NFP_CPP_MEMIO_BOUNDARY          (1 << 20)
3001
3002 /*
3003  * Serving a write request to NFP from host programs. The request
3004  * sends the write size and the CPP target. The bridge makes use
3005  * of CPP interface handler configured by the PMD setup.
3006  */
3007 static int
3008 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3009 {
3010         struct nfp_cpp_area *area;
3011         off_t offset, nfp_offset;
3012         uint32_t cpp_id, pos, len;
3013         uint32_t tmpbuf[16];
3014         size_t count, curlen, totlen = 0;
3015         int err = 0;
3016
3017         PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3018                 sizeof(off_t), sizeof(size_t));
3019
3020         /* Reading the count param */
3021         err = recv(sockfd, &count, sizeof(off_t), 0);
3022         if (err != sizeof(off_t))
3023                 return -EINVAL;
3024
3025         curlen = count;
3026
3027         /* Reading the offset param */
3028         err = recv(sockfd, &offset, sizeof(off_t), 0);
3029         if (err != sizeof(off_t))
3030                 return -EINVAL;
3031
3032         /* Obtain target's CPP ID and offset in target */
3033         cpp_id = (offset >> 40) << 8;
3034         nfp_offset = offset & ((1ull << 40) - 1);
3035
3036         PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3037                 offset);
3038         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3039                 cpp_id, nfp_offset);
3040
3041         /* Adjust length if not aligned */
3042         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3043             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3044                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3045                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3046         }
3047
3048         while (count > 0) {
3049                 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3050                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3051                                                     nfp_offset, curlen);
3052                 if (!area) {
3053                         RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3054                         return -EIO;
3055                 }
3056
3057                 /* mapping the target */
3058                 err = nfp_cpp_area_acquire(area);
3059                 if (err < 0) {
3060                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3061                         nfp_cpp_area_free(area);
3062                         return -EIO;
3063                 }
3064
3065                 for (pos = 0; pos < curlen; pos += len) {
3066                         len = curlen - pos;
3067                         if (len > sizeof(tmpbuf))
3068                                 len = sizeof(tmpbuf);
3069
3070                         PMD_CPP_LOG(DEBUG, "%s: Receive %u of %zu\n", __func__,
3071                                            len, count);
3072                         err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3073                         if (err != (int)len) {
3074                                 RTE_LOG(ERR, PMD,
3075                                         "%s: error when receiving, %d of %zu\n",
3076                                         __func__, err, count);
3077                                 nfp_cpp_area_release(area);
3078                                 nfp_cpp_area_free(area);
3079                                 return -EIO;
3080                         }
3081                         err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3082                         if (err < 0) {
3083                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3084                                 nfp_cpp_area_release(area);
3085                                 nfp_cpp_area_free(area);
3086                                 return -EIO;
3087                         }
3088                 }
3089
3090                 nfp_offset += pos;
3091                 totlen += pos;
3092                 nfp_cpp_area_release(area);
3093                 nfp_cpp_area_free(area);
3094
3095                 count -= pos;
3096                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3097                          NFP_CPP_MEMIO_BOUNDARY : count;
3098         }
3099
3100         return 0;
3101 }
3102
3103 /*
3104  * Serving a read request to NFP from host programs. The request
3105  * sends the read size and the CPP target. The bridge makes use
3106  * of CPP interface handler configured by the PMD setup. The read
3107  * data is sent to the requester using the same socket.
3108  */
3109 static int
3110 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3111 {
3112         struct nfp_cpp_area *area;
3113         off_t offset, nfp_offset;
3114         uint32_t cpp_id, pos, len;
3115         uint32_t tmpbuf[16];
3116         size_t count, curlen, totlen = 0;
3117         int err = 0;
3118
3119         PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3120                 sizeof(off_t), sizeof(size_t));
3121
3122         /* Reading the count param */
3123         err = recv(sockfd, &count, sizeof(off_t), 0);
3124         if (err != sizeof(off_t))
3125                 return -EINVAL;
3126
3127         curlen = count;
3128
3129         /* Reading the offset param */
3130         err = recv(sockfd, &offset, sizeof(off_t), 0);
3131         if (err != sizeof(off_t))
3132                 return -EINVAL;
3133
3134         /* Obtain target's CPP ID and offset in target */
3135         cpp_id = (offset >> 40) << 8;
3136         nfp_offset = offset & ((1ull << 40) - 1);
3137
3138         PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3139                            offset);
3140         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3141                            cpp_id, nfp_offset);
3142
3143         /* Adjust length if not aligned */
3144         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3145             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3146                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3147                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3148         }
3149
3150         while (count > 0) {
3151                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3152                                                     nfp_offset, curlen);
3153                 if (!area) {
3154                         RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3155                         return -EIO;
3156                 }
3157
3158                 err = nfp_cpp_area_acquire(area);
3159                 if (err < 0) {
3160                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3161                         nfp_cpp_area_free(area);
3162                         return -EIO;
3163                 }
3164
3165                 for (pos = 0; pos < curlen; pos += len) {
3166                         len = curlen - pos;
3167                         if (len > sizeof(tmpbuf))
3168                                 len = sizeof(tmpbuf);
3169
3170                         err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3171                         if (err < 0) {
3172                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3173                                 nfp_cpp_area_release(area);
3174                                 nfp_cpp_area_free(area);
3175                                 return -EIO;
3176                         }
3177                         PMD_CPP_LOG(DEBUG, "%s: sending %u of %zu\n", __func__,
3178                                            len, count);
3179
3180                         err = send(sockfd, tmpbuf, len, 0);
3181                         if (err != (int)len) {
3182                                 RTE_LOG(ERR, PMD,
3183                                         "%s: error when sending: %d of %zu\n",
3184                                         __func__, err, count);
3185                                 nfp_cpp_area_release(area);
3186                                 nfp_cpp_area_free(area);
3187                                 return -EIO;
3188                         }
3189                 }
3190
3191                 nfp_offset += pos;
3192                 totlen += pos;
3193                 nfp_cpp_area_release(area);
3194                 nfp_cpp_area_free(area);
3195
3196                 count -= pos;
3197                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3198                         NFP_CPP_MEMIO_BOUNDARY : count;
3199         }
3200         return 0;
3201 }
3202
3203 #define NFP_IOCTL 'n'
3204 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3205 /*
3206  * Serving a ioctl command from host NFP tools. This usually goes to
3207  * a kernel driver char driver but it is not available when the PF is
3208  * bound to the PMD. Currently just one ioctl command is served and it
3209  * does not require any CPP access at all.
3210  */
3211 static int
3212 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3213 {
3214         uint32_t cmd, ident_size, tmp;
3215         int err;
3216
3217         /* Reading now the IOCTL command */
3218         err = recv(sockfd, &cmd, 4, 0);
3219         if (err != 4) {
3220                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3221                 return -EIO;
3222         }
3223
3224         /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3225         if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3226                 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3227                 return -EINVAL;
3228         }
3229
3230         err = recv(sockfd, &ident_size, 4, 0);
3231         if (err != 4) {
3232                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3233                 return -EIO;
3234         }
3235
3236         tmp = nfp_cpp_model(cpp);
3237
3238         PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3239
3240         err = send(sockfd, &tmp, 4, 0);
3241         if (err != 4) {
3242                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3243                 return -EIO;
3244         }
3245
3246         tmp = cpp->interface;
3247
3248         PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3249
3250         err = send(sockfd, &tmp, 4, 0);
3251         if (err != 4) {
3252                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3253                 return -EIO;
3254         }
3255
3256         return 0;
3257 }
3258
3259 #define NFP_BRIDGE_OP_READ      20
3260 #define NFP_BRIDGE_OP_WRITE     30
3261 #define NFP_BRIDGE_OP_IOCTL     40
3262
3263 /*
3264  * This is the code to be executed by a service core. The CPP bridge interface
3265  * is based on a unix socket and requests usually received by a kernel char
3266  * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3267  * can be executed with a wrapper library and LD_LIBRARY being completely
3268  * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3269  * accesses.
3270  */
3271 static int32_t
3272 nfp_cpp_bridge_service_func(void *args)
3273 {
3274         struct sockaddr address;
3275         struct nfp_cpp *cpp = args;
3276         int sockfd, datafd, op, ret;
3277
3278         unlink("/tmp/nfp_cpp");
3279         sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3280         if (sockfd < 0) {
3281                 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3282                         __func__);
3283                 return -EIO;
3284         }
3285
3286         memset(&address, 0, sizeof(struct sockaddr));
3287
3288         address.sa_family = AF_UNIX;
3289         strcpy(address.sa_data, "/tmp/nfp_cpp");
3290
3291         ret = bind(sockfd, (const struct sockaddr *)&address,
3292                    sizeof(struct sockaddr));
3293         if (ret < 0) {
3294                 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3295                                   __func__, errno);
3296                 close(sockfd);
3297                 return ret;
3298         }
3299
3300         ret = listen(sockfd, 20);
3301         if (ret < 0) {
3302                 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3303                                   __func__, errno);
3304                 close(sockfd);
3305                 return ret;
3306         }
3307
3308         for (;;) {
3309                 datafd = accept(sockfd, NULL, NULL);
3310                 if (datafd < 0) {
3311                         RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3312                                           __func__, errno);
3313                         RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3314                         close(sockfd);
3315                         return -EIO;
3316                 }
3317
3318                 while (1) {
3319                         ret = recv(datafd, &op, 4, 0);
3320                         if (ret <= 0) {
3321                                 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3322                                                    __func__);
3323                                 break;
3324                         }
3325
3326                         PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3327
3328                         if (op == NFP_BRIDGE_OP_READ)
3329                                 nfp_cpp_bridge_serve_read(datafd, cpp);
3330
3331                         if (op == NFP_BRIDGE_OP_WRITE)
3332                                 nfp_cpp_bridge_serve_write(datafd, cpp);
3333
3334                         if (op == NFP_BRIDGE_OP_IOCTL)
3335                                 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3336
3337                         if (op == 0)
3338                                 break;
3339                 }
3340                 close(datafd);
3341         }
3342         close(sockfd);
3343
3344         return 0;
3345 }
3346
3347 static int
3348 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3349                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3350                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3351 {
3352         struct rte_eth_dev *eth_dev;
3353         struct nfp_net_hw *hw = NULL;
3354         char *port_name;
3355         struct rte_service_spec service;
3356         int retval;
3357
3358         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3359         if (!port_name)
3360                 return -ENOMEM;
3361
3362         if (ports > 1)
3363                 snprintf(port_name, 100, "%s_port%d", dev->device.name, port);
3364         else
3365                 strlcat(port_name, dev->device.name, 100);
3366
3367
3368         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3369                 eth_dev = rte_eth_dev_allocate(port_name);
3370                 if (!eth_dev) {
3371                         rte_free(port_name);
3372                         return -ENODEV;
3373                 }
3374                 if (port == 0) {
3375                         *priv = rte_zmalloc(port_name,
3376                                             sizeof(struct nfp_net_adapter) *
3377                                             ports, RTE_CACHE_LINE_SIZE);
3378                         if (!*priv) {
3379                                 rte_free(port_name);
3380                                 rte_eth_dev_release_port(eth_dev);
3381                                 return -ENOMEM;
3382                         }
3383                 }
3384                 eth_dev->data->dev_private = *priv;
3385
3386                 /*
3387                  * dev_private pointing to port0 dev_private because we need
3388                  * to configure vNIC bars based on port0 at nfp_net_init.
3389                  * Then dev_private is adjusted per port.
3390                  */
3391                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3392                 hw->cpp = cpp;
3393                 hw->hwinfo = hwinfo;
3394                 hw->sym_tbl = sym_tbl;
3395                 hw->pf_port_idx = phys_port;
3396                 hw->is_pf = 1;
3397                 if (ports > 1)
3398                         hw->pf_multiport_enabled = 1;
3399
3400                 hw->total_ports = ports;
3401         } else {
3402                 eth_dev = rte_eth_dev_attach_secondary(port_name);
3403                 if (!eth_dev) {
3404                         RTE_LOG(ERR, EAL, "secondary process attach failed, "
3405                                 "ethdev doesn't exist");
3406                         rte_free(port_name);
3407                         return -ENODEV;
3408                 }
3409                 eth_dev->process_private = cpp;
3410         }
3411
3412         eth_dev->device = &dev->device;
3413         rte_eth_copy_pci_info(eth_dev, dev);
3414
3415         retval = nfp_net_init(eth_dev);
3416
3417         if (retval) {
3418                 retval = -ENODEV;
3419                 goto probe_failed;
3420         } else {
3421                 rte_eth_dev_probing_finish(eth_dev);
3422         }
3423
3424         rte_free(port_name);
3425
3426         if (port == 0) {
3427                 /*
3428                  * The rte_service needs to be created just once per PMD.
3429                  * And the cpp handler needs to be linked to the service.
3430                  * Secondary processes will be used for debugging DPDK apps
3431                  * when requiring to use the CPP interface for accessing NFP
3432                  * components. And the cpp handler for secondary processes is
3433                  * available at this point.
3434                  */
3435                 memset(&service, 0, sizeof(struct rte_service_spec));
3436                 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3437                 service.callback = nfp_cpp_bridge_service_func;
3438                 service.callback_userdata = (void *)cpp;
3439
3440                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
3441
3442                 if (rte_service_component_register(&service,
3443                                                    &hw->nfp_cpp_service_id))
3444                         RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3445                 else
3446                         RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3447         }
3448
3449         return retval;
3450
3451 probe_failed:
3452         rte_free(port_name);
3453         /* free ports private data if primary process */
3454         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3455                 rte_free(eth_dev->data->dev_private);
3456                 eth_dev->data->dev_private = NULL;
3457         }
3458         rte_eth_dev_release_port(eth_dev);
3459
3460         return retval;
3461 }
3462
3463 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
3464
3465 static int
3466 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3467 {
3468         struct nfp_cpp *cpp = nsp->cpp;
3469         int fw_f;
3470         char *fw_buf;
3471         char fw_name[125];
3472         char serial[40];
3473         struct stat file_stat;
3474         off_t fsize, bytes;
3475
3476         /* Looking for firmware file in order of priority */
3477
3478         /* First try to find a firmware image specific for this device */
3479         snprintf(serial, sizeof(serial),
3480                         "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3481                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3482                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3483                 cpp->interface & 0xff);
3484
3485         snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3486                         serial);
3487
3488         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3489         fw_f = open(fw_name, O_RDONLY);
3490         if (fw_f >= 0)
3491                 goto read_fw;
3492
3493         /* Then try the PCI name */
3494         snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3495                         dev->device.name);
3496
3497         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3498         fw_f = open(fw_name, O_RDONLY);
3499         if (fw_f >= 0)
3500                 goto read_fw;
3501
3502         /* Finally try the card type and media */
3503         snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3504         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3505         fw_f = open(fw_name, O_RDONLY);
3506         if (fw_f < 0) {
3507                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3508                 return -ENOENT;
3509         }
3510
3511 read_fw:
3512         if (fstat(fw_f, &file_stat) < 0) {
3513                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3514                 close(fw_f);
3515                 return -ENOENT;
3516         }
3517
3518         fsize = file_stat.st_size;
3519         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3520                             fw_name, (uint64_t)fsize);
3521
3522         fw_buf = malloc((size_t)fsize);
3523         if (!fw_buf) {
3524                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3525                 close(fw_f);
3526                 return -ENOMEM;
3527         }
3528         memset(fw_buf, 0, fsize);
3529
3530         bytes = read(fw_f, fw_buf, fsize);
3531         if (bytes != fsize) {
3532                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3533                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3534                                    (uint64_t)bytes, (uint64_t)fsize);
3535                 free(fw_buf);
3536                 close(fw_f);
3537                 return -EIO;
3538         }
3539
3540         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3541         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3542         PMD_DRV_LOG(INFO, "Done");
3543
3544         free(fw_buf);
3545         close(fw_f);
3546
3547         return 0;
3548 }
3549
3550 static int
3551 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3552              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3553 {
3554         struct nfp_nsp *nsp;
3555         const char *nfp_fw_model;
3556         char card_desc[100];
3557         int err = 0;
3558
3559         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3560
3561         if (nfp_fw_model) {
3562                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3563         } else {
3564                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3565                 return -EIO;
3566         }
3567
3568         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3569                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3570                        nfp_eth_table->count);
3571                 return -EIO;
3572         }
3573
3574         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3575                            nfp_eth_table->count);
3576
3577         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3578
3579         snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3580                         nfp_fw_model, nfp_eth_table->count,
3581                         nfp_eth_table->ports[0].speed / 1000);
3582
3583         nsp = nfp_nsp_open(cpp);
3584         if (!nsp) {
3585                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3586                 return -EIO;
3587         }
3588
3589         nfp_nsp_device_soft_reset(nsp);
3590         err = nfp_fw_upload(dev, nsp, card_desc);
3591
3592         nfp_nsp_close(nsp);
3593         return err;
3594 }
3595
3596 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3597                             struct rte_pci_device *dev)
3598 {
3599         struct nfp_cpp *cpp;
3600         struct nfp_hwinfo *hwinfo;
3601         struct nfp_rtsym_table *sym_tbl;
3602         struct nfp_eth_table *nfp_eth_table = NULL;
3603         int total_ports;
3604         void *priv = 0;
3605         int ret = -ENODEV;
3606         int err;
3607         int i;
3608
3609         if (!dev)
3610                 return ret;
3611
3612         /*
3613          * When device bound to UIO, the device could be used, by mistake,
3614          * by two DPDK apps, and the UIO driver does not avoid it. This
3615          * could lead to a serious problem when configuring the NFP CPP
3616          * interface. Here we avoid this telling to the CPP init code to
3617          * use a lock file if UIO is being used.
3618          */
3619         if (dev->kdrv == RTE_KDRV_VFIO)
3620                 cpp = nfp_cpp_from_device_name(dev, 0);
3621         else
3622                 cpp = nfp_cpp_from_device_name(dev, 1);
3623
3624         if (!cpp) {
3625                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3626                 ret = -EIO;
3627                 goto error;
3628         }
3629
3630         hwinfo = nfp_hwinfo_read(cpp);
3631         if (!hwinfo) {
3632                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3633                 return -EIO;
3634         }
3635
3636         nfp_eth_table = nfp_eth_read_ports(cpp);
3637         if (!nfp_eth_table) {
3638                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3639                 return -EIO;
3640         }
3641
3642         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3643                 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3644                         PMD_DRV_LOG(INFO, "Error when uploading firmware");
3645                         ret = -EIO;
3646                         goto error;
3647                 }
3648         }
3649
3650         /* Now the symbol table should be there */
3651         sym_tbl = nfp_rtsym_table_read(cpp);
3652         if (!sym_tbl) {
3653                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3654                                 " symbol table");
3655                 ret = -EIO;
3656                 goto error;
3657         }
3658
3659         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3660         if (total_ports != (int)nfp_eth_table->count) {
3661                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3662                 ret = -EIO;
3663                 goto error;
3664         }
3665         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3666
3667         if (total_ports <= 0 || total_ports > 8) {
3668                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3669                 ret = -ENODEV;
3670                 goto error;
3671         }
3672
3673         for (i = 0; i < total_ports; i++) {
3674                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3675                                         nfp_eth_table->ports[i].index,
3676                                         sym_tbl, &priv);
3677                 if (ret)
3678                         break;
3679         }
3680
3681 error:
3682         free(nfp_eth_table);
3683         return ret;
3684 }
3685
3686 int nfp_logtype_init;
3687 int nfp_logtype_driver;
3688
3689 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3690         {
3691                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3692                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3693         },
3694         {
3695                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3696                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3697         },
3698         {
3699                 .vendor_id = 0,
3700         },
3701 };
3702
3703 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3704         {
3705                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3706                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3707         },
3708         {
3709                 .vendor_id = 0,
3710         },
3711 };
3712
3713 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3714         struct rte_pci_device *pci_dev)
3715 {
3716         return rte_eth_dev_pci_generic_probe(pci_dev,
3717                 sizeof(struct nfp_net_adapter), nfp_net_init);
3718 }
3719
3720 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3721 {
3722         struct rte_eth_dev *eth_dev;
3723         struct nfp_net_hw *hw, *hwport0;
3724         int port = 0;
3725
3726         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3727         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3728             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3729                 port = get_pf_port_number(eth_dev->data->name);
3730                 /*
3731                  * hotplug is not possible with multiport PF although freeing
3732                  * data structures can be done for first port.
3733                  */
3734                 if (port != 0)
3735                         return -ENOTSUP;
3736                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3737                 hw = &hwport0[port];
3738                 nfp_cpp_area_free(hw->ctrl_area);
3739                 nfp_cpp_area_free(hw->hwqueues_area);
3740                 free(hw->hwinfo);
3741                 free(hw->sym_tbl);
3742                 nfp_cpp_free(hw->cpp);
3743         } else {
3744                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3745         }
3746         /* hotplug is not possible with multiport PF */
3747         if (hw->pf_multiport_enabled)
3748                 return -ENOTSUP;
3749         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3750 }
3751
3752 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3753         .id_table = pci_id_nfp_pf_net_map,
3754         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3755         .probe = nfp_pf_pci_probe,
3756         .remove = eth_nfp_pci_remove,
3757 };
3758
3759 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3760         .id_table = pci_id_nfp_vf_net_map,
3761         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3762         .probe = eth_nfp_pci_probe,
3763         .remove = eth_nfp_pci_remove,
3764 };
3765
3766 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3767 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3768 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3769 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3770 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3771 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3772
3773 RTE_INIT(nfp_init_log)
3774 {
3775         nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3776         if (nfp_logtype_init >= 0)
3777                 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3778         nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3779         if (nfp_logtype_driver >= 0)
3780                 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3781 }
3782 /*
3783  * Local variables:
3784  * c-file-style: "Linux"
3785  * indent-tabs-mode: t
3786  * End:
3787  */