1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
9 * vim:shiftwidth=8:noexpandtab
11 * @file dpdk/pmd/nfp_net.c
13 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
19 #include <rte_debug.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
23 #include <rte_ether.h>
24 #include <rte_malloc.h>
25 #include <rte_memzone.h>
26 #include <rte_mempool.h>
27 #include <rte_version.h>
28 #include <rte_string_fns.h>
29 #include <rte_alarm.h>
30 #include <rte_spinlock.h>
31 #include <rte_service_component.h>
33 #include "nfpcore/nfp_cpp.h"
34 #include "nfpcore/nfp_nffw.h"
35 #include "nfpcore/nfp_hwinfo.h"
36 #include "nfpcore/nfp_mip.h"
37 #include "nfpcore/nfp_rtsym.h"
38 #include "nfpcore/nfp_nsp.h"
40 #include "nfp_net_pmd.h"
41 #include "nfp_net_logs.h"
42 #include "nfp_net_ctrl.h"
44 #include <sys/types.h>
45 #include <sys/socket.h>
49 #include <sys/ioctl.h>
53 static int nfp_net_close(struct rte_eth_dev *dev);
54 static int nfp_net_configure(struct rte_eth_dev *dev);
55 static void nfp_net_dev_interrupt_handler(void *param);
56 static void nfp_net_dev_interrupt_delayed_handler(void *param);
57 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
58 static int nfp_net_infos_get(struct rte_eth_dev *dev,
59 struct rte_eth_dev_info *dev_info);
60 static int nfp_net_init(struct rte_eth_dev *eth_dev);
61 static int nfp_pf_init(struct rte_eth_dev *eth_dev);
62 static int nfp_pci_uninit(struct rte_eth_dev *eth_dev);
63 static int nfp_init_phyports(struct nfp_pf_dev *pf_dev);
64 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
65 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
66 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
67 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
68 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
70 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
72 static void nfp_net_rx_queue_release(void *rxq);
73 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
74 uint16_t nb_desc, unsigned int socket_id,
75 const struct rte_eth_rxconf *rx_conf,
76 struct rte_mempool *mp);
77 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
78 static void nfp_net_tx_queue_release(void *txq);
79 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
80 uint16_t nb_desc, unsigned int socket_id,
81 const struct rte_eth_txconf *tx_conf);
82 static int nfp_net_start(struct rte_eth_dev *dev);
83 static int nfp_net_stats_get(struct rte_eth_dev *dev,
84 struct rte_eth_stats *stats);
85 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
86 static int nfp_net_stop(struct rte_eth_dev *dev);
87 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
90 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
91 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
92 struct rte_eth_rss_conf *rss_conf);
93 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
94 struct rte_eth_rss_reta_entry64 *reta_conf,
96 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
97 struct rte_eth_rss_conf *rss_conf);
98 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
99 struct rte_ether_addr *mac_addr);
100 static int32_t nfp_cpp_bridge_service_func(void *args);
101 static int nfp_fw_setup(struct rte_pci_device *dev,
103 struct nfp_eth_table *nfp_eth_table,
104 struct nfp_hwinfo *hwinfo);
107 /* The offset of the queue controller queues in the PCIe Target */
108 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
110 /* Maximum value which can be added to a queue with one transaction */
111 #define NFP_QCP_MAX_ADD 0x7f
113 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
114 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
116 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
118 NFP_QCP_READ_PTR = 0,
123 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
124 * @q: Base address for queue structure
125 * @ptr: Add to the Read or Write pointer
126 * @val: Value to add to the queue pointer
128 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
131 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
135 if (ptr == NFP_QCP_READ_PTR)
136 off = NFP_QCP_QUEUE_ADD_RPTR;
138 off = NFP_QCP_QUEUE_ADD_WPTR;
140 while (val > NFP_QCP_MAX_ADD) {
141 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
142 val -= NFP_QCP_MAX_ADD;
145 nn_writel(rte_cpu_to_le_32(val), q + off);
149 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
150 * @q: Base address for queue structure
151 * @ptr: Read or Write pointer
153 static inline uint32_t
154 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
159 if (ptr == NFP_QCP_READ_PTR)
160 off = NFP_QCP_QUEUE_STS_LO;
162 off = NFP_QCP_QUEUE_STS_HI;
164 val = rte_cpu_to_le_32(nn_readl(q + off));
166 if (ptr == NFP_QCP_READ_PTR)
167 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
169 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
173 * Functions to read/write from/to Config BAR
174 * Performs any endian conversion necessary.
176 static inline uint8_t
177 nn_cfg_readb(struct nfp_net_hw *hw, int off)
179 return nn_readb(hw->ctrl_bar + off);
183 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
185 nn_writeb(val, hw->ctrl_bar + off);
188 static inline uint32_t
189 nn_cfg_readl(struct nfp_net_hw *hw, int off)
191 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
195 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
197 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
200 static inline uint64_t
201 nn_cfg_readq(struct nfp_net_hw *hw, int off)
203 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
207 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
209 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
213 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
217 if (rxq->rxbufs == NULL)
220 for (i = 0; i < rxq->rx_count; i++) {
221 if (rxq->rxbufs[i].mbuf) {
222 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
223 rxq->rxbufs[i].mbuf = NULL;
229 nfp_net_rx_queue_release(void *rx_queue)
231 struct nfp_net_rxq *rxq = rx_queue;
234 nfp_net_rx_queue_release_mbufs(rxq);
235 rte_free(rxq->rxbufs);
241 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
243 nfp_net_rx_queue_release_mbufs(rxq);
249 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
253 if (txq->txbufs == NULL)
256 for (i = 0; i < txq->tx_count; i++) {
257 if (txq->txbufs[i].mbuf) {
258 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
259 txq->txbufs[i].mbuf = NULL;
265 nfp_net_tx_queue_release(void *tx_queue)
267 struct nfp_net_txq *txq = tx_queue;
270 nfp_net_tx_queue_release_mbufs(txq);
271 rte_free(txq->txbufs);
277 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
279 nfp_net_tx_queue_release_mbufs(txq);
285 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
289 struct timespec wait;
291 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
294 if (hw->qcp_cfg == NULL)
295 rte_panic("Bad configuration queue pointer\n");
297 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
300 wait.tv_nsec = 1000000;
302 PMD_DRV_LOG(DEBUG, "Polling for update ack...");
304 /* Poll update field, waiting for NFP to ack the config */
305 for (cnt = 0; ; cnt++) {
306 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
309 if (new & NFP_NET_CFG_UPDATE_ERR) {
310 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
313 if (cnt >= NFP_NET_POLL_TIMEOUT) {
314 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
315 " %dms", update, cnt);
316 rte_panic("Exiting\n");
318 nanosleep(&wait, 0); /* waiting for a 1ms */
320 PMD_DRV_LOG(DEBUG, "Ack DONE");
325 * Reconfigure the NIC
326 * @nn: device to reconfigure
327 * @ctrl: The value for the ctrl field in the BAR config
328 * @update: The value for the update field in the BAR config
330 * Write the update word to the BAR and ping the reconfig queue. Then poll
331 * until the firmware has acknowledged the update by zeroing the update word.
334 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
338 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
341 rte_spinlock_lock(&hw->reconfig_lock);
343 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
344 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
348 err = __nfp_net_reconfig(hw, update);
350 rte_spinlock_unlock(&hw->reconfig_lock);
356 * Reconfig errors imply situations where they can be handled.
357 * Otherwise, rte_panic is called inside __nfp_net_reconfig
359 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
365 * Configure an Ethernet device. This function must be invoked first
366 * before any other function in the Ethernet API. This function can
367 * also be re-invoked when a device is in the stopped state.
370 nfp_net_configure(struct rte_eth_dev *dev)
372 struct rte_eth_conf *dev_conf;
373 struct rte_eth_rxmode *rxmode;
374 struct rte_eth_txmode *txmode;
375 struct nfp_net_hw *hw;
377 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
380 * A DPDK app sends info about how many queues to use and how
381 * those queues need to be configured. This is used by the
382 * DPDK core and it makes sure no more queues than those
383 * advertised by the driver are requested. This function is
384 * called after that internal process
387 PMD_INIT_LOG(DEBUG, "Configure");
389 dev_conf = &dev->data->dev_conf;
390 rxmode = &dev_conf->rxmode;
391 txmode = &dev_conf->txmode;
393 if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
394 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
396 /* Checking TX mode */
397 if (txmode->mq_mode) {
398 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
402 /* Checking RX mode */
403 if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
404 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
405 PMD_INIT_LOG(INFO, "RSS not supported");
413 nfp_net_enable_queues(struct rte_eth_dev *dev)
415 struct nfp_net_hw *hw;
416 uint64_t enabled_queues = 0;
419 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
421 /* Enabling the required TX queues in the device */
422 for (i = 0; i < dev->data->nb_tx_queues; i++)
423 enabled_queues |= (1 << i);
425 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
429 /* Enabling the required RX queues in the device */
430 for (i = 0; i < dev->data->nb_rx_queues; i++)
431 enabled_queues |= (1 << i);
433 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
437 nfp_net_disable_queues(struct rte_eth_dev *dev)
439 struct nfp_net_hw *hw;
440 uint32_t new_ctrl, update = 0;
442 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
444 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
445 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
447 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
448 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
449 NFP_NET_CFG_UPDATE_MSIX;
451 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
452 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
454 /* If an error when reconfig we avoid to change hw state */
455 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
462 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
466 for (i = 0; i < dev->data->nb_rx_queues; i++) {
467 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
474 nfp_net_params_setup(struct nfp_net_hw *hw)
476 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
477 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
481 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
483 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
486 #define ETH_ADDR_LEN 6
489 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
493 for (i = 0; i < ETH_ADDR_LEN; i++)
498 nfp_net_pf_read_mac(struct nfp_pf_dev *pf_dev, int port)
500 struct nfp_eth_table *nfp_eth_table;
501 struct nfp_net_hw *hw = NULL;
503 /* Grab a pointer to the correct physical port */
504 hw = pf_dev->ports[port];
506 nfp_eth_table = nfp_eth_read_ports(pf_dev->cpp);
508 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
509 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
516 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
520 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
521 memcpy(&hw->mac_addr[0], &tmp, 4);
523 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
524 memcpy(&hw->mac_addr[4], &tmp, 2);
528 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
530 uint32_t mac0 = *(uint32_t *)mac;
533 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
536 mac1 = *(uint16_t *)mac;
537 nn_writew(rte_cpu_to_be_16(mac1),
538 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
542 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
544 struct nfp_net_hw *hw;
545 uint32_t update, ctrl;
547 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
548 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
549 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
550 PMD_INIT_LOG(INFO, "MAC address unable to change when"
555 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
556 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
559 /* Writing new MAC to the specific port BAR address */
560 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
562 /* Signal the NIC about the change */
563 update = NFP_NET_CFG_UPDATE_MACADDR;
565 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
566 (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
567 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
568 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
569 PMD_INIT_LOG(INFO, "MAC address update failed");
576 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
577 struct rte_intr_handle *intr_handle)
579 struct nfp_net_hw *hw;
582 if (!intr_handle->intr_vec) {
583 intr_handle->intr_vec =
584 rte_zmalloc("intr_vec",
585 dev->data->nb_rx_queues * sizeof(int), 0);
586 if (!intr_handle->intr_vec) {
587 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
588 " intr_vec", dev->data->nb_rx_queues);
593 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
595 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
596 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
597 /* UIO just supports one queue and no LSC*/
598 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
599 intr_handle->intr_vec[0] = 0;
601 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
602 for (i = 0; i < dev->data->nb_rx_queues; i++) {
604 * The first msix vector is reserved for non
607 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
608 intr_handle->intr_vec[i] = i + 1;
609 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
610 intr_handle->intr_vec[i]);
614 /* Avoiding TX interrupts */
615 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
620 nfp_check_offloads(struct rte_eth_dev *dev)
622 struct nfp_net_hw *hw;
623 struct rte_eth_conf *dev_conf;
624 struct rte_eth_rxmode *rxmode;
625 struct rte_eth_txmode *txmode;
628 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
630 dev_conf = &dev->data->dev_conf;
631 rxmode = &dev_conf->rxmode;
632 txmode = &dev_conf->txmode;
634 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
635 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
636 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
639 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
640 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
641 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
644 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
645 hw->mtu = rxmode->max_rx_pkt_len;
647 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
648 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
651 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
652 ctrl |= NFP_NET_CFG_CTRL_L2BC;
655 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
656 ctrl |= NFP_NET_CFG_CTRL_L2MC;
658 /* TX checksum offload */
659 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
660 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
661 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
662 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
665 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
666 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
667 ctrl |= NFP_NET_CFG_CTRL_LSO;
669 ctrl |= NFP_NET_CFG_CTRL_LSO2;
673 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
674 ctrl |= NFP_NET_CFG_CTRL_GATHER;
680 nfp_net_start(struct rte_eth_dev *dev)
682 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
683 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
684 uint32_t new_ctrl, update = 0;
685 struct nfp_net_hw *hw;
686 struct nfp_pf_dev *pf_dev;
687 struct rte_eth_conf *dev_conf;
688 struct rte_eth_rxmode *rxmode;
689 uint32_t intr_vector;
692 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
693 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(dev->data->dev_private);
695 PMD_INIT_LOG(DEBUG, "Start");
697 /* Disabling queues just in case... */
698 nfp_net_disable_queues(dev);
700 /* Enabling the required queues in the device */
701 nfp_net_enable_queues(dev);
703 /* check and configure queue intr-vector mapping */
704 if (dev->data->dev_conf.intr_conf.rxq != 0) {
705 if (pf_dev->multiport) {
706 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
707 "with NFP multiport PF");
710 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
712 * Better not to share LSC with RX interrupts.
713 * Unregistering LSC interrupt handler
715 rte_intr_callback_unregister(&pci_dev->intr_handle,
716 nfp_net_dev_interrupt_handler, (void *)dev);
718 if (dev->data->nb_rx_queues > 1) {
719 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
720 "supports 1 queue with UIO");
724 intr_vector = dev->data->nb_rx_queues;
725 if (rte_intr_efd_enable(intr_handle, intr_vector))
728 nfp_configure_rx_interrupt(dev, intr_handle);
729 update = NFP_NET_CFG_UPDATE_MSIX;
732 rte_intr_enable(intr_handle);
734 new_ctrl = nfp_check_offloads(dev);
736 /* Writing configuration parameters in the device */
737 nfp_net_params_setup(hw);
739 dev_conf = &dev->data->dev_conf;
740 rxmode = &dev_conf->rxmode;
742 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
743 nfp_net_rss_config_default(dev);
744 update |= NFP_NET_CFG_UPDATE_RSS;
745 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
749 new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
751 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
753 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
754 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
756 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
757 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
761 * Allocating rte mbufs for configured rx queues.
762 * This requires queues being enabled before
764 if (nfp_net_rx_freelist_setup(dev) < 0) {
769 if (hw->is_phyport) {
770 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
771 /* Configure the physical port up */
772 nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 1);
774 nfp_eth_set_configured(dev->process_private,
784 * An error returned by this function should mean the app
785 * exiting and then the system releasing all the memory
786 * allocated even memory coming from hugepages.
788 * The device could be enabled at this point with some queues
789 * ready for getting packets. This is true if the call to
790 * nfp_net_rx_freelist_setup() succeeds for some queues but
791 * fails for subsequent queues.
793 * This should make the app exiting but better if we tell the
796 nfp_net_disable_queues(dev);
801 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
803 nfp_net_stop(struct rte_eth_dev *dev)
806 struct nfp_net_hw *hw;
808 PMD_INIT_LOG(DEBUG, "Stop");
810 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
812 nfp_net_disable_queues(dev);
815 for (i = 0; i < dev->data->nb_tx_queues; i++) {
816 nfp_net_reset_tx_queue(
817 (struct nfp_net_txq *)dev->data->tx_queues[i]);
820 for (i = 0; i < dev->data->nb_rx_queues; i++) {
821 nfp_net_reset_rx_queue(
822 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
825 if (hw->is_phyport) {
826 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
827 /* Configure the physical port down */
828 nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 0);
830 nfp_eth_set_configured(dev->process_private,
837 /* Set the link up. */
839 nfp_net_set_link_up(struct rte_eth_dev *dev)
841 struct nfp_net_hw *hw;
843 PMD_DRV_LOG(DEBUG, "Set link up");
845 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
850 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
851 /* Configure the physical port down */
852 return nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 1);
854 return nfp_eth_set_configured(dev->process_private,
858 /* Set the link down. */
860 nfp_net_set_link_down(struct rte_eth_dev *dev)
862 struct nfp_net_hw *hw;
864 PMD_DRV_LOG(DEBUG, "Set link down");
866 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
871 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
872 /* Configure the physical port down */
873 return nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 0);
875 return nfp_eth_set_configured(dev->process_private,
879 /* Reset and stop device. The device can not be restarted. */
881 nfp_net_close(struct rte_eth_dev *dev)
883 struct nfp_net_hw *hw;
884 struct rte_pci_device *pci_dev;
887 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
890 PMD_INIT_LOG(DEBUG, "Close");
892 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
893 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
896 * We assume that the DPDK application is stopping all the
897 * threads/queues before calling the device close function.
900 nfp_net_disable_queues(dev);
903 for (i = 0; i < dev->data->nb_tx_queues; i++) {
904 nfp_net_reset_tx_queue(
905 (struct nfp_net_txq *)dev->data->tx_queues[i]);
908 for (i = 0; i < dev->data->nb_rx_queues; i++) {
909 nfp_net_reset_rx_queue(
910 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
913 /* Only free PF resources after all physical ports have been closed */
914 if (pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC ||
915 pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC) {
916 struct nfp_pf_dev *pf_dev;
917 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(dev->data->dev_private);
919 /* Mark this port as unused and free device priv resources*/
920 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
921 pf_dev->ports[hw->idx] = NULL;
922 rte_eth_dev_release_port(dev);
924 for (i = 0; i < pf_dev->total_phyports; i++) {
925 /* Check to see if ports are still in use */
926 if (pf_dev->ports[i])
930 /* Now it is safe to free all PF resources */
931 PMD_INIT_LOG(INFO, "Freeing PF resources");
932 nfp_cpp_area_free(pf_dev->ctrl_area);
933 nfp_cpp_area_free(pf_dev->hwqueues_area);
934 free(pf_dev->hwinfo);
935 free(pf_dev->sym_tbl);
936 nfp_cpp_free(pf_dev->cpp);
940 rte_intr_disable(&pci_dev->intr_handle);
942 /* unregister callback func from eal lib */
943 rte_intr_callback_unregister(&pci_dev->intr_handle,
944 nfp_net_dev_interrupt_handler,
948 * The ixgbe PMD driver disables the pcie master on the
949 * device. The i40e does not...
956 nfp_net_promisc_enable(struct rte_eth_dev *dev)
958 uint32_t new_ctrl, update = 0;
959 struct nfp_net_hw *hw;
962 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
964 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
966 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
967 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
971 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
972 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
976 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
977 update = NFP_NET_CFG_UPDATE_GEN;
980 * DPDK sets promiscuous mode on just after this call assuming
981 * it can not fail ...
983 ret = nfp_net_reconfig(hw, new_ctrl, update);
993 nfp_net_promisc_disable(struct rte_eth_dev *dev)
995 uint32_t new_ctrl, update = 0;
996 struct nfp_net_hw *hw;
999 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1001 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
1002 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
1006 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
1007 update = NFP_NET_CFG_UPDATE_GEN;
1010 * DPDK sets promiscuous mode off just before this call
1011 * assuming it can not fail ...
1013 ret = nfp_net_reconfig(hw, new_ctrl, update);
1017 hw->ctrl = new_ctrl;
1023 * return 0 means link status changed, -1 means not changed
1025 * Wait to complete is needed as it can take up to 9 seconds to get the Link
1029 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1031 struct nfp_net_hw *hw;
1032 struct rte_eth_link link;
1033 uint32_t nn_link_status;
1036 static const uint32_t ls_to_ethtool[] = {
1037 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
1038 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
1039 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
1040 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
1041 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
1042 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
1043 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
1044 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
1047 PMD_DRV_LOG(DEBUG, "Link update");
1049 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1051 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1053 memset(&link, 0, sizeof(struct rte_eth_link));
1055 if (nn_link_status & NFP_NET_CFG_STS_LINK)
1056 link.link_status = ETH_LINK_UP;
1058 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1060 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1061 NFP_NET_CFG_STS_LINK_RATE_MASK;
1063 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1064 link.link_speed = ETH_SPEED_NUM_NONE;
1066 link.link_speed = ls_to_ethtool[nn_link_status];
1068 ret = rte_eth_linkstatus_set(dev, &link);
1070 if (link.link_status)
1071 PMD_DRV_LOG(INFO, "NIC Link is Up");
1073 PMD_DRV_LOG(INFO, "NIC Link is Down");
1079 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1082 struct nfp_net_hw *hw;
1083 struct rte_eth_stats nfp_dev_stats;
1085 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1087 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1089 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1091 /* reading per RX ring stats */
1092 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1093 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1096 nfp_dev_stats.q_ipackets[i] =
1097 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1099 nfp_dev_stats.q_ipackets[i] -=
1100 hw->eth_stats_base.q_ipackets[i];
1102 nfp_dev_stats.q_ibytes[i] =
1103 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1105 nfp_dev_stats.q_ibytes[i] -=
1106 hw->eth_stats_base.q_ibytes[i];
1109 /* reading per TX ring stats */
1110 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1111 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1114 nfp_dev_stats.q_opackets[i] =
1115 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1117 nfp_dev_stats.q_opackets[i] -=
1118 hw->eth_stats_base.q_opackets[i];
1120 nfp_dev_stats.q_obytes[i] =
1121 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1123 nfp_dev_stats.q_obytes[i] -=
1124 hw->eth_stats_base.q_obytes[i];
1127 nfp_dev_stats.ipackets =
1128 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1130 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1132 nfp_dev_stats.ibytes =
1133 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1135 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1137 nfp_dev_stats.opackets =
1138 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1140 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1142 nfp_dev_stats.obytes =
1143 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1145 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1147 /* reading general device stats */
1148 nfp_dev_stats.ierrors =
1149 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1151 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1153 nfp_dev_stats.oerrors =
1154 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1156 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1158 /* RX ring mbuf allocation failures */
1159 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1161 nfp_dev_stats.imissed =
1162 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1164 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1167 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1174 nfp_net_stats_reset(struct rte_eth_dev *dev)
1177 struct nfp_net_hw *hw;
1179 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1182 * hw->eth_stats_base records the per counter starting point.
1183 * Lets update it now
1186 /* reading per RX ring stats */
1187 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1188 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1191 hw->eth_stats_base.q_ipackets[i] =
1192 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1194 hw->eth_stats_base.q_ibytes[i] =
1195 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1198 /* reading per TX ring stats */
1199 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1200 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1203 hw->eth_stats_base.q_opackets[i] =
1204 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1206 hw->eth_stats_base.q_obytes[i] =
1207 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1210 hw->eth_stats_base.ipackets =
1211 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1213 hw->eth_stats_base.ibytes =
1214 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1216 hw->eth_stats_base.opackets =
1217 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1219 hw->eth_stats_base.obytes =
1220 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1222 /* reading general device stats */
1223 hw->eth_stats_base.ierrors =
1224 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1226 hw->eth_stats_base.oerrors =
1227 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1229 /* RX ring mbuf allocation failures */
1230 dev->data->rx_mbuf_alloc_failed = 0;
1232 hw->eth_stats_base.imissed =
1233 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1239 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1241 struct nfp_net_hw *hw;
1243 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1246 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1247 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1248 dev_info->max_rx_pktlen = hw->max_mtu;
1249 /* Next should change when PF support is implemented */
1250 dev_info->max_mac_addrs = 1;
1252 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1253 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1255 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1256 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1257 DEV_RX_OFFLOAD_UDP_CKSUM |
1258 DEV_RX_OFFLOAD_TCP_CKSUM;
1260 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1261 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1263 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1264 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1265 DEV_TX_OFFLOAD_UDP_CKSUM |
1266 DEV_TX_OFFLOAD_TCP_CKSUM;
1268 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1269 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1271 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1272 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1274 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1276 .pthresh = DEFAULT_RX_PTHRESH,
1277 .hthresh = DEFAULT_RX_HTHRESH,
1278 .wthresh = DEFAULT_RX_WTHRESH,
1280 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1284 dev_info->default_txconf = (struct rte_eth_txconf) {
1286 .pthresh = DEFAULT_TX_PTHRESH,
1287 .hthresh = DEFAULT_TX_HTHRESH,
1288 .wthresh = DEFAULT_TX_WTHRESH,
1290 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1291 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1294 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1295 .nb_max = NFP_NET_MAX_RX_DESC,
1296 .nb_min = NFP_NET_MIN_RX_DESC,
1297 .nb_align = NFP_ALIGN_RING_DESC,
1300 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1301 .nb_max = NFP_NET_MAX_TX_DESC,
1302 .nb_min = NFP_NET_MIN_TX_DESC,
1303 .nb_align = NFP_ALIGN_RING_DESC,
1304 .nb_seg_max = NFP_TX_MAX_SEG,
1305 .nb_mtu_seg_max = NFP_TX_MAX_MTU_SEG,
1308 /* All NFP devices support jumbo frames */
1309 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1311 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
1312 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_RSS_HASH;
1314 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1315 ETH_RSS_NONFRAG_IPV4_TCP |
1316 ETH_RSS_NONFRAG_IPV4_UDP |
1318 ETH_RSS_NONFRAG_IPV6_TCP |
1319 ETH_RSS_NONFRAG_IPV6_UDP;
1321 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1322 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1325 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1326 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1327 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1332 static const uint32_t *
1333 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1335 static const uint32_t ptypes[] = {
1336 /* refers to nfp_net_set_hash() */
1337 RTE_PTYPE_INNER_L3_IPV4,
1338 RTE_PTYPE_INNER_L3_IPV6,
1339 RTE_PTYPE_INNER_L3_IPV6_EXT,
1340 RTE_PTYPE_INNER_L4_MASK,
1344 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1350 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1352 struct nfp_net_rxq *rxq;
1353 struct nfp_net_rx_desc *rxds;
1357 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1364 * Other PMDs are just checking the DD bit in intervals of 4
1365 * descriptors and counting all four if the first has the DD
1366 * bit on. Of course, this is not accurate but can be good for
1367 * performance. But ideally that should be done in descriptors
1368 * chunks belonging to the same cache line
1371 while (count < rxq->rx_count) {
1372 rxds = &rxq->rxds[idx];
1373 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1380 if ((idx) == rxq->rx_count)
1388 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1390 struct rte_pci_device *pci_dev;
1391 struct nfp_net_hw *hw;
1394 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1395 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1397 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1400 /* Make sure all updates are written before un-masking */
1402 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1403 NFP_NET_CFG_ICR_UNMASKED);
1408 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1410 struct rte_pci_device *pci_dev;
1411 struct nfp_net_hw *hw;
1414 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1417 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1420 /* Make sure all updates are written before un-masking */
1422 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1427 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1429 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1430 struct rte_eth_link link;
1432 rte_eth_linkstatus_get(dev, &link);
1433 if (link.link_status)
1434 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1435 dev->data->port_id, link.link_speed,
1436 link.link_duplex == ETH_LINK_FULL_DUPLEX
1437 ? "full-duplex" : "half-duplex");
1439 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1440 dev->data->port_id);
1442 PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
1443 pci_dev->addr.domain, pci_dev->addr.bus,
1444 pci_dev->addr.devid, pci_dev->addr.function);
1447 /* Interrupt configuration and handling */
1450 * nfp_net_irq_unmask - Unmask an interrupt
1452 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1453 * clear the ICR for the entry.
1456 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1458 struct nfp_net_hw *hw;
1459 struct rte_pci_device *pci_dev;
1461 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1462 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1464 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1465 /* If MSI-X auto-masking is used, clear the entry */
1467 rte_intr_ack(&pci_dev->intr_handle);
1469 /* Make sure all updates are written before un-masking */
1471 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1472 NFP_NET_CFG_ICR_UNMASKED);
1477 nfp_net_dev_interrupt_handler(void *param)
1480 struct rte_eth_link link;
1481 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1483 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1485 rte_eth_linkstatus_get(dev, &link);
1487 nfp_net_link_update(dev, 0);
1490 if (!link.link_status) {
1491 /* handle it 1 sec later, wait it being stable */
1492 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1493 /* likely to down */
1495 /* handle it 4 sec later, wait it being stable */
1496 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1499 if (rte_eal_alarm_set(timeout * 1000,
1500 nfp_net_dev_interrupt_delayed_handler,
1502 PMD_INIT_LOG(ERR, "Error setting alarm");
1504 nfp_net_irq_unmask(dev);
1509 * Interrupt handler which shall be registered for alarm callback for delayed
1510 * handling specific interrupt to wait for the stable nic state. As the NIC
1511 * interrupt state is not stable for nfp after link is just down, it needs
1512 * to wait 4 seconds to get the stable status.
1514 * @param handle Pointer to interrupt handle.
1515 * @param param The address of parameter (struct rte_eth_dev *)
1520 nfp_net_dev_interrupt_delayed_handler(void *param)
1522 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1524 nfp_net_link_update(dev, 0);
1525 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1527 nfp_net_dev_link_status_print(dev);
1530 nfp_net_irq_unmask(dev);
1534 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1536 struct nfp_net_hw *hw;
1538 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540 /* check that mtu is within the allowed range */
1541 if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1544 /* mtu setting is forbidden if port is started */
1545 if (dev->data->dev_started) {
1546 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1547 dev->data->port_id);
1551 /* switch to jumbo mode if needed */
1552 if ((uint32_t)mtu > RTE_ETHER_MTU)
1553 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1555 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1557 /* update max frame size */
1558 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1560 /* writing to configuration space */
1561 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1569 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1570 uint16_t queue_idx, uint16_t nb_desc,
1571 unsigned int socket_id,
1572 const struct rte_eth_rxconf *rx_conf,
1573 struct rte_mempool *mp)
1575 const struct rte_memzone *tz;
1576 struct nfp_net_rxq *rxq;
1577 struct nfp_net_hw *hw;
1578 uint32_t rx_desc_sz;
1580 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582 PMD_INIT_FUNC_TRACE();
1584 /* Validating number of descriptors */
1585 rx_desc_sz = nb_desc * sizeof(struct nfp_net_rx_desc);
1586 if (rx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1587 nb_desc > NFP_NET_MAX_RX_DESC ||
1588 nb_desc < NFP_NET_MIN_RX_DESC) {
1589 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1594 * Free memory prior to re-allocation if needed. This is the case after
1595 * calling nfp_net_stop
1597 if (dev->data->rx_queues[queue_idx]) {
1598 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1599 dev->data->rx_queues[queue_idx] = NULL;
1602 /* Allocating rx queue data structure */
1603 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1604 RTE_CACHE_LINE_SIZE, socket_id);
1608 /* Hw queues mapping based on firmware configuration */
1609 rxq->qidx = queue_idx;
1610 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1611 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1612 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1613 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1616 * Tracking mbuf size for detecting a potential mbuf overflow due to
1620 rxq->mbuf_size = rxq->mem_pool->elt_size;
1621 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1622 hw->flbufsz = rxq->mbuf_size;
1624 rxq->rx_count = nb_desc;
1625 rxq->port_id = dev->data->port_id;
1626 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1627 rxq->drop_en = rx_conf->rx_drop_en;
1630 * Allocate RX ring hardware descriptors. A memzone large enough to
1631 * handle the maximum ring size is allocated in order to allow for
1632 * resizing in later calls to the queue setup function.
1634 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1635 sizeof(struct nfp_net_rx_desc) *
1636 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1640 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1641 nfp_net_rx_queue_release(rxq);
1645 /* Saving physical and virtual addresses for the RX ring */
1646 rxq->dma = (uint64_t)tz->iova;
1647 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1649 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1650 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1651 sizeof(*rxq->rxbufs) * nb_desc,
1652 RTE_CACHE_LINE_SIZE, socket_id);
1653 if (rxq->rxbufs == NULL) {
1654 nfp_net_rx_queue_release(rxq);
1658 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1659 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1661 nfp_net_reset_rx_queue(rxq);
1663 dev->data->rx_queues[queue_idx] = rxq;
1667 * Telling the HW about the physical address of the RX ring and number
1668 * of descriptors in log2 format
1670 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1671 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1677 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1679 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1683 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1686 for (i = 0; i < rxq->rx_count; i++) {
1687 struct nfp_net_rx_desc *rxd;
1688 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1691 PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1692 (unsigned)rxq->qidx);
1696 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1698 rxd = &rxq->rxds[i];
1700 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1701 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1703 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1706 /* Make sure all writes are flushed before telling the hardware */
1709 /* Not advertising the whole ring as the firmware gets confused if so */
1710 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1713 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1719 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1720 uint16_t nb_desc, unsigned int socket_id,
1721 const struct rte_eth_txconf *tx_conf)
1723 const struct rte_memzone *tz;
1724 struct nfp_net_txq *txq;
1725 uint16_t tx_free_thresh;
1726 struct nfp_net_hw *hw;
1727 uint32_t tx_desc_sz;
1729 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1731 PMD_INIT_FUNC_TRACE();
1733 /* Validating number of descriptors */
1734 tx_desc_sz = nb_desc * sizeof(struct nfp_net_tx_desc);
1735 if (tx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1736 nb_desc > NFP_NET_MAX_TX_DESC ||
1737 nb_desc < NFP_NET_MIN_TX_DESC) {
1738 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1742 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1743 tx_conf->tx_free_thresh :
1744 DEFAULT_TX_FREE_THRESH);
1746 if (tx_free_thresh > (nb_desc)) {
1748 "tx_free_thresh must be less than the number of TX "
1749 "descriptors. (tx_free_thresh=%u port=%d "
1750 "queue=%d)", (unsigned int)tx_free_thresh,
1751 dev->data->port_id, (int)queue_idx);
1756 * Free memory prior to re-allocation if needed. This is the case after
1757 * calling nfp_net_stop
1759 if (dev->data->tx_queues[queue_idx]) {
1760 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1762 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1763 dev->data->tx_queues[queue_idx] = NULL;
1766 /* Allocating tx queue data structure */
1767 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1768 RTE_CACHE_LINE_SIZE, socket_id);
1770 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1775 * Allocate TX ring hardware descriptors. A memzone large enough to
1776 * handle the maximum ring size is allocated in order to allow for
1777 * resizing in later calls to the queue setup function.
1779 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1780 sizeof(struct nfp_net_tx_desc) *
1781 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1784 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1785 nfp_net_tx_queue_release(txq);
1789 txq->tx_count = nb_desc;
1790 txq->tx_free_thresh = tx_free_thresh;
1791 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1792 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1793 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1795 /* queue mapping based on firmware configuration */
1796 txq->qidx = queue_idx;
1797 txq->tx_qcidx = queue_idx * hw->stride_tx;
1798 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1800 txq->port_id = dev->data->port_id;
1802 /* Saving physical and virtual addresses for the TX ring */
1803 txq->dma = (uint64_t)tz->iova;
1804 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1806 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1807 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1808 sizeof(*txq->txbufs) * nb_desc,
1809 RTE_CACHE_LINE_SIZE, socket_id);
1810 if (txq->txbufs == NULL) {
1811 nfp_net_tx_queue_release(txq);
1814 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1815 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1817 nfp_net_reset_tx_queue(txq);
1819 dev->data->tx_queues[queue_idx] = txq;
1823 * Telling the HW about the physical address of the TX ring and number
1824 * of descriptors in log2 format
1826 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1827 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1832 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1834 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1835 struct rte_mbuf *mb)
1838 struct nfp_net_hw *hw = txq->hw;
1840 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1843 ol_flags = mb->ol_flags;
1845 if (!(ol_flags & PKT_TX_TCP_SEG))
1848 txd->l3_offset = mb->l2_len;
1849 txd->l4_offset = mb->l2_len + mb->l3_len;
1850 txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1851 txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1852 txd->flags = PCIE_DESC_TX_LSO;
1859 txd->lso_hdrlen = 0;
1863 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1865 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1866 struct rte_mbuf *mb)
1869 struct nfp_net_hw *hw = txq->hw;
1871 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1874 ol_flags = mb->ol_flags;
1876 /* IPv6 does not need checksum */
1877 if (ol_flags & PKT_TX_IP_CKSUM)
1878 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1880 switch (ol_flags & PKT_TX_L4_MASK) {
1881 case PKT_TX_UDP_CKSUM:
1882 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1884 case PKT_TX_TCP_CKSUM:
1885 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1889 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1890 txd->flags |= PCIE_DESC_TX_CSUM;
1893 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1895 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1896 struct rte_mbuf *mb)
1898 struct nfp_net_hw *hw = rxq->hw;
1900 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1903 /* If IPv4 and IP checksum error, fail */
1904 if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1905 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1906 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1908 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1910 /* If neither UDP nor TCP return */
1911 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1912 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1915 if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1916 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1918 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1921 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1922 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1924 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1927 * nfp_net_set_hash - Set mbuf hash data
1929 * The RSS hash and hash-type are pre-pended to the packet data.
1930 * Extract and decode it and set the mbuf fields.
1933 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1934 struct rte_mbuf *mbuf)
1936 struct nfp_net_hw *hw = rxq->hw;
1937 uint8_t *meta_offset;
1940 uint32_t hash_type = 0;
1942 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1945 /* this is true for new firmwares */
1946 if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1947 (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1948 NFP_DESC_META_LEN(rxd))) {
1951 * <---- 32 bit ----->
1956 * ====================
1959 * Field type word contains up to 8 4bit field types
1960 * A 4bit field type refers to a data field word
1961 * A data field word can have several 4bit field types
1963 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1964 meta_offset -= NFP_DESC_META_LEN(rxd);
1965 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1967 /* NFP PMD just supports metadata for hashing */
1968 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1969 case NFP_NET_META_HASH:
1970 /* next field type is about the hash type */
1971 meta_info >>= NFP_NET_META_FIELD_SIZE;
1972 /* hash value is in the data field */
1973 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1974 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1977 /* Unsupported metadata can be a performance issue */
1981 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1984 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1985 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1988 mbuf->hash.rss = hash;
1989 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1991 switch (hash_type) {
1992 case NFP_NET_RSS_IPV4:
1993 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1995 case NFP_NET_RSS_IPV6:
1996 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1998 case NFP_NET_RSS_IPV6_EX:
1999 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2001 case NFP_NET_RSS_IPV4_TCP:
2002 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2004 case NFP_NET_RSS_IPV6_TCP:
2005 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2007 case NFP_NET_RSS_IPV4_UDP:
2008 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2010 case NFP_NET_RSS_IPV6_UDP:
2011 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2014 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
2019 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
2021 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
2024 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
2029 * There are some decisions to take:
2030 * 1) How to check DD RX descriptors bit
2031 * 2) How and when to allocate new mbufs
2033 * Current implementation checks just one single DD bit each loop. As each
2034 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
2035 * a single cache line instead. Tests with this change have not shown any
2036 * performance improvement but it requires further investigation. For example,
2037 * depending on which descriptor is next, the number of descriptors could be
2038 * less than 8 for just checking those in the same cache line. This implies
2039 * extra work which could be counterproductive by itself. Indeed, last firmware
2040 * changes are just doing this: writing several descriptors with the DD bit
2041 * for saving PCIe bandwidth and DMA operations from the NFP.
2043 * Mbuf allocation is done when a new packet is received. Then the descriptor
2044 * is automatically linked with the new mbuf and the old one is given to the
2045 * user. The main drawback with this design is mbuf allocation is heavier than
2046 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2047 * cache point of view it does not seem allocating the mbuf early on as we are
2048 * doing now have any benefit at all. Again, tests with this change have not
2049 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2050 * so looking at the implications of this type of allocation should be studied
2055 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2057 struct nfp_net_rxq *rxq;
2058 struct nfp_net_rx_desc *rxds;
2059 struct nfp_net_rx_buff *rxb;
2060 struct nfp_net_hw *hw;
2061 struct rte_mbuf *mb;
2062 struct rte_mbuf *new_mb;
2068 if (unlikely(rxq == NULL)) {
2070 * DPDK just checks the queue is lower than max queues
2071 * enabled. But the queue needs to be configured
2073 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2081 while (avail < nb_pkts) {
2082 rxb = &rxq->rxbufs[rxq->rd_p];
2083 if (unlikely(rxb == NULL)) {
2084 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2088 rxds = &rxq->rxds[rxq->rd_p];
2089 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2093 * Memory barrier to ensure that we won't do other
2094 * reads before the DD bit.
2099 * We got a packet. Let's alloc a new mbuf for refilling the
2100 * free descriptor ring as soon as possible
2102 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2103 if (unlikely(new_mb == NULL)) {
2104 RTE_LOG_DP(DEBUG, PMD,
2105 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2106 rxq->port_id, (unsigned int)rxq->qidx);
2107 nfp_net_mbuf_alloc_failed(rxq);
2114 * Grab the mbuf and refill the descriptor with the
2115 * previously allocated mbuf
2120 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2121 rxds->rxd.data_len, rxq->mbuf_size);
2123 /* Size of this segment */
2124 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2125 /* Size of the whole packet. We just support 1 segment */
2126 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2128 if (unlikely((mb->data_len + hw->rx_offset) >
2131 * This should not happen and the user has the
2132 * responsibility of avoiding it. But we have
2133 * to give some info about the error
2135 RTE_LOG_DP(ERR, PMD,
2136 "mbuf overflow likely due to the RX offset.\n"
2137 "\t\tYour mbuf size should have extra space for"
2138 " RX offset=%u bytes.\n"
2139 "\t\tCurrently you just have %u bytes available"
2140 " but the received packet is %u bytes long",
2142 rxq->mbuf_size - hw->rx_offset,
2147 /* Filling the received mbuf with packet info */
2149 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2151 mb->data_off = RTE_PKTMBUF_HEADROOM +
2152 NFP_DESC_META_LEN(rxds);
2154 /* No scatter mode supported */
2158 mb->port = rxq->port_id;
2160 /* Checking the RSS flag */
2161 nfp_net_set_hash(rxq, rxds, mb);
2163 /* Checking the checksum flag */
2164 nfp_net_rx_cksum(rxq, rxds, mb);
2166 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2167 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2168 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2169 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2172 /* Adding the mbuf to the mbuf array passed by the app */
2173 rx_pkts[avail++] = mb;
2175 /* Now resetting and updating the descriptor */
2178 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2180 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2181 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2184 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2191 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received",
2192 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2194 nb_hold += rxq->nb_rx_hold;
2197 * FL descriptors needs to be written before incrementing the
2198 * FL queue WR pointer
2201 if (nb_hold > rxq->rx_free_thresh) {
2202 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2203 rxq->port_id, (unsigned int)rxq->qidx,
2204 (unsigned)nb_hold, (unsigned)avail);
2205 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2208 rxq->nb_rx_hold = nb_hold;
2214 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2216 * @txq: TX queue to work with
2217 * Returns number of descriptors freed
2220 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2225 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2226 " status", txq->qidx);
2228 /* Work out how many packets have been sent */
2229 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2231 if (qcp_rd_p == txq->rd_p) {
2232 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2233 "packets (%u, %u)", txq->qidx,
2234 qcp_rd_p, txq->rd_p);
2238 if (qcp_rd_p > txq->rd_p)
2239 todo = qcp_rd_p - txq->rd_p;
2241 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2243 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2244 qcp_rd_p, txq->rd_p, txq->rd_p);
2250 if (unlikely(txq->rd_p >= txq->tx_count))
2251 txq->rd_p -= txq->tx_count;
2256 /* Leaving always free descriptors for avoiding wrapping confusion */
2258 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2260 if (txq->wr_p >= txq->rd_p)
2261 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2263 return txq->rd_p - txq->wr_p - 8;
2267 * nfp_net_txq_full - Check if the TX queue free descriptors
2268 * is below tx_free_threshold
2270 * @txq: TX queue to check
2272 * This function uses the host copy* of read/write pointers
2275 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2277 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2281 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2283 struct nfp_net_txq *txq;
2284 struct nfp_net_hw *hw;
2285 struct nfp_net_tx_desc *txds, txd;
2286 struct rte_mbuf *pkt;
2288 int pkt_size, dma_size;
2289 uint16_t free_descs, issued_descs;
2290 struct rte_mbuf **lmbuf;
2295 txds = &txq->txds[txq->wr_p];
2297 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2298 txq->qidx, txq->wr_p, nb_pkts);
2300 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2301 nfp_net_tx_free_bufs(txq);
2303 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2304 if (unlikely(free_descs == 0))
2311 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2312 txq->qidx, nb_pkts);
2313 /* Sending packets */
2314 while ((i < nb_pkts) && free_descs) {
2315 /* Grabbing the mbuf linked to the current descriptor */
2316 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2317 /* Warming the cache for releasing the mbuf later on */
2318 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2320 pkt = *(tx_pkts + i);
2322 if (unlikely((pkt->nb_segs > 1) &&
2323 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2324 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2325 rte_panic("Multisegment packet unsupported\n");
2328 /* Checking if we have enough descriptors */
2329 if (unlikely(pkt->nb_segs > free_descs))
2333 * Checksum and VLAN flags just in the first descriptor for a
2334 * multisegment packet, but TSO info needs to be in all of them.
2336 txd.data_len = pkt->pkt_len;
2337 nfp_net_tx_tso(txq, &txd, pkt);
2338 nfp_net_tx_cksum(txq, &txd, pkt);
2340 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2341 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2342 txd.flags |= PCIE_DESC_TX_VLAN;
2343 txd.vlan = pkt->vlan_tci;
2347 * mbuf data_len is the data in one segment and pkt_len data
2348 * in the whole packet. When the packet is just one segment,
2349 * then data_len = pkt_len
2351 pkt_size = pkt->pkt_len;
2354 /* Copying TSO, VLAN and cksum info */
2357 /* Releasing mbuf used by this descriptor previously*/
2359 rte_pktmbuf_free_seg(*lmbuf);
2362 * Linking mbuf with descriptor for being released
2363 * next time descriptor is used
2367 dma_size = pkt->data_len;
2368 dma_addr = rte_mbuf_data_iova(pkt);
2369 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2370 "%" PRIx64 "", dma_addr);
2372 /* Filling descriptors fields */
2373 txds->dma_len = dma_size;
2374 txds->data_len = txd.data_len;
2375 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2376 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2377 ASSERT(free_descs > 0);
2381 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2384 pkt_size -= dma_size;
2387 * Making the EOP, packets with just one segment
2390 if (likely(!pkt_size))
2391 txds->offset_eop = PCIE_DESC_TX_EOP;
2393 txds->offset_eop = 0;
2396 /* Referencing next free TX descriptor */
2397 txds = &txq->txds[txq->wr_p];
2398 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2405 /* Increment write pointers. Force memory write before we let HW know */
2407 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2413 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2415 uint32_t new_ctrl, update;
2416 struct nfp_net_hw *hw;
2419 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2422 /* Enable vlan strip if it is not configured yet */
2423 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2424 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2425 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2427 /* Disable vlan strip just if it is configured */
2428 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2429 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2430 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2435 update = NFP_NET_CFG_UPDATE_GEN;
2437 ret = nfp_net_reconfig(hw, new_ctrl, update);
2439 hw->ctrl = new_ctrl;
2445 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2446 struct rte_eth_rss_reta_entry64 *reta_conf,
2449 uint32_t reta, mask;
2452 struct nfp_net_hw *hw =
2453 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2455 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2456 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2457 "(%d) doesn't match the number hardware can supported "
2458 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2463 * Update Redirection Table. There are 128 8bit-entries which can be
2464 * manage as 32 32bit-entries
2466 for (i = 0; i < reta_size; i += 4) {
2467 /* Handling 4 RSS entries per loop */
2468 idx = i / RTE_RETA_GROUP_SIZE;
2469 shift = i % RTE_RETA_GROUP_SIZE;
2470 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2476 /* If all 4 entries were set, don't need read RETA register */
2478 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2480 for (j = 0; j < 4; j++) {
2481 if (!(mask & (0x1 << j)))
2484 /* Clearing the entry bits */
2485 reta &= ~(0xFF << (8 * j));
2486 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2488 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2494 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2496 nfp_net_reta_update(struct rte_eth_dev *dev,
2497 struct rte_eth_rss_reta_entry64 *reta_conf,
2500 struct nfp_net_hw *hw =
2501 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2505 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2508 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2512 update = NFP_NET_CFG_UPDATE_RSS;
2514 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2520 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2522 nfp_net_reta_query(struct rte_eth_dev *dev,
2523 struct rte_eth_rss_reta_entry64 *reta_conf,
2529 struct nfp_net_hw *hw;
2531 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2533 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2536 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2537 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2538 "(%d) doesn't match the number hardware can supported "
2539 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2544 * Reading Redirection Table. There are 128 8bit-entries which can be
2545 * manage as 32 32bit-entries
2547 for (i = 0; i < reta_size; i += 4) {
2548 /* Handling 4 RSS entries per loop */
2549 idx = i / RTE_RETA_GROUP_SIZE;
2550 shift = i % RTE_RETA_GROUP_SIZE;
2551 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2556 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2558 for (j = 0; j < 4; j++) {
2559 if (!(mask & (0x1 << j)))
2561 reta_conf[idx].reta[shift + j] =
2562 (uint8_t)((reta >> (8 * j)) & 0xF);
2569 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2570 struct rte_eth_rss_conf *rss_conf)
2572 struct nfp_net_hw *hw;
2574 uint32_t cfg_rss_ctrl = 0;
2578 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2580 /* Writing the key byte a byte */
2581 for (i = 0; i < rss_conf->rss_key_len; i++) {
2582 memcpy(&key, &rss_conf->rss_key[i], 1);
2583 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2586 rss_hf = rss_conf->rss_hf;
2588 if (rss_hf & ETH_RSS_IPV4)
2589 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2591 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2592 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2594 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2595 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2597 if (rss_hf & ETH_RSS_IPV6)
2598 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2600 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2601 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2603 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2604 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2606 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2607 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2609 /* configuring where to apply the RSS hash */
2610 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2612 /* Writing the key size */
2613 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2619 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2620 struct rte_eth_rss_conf *rss_conf)
2624 struct nfp_net_hw *hw;
2626 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628 rss_hf = rss_conf->rss_hf;
2630 /* Checking if RSS is enabled */
2631 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2632 if (rss_hf != 0) { /* Enable RSS? */
2633 PMD_DRV_LOG(ERR, "RSS unsupported");
2636 return 0; /* Nothing to do */
2639 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2640 PMD_DRV_LOG(ERR, "hash key too long");
2644 nfp_net_rss_hash_write(dev, rss_conf);
2646 update = NFP_NET_CFG_UPDATE_RSS;
2648 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2655 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2656 struct rte_eth_rss_conf *rss_conf)
2659 uint32_t cfg_rss_ctrl;
2662 struct nfp_net_hw *hw;
2664 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2666 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2669 rss_hf = rss_conf->rss_hf;
2670 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2672 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2673 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2675 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2676 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2678 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2679 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2681 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2682 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2684 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2685 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2687 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2688 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2690 /* Propagate current RSS hash functions to caller */
2691 rss_conf->rss_hf = rss_hf;
2693 /* Reading the key size */
2694 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2696 /* Reading the key byte a byte */
2697 for (i = 0; i < rss_conf->rss_key_len; i++) {
2698 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2699 memcpy(&rss_conf->rss_key[i], &key, 1);
2706 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2708 struct rte_eth_conf *dev_conf;
2709 struct rte_eth_rss_conf rss_conf;
2710 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2711 uint16_t rx_queues = dev->data->nb_rx_queues;
2715 PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2718 nfp_reta_conf[0].mask = ~0x0;
2719 nfp_reta_conf[1].mask = ~0x0;
2722 for (i = 0; i < 0x40; i += 8) {
2723 for (j = i; j < (i + 8); j++) {
2724 nfp_reta_conf[0].reta[j] = queue;
2725 nfp_reta_conf[1].reta[j] = queue++;
2729 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2733 dev_conf = &dev->data->dev_conf;
2735 PMD_DRV_LOG(INFO, "wrong rss conf");
2738 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2740 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2746 /* Initialise and register driver with DPDK Application */
2747 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2748 .dev_configure = nfp_net_configure,
2749 .dev_start = nfp_net_start,
2750 .dev_stop = nfp_net_stop,
2751 .dev_set_link_up = nfp_net_set_link_up,
2752 .dev_set_link_down = nfp_net_set_link_down,
2753 .dev_close = nfp_net_close,
2754 .promiscuous_enable = nfp_net_promisc_enable,
2755 .promiscuous_disable = nfp_net_promisc_disable,
2756 .link_update = nfp_net_link_update,
2757 .stats_get = nfp_net_stats_get,
2758 .stats_reset = nfp_net_stats_reset,
2759 .dev_infos_get = nfp_net_infos_get,
2760 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2761 .mtu_set = nfp_net_dev_mtu_set,
2762 .mac_addr_set = nfp_set_mac_addr,
2763 .vlan_offload_set = nfp_net_vlan_offload_set,
2764 .reta_update = nfp_net_reta_update,
2765 .reta_query = nfp_net_reta_query,
2766 .rss_hash_update = nfp_net_rss_hash_update,
2767 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2768 .rx_queue_setup = nfp_net_rx_queue_setup,
2769 .rx_queue_release = nfp_net_rx_queue_release,
2770 .tx_queue_setup = nfp_net_tx_queue_setup,
2771 .tx_queue_release = nfp_net_tx_queue_release,
2772 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2773 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2778 nfp_net_init(struct rte_eth_dev *eth_dev)
2780 struct rte_pci_device *pci_dev;
2781 struct nfp_pf_dev *pf_dev;
2782 struct nfp_net_hw *hw;
2784 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2790 PMD_INIT_FUNC_TRACE();
2792 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2794 /* Use backpointer here to the PF of this eth_dev */
2795 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(eth_dev->data->dev_private);
2797 /* NFP can not handle DMA addresses requiring more than 40 bits */
2798 if (rte_mem_check_dma_mask(40)) {
2799 RTE_LOG(ERR, PMD, "device %s can not be used:",
2800 pci_dev->device.name);
2801 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2805 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2806 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2807 port = ((struct nfp_net_hw *)eth_dev->data->dev_private)->idx;
2808 if (port < 0 || port > 7) {
2809 PMD_DRV_LOG(ERR, "Port value is wrong");
2813 /* Use PF array of physical ports to get pointer to
2814 * this specific port
2816 hw = pf_dev->ports[port];
2818 PMD_INIT_LOG(DEBUG, "Working with physical port number: %d, "
2819 "NFP internal port number: %d",
2823 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2826 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2827 eth_dev->rx_queue_count = nfp_net_rx_queue_count;
2828 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2829 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2831 /* For secondary processes, the primary has done all the work */
2832 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2835 rte_eth_copy_pci_info(eth_dev, pci_dev);
2837 hw->device_id = pci_dev->id.device_id;
2838 hw->vendor_id = pci_dev->id.vendor_id;
2839 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2840 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2842 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2843 pci_dev->id.vendor_id, pci_dev->id.device_id,
2844 pci_dev->addr.domain, pci_dev->addr.bus,
2845 pci_dev->addr.devid, pci_dev->addr.function);
2847 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2848 if (hw->ctrl_bar == NULL) {
2850 "hw->ctrl_bar is NULL. BAR0 not configured");
2854 if (hw->is_phyport) {
2856 hw->ctrl_bar = pf_dev->ctrl_bar;
2858 if (!pf_dev->ctrl_bar)
2860 /* Use port offset in pf ctrl_bar for this
2863 hw->ctrl_bar = pf_dev->ctrl_bar +
2864 (port * NFP_PF_CSR_SLICE_SIZE);
2868 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2870 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2871 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2873 /* Work out where in the BAR the queues start. */
2874 switch (pci_dev->id.device_id) {
2875 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2876 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2877 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2878 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2879 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2880 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2881 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2884 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2886 goto dev_err_ctrl_map;
2889 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2890 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2892 if (hw->is_phyport) {
2893 hw->tx_bar = pf_dev->hw_queues + tx_bar_off;
2894 hw->rx_bar = pf_dev->hw_queues + rx_bar_off;
2895 eth_dev->data->dev_private = hw;
2897 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2899 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2903 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2904 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2906 nfp_net_cfg_queue_setup(hw);
2908 /* Get some of the read-only fields from the config BAR */
2909 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2910 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2911 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2912 hw->mtu = RTE_ETHER_MTU;
2914 /* VLAN insertion is incompatible with LSOv2 */
2915 if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2916 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2918 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2919 hw->rx_offset = NFP_NET_RX_OFFSET;
2921 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2923 PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2924 NFD_CFG_MAJOR_VERSION_of(hw->ver),
2925 NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2927 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2928 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2929 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2930 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2931 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2932 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2933 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2934 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2935 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2936 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2937 hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "",
2938 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2939 hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "",
2940 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "",
2941 hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : "");
2945 hw->stride_rx = stride;
2946 hw->stride_tx = stride;
2948 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2949 hw->max_rx_queues, hw->max_tx_queues);
2951 /* Initializing spinlock for reconfigs */
2952 rte_spinlock_init(&hw->reconfig_lock);
2954 /* Allocating memory for mac addr */
2955 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2956 RTE_ETHER_ADDR_LEN, 0);
2957 if (eth_dev->data->mac_addrs == NULL) {
2958 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2960 goto dev_err_queues_map;
2963 if (hw->is_phyport) {
2964 nfp_net_pf_read_mac(pf_dev, port);
2965 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2967 nfp_net_vf_read_mac(hw);
2970 if (!rte_is_valid_assigned_ether_addr(
2971 (struct rte_ether_addr *)&hw->mac_addr)) {
2972 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2974 /* Using random mac addresses for VFs */
2975 rte_eth_random_addr(&hw->mac_addr[0]);
2976 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2979 /* Copying mac address to DPDK eth_dev struct */
2980 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2981 ð_dev->data->mac_addrs[0]);
2983 if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2984 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2986 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2988 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2989 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2990 eth_dev->data->port_id, pci_dev->id.vendor_id,
2991 pci_dev->id.device_id,
2992 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2993 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2995 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2996 /* Registering LSC interrupt handler */
2997 rte_intr_callback_register(&pci_dev->intr_handle,
2998 nfp_net_dev_interrupt_handler,
3000 /* Telling the firmware about the LSC interrupt entry */
3001 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3002 /* Recording current stats counters values */
3003 nfp_net_stats_reset(eth_dev);
3009 nfp_cpp_area_free(hw->hwqueues_area);
3011 nfp_cpp_area_free(hw->ctrl_area);
3016 #define NFP_CPP_MEMIO_BOUNDARY (1 << 20)
3019 * Serving a write request to NFP from host programs. The request
3020 * sends the write size and the CPP target. The bridge makes use
3021 * of CPP interface handler configured by the PMD setup.
3024 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3026 struct nfp_cpp_area *area;
3027 off_t offset, nfp_offset;
3028 uint32_t cpp_id, pos, len;
3029 uint32_t tmpbuf[16];
3030 size_t count, curlen, totlen = 0;
3033 PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3034 sizeof(off_t), sizeof(size_t));
3036 /* Reading the count param */
3037 err = recv(sockfd, &count, sizeof(off_t), 0);
3038 if (err != sizeof(off_t))
3043 /* Reading the offset param */
3044 err = recv(sockfd, &offset, sizeof(off_t), 0);
3045 if (err != sizeof(off_t))
3048 /* Obtain target's CPP ID and offset in target */
3049 cpp_id = (offset >> 40) << 8;
3050 nfp_offset = offset & ((1ull << 40) - 1);
3052 PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3054 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3055 cpp_id, nfp_offset);
3057 /* Adjust length if not aligned */
3058 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3059 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3060 curlen = NFP_CPP_MEMIO_BOUNDARY -
3061 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3065 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3066 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3067 nfp_offset, curlen);
3069 RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3073 /* mapping the target */
3074 err = nfp_cpp_area_acquire(area);
3076 RTE_LOG(ERR, PMD, "area acquire failed\n");
3077 nfp_cpp_area_free(area);
3081 for (pos = 0; pos < curlen; pos += len) {
3083 if (len > sizeof(tmpbuf))
3084 len = sizeof(tmpbuf);
3086 PMD_CPP_LOG(DEBUG, "%s: Receive %u of %zu\n", __func__,
3088 err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3089 if (err != (int)len) {
3091 "%s: error when receiving, %d of %zu\n",
3092 __func__, err, count);
3093 nfp_cpp_area_release(area);
3094 nfp_cpp_area_free(area);
3097 err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3099 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3100 nfp_cpp_area_release(area);
3101 nfp_cpp_area_free(area);
3108 nfp_cpp_area_release(area);
3109 nfp_cpp_area_free(area);
3112 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3113 NFP_CPP_MEMIO_BOUNDARY : count;
3120 * Serving a read request to NFP from host programs. The request
3121 * sends the read size and the CPP target. The bridge makes use
3122 * of CPP interface handler configured by the PMD setup. The read
3123 * data is sent to the requester using the same socket.
3126 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3128 struct nfp_cpp_area *area;
3129 off_t offset, nfp_offset;
3130 uint32_t cpp_id, pos, len;
3131 uint32_t tmpbuf[16];
3132 size_t count, curlen, totlen = 0;
3135 PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3136 sizeof(off_t), sizeof(size_t));
3138 /* Reading the count param */
3139 err = recv(sockfd, &count, sizeof(off_t), 0);
3140 if (err != sizeof(off_t))
3145 /* Reading the offset param */
3146 err = recv(sockfd, &offset, sizeof(off_t), 0);
3147 if (err != sizeof(off_t))
3150 /* Obtain target's CPP ID and offset in target */
3151 cpp_id = (offset >> 40) << 8;
3152 nfp_offset = offset & ((1ull << 40) - 1);
3154 PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3156 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3157 cpp_id, nfp_offset);
3159 /* Adjust length if not aligned */
3160 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3161 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3162 curlen = NFP_CPP_MEMIO_BOUNDARY -
3163 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3167 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3168 nfp_offset, curlen);
3170 RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3174 err = nfp_cpp_area_acquire(area);
3176 RTE_LOG(ERR, PMD, "area acquire failed\n");
3177 nfp_cpp_area_free(area);
3181 for (pos = 0; pos < curlen; pos += len) {
3183 if (len > sizeof(tmpbuf))
3184 len = sizeof(tmpbuf);
3186 err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3188 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3189 nfp_cpp_area_release(area);
3190 nfp_cpp_area_free(area);
3193 PMD_CPP_LOG(DEBUG, "%s: sending %u of %zu\n", __func__,
3196 err = send(sockfd, tmpbuf, len, 0);
3197 if (err != (int)len) {
3199 "%s: error when sending: %d of %zu\n",
3200 __func__, err, count);
3201 nfp_cpp_area_release(area);
3202 nfp_cpp_area_free(area);
3209 nfp_cpp_area_release(area);
3210 nfp_cpp_area_free(area);
3213 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3214 NFP_CPP_MEMIO_BOUNDARY : count;
3219 #define NFP_IOCTL 'n'
3220 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3222 * Serving a ioctl command from host NFP tools. This usually goes to
3223 * a kernel driver char driver but it is not available when the PF is
3224 * bound to the PMD. Currently just one ioctl command is served and it
3225 * does not require any CPP access at all.
3228 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3230 uint32_t cmd, ident_size, tmp;
3233 /* Reading now the IOCTL command */
3234 err = recv(sockfd, &cmd, 4, 0);
3236 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3240 /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3241 if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3242 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3246 err = recv(sockfd, &ident_size, 4, 0);
3248 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3252 tmp = nfp_cpp_model(cpp);
3254 PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3256 err = send(sockfd, &tmp, 4, 0);
3258 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3262 tmp = cpp->interface;
3264 PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3266 err = send(sockfd, &tmp, 4, 0);
3268 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3275 #define NFP_BRIDGE_OP_READ 20
3276 #define NFP_BRIDGE_OP_WRITE 30
3277 #define NFP_BRIDGE_OP_IOCTL 40
3280 * This is the code to be executed by a service core. The CPP bridge interface
3281 * is based on a unix socket and requests usually received by a kernel char
3282 * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3283 * can be executed with a wrapper library and LD_LIBRARY being completely
3284 * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3288 nfp_cpp_bridge_service_func(void *args)
3290 struct sockaddr address;
3291 struct nfp_cpp *cpp = args;
3292 int sockfd, datafd, op, ret;
3294 unlink("/tmp/nfp_cpp");
3295 sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3297 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3302 memset(&address, 0, sizeof(struct sockaddr));
3304 address.sa_family = AF_UNIX;
3305 strcpy(address.sa_data, "/tmp/nfp_cpp");
3307 ret = bind(sockfd, (const struct sockaddr *)&address,
3308 sizeof(struct sockaddr));
3310 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3316 ret = listen(sockfd, 20);
3318 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3325 datafd = accept(sockfd, NULL, NULL);
3327 RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3329 RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3335 ret = recv(datafd, &op, 4, 0);
3337 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3342 PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3344 if (op == NFP_BRIDGE_OP_READ)
3345 nfp_cpp_bridge_serve_read(datafd, cpp);
3347 if (op == NFP_BRIDGE_OP_WRITE)
3348 nfp_cpp_bridge_serve_write(datafd, cpp);
3350 if (op == NFP_BRIDGE_OP_IOCTL)
3351 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3363 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
3366 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3368 struct nfp_cpp *cpp = nsp->cpp;
3373 struct stat file_stat;
3376 /* Looking for firmware file in order of priority */
3378 /* First try to find a firmware image specific for this device */
3379 snprintf(serial, sizeof(serial),
3380 "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3381 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3382 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3383 cpp->interface & 0xff);
3385 snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3388 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3389 fw_f = open(fw_name, O_RDONLY);
3393 /* Then try the PCI name */
3394 snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3397 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3398 fw_f = open(fw_name, O_RDONLY);
3402 /* Finally try the card type and media */
3403 snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3404 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3405 fw_f = open(fw_name, O_RDONLY);
3407 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3412 if (fstat(fw_f, &file_stat) < 0) {
3413 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3418 fsize = file_stat.st_size;
3419 PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3420 fw_name, (uint64_t)fsize);
3422 fw_buf = malloc((size_t)fsize);
3424 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3428 memset(fw_buf, 0, fsize);
3430 bytes = read(fw_f, fw_buf, fsize);
3431 if (bytes != fsize) {
3432 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3433 "Just %" PRIu64 " of %" PRIu64 " bytes read",
3434 (uint64_t)bytes, (uint64_t)fsize);
3440 PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3441 nfp_nsp_load_fw(nsp, fw_buf, bytes);
3442 PMD_DRV_LOG(INFO, "Done");
3451 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3452 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3454 struct nfp_nsp *nsp;
3455 const char *nfp_fw_model;
3456 char card_desc[100];
3459 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3462 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3464 PMD_DRV_LOG(ERR, "firmware model NOT found");
3468 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3469 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3470 nfp_eth_table->count);
3474 PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3475 nfp_eth_table->count);
3477 PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3479 snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3480 nfp_fw_model, nfp_eth_table->count,
3481 nfp_eth_table->ports[0].speed / 1000);
3483 nsp = nfp_nsp_open(cpp);
3485 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3489 nfp_nsp_device_soft_reset(nsp);
3490 err = nfp_fw_upload(dev, nsp, card_desc);
3496 static int nfp_init_phyports(struct nfp_pf_dev *pf_dev)
3498 struct nfp_net_hw *hw;
3499 struct rte_eth_dev *eth_dev;
3500 struct nfp_eth_table *nfp_eth_table = NULL;
3504 nfp_eth_table = nfp_eth_read_ports(pf_dev->cpp);
3505 if (!nfp_eth_table) {
3506 PMD_INIT_LOG(ERR, "Error reading NFP ethernet table");
3511 /* Loop through all physical ports on PF */
3512 for (i = 0; i < pf_dev->total_phyports; i++) {
3513 const unsigned int numa_node = rte_socket_id();
3514 char port_name[RTE_ETH_NAME_MAX_LEN];
3516 snprintf(port_name, sizeof(port_name), "%s_port%d",
3517 pf_dev->pci_dev->device.name, i);
3519 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3520 eth_dev = rte_eth_dev_attach_secondary(port_name);
3523 "secondary process attach failed, "
3524 "ethdev doesn't exist");
3529 eth_dev->process_private = pf_dev->cpp;
3533 /* First port has already been initialized */
3535 eth_dev = pf_dev->eth_dev;
3536 goto skip_dev_alloc;
3539 /* Allocate a eth_dev for remaining ports */
3540 eth_dev = rte_eth_dev_allocate(port_name);
3546 /* Allocate memory for remaining ports */
3547 eth_dev->data->dev_private =
3548 rte_zmalloc_socket(port_name, sizeof(struct nfp_net_hw),
3549 RTE_CACHE_LINE_SIZE, numa_node);
3550 if (!eth_dev->data->dev_private) {
3552 rte_eth_dev_release_port(eth_dev);
3557 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3559 /* Add this device to the PF's array of physical ports */
3560 pf_dev->ports[i] = hw;
3562 hw->pf_dev = pf_dev;
3563 hw->cpp = pf_dev->cpp;
3564 hw->eth_dev = eth_dev;
3566 hw->nfp_idx = nfp_eth_table->ports[i].index;
3567 hw->is_phyport = true;
3570 eth_dev->device = &pf_dev->pci_dev->device;
3572 /* ctrl/tx/rx BAR mappings and remaining init happens in
3575 ret = nfp_net_init(eth_dev);
3582 rte_eth_dev_probing_finish(eth_dev);
3584 } /* End loop, all ports on this PF */
3586 goto eth_table_cleanup;
3589 for (i = 0; i < pf_dev->total_phyports; i++) {
3590 if (pf_dev->ports[i] && pf_dev->ports[i]->eth_dev) {
3591 struct rte_eth_dev *tmp_dev;
3592 tmp_dev = pf_dev->ports[i]->eth_dev;
3593 rte_eth_dev_release_port(tmp_dev);
3594 pf_dev->ports[i] = NULL;
3598 free(nfp_eth_table);
3603 static int nfp_pf_init(struct rte_eth_dev *eth_dev)
3605 struct rte_pci_device *pci_dev;
3606 struct nfp_net_hw *hw = NULL;
3607 struct nfp_pf_dev *pf_dev = NULL;
3608 struct nfp_cpp *cpp;
3609 struct nfp_hwinfo *hwinfo;
3610 struct nfp_rtsym_table *sym_tbl;
3611 struct nfp_eth_table *nfp_eth_table = NULL;
3612 struct rte_service_spec service;
3613 char name[RTE_ETH_NAME_MAX_LEN];
3618 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3619 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev);
3625 * When device bound to UIO, the device could be used, by mistake,
3626 * by two DPDK apps, and the UIO driver does not avoid it. This
3627 * could lead to a serious problem when configuring the NFP CPP
3628 * interface. Here we avoid this telling to the CPP init code to
3629 * use a lock file if UIO is being used.
3631 if (pci_dev->kdrv == RTE_PCI_KDRV_VFIO)
3632 cpp = nfp_cpp_from_device_name(pci_dev, 0);
3634 cpp = nfp_cpp_from_device_name(pci_dev, 1);
3637 PMD_INIT_LOG(ERR, "A CPP handle can not be obtained");
3642 hwinfo = nfp_hwinfo_read(cpp);
3644 PMD_INIT_LOG(ERR, "Error reading hwinfo table");
3649 nfp_eth_table = nfp_eth_read_ports(cpp);
3650 if (!nfp_eth_table) {
3651 PMD_INIT_LOG(ERR, "Error reading NFP ethernet table");
3653 goto hwinfo_cleanup;
3656 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3657 if (nfp_fw_setup(pci_dev, cpp, nfp_eth_table, hwinfo)) {
3658 PMD_INIT_LOG(ERR, "Error when uploading firmware");
3660 goto eth_table_cleanup;
3664 /* Now the symbol table should be there */
3665 sym_tbl = nfp_rtsym_table_read(cpp);
3667 PMD_INIT_LOG(ERR, "Something is wrong with the firmware"
3670 goto eth_table_cleanup;
3673 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3674 if (total_ports != (int)nfp_eth_table->count) {
3675 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3677 goto sym_tbl_cleanup;
3680 PMD_INIT_LOG(INFO, "Total physical ports: %d", total_ports);
3682 if (total_ports <= 0 || total_ports > 8) {
3683 PMD_INIT_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3685 goto sym_tbl_cleanup;
3687 /* Allocate memory for the PF "device" */
3688 snprintf(name, sizeof(name), "nfp_pf%d", eth_dev->data->port_id);
3689 pf_dev = rte_zmalloc(name, sizeof(*pf_dev), 0);
3692 goto sym_tbl_cleanup;
3695 /* Populate the newly created PF device */
3697 pf_dev->hwinfo = hwinfo;
3698 pf_dev->sym_tbl = sym_tbl;
3699 pf_dev->total_phyports = total_ports;
3701 if (total_ports > 1)
3702 pf_dev->multiport = true;
3704 pf_dev->pci_dev = pci_dev;
3706 /* The first eth_dev is part of the PF struct */
3707 pf_dev->eth_dev = eth_dev;
3709 /* Map the symbol table */
3710 pf_dev->ctrl_bar = nfp_rtsym_map(pf_dev->sym_tbl, "_pf0_net_bar0",
3711 pf_dev->total_phyports * 32768,
3712 &pf_dev->ctrl_area);
3713 if (!pf_dev->ctrl_bar) {
3714 PMD_INIT_LOG(ERR, "nfp_rtsym_map fails for _pf0_net_ctrl_bar");
3719 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", pf_dev->ctrl_bar);
3721 /* configure access to tx/rx vNIC BARs */
3722 pf_dev->hw_queues = nfp_cpp_map_area(pf_dev->cpp, 0, 0,
3724 NFP_QCP_QUEUE_AREA_SZ,
3725 &pf_dev->hwqueues_area);
3726 if (!pf_dev->hw_queues) {
3727 PMD_INIT_LOG(ERR, "nfp_rtsym_map fails for net.qc");
3729 goto ctrl_area_cleanup;
3732 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p", pf_dev->hw_queues);
3734 /* Initialize and prep physical ports now
3735 * This will loop through all physical ports
3737 ret = nfp_init_phyports(pf_dev);
3739 PMD_INIT_LOG(ERR, "Could not create physical ports");
3740 goto hwqueues_cleanup;
3744 * The rte_service needs to be created just once per PMD.
3745 * And the cpp handler needs to be linked to the service.
3746 * Secondary processes will be used for debugging DPDK apps
3747 * when requiring to use the CPP interface for accessing NFP
3748 * components. And the cpp handler for secondary processes is
3749 * available at this point.
3751 memset(&service, 0, sizeof(struct rte_service_spec));
3752 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3753 service.callback = nfp_cpp_bridge_service_func;
3754 service.callback_userdata = (void *)cpp;
3756 if (rte_service_component_register(&service,
3757 &hw->nfp_cpp_service_id))
3758 RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3760 RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3765 nfp_cpp_area_free(pf_dev->hwqueues_area);
3767 nfp_cpp_area_free(pf_dev->ctrl_area);
3773 free(nfp_eth_table);
3780 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3781 struct rte_pci_device *dev)
3783 return rte_eth_dev_pci_generic_probe(dev,
3784 sizeof(struct nfp_net_hw), nfp_pf_init);
3787 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3789 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3790 PCI_DEVICE_ID_NFP4000_PF_NIC)
3793 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3794 PCI_DEVICE_ID_NFP6000_PF_NIC)
3801 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3803 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3804 PCI_DEVICE_ID_NFP6000_VF_NIC)
3811 static int nfp_pci_uninit(struct rte_eth_dev *eth_dev)
3813 struct rte_pci_device *pci_dev;
3816 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3818 if (pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC ||
3819 pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC) {
3820 /* Free up all physical ports under PF */
3821 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3822 rte_eth_dev_close(port_id);
3824 * Ports can be closed and freed but hotplugging is not
3825 * currently supported
3830 /* VF cleanup, just free private port data */
3831 return nfp_net_close(eth_dev);
3834 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3835 struct rte_pci_device *pci_dev)
3837 return rte_eth_dev_pci_generic_probe(pci_dev,
3838 sizeof(struct nfp_net_adapter), nfp_net_init);
3841 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3843 return rte_eth_dev_pci_generic_remove(pci_dev, nfp_pci_uninit);
3846 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3847 .id_table = pci_id_nfp_pf_net_map,
3848 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3849 .probe = nfp_pf_pci_probe,
3850 .remove = eth_nfp_pci_remove,
3853 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3854 .id_table = pci_id_nfp_vf_net_map,
3855 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3856 .probe = eth_nfp_pci_probe,
3857 .remove = eth_nfp_pci_remove,
3860 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3861 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3862 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3863 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3864 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3865 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3866 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_init, init, NOTICE);
3867 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_driver, driver, NOTICE);
3870 * c-file-style: "Linux"
3871 * indent-tabs-mode: t