drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014, 2015 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <math.h>
  43
  44 #include <rte_byteorder.h>
  45 #include <rte_common.h>
  46 #include <rte_log.h>
  47 #include <rte_debug.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_dev.h>
  50 #include <rte_ether.h>
  51 #include <rte_malloc.h>
  52 #include <rte_memzone.h>
  53 #include <rte_mempool.h>
  54 #include <rte_version.h>
  55 #include <rte_string_fns.h>
  56 #include <rte_alarm.h>
  57 #include <rte_spinlock.h>
  58
  59 #include "nfp_net_pmd.h"
  60 #include "nfp_net_logs.h"
  61 #include "nfp_net_ctrl.h"
  62
  63 /* Prototypes */
  64 static void nfp_net_close(struct rte_eth_dev *dev);
  65 static int nfp_net_configure(struct rte_eth_dev *dev);
  66 static void nfp_net_dev_interrupt_handler(struct rte_intr_handle *handle,
  67                                           void *param);
  68 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  69 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  70 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  71                               struct rte_eth_dev_info *dev_info);
  72 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  73 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  74 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  75 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  76 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  77 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  78                                        uint16_t queue_idx);
  79 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  80                                   uint16_t nb_pkts);
  81 static void nfp_net_rx_queue_release(void *rxq);
  82 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  83                                   uint16_t nb_desc, unsigned int socket_id,
  84                                   const struct rte_eth_rxconf *rx_conf,
  85                                   struct rte_mempool *mp);
  86 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  87 static void nfp_net_tx_queue_release(void *txq);
  88 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  89                                   uint16_t nb_desc, unsigned int socket_id,
  90                                   const struct rte_eth_txconf *tx_conf);
  91 static int nfp_net_start(struct rte_eth_dev *dev);
  92 static void nfp_net_stats_get(struct rte_eth_dev *dev,
  93                               struct rte_eth_stats *stats);
  94 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
  95 static void nfp_net_stop(struct rte_eth_dev *dev);
  96 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  97                                   uint16_t nb_pkts);
  98
  99 /*
 100  * The offset of the queue controller queues in the PCIe Target. These
 101  * happen to be at the same offset on the NFP6000 and the NFP3200 so
 102  * we use a single macro here.
 103  */
 104 #define NFP_PCIE_QUEUE(_q)      (0x80000 + (0x800 * ((_q) & 0xff)))
 105
 106 /* Maximum value which can be added to a queue with one transaction */
 107 #define NFP_QCP_MAX_ADD 0x7f
 108
 109 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 110         (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
 111
 112 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 113 enum nfp_qcp_ptr {
 114         NFP_QCP_READ_PTR = 0,
 115         NFP_QCP_WRITE_PTR
 116 };
 117
 118 /*
 119  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 120  * @q: Base address for queue structure
 121  * @ptr: Add to the Read or Write pointer
 122  * @val: Value to add to the queue pointer
 123  *
 124  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 125  */
 126 static inline void
 127 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 128 {
 129         uint32_t off;
 130
 131         if (ptr == NFP_QCP_READ_PTR)
 132                 off = NFP_QCP_QUEUE_ADD_RPTR;
 133         else
 134                 off = NFP_QCP_QUEUE_ADD_WPTR;
 135
 136         while (val > NFP_QCP_MAX_ADD) {
 137                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 138                 val -= NFP_QCP_MAX_ADD;
 139         }
 140
 141         nn_writel(rte_cpu_to_le_32(val), q + off);
 142 }
 143
 144 /*
 145  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 146  * @q:  Base address for queue structure
 147  * @ptr: Read or Write pointer
 148  */
 149 static inline uint32_t
 150 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 151 {
 152         uint32_t off;
 153         uint32_t val;
 154
 155         if (ptr == NFP_QCP_READ_PTR)
 156                 off = NFP_QCP_QUEUE_STS_LO;
 157         else
 158                 off = NFP_QCP_QUEUE_STS_HI;
 159
 160         val = rte_cpu_to_le_32(nn_readl(q + off));
 161
 162         if (ptr == NFP_QCP_READ_PTR)
 163                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 164         else
 165                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 166 }
 167
 168 /*
 169  * Functions to read/write from/to Config BAR
 170  * Performs any endian conversion necessary.
 171  */
 172 static inline uint8_t
 173 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 174 {
 175         return nn_readb(hw->ctrl_bar + off);
 176 }
 177
 178 static inline void
 179 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 180 {
 181         nn_writeb(val, hw->ctrl_bar + off);
 182 }
 183
 184 static inline uint32_t
 185 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 186 {
 187         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 188 }
 189
 190 static inline void
 191 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 192 {
 193         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 194 }
 195
 196 static inline uint64_t
 197 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 198 {
 199         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 200 }
 201
 202 static inline void
 203 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 204 {
 205         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 206 }
 207
 208 /* Creating memzone for hardware rings. */
 209 static const struct rte_memzone *
 210 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
 211                       uint16_t queue_id, uint32_t ring_size, int socket_id)
 212 {
 213         char z_name[RTE_MEMZONE_NAMESIZE];
 214         const struct rte_memzone *mz;
 215
 216         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
 217                  dev->driver->pci_drv.driver.name,
 218                  ring_name, dev->data->port_id, queue_id);
 219
 220         mz = rte_memzone_lookup(z_name);
 221         if (mz)
 222                 return mz;
 223
 224         return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
 225                                            NFP_MEMZONE_ALIGN);
 226 }
 227
 228 /*
 229  * Atomically reads link status information from global structure rte_eth_dev.
 230  *
 231  * @param dev
 232  *   - Pointer to the structure rte_eth_dev to read from.
 233  *   - Pointer to the buffer to be saved with the link status.
 234  *
 235  * @return
 236  *   - On success, zero.
 237  *   - On failure, negative value.
 238  */
 239 static inline int
 240 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 241                                     struct rte_eth_link *link)
 242 {
 243         struct rte_eth_link *dst = link;
 244         struct rte_eth_link *src = &dev->data->dev_link;
 245
 246         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 247                                 *(uint64_t *)src) == 0)
 248                 return -1;
 249
 250         return 0;
 251 }
 252
 253 /*
 254  * Atomically writes the link status information into global
 255  * structure rte_eth_dev.
 256  *
 257  * @param dev
 258  *   - Pointer to the structure rte_eth_dev to read from.
 259  *   - Pointer to the buffer to be saved with the link status.
 260  *
 261  * @return
 262  *   - On success, zero.
 263  *   - On failure, negative value.
 264  */
 265 static inline int
 266 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 267                                      struct rte_eth_link *link)
 268 {
 269         struct rte_eth_link *dst = &dev->data->dev_link;
 270         struct rte_eth_link *src = link;
 271
 272         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 273                                 *(uint64_t *)src) == 0)
 274                 return -1;
 275
 276         return 0;
 277 }
 278
 279 static void
 280 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 281 {
 282         unsigned i;
 283
 284         if (rxq->rxbufs == NULL)
 285                 return;
 286
 287         for (i = 0; i < rxq->rx_count; i++) {
 288                 if (rxq->rxbufs[i].mbuf) {
 289                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 290                         rxq->rxbufs[i].mbuf = NULL;
 291                 }
 292         }
 293 }
 294
 295 static void
 296 nfp_net_rx_queue_release(void *rx_queue)
 297 {
 298         struct nfp_net_rxq *rxq = rx_queue;
 299
 300         if (rxq) {
 301                 nfp_net_rx_queue_release_mbufs(rxq);
 302                 rte_free(rxq->rxbufs);
 303                 rte_free(rxq);
 304         }
 305 }
 306
 307 static void
 308 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 309 {
 310         nfp_net_rx_queue_release_mbufs(rxq);
 311         rxq->rd_p = 0;
 312         rxq->nb_rx_hold = 0;
 313 }
 314
 315 static void
 316 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 317 {
 318         unsigned i;
 319
 320         if (txq->txbufs == NULL)
 321                 return;
 322
 323         for (i = 0; i < txq->tx_count; i++) {
 324                 if (txq->txbufs[i].mbuf) {
 325                         rte_pktmbuf_free(txq->txbufs[i].mbuf);
 326                         txq->txbufs[i].mbuf = NULL;
 327                 }
 328         }
 329 }
 330
 331 static void
 332 nfp_net_tx_queue_release(void *tx_queue)
 333 {
 334         struct nfp_net_txq *txq = tx_queue;
 335
 336         if (txq) {
 337                 nfp_net_tx_queue_release_mbufs(txq);
 338                 rte_free(txq->txbufs);
 339                 rte_free(txq);
 340         }
 341 }
 342
 343 static void
 344 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 345 {
 346         nfp_net_tx_queue_release_mbufs(txq);
 347         txq->wr_p = 0;
 348         txq->rd_p = 0;
 349 }
 350
 351 static int
 352 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 353 {
 354         int cnt;
 355         uint32_t new;
 356         struct timespec wait;
 357
 358         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
 359                     hw->qcp_cfg);
 360
 361         if (hw->qcp_cfg == NULL)
 362                 rte_panic("Bad configuration queue pointer\n");
 363
 364         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 365
 366         wait.tv_sec = 0;
 367         wait.tv_nsec = 1000000;
 368
 369         PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
 370
 371         /* Poll update field, waiting for NFP to ack the config */
 372         for (cnt = 0; ; cnt++) {
 373                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 374                 if (new == 0)
 375                         break;
 376                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 377                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x\n", new);
 378                         return -1;
 379                 }
 380                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 381                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 382                                           " %dms\n", update, cnt);
 383                         rte_panic("Exiting\n");
 384                 }
 385                 nanosleep(&wait, 0); /* waiting for a 1ms */
 386         }
 387         PMD_DRV_LOG(DEBUG, "Ack DONE\n");
 388         return 0;
 389 }
 390
 391 /*
 392  * Reconfigure the NIC
 393  * @nn:    device to reconfigure
 394  * @ctrl:    The value for the ctrl field in the BAR config
 395  * @update:  The value for the update field in the BAR config
 396  *
 397  * Write the update word to the BAR and ping the reconfig queue. Then poll
 398  * until the firmware has acknowledged the update by zeroing the update word.
 399  */
 400 static int
 401 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 402 {
 403         uint32_t err;
 404
 405         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
 406                     ctrl, update);
 407
 408         rte_spinlock_lock(&hw->reconfig_lock);
 409
 410         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 411         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 412
 413         rte_wmb();
 414
 415         err = __nfp_net_reconfig(hw, update);
 416
 417         rte_spinlock_unlock(&hw->reconfig_lock);
 418
 419         if (!err)
 420                 return 0;
 421
 422         /*
 423          * Reconfig errors imply situations where they can be handled.
 424          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 425          */
 426         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x\n",
 427                      ctrl, update);
 428         return -EIO;
 429 }
 430
 431 /*
 432  * Configure an Ethernet device. This function must be invoked first
 433  * before any other function in the Ethernet API. This function can
 434  * also be re-invoked when a device is in the stopped state.
 435  */
 436 static int
 437 nfp_net_configure(struct rte_eth_dev *dev)
 438 {
 439         struct rte_eth_conf *dev_conf;
 440         struct rte_eth_rxmode *rxmode;
 441         struct rte_eth_txmode *txmode;
 442         uint32_t new_ctrl = 0;
 443         uint32_t update = 0;
 444         struct nfp_net_hw *hw;
 445
 446         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 447
 448         /*
 449          * A DPDK app sends info about how many queues to use and how
 450          * those queues need to be configured. This is used by the
 451          * DPDK core and it makes sure no more queues than those
 452          * advertised by the driver are requested. This function is
 453          * called after that internal process
 454          */
 455
 456         PMD_INIT_LOG(DEBUG, "Configure\n");
 457
 458         dev_conf = &dev->data->dev_conf;
 459         rxmode = &dev_conf->rxmode;
 460         txmode = &dev_conf->txmode;
 461
 462         /* Checking TX mode */
 463         if (txmode->mq_mode) {
 464                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported\n");
 465                 return -EINVAL;
 466         }
 467
 468         /* Checking RX mode */
 469         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 470                 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
 471                         update = NFP_NET_CFG_UPDATE_RSS;
 472                         new_ctrl = NFP_NET_CFG_CTRL_RSS;
 473                 } else {
 474                         PMD_INIT_LOG(INFO, "RSS not supported\n");
 475                         return -EINVAL;
 476                 }
 477         }
 478
 479         if (rxmode->split_hdr_size) {
 480                 PMD_INIT_LOG(INFO, "rxmode does not support split header\n");
 481                 return -EINVAL;
 482         }
 483
 484         if (rxmode->hw_ip_checksum) {
 485                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
 486                         new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 487                 } else {
 488                         PMD_INIT_LOG(INFO, "RXCSUM not supported\n");
 489                         return -EINVAL;
 490                 }
 491         }
 492
 493         if (rxmode->hw_vlan_filter) {
 494                 PMD_INIT_LOG(INFO, "VLAN filter not supported\n");
 495                 return -EINVAL;
 496         }
 497
 498         if (rxmode->hw_vlan_strip) {
 499                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
 500                         new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 501                 } else {
 502                         PMD_INIT_LOG(INFO, "hw vlan strip not supported\n");
 503                         return -EINVAL;
 504                 }
 505         }
 506
 507         if (rxmode->hw_vlan_extend) {
 508                 PMD_INIT_LOG(INFO, "VLAN extended not supported\n");
 509                 return -EINVAL;
 510         }
 511
 512         /* Supporting VLAN insertion by default */
 513         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
 514                 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 515
 516         if (rxmode->jumbo_frame)
 517                 /* this is handled in rte_eth_dev_configure */
 518
 519         if (rxmode->hw_strip_crc) {
 520                 PMD_INIT_LOG(INFO, "strip CRC not supported\n");
 521                 return -EINVAL;
 522         }
 523
 524         if (rxmode->enable_scatter) {
 525                 PMD_INIT_LOG(INFO, "Scatter not supported\n");
 526                 return -EINVAL;
 527         }
 528
 529         if (!new_ctrl)
 530                 return 0;
 531
 532         update |= NFP_NET_CFG_UPDATE_GEN;
 533
 534         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 535         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 536                 return -EIO;
 537
 538         hw->ctrl = new_ctrl;
 539
 540         return 0;
 541 }
 542
 543 static void
 544 nfp_net_enable_queues(struct rte_eth_dev *dev)
 545 {
 546         struct nfp_net_hw *hw;
 547         uint64_t enabled_queues = 0;
 548         int i;
 549
 550         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 551
 552         /* Enabling the required TX queues in the device */
 553         for (i = 0; i < dev->data->nb_tx_queues; i++)
 554                 enabled_queues |= (1 << i);
 555
 556         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 557
 558         enabled_queues = 0;
 559
 560         /* Enabling the required RX queues in the device */
 561         for (i = 0; i < dev->data->nb_rx_queues; i++)
 562                 enabled_queues |= (1 << i);
 563
 564         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 565 }
 566
 567 static void
 568 nfp_net_disable_queues(struct rte_eth_dev *dev)
 569 {
 570         struct nfp_net_hw *hw;
 571         uint32_t new_ctrl, update = 0;
 572
 573         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 574
 575         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 576         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 577
 578         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 579         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 580                  NFP_NET_CFG_UPDATE_MSIX;
 581
 582         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 583                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 584
 585         /* If an error when reconfig we avoid to change hw state */
 586         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 587                 return;
 588
 589         hw->ctrl = new_ctrl;
 590 }
 591
 592 static int
 593 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 594 {
 595         int i;
 596
 597         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 598                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 599                         return -1;
 600         }
 601         return 0;
 602 }
 603
 604 static void
 605 nfp_net_params_setup(struct nfp_net_hw *hw)
 606 {
 607         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 608         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 609 }
 610
 611 static void
 612 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 613 {
 614         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 615 }
 616
 617 static void nfp_net_read_mac(struct nfp_net_hw *hw)
 618 {
 619         uint32_t tmp;
 620
 621         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 622         memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
 623
 624         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 625         memcpy(&hw->mac_addr[4], &tmp, 2);
 626 }
 627
 628 static int
 629 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 630                            struct rte_intr_handle *intr_handle)
 631 {
 632         struct nfp_net_hw *hw;
 633         int i;
 634
 635         if (!intr_handle->intr_vec) {
 636                 intr_handle->intr_vec =
 637                         rte_zmalloc("intr_vec",
 638                                     dev->data->nb_rx_queues * sizeof(int), 0);
 639                 if (!intr_handle->intr_vec) {
 640                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 641                                      " intr_vec\n", dev->data->nb_rx_queues);
 642                         return -ENOMEM;
 643                 }
 644         }
 645
 646         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 647
 648         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 649                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO\n");
 650                 /* UIO just supports one queue and no LSC*/
 651                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 652         } else {
 653                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO\n");
 654                 for (i = 0; i < dev->data->nb_rx_queues; i++)
 655                         /*
 656                          * The first msix vector is reserved for non
 657                          * efd interrupts
 658                         */
 659                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 660         }
 661
 662         /* Avoiding TX interrupts */
 663         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 664         return 0;
 665 }
 666
 667 static int
 668 nfp_net_start(struct rte_eth_dev *dev)
 669 {
 670         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
 671         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 672         uint32_t new_ctrl, update = 0;
 673         struct nfp_net_hw *hw;
 674         uint32_t intr_vector;
 675         int ret;
 676
 677         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 678
 679         PMD_INIT_LOG(DEBUG, "Start\n");
 680
 681         /* Disabling queues just in case... */
 682         nfp_net_disable_queues(dev);
 683
 684         /* Writing configuration parameters in the device */
 685         nfp_net_params_setup(hw);
 686
 687         /* Enabling the required queues in the device */
 688         nfp_net_enable_queues(dev);
 689
 690         /* check and configure queue intr-vector mapping */
 691         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 692                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 693                         /*
 694                          * Better not to share LSC with RX interrupts.
 695                          * Unregistering LSC interrupt handler
 696                          */
 697                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 698                                 nfp_net_dev_interrupt_handler, (void *)dev);
 699
 700                         if (dev->data->nb_rx_queues > 1) {
 701                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 702                                              "supports 1 queue with UIO");
 703                                 return -EIO;
 704                         }
 705                 }
 706                 intr_vector = dev->data->nb_rx_queues;
 707                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 708                         return -1;
 709         }
 710
 711         nfp_configure_rx_interrupt(dev, intr_handle);
 712
 713         rte_intr_enable(intr_handle);
 714
 715         /* Enable device */
 716         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
 717         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 718
 719         /* Just configuring queues interrupts when necessary */
 720         if (rte_intr_dp_is_en(intr_handle))
 721                 update |= NFP_NET_CFG_UPDATE_MSIX;
 722
 723         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 724                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 725
 726         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 727         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 728                 return -EIO;
 729
 730         /*
 731          * Allocating rte mbuffs for configured rx queues.
 732          * This requires queues being enabled before
 733          */
 734         if (nfp_net_rx_freelist_setup(dev) < 0) {
 735                 ret = -ENOMEM;
 736                 goto error;
 737         }
 738
 739         hw->ctrl = new_ctrl;
 740
 741         return 0;
 742
 743 error:
 744         /*
 745          * An error returned by this function should mean the app
 746          * exiting and then the system releasing all the memory
 747          * allocated even memory coming from hugepages.
 748          *
 749          * The device could be enabled at this point with some queues
 750          * ready for getting packets. This is true if the call to
 751          * nfp_net_rx_freelist_setup() succeeds for some queues but
 752          * fails for subsequent queues.
 753          *
 754          * This should make the app exiting but better if we tell the
 755          * device first.
 756          */
 757         nfp_net_disable_queues(dev);
 758
 759         return ret;
 760 }
 761
 762 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 763 static void
 764 nfp_net_stop(struct rte_eth_dev *dev)
 765 {
 766         int i;
 767
 768         PMD_INIT_LOG(DEBUG, "Stop\n");
 769
 770         nfp_net_disable_queues(dev);
 771
 772         /* Clear queues */
 773         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 774                 nfp_net_reset_tx_queue(
 775                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 776         }
 777
 778         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 779                 nfp_net_reset_rx_queue(
 780                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 781         }
 782 }
 783
 784 /* Reset and stop device. The device can not be restarted. */
 785 static void
 786 nfp_net_close(struct rte_eth_dev *dev)
 787 {
 788         struct nfp_net_hw *hw;
 789         struct rte_pci_device *pci_dev;
 790
 791         PMD_INIT_LOG(DEBUG, "Close\n");
 792
 793         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 794         pci_dev = RTE_DEV_TO_PCI(dev->device);
 795
 796         /*
 797          * We assume that the DPDK application is stopping all the
 798          * threads/queues before calling the device close function.
 799          */
 800
 801         nfp_net_stop(dev);
 802
 803         rte_intr_disable(&pci_dev->intr_handle);
 804         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 805
 806         /* unregister callback func from eal lib */
 807         rte_intr_callback_unregister(&pci_dev->intr_handle,
 808                                      nfp_net_dev_interrupt_handler,
 809                                      (void *)dev);
 810
 811         /*
 812          * The ixgbe PMD driver disables the pcie master on the
 813          * device. The i40e does not...
 814          */
 815 }
 816
 817 static void
 818 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 819 {
 820         uint32_t new_ctrl, update = 0;
 821         struct nfp_net_hw *hw;
 822
 823         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
 824
 825         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 826
 827         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 828                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported\n");
 829                 return;
 830         }
 831
 832         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 833                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
 834                 return;
 835         }
 836
 837         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 838         update = NFP_NET_CFG_UPDATE_GEN;
 839
 840         /*
 841          * DPDK sets promiscuous mode on just after this call assuming
 842          * it can not fail ...
 843          */
 844         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 845                 return;
 846
 847         hw->ctrl = new_ctrl;
 848 }
 849
 850 static void
 851 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 852 {
 853         uint32_t new_ctrl, update = 0;
 854         struct nfp_net_hw *hw;
 855
 856         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 857
 858         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 859                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
 860                 return;
 861         }
 862
 863         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 864         update = NFP_NET_CFG_UPDATE_GEN;
 865
 866         /*
 867          * DPDK sets promiscuous mode off just before this call
 868          * assuming it can not fail ...
 869          */
 870         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 871                 return;
 872
 873         hw->ctrl = new_ctrl;
 874 }
 875
 876 /*
 877  * return 0 means link status changed, -1 means not changed
 878  *
 879  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 880  * status.
 881  */
 882 static int
 883 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 884 {
 885         struct nfp_net_hw *hw;
 886         struct rte_eth_link link, old;
 887         uint32_t nn_link_status;
 888
 889         static const uint32_t ls_to_ethtool[] = {
 890                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 891                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 892                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 893                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 894                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 895                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 896                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 897                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 898         };
 899
 900         PMD_DRV_LOG(DEBUG, "Link update\n");
 901
 902         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 903
 904         memset(&old, 0, sizeof(old));
 905         nfp_net_dev_atomic_read_link_status(dev, &old);
 906
 907         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 908
 909         memset(&link, 0, sizeof(struct rte_eth_link));
 910
 911         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 912                 link.link_status = ETH_LINK_UP;
 913
 914         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 915
 916         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 917                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 918
 919         if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
 920             ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
 921             (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
 922                 /* We really do not know the speed wil old firmware */
 923                 link.link_speed = ETH_SPEED_NUM_NONE;
 924         else {
 925                 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 926                         link.link_speed = ETH_SPEED_NUM_NONE;
 927                 else
 928                         link.link_speed = ls_to_ethtool[nn_link_status];
 929         }
 930
 931         if (old.link_status != link.link_status) {
 932                 nfp_net_dev_atomic_write_link_status(dev, &link);
 933                 if (link.link_status)
 934                         PMD_DRV_LOG(INFO, "NIC Link is Up\n");
 935                 else
 936                         PMD_DRV_LOG(INFO, "NIC Link is Down\n");
 937                 return 0;
 938         }
 939
 940         return -1;
 941 }
 942
 943 static void
 944 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 945 {
 946         int i;
 947         struct nfp_net_hw *hw;
 948         struct rte_eth_stats nfp_dev_stats;
 949
 950         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951
 952         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
 953
 954         /* reading per RX ring stats */
 955         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 956                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 957                         break;
 958
 959                 nfp_dev_stats.q_ipackets[i] =
 960                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
 961
 962                 nfp_dev_stats.q_ipackets[i] -=
 963                         hw->eth_stats_base.q_ipackets[i];
 964
 965                 nfp_dev_stats.q_ibytes[i] =
 966                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
 967
 968                 nfp_dev_stats.q_ibytes[i] -=
 969                         hw->eth_stats_base.q_ibytes[i];
 970         }
 971
 972         /* reading per TX ring stats */
 973         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 974                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 975                         break;
 976
 977                 nfp_dev_stats.q_opackets[i] =
 978                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
 979
 980                 nfp_dev_stats.q_opackets[i] -=
 981                         hw->eth_stats_base.q_opackets[i];
 982
 983                 nfp_dev_stats.q_obytes[i] =
 984                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
 985
 986                 nfp_dev_stats.q_obytes[i] -=
 987                         hw->eth_stats_base.q_obytes[i];
 988         }
 989
 990         nfp_dev_stats.ipackets =
 991                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
 992
 993         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
 994
 995         nfp_dev_stats.ibytes =
 996                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
 997
 998         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
 999
1000         nfp_dev_stats.opackets =
1001                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1002
1003         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1004
1005         nfp_dev_stats.obytes =
1006                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1007
1008         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1009
1010         /* reading general device stats */
1011         nfp_dev_stats.ierrors =
1012                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1013
1014         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1015
1016         nfp_dev_stats.oerrors =
1017                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1018
1019         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1020
1021         /* RX ring mbuf allocation failures */
1022         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1023
1024         nfp_dev_stats.imissed =
1025                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1026
1027         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1028
1029         if (stats)
1030                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1031 }
1032
1033 static void
1034 nfp_net_stats_reset(struct rte_eth_dev *dev)
1035 {
1036         int i;
1037         struct nfp_net_hw *hw;
1038
1039         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1040
1041         /*
1042          * hw->eth_stats_base records the per counter starting point.
1043          * Lets update it now
1044          */
1045
1046         /* reading per RX ring stats */
1047         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1048                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1049                         break;
1050
1051                 hw->eth_stats_base.q_ipackets[i] =
1052                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1053
1054                 hw->eth_stats_base.q_ibytes[i] =
1055                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1056         }
1057
1058         /* reading per TX ring stats */
1059         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1060                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1061                         break;
1062
1063                 hw->eth_stats_base.q_opackets[i] =
1064                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1065
1066                 hw->eth_stats_base.q_obytes[i] =
1067                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1068         }
1069
1070         hw->eth_stats_base.ipackets =
1071                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1072
1073         hw->eth_stats_base.ibytes =
1074                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1075
1076         hw->eth_stats_base.opackets =
1077                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1078
1079         hw->eth_stats_base.obytes =
1080                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1081
1082         /* reading general device stats */
1083         hw->eth_stats_base.ierrors =
1084                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1085
1086         hw->eth_stats_base.oerrors =
1087                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1088
1089         /* RX ring mbuf allocation failures */
1090         dev->data->rx_mbuf_alloc_failed = 0;
1091
1092         hw->eth_stats_base.imissed =
1093                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1094 }
1095
1096 static void
1097 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1098 {
1099         struct nfp_net_hw *hw;
1100
1101         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1102
1103         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1104         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1105         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1106         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1107         dev_info->max_rx_pktlen = hw->mtu;
1108         /* Next should change when PF support is implemented */
1109         dev_info->max_mac_addrs = 1;
1110
1111         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1112                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1113
1114         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1115                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1116                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1117                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1118
1119         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1120                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1121
1122         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1123                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1124                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1125                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1126
1127         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1128                 .rx_thresh = {
1129                         .pthresh = DEFAULT_RX_PTHRESH,
1130                         .hthresh = DEFAULT_RX_HTHRESH,
1131                         .wthresh = DEFAULT_RX_WTHRESH,
1132                 },
1133                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1134                 .rx_drop_en = 0,
1135         };
1136
1137         dev_info->default_txconf = (struct rte_eth_txconf) {
1138                 .tx_thresh = {
1139                         .pthresh = DEFAULT_TX_PTHRESH,
1140                         .hthresh = DEFAULT_TX_HTHRESH,
1141                         .wthresh = DEFAULT_TX_WTHRESH,
1142                 },
1143                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1144                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1145                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1146                              ETH_TXQ_FLAGS_NOOFFLOADS,
1147         };
1148
1149         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1150         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1151
1152         dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1153                                ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1154                                ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1155 }
1156
1157 static const uint32_t *
1158 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1159 {
1160         static const uint32_t ptypes[] = {
1161                 /* refers to nfp_net_set_hash() */
1162                 RTE_PTYPE_INNER_L3_IPV4,
1163                 RTE_PTYPE_INNER_L3_IPV6,
1164                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1165                 RTE_PTYPE_INNER_L4_MASK,
1166                 RTE_PTYPE_UNKNOWN
1167         };
1168
1169         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1170                 return ptypes;
1171         return NULL;
1172 }
1173
1174 static uint32_t
1175 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1176 {
1177         struct nfp_net_rxq *rxq;
1178         struct nfp_net_rx_desc *rxds;
1179         uint32_t idx;
1180         uint32_t count;
1181
1182         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1183
1184         if (rxq == NULL) {
1185                 PMD_INIT_LOG(ERR, "Bad queue: %u\n", queue_idx);
1186                 return 0;
1187         }
1188
1189         idx = rxq->rd_p;
1190
1191         count = 0;
1192
1193         /*
1194          * Other PMDs are just checking the DD bit in intervals of 4
1195          * descriptors and counting all four if the first has the DD
1196          * bit on. Of course, this is not accurate but can be good for
1197          * perfomance. But ideally that should be done in descriptors
1198          * chunks belonging to the same cache line
1199          */
1200
1201         while (count < rxq->rx_count) {
1202                 rxds = &rxq->rxds[idx];
1203                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1204                         break;
1205
1206                 count++;
1207                 idx++;
1208
1209                 /* Wrapping? */
1210                 if ((idx) == rxq->rx_count)
1211                         idx = 0;
1212         }
1213
1214         return count;
1215 }
1216
1217 static int
1218 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1219 {
1220         struct rte_pci_device *pci_dev;
1221         struct nfp_net_hw *hw;
1222         int base = 0;
1223
1224         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1225         pci_dev = RTE_DEV_TO_PCI(dev->device);
1226
1227         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1228                 base = 1;
1229
1230         /* Make sure all updates are written before un-masking */
1231         rte_wmb();
1232         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1233                       NFP_NET_CFG_ICR_UNMASKED);
1234         return 0;
1235 }
1236
1237 static int
1238 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1239 {
1240         struct rte_pci_device *pci_dev;
1241         struct nfp_net_hw *hw;
1242         int base = 0;
1243
1244         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245         pci_dev = RTE_DEV_TO_PCI(dev->device);
1246
1247         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1248                 base = 1;
1249
1250         /* Make sure all updates are written before un-masking */
1251         rte_wmb();
1252         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1253         return 0;
1254 }
1255
1256 static void
1257 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1258 {
1259         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1260         struct rte_eth_link link;
1261
1262         memset(&link, 0, sizeof(link));
1263         nfp_net_dev_atomic_read_link_status(dev, &link);
1264         if (link.link_status)
1265                 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1266                         (int)(dev->data->port_id), (unsigned)link.link_speed,
1267                         link.link_duplex == ETH_LINK_FULL_DUPLEX
1268                         ? "full-duplex" : "half-duplex");
1269         else
1270                 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1271                         (int)(dev->data->port_id));
1272
1273         RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1274                 pci_dev->addr.domain, pci_dev->addr.bus,
1275                 pci_dev->addr.devid, pci_dev->addr.function);
1276 }
1277
1278 /* Interrupt configuration and handling */
1279
1280 /*
1281  * nfp_net_irq_unmask - Unmask an interrupt
1282  *
1283  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1284  * clear the ICR for the entry.
1285  */
1286 static void
1287 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1288 {
1289         struct nfp_net_hw *hw;
1290         struct rte_pci_device *pci_dev;
1291
1292         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1293         pci_dev = RTE_DEV_TO_PCI(dev->device);
1294
1295         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1296                 /* If MSI-X auto-masking is used, clear the entry */
1297                 rte_wmb();
1298                 rte_intr_enable(&pci_dev->intr_handle);
1299         } else {
1300                 /* Make sure all updates are written before un-masking */
1301                 rte_wmb();
1302                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1303                               NFP_NET_CFG_ICR_UNMASKED);
1304         }
1305 }
1306
1307 static void
1308 nfp_net_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1309                               void *param)
1310 {
1311         int64_t timeout;
1312         struct rte_eth_link link;
1313         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1314
1315         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1316
1317         /* get the link status */
1318         memset(&link, 0, sizeof(link));
1319         nfp_net_dev_atomic_read_link_status(dev, &link);
1320
1321         nfp_net_link_update(dev, 0);
1322
1323         /* likely to up */
1324         if (!link.link_status) {
1325                 /* handle it 1 sec later, wait it being stable */
1326                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1327                 /* likely to down */
1328         } else {
1329                 /* handle it 4 sec later, wait it being stable */
1330                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1331         }
1332
1333         if (rte_eal_alarm_set(timeout * 1000,
1334                               nfp_net_dev_interrupt_delayed_handler,
1335                               (void *)dev) < 0) {
1336                 RTE_LOG(ERR, PMD, "Error setting alarm");
1337                 /* Unmasking */
1338                 nfp_net_irq_unmask(dev);
1339         }
1340 }
1341
1342 /*
1343  * Interrupt handler which shall be registered for alarm callback for delayed
1344  * handling specific interrupt to wait for the stable nic state. As the NIC
1345  * interrupt state is not stable for nfp after link is just down, it needs
1346  * to wait 4 seconds to get the stable status.
1347  *
1348  * @param handle   Pointer to interrupt handle.
1349  * @param param    The address of parameter (struct rte_eth_dev *)
1350  *
1351  * @return  void
1352  */
1353 static void
1354 nfp_net_dev_interrupt_delayed_handler(void *param)
1355 {
1356         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1357
1358         nfp_net_link_update(dev, 0);
1359         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1360
1361         nfp_net_dev_link_status_print(dev);
1362
1363         /* Unmasking */
1364         nfp_net_irq_unmask(dev);
1365 }
1366
1367 static int
1368 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1369 {
1370         struct nfp_net_hw *hw;
1371
1372         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373
1374         /* check that mtu is within the allowed range */
1375         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1376                 return -EINVAL;
1377
1378         /* switch to jumbo mode if needed */
1379         if ((uint32_t)mtu > ETHER_MAX_LEN)
1380                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1381         else
1382                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1383
1384         /* update max frame size */
1385         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1386
1387         /* writing to configuration space */
1388         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1389
1390         hw->mtu = mtu;
1391
1392         return 0;
1393 }
1394
1395 static int
1396 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1397                        uint16_t queue_idx, uint16_t nb_desc,
1398                        unsigned int socket_id,
1399                        const struct rte_eth_rxconf *rx_conf,
1400                        struct rte_mempool *mp)
1401 {
1402         const struct rte_memzone *tz;
1403         struct nfp_net_rxq *rxq;
1404         struct nfp_net_hw *hw;
1405
1406         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1407
1408         PMD_INIT_FUNC_TRACE();
1409
1410         /* Validating number of descriptors */
1411         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1412             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1413             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1414                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1415                 return -EINVAL;
1416         }
1417
1418         /*
1419          * Free memory prior to re-allocation if needed. This is the case after
1420          * calling nfp_net_stop
1421          */
1422         if (dev->data->rx_queues[queue_idx]) {
1423                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1424                 dev->data->rx_queues[queue_idx] = NULL;
1425         }
1426
1427         /* Allocating rx queue data structure */
1428         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1429                                  RTE_CACHE_LINE_SIZE, socket_id);
1430         if (rxq == NULL)
1431                 return -ENOMEM;
1432
1433         /* Hw queues mapping based on firmware confifguration */
1434         rxq->qidx = queue_idx;
1435         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1436         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1437         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1438         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1439
1440         /*
1441          * Tracking mbuf size for detecting a potential mbuf overflow due to
1442          * RX offset
1443          */
1444         rxq->mem_pool = mp;
1445         rxq->mbuf_size = rxq->mem_pool->elt_size;
1446         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1447         hw->flbufsz = rxq->mbuf_size;
1448
1449         rxq->rx_count = nb_desc;
1450         rxq->port_id = dev->data->port_id;
1451         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1452         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1453                                   : ETHER_CRC_LEN);
1454         rxq->drop_en = rx_conf->rx_drop_en;
1455
1456         /*
1457          * Allocate RX ring hardware descriptors. A memzone large enough to
1458          * handle the maximum ring size is allocated in order to allow for
1459          * resizing in later calls to the queue setup function.
1460          */
1461         tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1462                                    sizeof(struct nfp_net_rx_desc) *
1463                                    NFP_NET_MAX_RX_DESC, socket_id);
1464
1465         if (tz == NULL) {
1466                 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1467                 nfp_net_rx_queue_release(rxq);
1468                 return -ENOMEM;
1469         }
1470
1471         /* Saving physical and virtual addresses for the RX ring */
1472         rxq->dma = (uint64_t)tz->phys_addr;
1473         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1474
1475         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1476         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1477                                          sizeof(*rxq->rxbufs) * nb_desc,
1478                                          RTE_CACHE_LINE_SIZE, socket_id);
1479         if (rxq->rxbufs == NULL) {
1480                 nfp_net_rx_queue_release(rxq);
1481                 return -ENOMEM;
1482         }
1483
1484         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1485                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1486
1487         nfp_net_reset_rx_queue(rxq);
1488
1489         dev->data->rx_queues[queue_idx] = rxq;
1490         rxq->hw = hw;
1491
1492         /*
1493          * Telling the HW about the physical address of the RX ring and number
1494          * of descriptors in log2 format
1495          */
1496         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1497         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1498
1499         return 0;
1500 }
1501
1502 static int
1503 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1504 {
1505         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1506         uint64_t dma_addr;
1507         unsigned i;
1508
1509         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1510                    rxq->rx_count);
1511
1512         for (i = 0; i < rxq->rx_count; i++) {
1513                 struct nfp_net_rx_desc *rxd;
1514                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1515
1516                 if (mbuf == NULL) {
1517                         RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1518                                 (unsigned)rxq->qidx);
1519                         return -ENOMEM;
1520                 }
1521
1522                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1523
1524                 rxd = &rxq->rxds[i];
1525                 rxd->fld.dd = 0;
1526                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1527                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1528                 rxe[i].mbuf = mbuf;
1529                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1530         }
1531
1532         /* Make sure all writes are flushed before telling the hardware */
1533         rte_wmb();
1534
1535         /* Not advertising the whole ring as the firmware gets confused if so */
1536         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1537                    rxq->rx_count - 1);
1538
1539         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1540
1541         return 0;
1542 }
1543
1544 static int
1545 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1546                        uint16_t nb_desc, unsigned int socket_id,
1547                        const struct rte_eth_txconf *tx_conf)
1548 {
1549         const struct rte_memzone *tz;
1550         struct nfp_net_txq *txq;
1551         uint16_t tx_free_thresh;
1552         struct nfp_net_hw *hw;
1553
1554         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555
1556         PMD_INIT_FUNC_TRACE();
1557
1558         /* Validating number of descriptors */
1559         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1560             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1561             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1562                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1563                 return -EINVAL;
1564         }
1565
1566         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1567                                     tx_conf->tx_free_thresh :
1568                                     DEFAULT_TX_FREE_THRESH);
1569
1570         if (tx_free_thresh > (nb_desc)) {
1571                 RTE_LOG(ERR, PMD,
1572                         "tx_free_thresh must be less than the number of TX "
1573                         "descriptors. (tx_free_thresh=%u port=%d "
1574                         "queue=%d)\n", (unsigned int)tx_free_thresh,
1575                         (int)dev->data->port_id, (int)queue_idx);
1576                 return -(EINVAL);
1577         }
1578
1579         /*
1580          * Free memory prior to re-allocation if needed. This is the case after
1581          * calling nfp_net_stop
1582          */
1583         if (dev->data->tx_queues[queue_idx]) {
1584                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1585                            queue_idx);
1586                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1587                 dev->data->tx_queues[queue_idx] = NULL;
1588         }
1589
1590         /* Allocating tx queue data structure */
1591         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1592                                  RTE_CACHE_LINE_SIZE, socket_id);
1593         if (txq == NULL) {
1594                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1595                 return -ENOMEM;
1596         }
1597
1598         /*
1599          * Allocate TX ring hardware descriptors. A memzone large enough to
1600          * handle the maximum ring size is allocated in order to allow for
1601          * resizing in later calls to the queue setup function.
1602          */
1603         tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1604                                    sizeof(struct nfp_net_tx_desc) *
1605                                    NFP_NET_MAX_TX_DESC, socket_id);
1606         if (tz == NULL) {
1607                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1608                 nfp_net_tx_queue_release(txq);
1609                 return -ENOMEM;
1610         }
1611
1612         txq->tx_count = nb_desc;
1613         txq->tx_free_thresh = tx_free_thresh;
1614         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1615         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1616         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1617
1618         /* queue mapping based on firmware configuration */
1619         txq->qidx = queue_idx;
1620         txq->tx_qcidx = queue_idx * hw->stride_tx;
1621         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1622
1623         txq->port_id = dev->data->port_id;
1624         txq->txq_flags = tx_conf->txq_flags;
1625
1626         /* Saving physical and virtual addresses for the TX ring */
1627         txq->dma = (uint64_t)tz->phys_addr;
1628         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1629
1630         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1631         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1632                                          sizeof(*txq->txbufs) * nb_desc,
1633                                          RTE_CACHE_LINE_SIZE, socket_id);
1634         if (txq->txbufs == NULL) {
1635                 nfp_net_tx_queue_release(txq);
1636                 return -ENOMEM;
1637         }
1638         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1639                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1640
1641         nfp_net_reset_tx_queue(txq);
1642
1643         dev->data->tx_queues[queue_idx] = txq;
1644         txq->hw = hw;
1645
1646         /*
1647          * Telling the HW about the physical address of the TX ring and number
1648          * of descriptors in log2 format
1649          */
1650         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1651         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1652
1653         return 0;
1654 }
1655
1656 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1657 static inline void
1658 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1659                  struct rte_mbuf *mb)
1660 {
1661         uint64_t ol_flags;
1662         struct nfp_net_hw *hw = txq->hw;
1663
1664         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1665                 return;
1666
1667         ol_flags = mb->ol_flags;
1668
1669         /* IPv6 does not need checksum */
1670         if (ol_flags & PKT_TX_IP_CKSUM)
1671                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1672
1673         switch (ol_flags & PKT_TX_L4_MASK) {
1674         case PKT_TX_UDP_CKSUM:
1675                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1676                 break;
1677         case PKT_TX_TCP_CKSUM:
1678                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1679                 break;
1680         }
1681
1682         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1683                 txd->flags |= PCIE_DESC_TX_CSUM;
1684 }
1685
1686 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1687 static inline void
1688 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1689                  struct rte_mbuf *mb)
1690 {
1691         struct nfp_net_hw *hw = rxq->hw;
1692
1693         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1694                 return;
1695
1696         /* If IPv4 and IP checksum error, fail */
1697         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1698             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1699                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1700
1701         /* If neither UDP nor TCP return */
1702         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1703             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1704                 return;
1705
1706         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1707             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1708                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1709
1710         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1711             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1712                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1713 }
1714
1715 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1716 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1717
1718 /*
1719  * nfp_net_set_hash - Set mbuf hash data
1720  *
1721  * The RSS hash and hash-type are pre-pended to the packet data.
1722  * Extract and decode it and set the mbuf fields.
1723  */
1724 static inline void
1725 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1726                  struct rte_mbuf *mbuf)
1727 {
1728         uint32_t hash;
1729         uint32_t hash_type;
1730         struct nfp_net_hw *hw = rxq->hw;
1731
1732         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1733                 return;
1734
1735         if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1736                 return;
1737
1738         hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1739         hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1740
1741         mbuf->hash.rss = hash;
1742         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1743
1744         switch (hash_type) {
1745         case NFP_NET_RSS_IPV4:
1746                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1747                 break;
1748         case NFP_NET_RSS_IPV6:
1749                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1750                 break;
1751         case NFP_NET_RSS_IPV6_EX:
1752                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1753                 break;
1754         default:
1755                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1756         }
1757 }
1758
1759 static inline void
1760 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1761 {
1762         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1763 }
1764
1765 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1766
1767 /*
1768  * RX path design:
1769  *
1770  * There are some decissions to take:
1771  * 1) How to check DD RX descriptors bit
1772  * 2) How and when to allocate new mbufs
1773  *
1774  * Current implementation checks just one single DD bit each loop. As each
1775  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1776  * a single cache line instead. Tests with this change have not shown any
1777  * performance improvement but it requires further investigation. For example,
1778  * depending on which descriptor is next, the number of descriptors could be
1779  * less than 8 for just checking those in the same cache line. This implies
1780  * extra work which could be counterproductive by itself. Indeed, last firmware
1781  * changes are just doing this: writing several descriptors with the DD bit
1782  * for saving PCIe bandwidth and DMA operations from the NFP.
1783  *
1784  * Mbuf allocation is done when a new packet is received. Then the descriptor
1785  * is automatically linked with the new mbuf and the old one is given to the
1786  * user. The main drawback with this design is mbuf allocation is heavier than
1787  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1788  * cache point of view it does not seem allocating the mbuf early on as we are
1789  * doing now have any benefit at all. Again, tests with this change have not
1790  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1791  * so looking at the implications of this type of allocation should be studied
1792  * deeply
1793  */
1794
1795 static uint16_t
1796 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1797 {
1798         struct nfp_net_rxq *rxq;
1799         struct nfp_net_rx_desc *rxds;
1800         struct nfp_net_rx_buff *rxb;
1801         struct nfp_net_hw *hw;
1802         struct rte_mbuf *mb;
1803         struct rte_mbuf *new_mb;
1804         uint16_t nb_hold;
1805         uint64_t dma_addr;
1806         int avail;
1807
1808         rxq = rx_queue;
1809         if (unlikely(rxq == NULL)) {
1810                 /*
1811                  * DPDK just checks the queue is lower than max queues
1812                  * enabled. But the queue needs to be configured
1813                  */
1814                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1815                 return -EINVAL;
1816         }
1817
1818         hw = rxq->hw;
1819         avail = 0;
1820         nb_hold = 0;
1821
1822         while (avail < nb_pkts) {
1823                 rxb = &rxq->rxbufs[rxq->rd_p];
1824                 if (unlikely(rxb == NULL)) {
1825                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1826                         break;
1827                 }
1828
1829                 /*
1830                  * Memory barrier to ensure that we won't do other
1831                  * reads before the DD bit.
1832                  */
1833                 rte_rmb();
1834
1835                 rxds = &rxq->rxds[rxq->rd_p];
1836                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1837                         break;
1838
1839                 /*
1840                  * We got a packet. Let's alloc a new mbuff for refilling the
1841                  * free descriptor ring as soon as possible
1842                  */
1843                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1844                 if (unlikely(new_mb == NULL)) {
1845                         RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1846                                 "queue_id=%u\n", (unsigned)rxq->port_id,
1847                                 (unsigned)rxq->qidx);
1848                         nfp_net_mbuf_alloc_failed(rxq);
1849                         break;
1850                 }
1851
1852                 nb_hold++;
1853
1854                 /*
1855                  * Grab the mbuff and refill the descriptor with the
1856                  * previously allocated mbuff
1857                  */
1858                 mb = rxb->mbuf;
1859                 rxb->mbuf = new_mb;
1860
1861                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1862                            rxds->rxd.data_len, rxq->mbuf_size);
1863
1864                 /* Size of this segment */
1865                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1866                 /* Size of the whole packet. We just support 1 segment */
1867                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1868
1869                 if (unlikely((mb->data_len + hw->rx_offset) >
1870                              rxq->mbuf_size)) {
1871                         /*
1872                          * This should not happen and the user has the
1873                          * responsibility of avoiding it. But we have
1874                          * to give some info about the error
1875                          */
1876                         RTE_LOG_DP(ERR, PMD,
1877                                 "mbuf overflow likely due to the RX offset.\n"
1878                                 "\t\tYour mbuf size should have extra space for"
1879                                 " RX offset=%u bytes.\n"
1880                                 "\t\tCurrently you just have %u bytes available"
1881                                 " but the received packet is %u bytes long",
1882                                 hw->rx_offset,
1883                                 rxq->mbuf_size - hw->rx_offset,
1884                                 mb->data_len);
1885                         return -EINVAL;
1886                 }
1887
1888                 /* Filling the received mbuff with packet info */
1889                 if (hw->rx_offset)
1890                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1891                 else
1892                         mb->data_off = RTE_PKTMBUF_HEADROOM +
1893                                        NFP_DESC_META_LEN(rxds);
1894
1895                 /* No scatter mode supported */
1896                 mb->nb_segs = 1;
1897                 mb->next = NULL;
1898
1899                 /* Checking the RSS flag */
1900                 nfp_net_set_hash(rxq, rxds, mb);
1901
1902                 /* Checking the checksum flag */
1903                 nfp_net_rx_cksum(rxq, rxds, mb);
1904
1905                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1906                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1907                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1908                         mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1909                 }
1910
1911                 /* Adding the mbuff to the mbuff array passed by the app */
1912                 rx_pkts[avail++] = mb;
1913
1914                 /* Now resetting and updating the descriptor */
1915                 rxds->vals[0] = 0;
1916                 rxds->vals[1] = 0;
1917                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1918                 rxds->fld.dd = 0;
1919                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1920                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1921
1922                 rxq->rd_p++;
1923                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
1924                         rxq->rd_p = 0;
1925         }
1926
1927         if (nb_hold == 0)
1928                 return nb_hold;
1929
1930         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received\n",
1931                    (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1932
1933         nb_hold += rxq->nb_rx_hold;
1934
1935         /*
1936          * FL descriptors needs to be written before incrementing the
1937          * FL queue WR pointer
1938          */
1939         rte_wmb();
1940         if (nb_hold > rxq->rx_free_thresh) {
1941                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1942                            (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1943                            (unsigned)nb_hold, (unsigned)avail);
1944                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1945                 nb_hold = 0;
1946         }
1947         rxq->nb_rx_hold = nb_hold;
1948
1949         return avail;
1950 }
1951
1952 /*
1953  * nfp_net_tx_free_bufs - Check for descriptors with a complete
1954  * status
1955  * @txq: TX queue to work with
1956  * Returns number of descriptors freed
1957  */
1958 int
1959 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1960 {
1961         uint32_t qcp_rd_p;
1962         int todo;
1963
1964         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1965                    " status\n", txq->qidx);
1966
1967         /* Work out how many packets have been sent */
1968         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1969
1970         if (qcp_rd_p == txq->rd_p) {
1971                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1972                            "packets (%u, %u)\n", txq->qidx,
1973                            qcp_rd_p, txq->rd_p);
1974                 return 0;
1975         }
1976
1977         if (qcp_rd_p > txq->rd_p)
1978                 todo = qcp_rd_p - txq->rd_p;
1979         else
1980                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
1981
1982         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
1983                    qcp_rd_p, txq->rd_p, txq->rd_p);
1984
1985         if (todo == 0)
1986                 return todo;
1987
1988         txq->rd_p += todo;
1989         if (unlikely(txq->rd_p >= txq->tx_count))
1990                 txq->rd_p -= txq->tx_count;
1991
1992         return todo;
1993 }
1994
1995 /* Leaving always free descriptors for avoiding wrapping confusion */
1996 static inline
1997 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
1998 {
1999         if (txq->wr_p >= txq->rd_p)
2000                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2001         else
2002                 return txq->rd_p - txq->wr_p - 8;
2003 }
2004
2005 /*
2006  * nfp_net_txq_full - Check if the TX queue free descriptors
2007  * is below tx_free_threshold
2008  *
2009  * @txq: TX queue to check
2010  *
2011  * This function uses the host copy* of read/write pointers
2012  */
2013 static inline
2014 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2015 {
2016         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2017 }
2018
2019 static uint16_t
2020 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2021 {
2022         struct nfp_net_txq *txq;
2023         struct nfp_net_hw *hw;
2024         struct nfp_net_tx_desc *txds;
2025         struct rte_mbuf *pkt;
2026         uint64_t dma_addr;
2027         int pkt_size, dma_size;
2028         uint16_t free_descs, issued_descs;
2029         struct rte_mbuf **lmbuf;
2030         int i;
2031
2032         txq = tx_queue;
2033         hw = txq->hw;
2034         txds = &txq->txds[txq->wr_p];
2035
2036         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2037                    txq->qidx, txq->wr_p, nb_pkts);
2038
2039         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2040                 nfp_net_tx_free_bufs(txq);
2041
2042         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2043         if (unlikely(free_descs == 0))
2044                 return 0;
2045
2046         pkt = *tx_pkts;
2047
2048         i = 0;
2049         issued_descs = 0;
2050         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2051                    txq->qidx, nb_pkts);
2052         /* Sending packets */
2053         while ((i < nb_pkts) && free_descs) {
2054                 /* Grabbing the mbuf linked to the current descriptor */
2055                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2056                 /* Warming the cache for releasing the mbuf later on */
2057                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2058
2059                 pkt = *(tx_pkts + i);
2060
2061                 if (unlikely((pkt->nb_segs > 1) &&
2062                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2063                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set\n");
2064                         rte_panic("Multisegment packet unsupported\n");
2065                 }
2066
2067                 /* Checking if we have enough descriptors */
2068                 if (unlikely(pkt->nb_segs > free_descs))
2069                         goto xmit_end;
2070
2071                 /*
2072                  * Checksum and VLAN flags just in the first descriptor for a
2073                  * multisegment packet
2074                  */
2075                 nfp_net_tx_cksum(txq, txds, pkt);
2076
2077                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2078                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2079                         txds->flags |= PCIE_DESC_TX_VLAN;
2080                         txds->vlan = pkt->vlan_tci;
2081                 }
2082
2083                 if (pkt->ol_flags & PKT_TX_TCP_SEG)
2084                         rte_panic("TSO is not supported\n");
2085
2086                 /*
2087                  * mbuf data_len is the data in one segment and pkt_len data
2088                  * in the whole packet. When the packet is just one segment,
2089                  * then data_len = pkt_len
2090                  */
2091                 pkt_size = pkt->pkt_len;
2092
2093                 /* Releasing mbuf which was prefetched above */
2094                 if (*lmbuf)
2095                         rte_pktmbuf_free(*lmbuf);
2096                 /*
2097                  * Linking mbuf with descriptor for being released
2098                  * next time descriptor is used
2099                  */
2100                 *lmbuf = pkt;
2101
2102                 while (pkt_size) {
2103                         dma_size = pkt->data_len;
2104                         dma_addr = rte_mbuf_data_dma_addr(pkt);
2105                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2106                                    "%" PRIx64 "\n", dma_addr);
2107
2108                         /* Filling descriptors fields */
2109                         txds->dma_len = dma_size;
2110                         txds->data_len = pkt->pkt_len;
2111                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2112                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2113                         ASSERT(free_descs > 0);
2114                         free_descs--;
2115
2116                         txq->wr_p++;
2117                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2118                                 txq->wr_p = 0;
2119
2120                         pkt_size -= dma_size;
2121                         if (!pkt_size) {
2122                                 /* End of packet */
2123                                 txds->offset_eop |= PCIE_DESC_TX_EOP;
2124                         } else {
2125                                 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2126                                 pkt = pkt->next;
2127                         }
2128                         /* Referencing next free TX descriptor */
2129                         txds = &txq->txds[txq->wr_p];
2130                         issued_descs++;
2131                 }
2132                 i++;
2133         }
2134
2135 xmit_end:
2136         /* Increment write pointers. Force memory write before we let HW know */
2137         rte_wmb();
2138         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2139
2140         return i;
2141 }
2142
2143 static void
2144 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2145 {
2146         uint32_t new_ctrl, update;
2147         struct nfp_net_hw *hw;
2148
2149         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         new_ctrl = 0;
2151
2152         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2153             (mask & ETH_VLAN_FILTER_OFFLOAD))
2154                 RTE_LOG(INFO, PMD, "Not support for ETH_VLAN_FILTER_OFFLOAD or"
2155                         " ETH_VLAN_FILTER_EXTEND");
2156
2157         /* Enable vlan strip if it is not configured yet */
2158         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2159             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2160                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2161
2162         /* Disable vlan strip just if it is configured */
2163         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2164             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2165                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2166
2167         if (new_ctrl == 0)
2168                 return;
2169
2170         update = NFP_NET_CFG_UPDATE_GEN;
2171
2172         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2173                 return;
2174
2175         hw->ctrl = new_ctrl;
2176 }
2177
2178 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2179 static int
2180 nfp_net_reta_update(struct rte_eth_dev *dev,
2181                     struct rte_eth_rss_reta_entry64 *reta_conf,
2182                     uint16_t reta_size)
2183 {
2184         uint32_t reta, mask;
2185         int i, j;
2186         int idx, shift;
2187         uint32_t update;
2188         struct nfp_net_hw *hw =
2189                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190
2191         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2192                 return -EINVAL;
2193
2194         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2195                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2196                         "(%d) doesn't match the number hardware can supported "
2197                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2198                 return -EINVAL;
2199         }
2200
2201         /*
2202          * Update Redirection Table. There are 128 8bit-entries which can be
2203          * manage as 32 32bit-entries
2204          */
2205         for (i = 0; i < reta_size; i += 4) {
2206                 /* Handling 4 RSS entries per loop */
2207                 idx = i / RTE_RETA_GROUP_SIZE;
2208                 shift = i % RTE_RETA_GROUP_SIZE;
2209                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2210
2211                 if (!mask)
2212                         continue;
2213
2214                 reta = 0;
2215                 /* If all 4 entries were set, don't need read RETA register */
2216                 if (mask != 0xF)
2217                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2218
2219                 for (j = 0; j < 4; j++) {
2220                         if (!(mask & (0x1 << j)))
2221                                 continue;
2222                         if (mask != 0xF)
2223                                 /* Clearing the entry bits */
2224                                 reta &= ~(0xFF << (8 * j));
2225                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2226                 }
2227                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2228         }
2229
2230         update = NFP_NET_CFG_UPDATE_RSS;
2231
2232         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2233                 return -EIO;
2234
2235         return 0;
2236 }
2237
2238  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2239 static int
2240 nfp_net_reta_query(struct rte_eth_dev *dev,
2241                    struct rte_eth_rss_reta_entry64 *reta_conf,
2242                    uint16_t reta_size)
2243 {
2244         uint8_t i, j, mask;
2245         int idx, shift;
2246         uint32_t reta;
2247         struct nfp_net_hw *hw;
2248
2249         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250
2251         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2252                 return -EINVAL;
2253
2254         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2255                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2256                         "(%d) doesn't match the number hardware can supported "
2257                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2258                 return -EINVAL;
2259         }
2260
2261         /*
2262          * Reading Redirection Table. There are 128 8bit-entries which can be
2263          * manage as 32 32bit-entries
2264          */
2265         for (i = 0; i < reta_size; i += 4) {
2266                 /* Handling 4 RSS entries per loop */
2267                 idx = i / RTE_RETA_GROUP_SIZE;
2268                 shift = i % RTE_RETA_GROUP_SIZE;
2269                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2270
2271                 if (!mask)
2272                         continue;
2273
2274                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2275                 for (j = 0; j < 4; j++) {
2276                         if (!(mask & (0x1 << j)))
2277                                 continue;
2278                         reta_conf->reta[shift + j] =
2279                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2280                 }
2281         }
2282         return 0;
2283 }
2284
2285 static int
2286 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2287                         struct rte_eth_rss_conf *rss_conf)
2288 {
2289         uint32_t update;
2290         uint32_t cfg_rss_ctrl = 0;
2291         uint8_t key;
2292         uint64_t rss_hf;
2293         int i;
2294         struct nfp_net_hw *hw;
2295
2296         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2297
2298         rss_hf = rss_conf->rss_hf;
2299
2300         /* Checking if RSS is enabled */
2301         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2302                 if (rss_hf != 0) { /* Enable RSS? */
2303                         RTE_LOG(ERR, PMD, "RSS unsupported\n");
2304                         return -EINVAL;
2305                 }
2306                 return 0; /* Nothing to do */
2307         }
2308
2309         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2310                 RTE_LOG(ERR, PMD, "hash key too long\n");
2311                 return -EINVAL;
2312         }
2313
2314         if (rss_hf & ETH_RSS_IPV4)
2315                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2316                                 NFP_NET_CFG_RSS_IPV4_TCP |
2317                                 NFP_NET_CFG_RSS_IPV4_UDP;
2318
2319         if (rss_hf & ETH_RSS_IPV6)
2320                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2321                                 NFP_NET_CFG_RSS_IPV6_TCP |
2322                                 NFP_NET_CFG_RSS_IPV6_UDP;
2323
2324         /* configuring where to apply the RSS hash */
2325         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2326
2327         /* Writing the key byte a byte */
2328         for (i = 0; i < rss_conf->rss_key_len; i++) {
2329                 memcpy(&key, &rss_conf->rss_key[i], 1);
2330                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2331         }
2332
2333         /* Writing the key size */
2334         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2335
2336         update = NFP_NET_CFG_UPDATE_RSS;
2337
2338         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2339                 return -EIO;
2340
2341         return 0;
2342 }
2343
2344 static int
2345 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2346                           struct rte_eth_rss_conf *rss_conf)
2347 {
2348         uint64_t rss_hf;
2349         uint32_t cfg_rss_ctrl;
2350         uint8_t key;
2351         int i;
2352         struct nfp_net_hw *hw;
2353
2354         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2355
2356         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2357                 return -EINVAL;
2358
2359         rss_hf = rss_conf->rss_hf;
2360         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2361
2362         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2363                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2364
2365         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2366                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2367
2368         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2369                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2370
2371         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2372                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2373
2374         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2375                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2376
2377         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2378                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2379
2380         /* Reading the key size */
2381         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2382
2383         /* Reading the key byte a byte */
2384         for (i = 0; i < rss_conf->rss_key_len; i++) {
2385                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2386                 memcpy(&rss_conf->rss_key[i], &key, 1);
2387         }
2388
2389         return 0;
2390 }
2391
2392 /* Initialise and register driver with DPDK Application */
2393 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2394         .dev_configure          = nfp_net_configure,
2395         .dev_start              = nfp_net_start,
2396         .dev_stop               = nfp_net_stop,
2397         .dev_close              = nfp_net_close,
2398         .promiscuous_enable     = nfp_net_promisc_enable,
2399         .promiscuous_disable    = nfp_net_promisc_disable,
2400         .link_update            = nfp_net_link_update,
2401         .stats_get              = nfp_net_stats_get,
2402         .stats_reset            = nfp_net_stats_reset,
2403         .dev_infos_get          = nfp_net_infos_get,
2404         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2405         .mtu_set                = nfp_net_dev_mtu_set,
2406         .vlan_offload_set       = nfp_net_vlan_offload_set,
2407         .reta_update            = nfp_net_reta_update,
2408         .reta_query             = nfp_net_reta_query,
2409         .rss_hash_update        = nfp_net_rss_hash_update,
2410         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2411         .rx_queue_setup         = nfp_net_rx_queue_setup,
2412         .rx_queue_release       = nfp_net_rx_queue_release,
2413         .rx_queue_count         = nfp_net_rx_queue_count,
2414         .tx_queue_setup         = nfp_net_tx_queue_setup,
2415         .tx_queue_release       = nfp_net_tx_queue_release,
2416         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2417         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2418 };
2419
2420 static int
2421 nfp_net_init(struct rte_eth_dev *eth_dev)
2422 {
2423         struct rte_pci_device *pci_dev;
2424         struct nfp_net_hw *hw;
2425
2426         uint32_t tx_bar_off, rx_bar_off;
2427         uint32_t start_q;
2428         int stride = 4;
2429
2430         PMD_INIT_FUNC_TRACE();
2431
2432         hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2433
2434         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2435         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2436         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2437
2438         /* For secondary processes, the primary has done all the work */
2439         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2440                 return 0;
2441
2442         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2443         rte_eth_copy_pci_info(eth_dev, pci_dev);
2444         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
2445
2446         hw->device_id = pci_dev->id.device_id;
2447         hw->vendor_id = pci_dev->id.vendor_id;
2448         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2449         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2450
2451         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u\n",
2452                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2453                      pci_dev->addr.domain, pci_dev->addr.bus,
2454                      pci_dev->addr.devid, pci_dev->addr.function);
2455
2456         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2457         if (hw->ctrl_bar == NULL) {
2458                 RTE_LOG(ERR, PMD,
2459                         "hw->ctrl_bar is NULL. BAR0 not configured\n");
2460                 return -ENODEV;
2461         }
2462         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2463         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2464
2465         /* Work out where in the BAR the queues start. */
2466         switch (pci_dev->id.device_id) {
2467         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2468                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2469                 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2470                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2471                 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2472                 break;
2473         default:
2474                 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2475                 return -ENODEV;
2476         }
2477
2478         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x\n", tx_bar_off);
2479         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x\n", rx_bar_off);
2480
2481         hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2482         hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2483
2484         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p\n",
2485                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2486
2487         nfp_net_cfg_queue_setup(hw);
2488
2489         /* Get some of the read-only fields from the config BAR */
2490         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2491         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2492         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2493         hw->mtu = hw->max_mtu;
2494
2495         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2496                 hw->rx_offset = NFP_NET_RX_OFFSET;
2497         else
2498                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2499
2500         PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d\n",
2501                      hw->ver, hw->max_mtu);
2502         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s\n", hw->cap,
2503                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2504                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2505                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2506                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2507                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2508                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2509                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2510                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2511                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "");
2512
2513         hw->ctrl = 0;
2514
2515         hw->stride_rx = stride;
2516         hw->stride_tx = stride;
2517
2518         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u\n",
2519                      hw->max_rx_queues, hw->max_tx_queues);
2520
2521         /* Initializing spinlock for reconfigs */
2522         rte_spinlock_init(&hw->reconfig_lock);
2523
2524         /* Allocating memory for mac addr */
2525         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2526         if (eth_dev->data->mac_addrs == NULL) {
2527                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2528                 return -ENOMEM;
2529         }
2530
2531         nfp_net_read_mac(hw);
2532
2533         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr))
2534                 /* Using random mac addresses for VFs */
2535                 eth_random_addr(&hw->mac_addr[0]);
2536
2537         /* Copying mac address to DPDK eth_dev struct */
2538         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2539                         &eth_dev->data->mac_addrs[0]);
2540
2541         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2542                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2543                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2544                      pci_dev->id.device_id,
2545                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2546                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2547
2548         /* Registering LSC interrupt handler */
2549         rte_intr_callback_register(&pci_dev->intr_handle,
2550                                    nfp_net_dev_interrupt_handler,
2551                                    (void *)eth_dev);
2552
2553         /* Telling the firmware about the LSC interrupt entry */
2554         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2555
2556         /* Recording current stats counters values */
2557         nfp_net_stats_reset(eth_dev);
2558
2559         return 0;
2560 }
2561
2562 static struct rte_pci_id pci_id_nfp_net_map[] = {
2563         {
2564                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2565                                PCI_DEVICE_ID_NFP6000_PF_NIC)
2566         },
2567         {
2568                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2569                                PCI_DEVICE_ID_NFP6000_VF_NIC)
2570         },
2571         {
2572                 .vendor_id = 0,
2573         },
2574 };
2575
2576 static struct eth_driver rte_nfp_net_pmd = {
2577         .pci_drv = {
2578                 .id_table = pci_id_nfp_net_map,
2579                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2580                 .probe = rte_eth_dev_pci_probe,
2581                 .remove = rte_eth_dev_pci_remove,
2582         },
2583         .eth_dev_init = nfp_net_init,
2584         .dev_private_size = sizeof(struct nfp_net_adapter),
2585 };
2586
2587 RTE_PMD_REGISTER_PCI(net_nfp, rte_nfp_net_pmd.pci_drv);
2588 RTE_PMD_REGISTER_PCI_TABLE(net_nfp, pci_id_nfp_net_map);
2589 RTE_PMD_REGISTER_KMOD_DEP(net_nfp, "* igb_uio | uio_pci_generic | vfio");
2590
2591 /*
2592  * Local variables:
2593  * c-file-style: "Linux"
2594  * indent-tabs-mode: t
2595  * End:
2596  */