drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014, 2015 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfp_nfpu.h"
  59 #include "nfp_net_pmd.h"
  60 #include "nfp_net_logs.h"
  61 #include "nfp_net_ctrl.h"
  62
  63 /* Prototypes */
  64 static void nfp_net_close(struct rte_eth_dev *dev);
  65 static int nfp_net_configure(struct rte_eth_dev *dev);
  66 static void nfp_net_dev_interrupt_handler(void *param);
  67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  70                               struct rte_eth_dev_info *dev_info);
  71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  77                                        uint16_t queue_idx);
  78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  79                                   uint16_t nb_pkts);
  80 static void nfp_net_rx_queue_release(void *rxq);
  81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  82                                   uint16_t nb_desc, unsigned int socket_id,
  83                                   const struct rte_eth_rxconf *rx_conf,
  84                                   struct rte_mempool *mp);
  85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  86 static void nfp_net_tx_queue_release(void *txq);
  87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_txconf *tx_conf);
  90 static int nfp_net_start(struct rte_eth_dev *dev);
  91 static void nfp_net_stats_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_stats *stats);
  93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
  94 static void nfp_net_stop(struct rte_eth_dev *dev);
  95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  96                                   uint16_t nb_pkts);
  97
  98 /*
  99  * The offset of the queue controller queues in the PCIe Target. These
 100  * happen to be at the same offset on the NFP6000 and the NFP3200 so
 101  * we use a single macro here.
 102  */
 103 #define NFP_PCIE_QUEUE(_q)      (0x800 * ((_q) & 0xff))
 104
 105 /* Maximum value which can be added to a queue with one transaction */
 106 #define NFP_QCP_MAX_ADD 0x7f
 107
 108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 109         (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
 110
 111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 112 enum nfp_qcp_ptr {
 113         NFP_QCP_READ_PTR = 0,
 114         NFP_QCP_WRITE_PTR
 115 };
 116
 117 /*
 118  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 119  * @q: Base address for queue structure
 120  * @ptr: Add to the Read or Write pointer
 121  * @val: Value to add to the queue pointer
 122  *
 123  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 124  */
 125 static inline void
 126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 127 {
 128         uint32_t off;
 129
 130         if (ptr == NFP_QCP_READ_PTR)
 131                 off = NFP_QCP_QUEUE_ADD_RPTR;
 132         else
 133                 off = NFP_QCP_QUEUE_ADD_WPTR;
 134
 135         while (val > NFP_QCP_MAX_ADD) {
 136                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 137                 val -= NFP_QCP_MAX_ADD;
 138         }
 139
 140         nn_writel(rte_cpu_to_le_32(val), q + off);
 141 }
 142
 143 /*
 144  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 145  * @q:  Base address for queue structure
 146  * @ptr: Read or Write pointer
 147  */
 148 static inline uint32_t
 149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 150 {
 151         uint32_t off;
 152         uint32_t val;
 153
 154         if (ptr == NFP_QCP_READ_PTR)
 155                 off = NFP_QCP_QUEUE_STS_LO;
 156         else
 157                 off = NFP_QCP_QUEUE_STS_HI;
 158
 159         val = rte_cpu_to_le_32(nn_readl(q + off));
 160
 161         if (ptr == NFP_QCP_READ_PTR)
 162                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 163         else
 164                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 165 }
 166
 167 /*
 168  * Functions to read/write from/to Config BAR
 169  * Performs any endian conversion necessary.
 170  */
 171 static inline uint8_t
 172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 173 {
 174         return nn_readb(hw->ctrl_bar + off);
 175 }
 176
 177 static inline void
 178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 179 {
 180         nn_writeb(val, hw->ctrl_bar + off);
 181 }
 182
 183 static inline uint32_t
 184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 185 {
 186         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 187 }
 188
 189 static inline void
 190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 191 {
 192         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 193 }
 194
 195 static inline uint64_t
 196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 197 {
 198         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 199 }
 200
 201 static inline void
 202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 203 {
 204         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 205 }
 206
 207 /*
 208  * Atomically reads link status information from global structure rte_eth_dev.
 209  *
 210  * @param dev
 211  *   - Pointer to the structure rte_eth_dev to read from.
 212  *   - Pointer to the buffer to be saved with the link status.
 213  *
 214  * @return
 215  *   - On success, zero.
 216  *   - On failure, negative value.
 217  */
 218 static inline int
 219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 220                                     struct rte_eth_link *link)
 221 {
 222         struct rte_eth_link *dst = link;
 223         struct rte_eth_link *src = &dev->data->dev_link;
 224
 225         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 226                                 *(uint64_t *)src) == 0)
 227                 return -1;
 228
 229         return 0;
 230 }
 231
 232 /*
 233  * Atomically writes the link status information into global
 234  * structure rte_eth_dev.
 235  *
 236  * @param dev
 237  *   - Pointer to the structure rte_eth_dev to read from.
 238  *   - Pointer to the buffer to be saved with the link status.
 239  *
 240  * @return
 241  *   - On success, zero.
 242  *   - On failure, negative value.
 243  */
 244 static inline int
 245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 246                                      struct rte_eth_link *link)
 247 {
 248         struct rte_eth_link *dst = &dev->data->dev_link;
 249         struct rte_eth_link *src = link;
 250
 251         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 252                                 *(uint64_t *)src) == 0)
 253                 return -1;
 254
 255         return 0;
 256 }
 257
 258 static void
 259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 260 {
 261         unsigned i;
 262
 263         if (rxq->rxbufs == NULL)
 264                 return;
 265
 266         for (i = 0; i < rxq->rx_count; i++) {
 267                 if (rxq->rxbufs[i].mbuf) {
 268                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 269                         rxq->rxbufs[i].mbuf = NULL;
 270                 }
 271         }
 272 }
 273
 274 static void
 275 nfp_net_rx_queue_release(void *rx_queue)
 276 {
 277         struct nfp_net_rxq *rxq = rx_queue;
 278
 279         if (rxq) {
 280                 nfp_net_rx_queue_release_mbufs(rxq);
 281                 rte_free(rxq->rxbufs);
 282                 rte_free(rxq);
 283         }
 284 }
 285
 286 static void
 287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 288 {
 289         nfp_net_rx_queue_release_mbufs(rxq);
 290         rxq->rd_p = 0;
 291         rxq->nb_rx_hold = 0;
 292 }
 293
 294 static void
 295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 296 {
 297         unsigned i;
 298
 299         if (txq->txbufs == NULL)
 300                 return;
 301
 302         for (i = 0; i < txq->tx_count; i++) {
 303                 if (txq->txbufs[i].mbuf) {
 304                         rte_pktmbuf_free(txq->txbufs[i].mbuf);
 305                         txq->txbufs[i].mbuf = NULL;
 306                 }
 307         }
 308 }
 309
 310 static void
 311 nfp_net_tx_queue_release(void *tx_queue)
 312 {
 313         struct nfp_net_txq *txq = tx_queue;
 314
 315         if (txq) {
 316                 nfp_net_tx_queue_release_mbufs(txq);
 317                 rte_free(txq->txbufs);
 318                 rte_free(txq);
 319         }
 320 }
 321
 322 static void
 323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 324 {
 325         nfp_net_tx_queue_release_mbufs(txq);
 326         txq->wr_p = 0;
 327         txq->rd_p = 0;
 328 }
 329
 330 static int
 331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 332 {
 333         int cnt;
 334         uint32_t new;
 335         struct timespec wait;
 336
 337         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
 338                     hw->qcp_cfg);
 339
 340         if (hw->qcp_cfg == NULL)
 341                 rte_panic("Bad configuration queue pointer\n");
 342
 343         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 344
 345         wait.tv_sec = 0;
 346         wait.tv_nsec = 1000000;
 347
 348         PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
 349
 350         /* Poll update field, waiting for NFP to ack the config */
 351         for (cnt = 0; ; cnt++) {
 352                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 353                 if (new == 0)
 354                         break;
 355                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 356                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 357                         return -1;
 358                 }
 359                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 360                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 361                                           " %dms", update, cnt);
 362                         rte_panic("Exiting\n");
 363                 }
 364                 nanosleep(&wait, 0); /* waiting for a 1ms */
 365         }
 366         PMD_DRV_LOG(DEBUG, "Ack DONE\n");
 367         return 0;
 368 }
 369
 370 /*
 371  * Reconfigure the NIC
 372  * @nn:    device to reconfigure
 373  * @ctrl:    The value for the ctrl field in the BAR config
 374  * @update:  The value for the update field in the BAR config
 375  *
 376  * Write the update word to the BAR and ping the reconfig queue. Then poll
 377  * until the firmware has acknowledged the update by zeroing the update word.
 378  */
 379 static int
 380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 381 {
 382         uint32_t err;
 383
 384         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
 385                     ctrl, update);
 386
 387         rte_spinlock_lock(&hw->reconfig_lock);
 388
 389         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 390         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 391
 392         rte_wmb();
 393
 394         err = __nfp_net_reconfig(hw, update);
 395
 396         rte_spinlock_unlock(&hw->reconfig_lock);
 397
 398         if (!err)
 399                 return 0;
 400
 401         /*
 402          * Reconfig errors imply situations where they can be handled.
 403          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 404          */
 405         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 406                      ctrl, update);
 407         return -EIO;
 408 }
 409
 410 /*
 411  * Configure an Ethernet device. This function must be invoked first
 412  * before any other function in the Ethernet API. This function can
 413  * also be re-invoked when a device is in the stopped state.
 414  */
 415 static int
 416 nfp_net_configure(struct rte_eth_dev *dev)
 417 {
 418         struct rte_eth_conf *dev_conf;
 419         struct rte_eth_rxmode *rxmode;
 420         struct rte_eth_txmode *txmode;
 421         uint32_t new_ctrl = 0;
 422         uint32_t update = 0;
 423         struct nfp_net_hw *hw;
 424
 425         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 426
 427         /*
 428          * A DPDK app sends info about how many queues to use and how
 429          * those queues need to be configured. This is used by the
 430          * DPDK core and it makes sure no more queues than those
 431          * advertised by the driver are requested. This function is
 432          * called after that internal process
 433          */
 434
 435         PMD_INIT_LOG(DEBUG, "Configure");
 436
 437         dev_conf = &dev->data->dev_conf;
 438         rxmode = &dev_conf->rxmode;
 439         txmode = &dev_conf->txmode;
 440
 441         /* Checking TX mode */
 442         if (txmode->mq_mode) {
 443                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 444                 return -EINVAL;
 445         }
 446
 447         /* Checking RX mode */
 448         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 449                 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
 450                         update = NFP_NET_CFG_UPDATE_RSS;
 451                         new_ctrl = NFP_NET_CFG_CTRL_RSS;
 452                 } else {
 453                         PMD_INIT_LOG(INFO, "RSS not supported");
 454                         return -EINVAL;
 455                 }
 456         }
 457
 458         if (rxmode->split_hdr_size) {
 459                 PMD_INIT_LOG(INFO, "rxmode does not support split header");
 460                 return -EINVAL;
 461         }
 462
 463         if (rxmode->hw_ip_checksum) {
 464                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
 465                         new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 466                 } else {
 467                         PMD_INIT_LOG(INFO, "RXCSUM not supported");
 468                         return -EINVAL;
 469                 }
 470         }
 471
 472         if (rxmode->hw_vlan_filter) {
 473                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
 474                 return -EINVAL;
 475         }
 476
 477         if (rxmode->hw_vlan_strip) {
 478                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
 479                         new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 480                 } else {
 481                         PMD_INIT_LOG(INFO, "hw vlan strip not supported");
 482                         return -EINVAL;
 483                 }
 484         }
 485
 486         if (rxmode->hw_vlan_extend) {
 487                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
 488                 return -EINVAL;
 489         }
 490
 491         if (rxmode->jumbo_frame)
 492                 /* this is handled in rte_eth_dev_configure */
 493
 494         if (rxmode->hw_strip_crc) {
 495                 PMD_INIT_LOG(INFO, "strip CRC not supported");
 496                 return -EINVAL;
 497         }
 498
 499         if (rxmode->enable_scatter) {
 500                 PMD_INIT_LOG(INFO, "Scatter not supported");
 501                 return -EINVAL;
 502         }
 503
 504         /* If next capabilities are supported, configure them by default */
 505
 506         /* VLAN insertion */
 507         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
 508                 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 509
 510         /* L2 broadcast */
 511         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 512                 new_ctrl |= NFP_NET_CFG_CTRL_L2BC;
 513
 514         /* L2 multicast */
 515         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 516                 new_ctrl |= NFP_NET_CFG_CTRL_L2MC;
 517
 518         /* TX checksum offload */
 519         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
 520                 new_ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 521
 522         /* LSO offload */
 523         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 524                 new_ctrl |= NFP_NET_CFG_CTRL_LSO;
 525
 526         /* RX gather */
 527         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
 528                 new_ctrl |= NFP_NET_CFG_CTRL_GATHER;
 529
 530         if (!new_ctrl)
 531                 return 0;
 532
 533         update |= NFP_NET_CFG_UPDATE_GEN;
 534
 535         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 536         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 537                 return -EIO;
 538
 539         hw->ctrl = new_ctrl;
 540
 541         return 0;
 542 }
 543
 544 static void
 545 nfp_net_enable_queues(struct rte_eth_dev *dev)
 546 {
 547         struct nfp_net_hw *hw;
 548         uint64_t enabled_queues = 0;
 549         int i;
 550
 551         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 552
 553         /* Enabling the required TX queues in the device */
 554         for (i = 0; i < dev->data->nb_tx_queues; i++)
 555                 enabled_queues |= (1 << i);
 556
 557         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 558
 559         enabled_queues = 0;
 560
 561         /* Enabling the required RX queues in the device */
 562         for (i = 0; i < dev->data->nb_rx_queues; i++)
 563                 enabled_queues |= (1 << i);
 564
 565         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 566 }
 567
 568 static void
 569 nfp_net_disable_queues(struct rte_eth_dev *dev)
 570 {
 571         struct nfp_net_hw *hw;
 572         uint32_t new_ctrl, update = 0;
 573
 574         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 575
 576         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 577         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 578
 579         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 580         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 581                  NFP_NET_CFG_UPDATE_MSIX;
 582
 583         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 584                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 585
 586         /* If an error when reconfig we avoid to change hw state */
 587         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 588                 return;
 589
 590         hw->ctrl = new_ctrl;
 591 }
 592
 593 static int
 594 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 595 {
 596         int i;
 597
 598         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 599                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 600                         return -1;
 601         }
 602         return 0;
 603 }
 604
 605 static void
 606 nfp_net_params_setup(struct nfp_net_hw *hw)
 607 {
 608         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 609         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 610 }
 611
 612 static void
 613 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 614 {
 615         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 616 }
 617
 618 #define ETH_ADDR_LEN    6
 619
 620 static void
 621 nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src)
 622 {
 623         int i;
 624
 625         for (i = 0; i < ETH_ADDR_LEN; i++)
 626                 dst[ETH_ADDR_LEN - i - 1] = src[i];
 627 }
 628
 629 static int
 630 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 631 {
 632         union eth_table_entry *entry;
 633         int idx, i;
 634
 635         idx = port;
 636         entry = hw->eth_table;
 637
 638         /* Reading NFP ethernet table obtained before */
 639         for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
 640                 if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
 641                         /* port not in use */
 642                         entry++;
 643                         continue;
 644                 }
 645                 if (idx == 0)
 646                         break;
 647                 idx--;
 648                 entry++;
 649         }
 650
 651         if (i == NSP_ETH_MAX_COUNT)
 652                 return -EINVAL;
 653
 654         /*
 655          * hw points to port0 private data. We need hw now pointing to
 656          * right port.
 657          */
 658         hw += port;
 659         nfp_eth_copy_mac_reverse((uint8_t *)&hw->mac_addr,
 660                                  (uint8_t *)&entry->mac_addr);
 661
 662         return 0;
 663 }
 664
 665 static void
 666 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 667 {
 668         uint32_t tmp;
 669
 670         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 671         memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
 672
 673         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 674         memcpy(&hw->mac_addr[4], &tmp, 2);
 675 }
 676
 677 static void
 678 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 679 {
 680         uint32_t mac0 = *(uint32_t *)mac;
 681         uint16_t mac1;
 682
 683         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 684
 685         mac += 4;
 686         mac1 = *(uint16_t *)mac;
 687         nn_writew(rte_cpu_to_be_16(mac1),
 688                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 689 }
 690
 691 static int
 692 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 693                            struct rte_intr_handle *intr_handle)
 694 {
 695         struct nfp_net_hw *hw;
 696         int i;
 697
 698         if (!intr_handle->intr_vec) {
 699                 intr_handle->intr_vec =
 700                         rte_zmalloc("intr_vec",
 701                                     dev->data->nb_rx_queues * sizeof(int), 0);
 702                 if (!intr_handle->intr_vec) {
 703                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 704                                      " intr_vec", dev->data->nb_rx_queues);
 705                         return -ENOMEM;
 706                 }
 707         }
 708
 709         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 710
 711         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 712                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 713                 /* UIO just supports one queue and no LSC*/
 714                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 715                 intr_handle->intr_vec[0] = 0;
 716         } else {
 717                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 718                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 719                         /*
 720                          * The first msix vector is reserved for non
 721                          * efd interrupts
 722                         */
 723                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 724                         intr_handle->intr_vec[i] = i + 1;
 725                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
 726                                             intr_handle->intr_vec[i]);
 727                 }
 728         }
 729
 730         /* Avoiding TX interrupts */
 731         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 732         return 0;
 733 }
 734
 735 static int
 736 nfp_net_start(struct rte_eth_dev *dev)
 737 {
 738         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 739         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 740         uint32_t new_ctrl, update = 0;
 741         struct nfp_net_hw *hw;
 742         uint32_t intr_vector;
 743         int ret;
 744
 745         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 746
 747         PMD_INIT_LOG(DEBUG, "Start");
 748
 749         /* Disabling queues just in case... */
 750         nfp_net_disable_queues(dev);
 751
 752         /* Writing configuration parameters in the device */
 753         nfp_net_params_setup(hw);
 754
 755         /* Enabling the required queues in the device */
 756         nfp_net_enable_queues(dev);
 757
 758         /* check and configure queue intr-vector mapping */
 759         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 760                 if (hw->pf_multiport_enabled) {
 761                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 762                                           "with NFP multiport PF");
 763                                 return -EINVAL;
 764                 }
 765                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 766                         /*
 767                          * Better not to share LSC with RX interrupts.
 768                          * Unregistering LSC interrupt handler
 769                          */
 770                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 771                                 nfp_net_dev_interrupt_handler, (void *)dev);
 772
 773                         if (dev->data->nb_rx_queues > 1) {
 774                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 775                                              "supports 1 queue with UIO");
 776                                 return -EIO;
 777                         }
 778                 }
 779                 intr_vector = dev->data->nb_rx_queues;
 780                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 781                         return -1;
 782
 783                 nfp_configure_rx_interrupt(dev, intr_handle);
 784                 update = NFP_NET_CFG_UPDATE_MSIX;
 785         }
 786
 787         rte_intr_enable(intr_handle);
 788
 789         /* Enable device */
 790         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
 791
 792         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 793
 794         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 795                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 796
 797         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 798         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 799                 return -EIO;
 800
 801         /*
 802          * Allocating rte mbuffs for configured rx queues.
 803          * This requires queues being enabled before
 804          */
 805         if (nfp_net_rx_freelist_setup(dev) < 0) {
 806                 ret = -ENOMEM;
 807                 goto error;
 808         }
 809
 810         if (hw->is_pf)
 811                 /* Configure the physical port up */
 812                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1);
 813
 814         hw->ctrl = new_ctrl;
 815
 816         return 0;
 817
 818 error:
 819         /*
 820          * An error returned by this function should mean the app
 821          * exiting and then the system releasing all the memory
 822          * allocated even memory coming from hugepages.
 823          *
 824          * The device could be enabled at this point with some queues
 825          * ready for getting packets. This is true if the call to
 826          * nfp_net_rx_freelist_setup() succeeds for some queues but
 827          * fails for subsequent queues.
 828          *
 829          * This should make the app exiting but better if we tell the
 830          * device first.
 831          */
 832         nfp_net_disable_queues(dev);
 833
 834         return ret;
 835 }
 836
 837 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 838 static void
 839 nfp_net_stop(struct rte_eth_dev *dev)
 840 {
 841         int i;
 842         struct nfp_net_hw *hw;
 843
 844         PMD_INIT_LOG(DEBUG, "Stop");
 845
 846         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 847
 848         nfp_net_disable_queues(dev);
 849
 850         /* Clear queues */
 851         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 852                 nfp_net_reset_tx_queue(
 853                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 854         }
 855
 856         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 857                 nfp_net_reset_rx_queue(
 858                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 859         }
 860
 861         if (hw->is_pf)
 862                 /* Configure the physical port down */
 863                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0);
 864 }
 865
 866 /* Reset and stop device. The device can not be restarted. */
 867 static void
 868 nfp_net_close(struct rte_eth_dev *dev)
 869 {
 870         struct nfp_net_hw *hw;
 871         struct rte_pci_device *pci_dev;
 872         int i;
 873
 874         PMD_INIT_LOG(DEBUG, "Close");
 875
 876         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 878
 879         /*
 880          * We assume that the DPDK application is stopping all the
 881          * threads/queues before calling the device close function.
 882          */
 883
 884         nfp_net_disable_queues(dev);
 885
 886         /* Clear queues */
 887         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 888                 nfp_net_reset_tx_queue(
 889                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 890         }
 891
 892         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 893                 nfp_net_reset_rx_queue(
 894                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 895         }
 896
 897         rte_intr_disable(&pci_dev->intr_handle);
 898         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 899
 900         /* unregister callback func from eal lib */
 901         rte_intr_callback_unregister(&pci_dev->intr_handle,
 902                                      nfp_net_dev_interrupt_handler,
 903                                      (void *)dev);
 904
 905         /*
 906          * The ixgbe PMD driver disables the pcie master on the
 907          * device. The i40e does not...
 908          */
 909 }
 910
 911 static void
 912 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 913 {
 914         uint32_t new_ctrl, update = 0;
 915         struct nfp_net_hw *hw;
 916
 917         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
 918
 919         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 920
 921         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 922                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 923                 return;
 924         }
 925
 926         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 927                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
 928                 return;
 929         }
 930
 931         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 932         update = NFP_NET_CFG_UPDATE_GEN;
 933
 934         /*
 935          * DPDK sets promiscuous mode on just after this call assuming
 936          * it can not fail ...
 937          */
 938         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 939                 return;
 940
 941         hw->ctrl = new_ctrl;
 942 }
 943
 944 static void
 945 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 946 {
 947         uint32_t new_ctrl, update = 0;
 948         struct nfp_net_hw *hw;
 949
 950         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951
 952         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 953                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
 954                 return;
 955         }
 956
 957         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 958         update = NFP_NET_CFG_UPDATE_GEN;
 959
 960         /*
 961          * DPDK sets promiscuous mode off just before this call
 962          * assuming it can not fail ...
 963          */
 964         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 965                 return;
 966
 967         hw->ctrl = new_ctrl;
 968 }
 969
 970 /*
 971  * return 0 means link status changed, -1 means not changed
 972  *
 973  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 974  * status.
 975  */
 976 static int
 977 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 978 {
 979         struct nfp_net_hw *hw;
 980         struct rte_eth_link link, old;
 981         uint32_t nn_link_status;
 982
 983         static const uint32_t ls_to_ethtool[] = {
 984                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 985                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 986                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 987                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 988                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 989                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 990                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 991                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 992         };
 993
 994         PMD_DRV_LOG(DEBUG, "Link update\n");
 995
 996         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997
 998         memset(&old, 0, sizeof(old));
 999         nfp_net_dev_atomic_read_link_status(dev, &old);
1000
1001         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1002
1003         memset(&link, 0, sizeof(struct rte_eth_link));
1004
1005         if (nn_link_status & NFP_NET_CFG_STS_LINK)
1006                 link.link_status = ETH_LINK_UP;
1007
1008         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1009
1010         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1011                          NFP_NET_CFG_STS_LINK_RATE_MASK;
1012
1013         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1014                 link.link_speed = ETH_SPEED_NUM_NONE;
1015         else
1016                 link.link_speed = ls_to_ethtool[nn_link_status];
1017
1018         if (old.link_status != link.link_status) {
1019                 nfp_net_dev_atomic_write_link_status(dev, &link);
1020                 if (link.link_status)
1021                         PMD_DRV_LOG(INFO, "NIC Link is Up\n");
1022                 else
1023                         PMD_DRV_LOG(INFO, "NIC Link is Down\n");
1024                 return 0;
1025         }
1026
1027         return -1;
1028 }
1029
1030 static void
1031 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1032 {
1033         int i;
1034         struct nfp_net_hw *hw;
1035         struct rte_eth_stats nfp_dev_stats;
1036
1037         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038
1039         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1040
1041         /* reading per RX ring stats */
1042         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1043                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1044                         break;
1045
1046                 nfp_dev_stats.q_ipackets[i] =
1047                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1048
1049                 nfp_dev_stats.q_ipackets[i] -=
1050                         hw->eth_stats_base.q_ipackets[i];
1051
1052                 nfp_dev_stats.q_ibytes[i] =
1053                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1054
1055                 nfp_dev_stats.q_ibytes[i] -=
1056                         hw->eth_stats_base.q_ibytes[i];
1057         }
1058
1059         /* reading per TX ring stats */
1060         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1061                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1062                         break;
1063
1064                 nfp_dev_stats.q_opackets[i] =
1065                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1066
1067                 nfp_dev_stats.q_opackets[i] -=
1068                         hw->eth_stats_base.q_opackets[i];
1069
1070                 nfp_dev_stats.q_obytes[i] =
1071                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1072
1073                 nfp_dev_stats.q_obytes[i] -=
1074                         hw->eth_stats_base.q_obytes[i];
1075         }
1076
1077         nfp_dev_stats.ipackets =
1078                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1079
1080         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1081
1082         nfp_dev_stats.ibytes =
1083                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1084
1085         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1086
1087         nfp_dev_stats.opackets =
1088                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1089
1090         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1091
1092         nfp_dev_stats.obytes =
1093                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1094
1095         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1096
1097         /* reading general device stats */
1098         nfp_dev_stats.ierrors =
1099                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1100
1101         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1102
1103         nfp_dev_stats.oerrors =
1104                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1105
1106         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1107
1108         /* RX ring mbuf allocation failures */
1109         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1110
1111         nfp_dev_stats.imissed =
1112                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1113
1114         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1115
1116         if (stats)
1117                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1118 }
1119
1120 static void
1121 nfp_net_stats_reset(struct rte_eth_dev *dev)
1122 {
1123         int i;
1124         struct nfp_net_hw *hw;
1125
1126         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127
1128         /*
1129          * hw->eth_stats_base records the per counter starting point.
1130          * Lets update it now
1131          */
1132
1133         /* reading per RX ring stats */
1134         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1135                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1136                         break;
1137
1138                 hw->eth_stats_base.q_ipackets[i] =
1139                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1140
1141                 hw->eth_stats_base.q_ibytes[i] =
1142                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1143         }
1144
1145         /* reading per TX ring stats */
1146         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1147                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1148                         break;
1149
1150                 hw->eth_stats_base.q_opackets[i] =
1151                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1152
1153                 hw->eth_stats_base.q_obytes[i] =
1154                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1155         }
1156
1157         hw->eth_stats_base.ipackets =
1158                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1159
1160         hw->eth_stats_base.ibytes =
1161                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1162
1163         hw->eth_stats_base.opackets =
1164                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1165
1166         hw->eth_stats_base.obytes =
1167                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1168
1169         /* reading general device stats */
1170         hw->eth_stats_base.ierrors =
1171                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1172
1173         hw->eth_stats_base.oerrors =
1174                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1175
1176         /* RX ring mbuf allocation failures */
1177         dev->data->rx_mbuf_alloc_failed = 0;
1178
1179         hw->eth_stats_base.imissed =
1180                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1181 }
1182
1183 static void
1184 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1185 {
1186         struct nfp_net_hw *hw;
1187
1188         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189
1190         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1191         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1192         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1193         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1194         dev_info->max_rx_pktlen = hw->mtu;
1195         /* Next should change when PF support is implemented */
1196         dev_info->max_mac_addrs = 1;
1197
1198         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1199                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1200
1201         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1202                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1203                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1204                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1205
1206         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1207                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1208
1209         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1210                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1211                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1212                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1213
1214         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1215                 .rx_thresh = {
1216                         .pthresh = DEFAULT_RX_PTHRESH,
1217                         .hthresh = DEFAULT_RX_HTHRESH,
1218                         .wthresh = DEFAULT_RX_WTHRESH,
1219                 },
1220                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1221                 .rx_drop_en = 0,
1222         };
1223
1224         dev_info->default_txconf = (struct rte_eth_txconf) {
1225                 .tx_thresh = {
1226                         .pthresh = DEFAULT_TX_PTHRESH,
1227                         .hthresh = DEFAULT_TX_HTHRESH,
1228                         .wthresh = DEFAULT_TX_WTHRESH,
1229                 },
1230                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1231                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1232                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1233                              ETH_TXQ_FLAGS_NOOFFLOADS,
1234         };
1235
1236         dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1237                                            ETH_RSS_NONFRAG_IPV4_UDP |
1238                                            ETH_RSS_NONFRAG_IPV6_TCP |
1239                                            ETH_RSS_NONFRAG_IPV6_UDP;
1240
1241         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1242         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1243
1244         dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1245                                ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1246                                ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1247
1248         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1249                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1250 }
1251
1252 static const uint32_t *
1253 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1254 {
1255         static const uint32_t ptypes[] = {
1256                 /* refers to nfp_net_set_hash() */
1257                 RTE_PTYPE_INNER_L3_IPV4,
1258                 RTE_PTYPE_INNER_L3_IPV6,
1259                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1260                 RTE_PTYPE_INNER_L4_MASK,
1261                 RTE_PTYPE_UNKNOWN
1262         };
1263
1264         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1265                 return ptypes;
1266         return NULL;
1267 }
1268
1269 static uint32_t
1270 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1271 {
1272         struct nfp_net_rxq *rxq;
1273         struct nfp_net_rx_desc *rxds;
1274         uint32_t idx;
1275         uint32_t count;
1276
1277         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1278
1279         idx = rxq->rd_p;
1280
1281         count = 0;
1282
1283         /*
1284          * Other PMDs are just checking the DD bit in intervals of 4
1285          * descriptors and counting all four if the first has the DD
1286          * bit on. Of course, this is not accurate but can be good for
1287          * performance. But ideally that should be done in descriptors
1288          * chunks belonging to the same cache line
1289          */
1290
1291         while (count < rxq->rx_count) {
1292                 rxds = &rxq->rxds[idx];
1293                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1294                         break;
1295
1296                 count++;
1297                 idx++;
1298
1299                 /* Wrapping? */
1300                 if ((idx) == rxq->rx_count)
1301                         idx = 0;
1302         }
1303
1304         return count;
1305 }
1306
1307 static int
1308 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1309 {
1310         struct rte_pci_device *pci_dev;
1311         struct nfp_net_hw *hw;
1312         int base = 0;
1313
1314         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1316
1317         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1318                 base = 1;
1319
1320         /* Make sure all updates are written before un-masking */
1321         rte_wmb();
1322         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1323                       NFP_NET_CFG_ICR_UNMASKED);
1324         return 0;
1325 }
1326
1327 static int
1328 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1329 {
1330         struct rte_pci_device *pci_dev;
1331         struct nfp_net_hw *hw;
1332         int base = 0;
1333
1334         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1335         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1336
1337         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1338                 base = 1;
1339
1340         /* Make sure all updates are written before un-masking */
1341         rte_wmb();
1342         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1343         return 0;
1344 }
1345
1346 static void
1347 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1348 {
1349         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1350         struct rte_eth_link link;
1351
1352         memset(&link, 0, sizeof(link));
1353         nfp_net_dev_atomic_read_link_status(dev, &link);
1354         if (link.link_status)
1355                 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1356                         dev->data->port_id, link.link_speed,
1357                         link.link_duplex == ETH_LINK_FULL_DUPLEX
1358                         ? "full-duplex" : "half-duplex");
1359         else
1360                 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1361                         dev->data->port_id);
1362
1363         RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1364                 pci_dev->addr.domain, pci_dev->addr.bus,
1365                 pci_dev->addr.devid, pci_dev->addr.function);
1366 }
1367
1368 /* Interrupt configuration and handling */
1369
1370 /*
1371  * nfp_net_irq_unmask - Unmask an interrupt
1372  *
1373  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1374  * clear the ICR for the entry.
1375  */
1376 static void
1377 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1378 {
1379         struct nfp_net_hw *hw;
1380         struct rte_pci_device *pci_dev;
1381
1382         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1383         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1384
1385         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1386                 /* If MSI-X auto-masking is used, clear the entry */
1387                 rte_wmb();
1388                 rte_intr_enable(&pci_dev->intr_handle);
1389         } else {
1390                 /* Make sure all updates are written before un-masking */
1391                 rte_wmb();
1392                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1393                               NFP_NET_CFG_ICR_UNMASKED);
1394         }
1395 }
1396
1397 static void
1398 nfp_net_dev_interrupt_handler(void *param)
1399 {
1400         int64_t timeout;
1401         struct rte_eth_link link;
1402         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1403
1404         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1405
1406         /* get the link status */
1407         memset(&link, 0, sizeof(link));
1408         nfp_net_dev_atomic_read_link_status(dev, &link);
1409
1410         nfp_net_link_update(dev, 0);
1411
1412         /* likely to up */
1413         if (!link.link_status) {
1414                 /* handle it 1 sec later, wait it being stable */
1415                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1416                 /* likely to down */
1417         } else {
1418                 /* handle it 4 sec later, wait it being stable */
1419                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1420         }
1421
1422         if (rte_eal_alarm_set(timeout * 1000,
1423                               nfp_net_dev_interrupt_delayed_handler,
1424                               (void *)dev) < 0) {
1425                 RTE_LOG(ERR, PMD, "Error setting alarm");
1426                 /* Unmasking */
1427                 nfp_net_irq_unmask(dev);
1428         }
1429 }
1430
1431 /*
1432  * Interrupt handler which shall be registered for alarm callback for delayed
1433  * handling specific interrupt to wait for the stable nic state. As the NIC
1434  * interrupt state is not stable for nfp after link is just down, it needs
1435  * to wait 4 seconds to get the stable status.
1436  *
1437  * @param handle   Pointer to interrupt handle.
1438  * @param param    The address of parameter (struct rte_eth_dev *)
1439  *
1440  * @return  void
1441  */
1442 static void
1443 nfp_net_dev_interrupt_delayed_handler(void *param)
1444 {
1445         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1446
1447         nfp_net_link_update(dev, 0);
1448         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1449
1450         nfp_net_dev_link_status_print(dev);
1451
1452         /* Unmasking */
1453         nfp_net_irq_unmask(dev);
1454 }
1455
1456 static int
1457 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1458 {
1459         struct nfp_net_hw *hw;
1460
1461         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1462
1463         /* check that mtu is within the allowed range */
1464         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1465                 return -EINVAL;
1466
1467         /* switch to jumbo mode if needed */
1468         if ((uint32_t)mtu > ETHER_MAX_LEN)
1469                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1470         else
1471                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1472
1473         /* update max frame size */
1474         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1475
1476         /* writing to configuration space */
1477         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1478
1479         hw->mtu = mtu;
1480
1481         return 0;
1482 }
1483
1484 static int
1485 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1486                        uint16_t queue_idx, uint16_t nb_desc,
1487                        unsigned int socket_id,
1488                        const struct rte_eth_rxconf *rx_conf,
1489                        struct rte_mempool *mp)
1490 {
1491         const struct rte_memzone *tz;
1492         struct nfp_net_rxq *rxq;
1493         struct nfp_net_hw *hw;
1494
1495         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1496
1497         PMD_INIT_FUNC_TRACE();
1498
1499         /* Validating number of descriptors */
1500         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1501             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1502             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1503                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1504                 return -EINVAL;
1505         }
1506
1507         /*
1508          * Free memory prior to re-allocation if needed. This is the case after
1509          * calling nfp_net_stop
1510          */
1511         if (dev->data->rx_queues[queue_idx]) {
1512                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1513                 dev->data->rx_queues[queue_idx] = NULL;
1514         }
1515
1516         /* Allocating rx queue data structure */
1517         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1518                                  RTE_CACHE_LINE_SIZE, socket_id);
1519         if (rxq == NULL)
1520                 return -ENOMEM;
1521
1522         /* Hw queues mapping based on firmware confifguration */
1523         rxq->qidx = queue_idx;
1524         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1525         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1526         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1527         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1528
1529         /*
1530          * Tracking mbuf size for detecting a potential mbuf overflow due to
1531          * RX offset
1532          */
1533         rxq->mem_pool = mp;
1534         rxq->mbuf_size = rxq->mem_pool->elt_size;
1535         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1536         hw->flbufsz = rxq->mbuf_size;
1537
1538         rxq->rx_count = nb_desc;
1539         rxq->port_id = dev->data->port_id;
1540         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1541         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1542                                   : ETHER_CRC_LEN);
1543         rxq->drop_en = rx_conf->rx_drop_en;
1544
1545         /*
1546          * Allocate RX ring hardware descriptors. A memzone large enough to
1547          * handle the maximum ring size is allocated in order to allow for
1548          * resizing in later calls to the queue setup function.
1549          */
1550         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1551                                    sizeof(struct nfp_net_rx_desc) *
1552                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1553                                    socket_id);
1554
1555         if (tz == NULL) {
1556                 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1557                 nfp_net_rx_queue_release(rxq);
1558                 return -ENOMEM;
1559         }
1560
1561         /* Saving physical and virtual addresses for the RX ring */
1562         rxq->dma = (uint64_t)tz->phys_addr;
1563         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1564
1565         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1566         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1567                                          sizeof(*rxq->rxbufs) * nb_desc,
1568                                          RTE_CACHE_LINE_SIZE, socket_id);
1569         if (rxq->rxbufs == NULL) {
1570                 nfp_net_rx_queue_release(rxq);
1571                 return -ENOMEM;
1572         }
1573
1574         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1575                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1576
1577         nfp_net_reset_rx_queue(rxq);
1578
1579         dev->data->rx_queues[queue_idx] = rxq;
1580         rxq->hw = hw;
1581
1582         /*
1583          * Telling the HW about the physical address of the RX ring and number
1584          * of descriptors in log2 format
1585          */
1586         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1587         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1588
1589         return 0;
1590 }
1591
1592 static int
1593 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1594 {
1595         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1596         uint64_t dma_addr;
1597         unsigned i;
1598
1599         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1600                    rxq->rx_count);
1601
1602         for (i = 0; i < rxq->rx_count; i++) {
1603                 struct nfp_net_rx_desc *rxd;
1604                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1605
1606                 if (mbuf == NULL) {
1607                         RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1608                                 (unsigned)rxq->qidx);
1609                         return -ENOMEM;
1610                 }
1611
1612                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1613
1614                 rxd = &rxq->rxds[i];
1615                 rxd->fld.dd = 0;
1616                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1617                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1618                 rxe[i].mbuf = mbuf;
1619                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1620         }
1621
1622         /* Make sure all writes are flushed before telling the hardware */
1623         rte_wmb();
1624
1625         /* Not advertising the whole ring as the firmware gets confused if so */
1626         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1627                    rxq->rx_count - 1);
1628
1629         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1630
1631         return 0;
1632 }
1633
1634 static int
1635 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1636                        uint16_t nb_desc, unsigned int socket_id,
1637                        const struct rte_eth_txconf *tx_conf)
1638 {
1639         const struct rte_memzone *tz;
1640         struct nfp_net_txq *txq;
1641         uint16_t tx_free_thresh;
1642         struct nfp_net_hw *hw;
1643
1644         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645
1646         PMD_INIT_FUNC_TRACE();
1647
1648         /* Validating number of descriptors */
1649         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1650             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1651             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1652                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1653                 return -EINVAL;
1654         }
1655
1656         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1657                                     tx_conf->tx_free_thresh :
1658                                     DEFAULT_TX_FREE_THRESH);
1659
1660         if (tx_free_thresh > (nb_desc)) {
1661                 RTE_LOG(ERR, PMD,
1662                         "tx_free_thresh must be less than the number of TX "
1663                         "descriptors. (tx_free_thresh=%u port=%d "
1664                         "queue=%d)\n", (unsigned int)tx_free_thresh,
1665                         dev->data->port_id, (int)queue_idx);
1666                 return -(EINVAL);
1667         }
1668
1669         /*
1670          * Free memory prior to re-allocation if needed. This is the case after
1671          * calling nfp_net_stop
1672          */
1673         if (dev->data->tx_queues[queue_idx]) {
1674                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1675                            queue_idx);
1676                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1677                 dev->data->tx_queues[queue_idx] = NULL;
1678         }
1679
1680         /* Allocating tx queue data structure */
1681         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1682                                  RTE_CACHE_LINE_SIZE, socket_id);
1683         if (txq == NULL) {
1684                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1685                 return -ENOMEM;
1686         }
1687
1688         /*
1689          * Allocate TX ring hardware descriptors. A memzone large enough to
1690          * handle the maximum ring size is allocated in order to allow for
1691          * resizing in later calls to the queue setup function.
1692          */
1693         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1694                                    sizeof(struct nfp_net_tx_desc) *
1695                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1696                                    socket_id);
1697         if (tz == NULL) {
1698                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1699                 nfp_net_tx_queue_release(txq);
1700                 return -ENOMEM;
1701         }
1702
1703         txq->tx_count = nb_desc;
1704         txq->tx_free_thresh = tx_free_thresh;
1705         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1706         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1707         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1708
1709         /* queue mapping based on firmware configuration */
1710         txq->qidx = queue_idx;
1711         txq->tx_qcidx = queue_idx * hw->stride_tx;
1712         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1713
1714         txq->port_id = dev->data->port_id;
1715         txq->txq_flags = tx_conf->txq_flags;
1716
1717         /* Saving physical and virtual addresses for the TX ring */
1718         txq->dma = (uint64_t)tz->phys_addr;
1719         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1720
1721         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1722         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1723                                          sizeof(*txq->txbufs) * nb_desc,
1724                                          RTE_CACHE_LINE_SIZE, socket_id);
1725         if (txq->txbufs == NULL) {
1726                 nfp_net_tx_queue_release(txq);
1727                 return -ENOMEM;
1728         }
1729         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1730                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1731
1732         nfp_net_reset_tx_queue(txq);
1733
1734         dev->data->tx_queues[queue_idx] = txq;
1735         txq->hw = hw;
1736
1737         /*
1738          * Telling the HW about the physical address of the TX ring and number
1739          * of descriptors in log2 format
1740          */
1741         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1742         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1743
1744         return 0;
1745 }
1746
1747 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1748 static inline void
1749 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1750                struct rte_mbuf *mb)
1751 {
1752         uint64_t ol_flags;
1753         struct nfp_net_hw *hw = txq->hw;
1754
1755         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1756                 goto clean_txd;
1757
1758         ol_flags = mb->ol_flags;
1759
1760         if (!(ol_flags & PKT_TX_TCP_SEG))
1761                 goto clean_txd;
1762
1763         txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1764         txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1765         txd->flags = PCIE_DESC_TX_LSO;
1766         return;
1767
1768 clean_txd:
1769         txd->flags = 0;
1770         txd->l4_offset = 0;
1771         txd->lso = 0;
1772 }
1773
1774 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1775 static inline void
1776 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1777                  struct rte_mbuf *mb)
1778 {
1779         uint64_t ol_flags;
1780         struct nfp_net_hw *hw = txq->hw;
1781
1782         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1783                 return;
1784
1785         ol_flags = mb->ol_flags;
1786
1787         /* IPv6 does not need checksum */
1788         if (ol_flags & PKT_TX_IP_CKSUM)
1789                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1790
1791         switch (ol_flags & PKT_TX_L4_MASK) {
1792         case PKT_TX_UDP_CKSUM:
1793                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1794                 break;
1795         case PKT_TX_TCP_CKSUM:
1796                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1797                 break;
1798         }
1799
1800         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1801                 txd->flags |= PCIE_DESC_TX_CSUM;
1802 }
1803
1804 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1805 static inline void
1806 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1807                  struct rte_mbuf *mb)
1808 {
1809         struct nfp_net_hw *hw = rxq->hw;
1810
1811         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1812                 return;
1813
1814         /* If IPv4 and IP checksum error, fail */
1815         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1816             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1817                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1818
1819         /* If neither UDP nor TCP return */
1820         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1821             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1822                 return;
1823
1824         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1825             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1826                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1827
1828         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1829             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1830                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1831 }
1832
1833 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1834 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1835
1836 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1837
1838 /*
1839  * nfp_net_set_hash - Set mbuf hash data
1840  *
1841  * The RSS hash and hash-type are pre-pended to the packet data.
1842  * Extract and decode it and set the mbuf fields.
1843  */
1844 static inline void
1845 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1846                  struct rte_mbuf *mbuf)
1847 {
1848         struct nfp_net_hw *hw = rxq->hw;
1849         uint8_t *meta_offset;
1850         uint32_t meta_info;
1851         uint32_t hash = 0;
1852         uint32_t hash_type = 0;
1853
1854         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1855                 return;
1856
1857         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1858                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1859                         return;
1860
1861                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1862                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1863
1864         } else if (NFP_DESC_META_LEN(rxd)) {
1865                 /*
1866                  * new metadata api:
1867                  * <----  32 bit  ----->
1868                  * m    field type word
1869                  * e     data field #2
1870                  * t     data field #1
1871                  * a     data field #0
1872                  * ====================
1873                  *    packet data
1874                  *
1875                  * Field type word contains up to 8 4bit field types
1876                  * A 4bit field type refers to a data field word
1877                  * A data field word can have several 4bit field types
1878                  */
1879                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1880                 meta_offset -= NFP_DESC_META_LEN(rxd);
1881                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1882                 meta_offset += 4;
1883                 /* NFP PMD just supports metadata for hashing */
1884                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1885                 case NFP_NET_META_HASH:
1886                         /* next field type is about the hash type */
1887                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1888                         /* hash value is in the data field */
1889                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1890                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1891                         break;
1892                 default:
1893                         /* Unsupported metadata can be a performance issue */
1894                         return;
1895                 }
1896         } else {
1897                 return;
1898         }
1899
1900         mbuf->hash.rss = hash;
1901         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1902
1903         switch (hash_type) {
1904         case NFP_NET_RSS_IPV4:
1905                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1906                 break;
1907         case NFP_NET_RSS_IPV6:
1908                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1909                 break;
1910         case NFP_NET_RSS_IPV6_EX:
1911                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1912                 break;
1913         default:
1914                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1915         }
1916 }
1917
1918 static inline void
1919 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1920 {
1921         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1922 }
1923
1924 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1925
1926 /*
1927  * RX path design:
1928  *
1929  * There are some decissions to take:
1930  * 1) How to check DD RX descriptors bit
1931  * 2) How and when to allocate new mbufs
1932  *
1933  * Current implementation checks just one single DD bit each loop. As each
1934  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1935  * a single cache line instead. Tests with this change have not shown any
1936  * performance improvement but it requires further investigation. For example,
1937  * depending on which descriptor is next, the number of descriptors could be
1938  * less than 8 for just checking those in the same cache line. This implies
1939  * extra work which could be counterproductive by itself. Indeed, last firmware
1940  * changes are just doing this: writing several descriptors with the DD bit
1941  * for saving PCIe bandwidth and DMA operations from the NFP.
1942  *
1943  * Mbuf allocation is done when a new packet is received. Then the descriptor
1944  * is automatically linked with the new mbuf and the old one is given to the
1945  * user. The main drawback with this design is mbuf allocation is heavier than
1946  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1947  * cache point of view it does not seem allocating the mbuf early on as we are
1948  * doing now have any benefit at all. Again, tests with this change have not
1949  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1950  * so looking at the implications of this type of allocation should be studied
1951  * deeply
1952  */
1953
1954 static uint16_t
1955 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1956 {
1957         struct nfp_net_rxq *rxq;
1958         struct nfp_net_rx_desc *rxds;
1959         struct nfp_net_rx_buff *rxb;
1960         struct nfp_net_hw *hw;
1961         struct rte_mbuf *mb;
1962         struct rte_mbuf *new_mb;
1963         uint16_t nb_hold;
1964         uint64_t dma_addr;
1965         int avail;
1966
1967         rxq = rx_queue;
1968         if (unlikely(rxq == NULL)) {
1969                 /*
1970                  * DPDK just checks the queue is lower than max queues
1971                  * enabled. But the queue needs to be configured
1972                  */
1973                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1974                 return -EINVAL;
1975         }
1976
1977         hw = rxq->hw;
1978         avail = 0;
1979         nb_hold = 0;
1980
1981         while (avail < nb_pkts) {
1982                 rxb = &rxq->rxbufs[rxq->rd_p];
1983                 if (unlikely(rxb == NULL)) {
1984                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1985                         break;
1986                 }
1987
1988                 /*
1989                  * Memory barrier to ensure that we won't do other
1990                  * reads before the DD bit.
1991                  */
1992                 rte_rmb();
1993
1994                 rxds = &rxq->rxds[rxq->rd_p];
1995                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1996                         break;
1997
1998                 /*
1999                  * We got a packet. Let's alloc a new mbuff for refilling the
2000                  * free descriptor ring as soon as possible
2001                  */
2002                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2003                 if (unlikely(new_mb == NULL)) {
2004                         RTE_LOG_DP(DEBUG, PMD,
2005                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2006                                 rxq->port_id, (unsigned int)rxq->qidx);
2007                         nfp_net_mbuf_alloc_failed(rxq);
2008                         break;
2009                 }
2010
2011                 nb_hold++;
2012
2013                 /*
2014                  * Grab the mbuff and refill the descriptor with the
2015                  * previously allocated mbuff
2016                  */
2017                 mb = rxb->mbuf;
2018                 rxb->mbuf = new_mb;
2019
2020                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
2021                            rxds->rxd.data_len, rxq->mbuf_size);
2022
2023                 /* Size of this segment */
2024                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2025                 /* Size of the whole packet. We just support 1 segment */
2026                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2027
2028                 if (unlikely((mb->data_len + hw->rx_offset) >
2029                              rxq->mbuf_size)) {
2030                         /*
2031                          * This should not happen and the user has the
2032                          * responsibility of avoiding it. But we have
2033                          * to give some info about the error
2034                          */
2035                         RTE_LOG_DP(ERR, PMD,
2036                                 "mbuf overflow likely due to the RX offset.\n"
2037                                 "\t\tYour mbuf size should have extra space for"
2038                                 " RX offset=%u bytes.\n"
2039                                 "\t\tCurrently you just have %u bytes available"
2040                                 " but the received packet is %u bytes long",
2041                                 hw->rx_offset,
2042                                 rxq->mbuf_size - hw->rx_offset,
2043                                 mb->data_len);
2044                         return -EINVAL;
2045                 }
2046
2047                 /* Filling the received mbuff with packet info */
2048                 if (hw->rx_offset)
2049                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2050                 else
2051                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2052                                        NFP_DESC_META_LEN(rxds);
2053
2054                 /* No scatter mode supported */
2055                 mb->nb_segs = 1;
2056                 mb->next = NULL;
2057
2058                 /* Checking the RSS flag */
2059                 nfp_net_set_hash(rxq, rxds, mb);
2060
2061                 /* Checking the checksum flag */
2062                 nfp_net_rx_cksum(rxq, rxds, mb);
2063
2064                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2065                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2066                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2067                         mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
2068                 }
2069
2070                 /* Adding the mbuff to the mbuff array passed by the app */
2071                 rx_pkts[avail++] = mb;
2072
2073                 /* Now resetting and updating the descriptor */
2074                 rxds->vals[0] = 0;
2075                 rxds->vals[1] = 0;
2076                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2077                 rxds->fld.dd = 0;
2078                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2079                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2080
2081                 rxq->rd_p++;
2082                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2083                         rxq->rd_p = 0;
2084         }
2085
2086         if (nb_hold == 0)
2087                 return nb_hold;
2088
2089         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received\n",
2090                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2091
2092         nb_hold += rxq->nb_rx_hold;
2093
2094         /*
2095          * FL descriptors needs to be written before incrementing the
2096          * FL queue WR pointer
2097          */
2098         rte_wmb();
2099         if (nb_hold > rxq->rx_free_thresh) {
2100                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2101                            rxq->port_id, (unsigned int)rxq->qidx,
2102                            (unsigned)nb_hold, (unsigned)avail);
2103                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2104                 nb_hold = 0;
2105         }
2106         rxq->nb_rx_hold = nb_hold;
2107
2108         return avail;
2109 }
2110
2111 /*
2112  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2113  * status
2114  * @txq: TX queue to work with
2115  * Returns number of descriptors freed
2116  */
2117 int
2118 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2119 {
2120         uint32_t qcp_rd_p;
2121         int todo;
2122
2123         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2124                    " status\n", txq->qidx);
2125
2126         /* Work out how many packets have been sent */
2127         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2128
2129         if (qcp_rd_p == txq->rd_p) {
2130                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2131                            "packets (%u, %u)\n", txq->qidx,
2132                            qcp_rd_p, txq->rd_p);
2133                 return 0;
2134         }
2135
2136         if (qcp_rd_p > txq->rd_p)
2137                 todo = qcp_rd_p - txq->rd_p;
2138         else
2139                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2140
2141         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2142                    qcp_rd_p, txq->rd_p, txq->rd_p);
2143
2144         if (todo == 0)
2145                 return todo;
2146
2147         txq->rd_p += todo;
2148         if (unlikely(txq->rd_p >= txq->tx_count))
2149                 txq->rd_p -= txq->tx_count;
2150
2151         return todo;
2152 }
2153
2154 /* Leaving always free descriptors for avoiding wrapping confusion */
2155 static inline
2156 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2157 {
2158         if (txq->wr_p >= txq->rd_p)
2159                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2160         else
2161                 return txq->rd_p - txq->wr_p - 8;
2162 }
2163
2164 /*
2165  * nfp_net_txq_full - Check if the TX queue free descriptors
2166  * is below tx_free_threshold
2167  *
2168  * @txq: TX queue to check
2169  *
2170  * This function uses the host copy* of read/write pointers
2171  */
2172 static inline
2173 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2174 {
2175         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2176 }
2177
2178 static uint16_t
2179 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2180 {
2181         struct nfp_net_txq *txq;
2182         struct nfp_net_hw *hw;
2183         struct nfp_net_tx_desc *txds, txd;
2184         struct rte_mbuf *pkt;
2185         uint64_t dma_addr;
2186         int pkt_size, dma_size;
2187         uint16_t free_descs, issued_descs;
2188         struct rte_mbuf **lmbuf;
2189         int i;
2190
2191         txq = tx_queue;
2192         hw = txq->hw;
2193         txds = &txq->txds[txq->wr_p];
2194
2195         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2196                    txq->qidx, txq->wr_p, nb_pkts);
2197
2198         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2199                 nfp_net_tx_free_bufs(txq);
2200
2201         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2202         if (unlikely(free_descs == 0))
2203                 return 0;
2204
2205         pkt = *tx_pkts;
2206
2207         i = 0;
2208         issued_descs = 0;
2209         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2210                    txq->qidx, nb_pkts);
2211         /* Sending packets */
2212         while ((i < nb_pkts) && free_descs) {
2213                 /* Grabbing the mbuf linked to the current descriptor */
2214                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2215                 /* Warming the cache for releasing the mbuf later on */
2216                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2217
2218                 pkt = *(tx_pkts + i);
2219
2220                 if (unlikely((pkt->nb_segs > 1) &&
2221                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2222                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2223                         rte_panic("Multisegment packet unsupported\n");
2224                 }
2225
2226                 /* Checking if we have enough descriptors */
2227                 if (unlikely(pkt->nb_segs > free_descs))
2228                         goto xmit_end;
2229
2230                 /*
2231                  * Checksum and VLAN flags just in the first descriptor for a
2232                  * multisegment packet, but TSO info needs to be in all of them.
2233                  */
2234                 txd.data_len = pkt->pkt_len;
2235                 nfp_net_tx_tso(txq, &txd, pkt);
2236                 nfp_net_tx_cksum(txq, &txd, pkt);
2237
2238                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2239                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2240                         txd.flags |= PCIE_DESC_TX_VLAN;
2241                         txd.vlan = pkt->vlan_tci;
2242                 }
2243
2244                 /*
2245                  * mbuf data_len is the data in one segment and pkt_len data
2246                  * in the whole packet. When the packet is just one segment,
2247                  * then data_len = pkt_len
2248                  */
2249                 pkt_size = pkt->pkt_len;
2250
2251                 while (pkt) {
2252                         /* Copying TSO, VLAN and cksum info */
2253                         *txds = txd;
2254
2255                         /* Releasing mbuf used by this descriptor previously*/
2256                         if (*lmbuf)
2257                                 rte_pktmbuf_free_seg(*lmbuf);
2258
2259                         /*
2260                          * Linking mbuf with descriptor for being released
2261                          * next time descriptor is used
2262                          */
2263                         *lmbuf = pkt;
2264
2265                         dma_size = pkt->data_len;
2266                         dma_addr = rte_mbuf_data_dma_addr(pkt);
2267                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2268                                    "%" PRIx64 "\n", dma_addr);
2269
2270                         /* Filling descriptors fields */
2271                         txds->dma_len = dma_size;
2272                         txds->data_len = txd.data_len;
2273                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2274                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2275                         ASSERT(free_descs > 0);
2276                         free_descs--;
2277
2278                         txq->wr_p++;
2279                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2280                                 txq->wr_p = 0;
2281
2282                         pkt_size -= dma_size;
2283                         if (!pkt_size)
2284                                 /* End of packet */
2285                                 txds->offset_eop |= PCIE_DESC_TX_EOP;
2286                         else
2287                                 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2288
2289                         pkt = pkt->next;
2290                         /* Referencing next free TX descriptor */
2291                         txds = &txq->txds[txq->wr_p];
2292                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2293                         issued_descs++;
2294                 }
2295                 i++;
2296         }
2297
2298 xmit_end:
2299         /* Increment write pointers. Force memory write before we let HW know */
2300         rte_wmb();
2301         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2302
2303         return i;
2304 }
2305
2306 static void
2307 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2308 {
2309         uint32_t new_ctrl, update;
2310         struct nfp_net_hw *hw;
2311
2312         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2313         new_ctrl = 0;
2314
2315         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2316             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2317                 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2318                         " ETH_VLAN_EXTEND_OFFLOAD");
2319
2320         /* Enable vlan strip if it is not configured yet */
2321         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2322             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2323                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2324
2325         /* Disable vlan strip just if it is configured */
2326         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2327             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2328                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2329
2330         if (new_ctrl == 0)
2331                 return;
2332
2333         update = NFP_NET_CFG_UPDATE_GEN;
2334
2335         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2336                 return;
2337
2338         hw->ctrl = new_ctrl;
2339 }
2340
2341 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2342 static int
2343 nfp_net_reta_update(struct rte_eth_dev *dev,
2344                     struct rte_eth_rss_reta_entry64 *reta_conf,
2345                     uint16_t reta_size)
2346 {
2347         uint32_t reta, mask;
2348         int i, j;
2349         int idx, shift;
2350         uint32_t update;
2351         struct nfp_net_hw *hw =
2352                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2353
2354         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2355                 return -EINVAL;
2356
2357         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2358                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2359                         "(%d) doesn't match the number hardware can supported "
2360                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2361                 return -EINVAL;
2362         }
2363
2364         /*
2365          * Update Redirection Table. There are 128 8bit-entries which can be
2366          * manage as 32 32bit-entries
2367          */
2368         for (i = 0; i < reta_size; i += 4) {
2369                 /* Handling 4 RSS entries per loop */
2370                 idx = i / RTE_RETA_GROUP_SIZE;
2371                 shift = i % RTE_RETA_GROUP_SIZE;
2372                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2373
2374                 if (!mask)
2375                         continue;
2376
2377                 reta = 0;
2378                 /* If all 4 entries were set, don't need read RETA register */
2379                 if (mask != 0xF)
2380                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2381
2382                 for (j = 0; j < 4; j++) {
2383                         if (!(mask & (0x1 << j)))
2384                                 continue;
2385                         if (mask != 0xF)
2386                                 /* Clearing the entry bits */
2387                                 reta &= ~(0xFF << (8 * j));
2388                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2389                 }
2390                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2391                               reta);
2392         }
2393
2394         update = NFP_NET_CFG_UPDATE_RSS;
2395
2396         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2397                 return -EIO;
2398
2399         return 0;
2400 }
2401
2402  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2403 static int
2404 nfp_net_reta_query(struct rte_eth_dev *dev,
2405                    struct rte_eth_rss_reta_entry64 *reta_conf,
2406                    uint16_t reta_size)
2407 {
2408         uint8_t i, j, mask;
2409         int idx, shift;
2410         uint32_t reta;
2411         struct nfp_net_hw *hw;
2412
2413         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414
2415         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2416                 return -EINVAL;
2417
2418         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2419                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2420                         "(%d) doesn't match the number hardware can supported "
2421                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2422                 return -EINVAL;
2423         }
2424
2425         /*
2426          * Reading Redirection Table. There are 128 8bit-entries which can be
2427          * manage as 32 32bit-entries
2428          */
2429         for (i = 0; i < reta_size; i += 4) {
2430                 /* Handling 4 RSS entries per loop */
2431                 idx = i / RTE_RETA_GROUP_SIZE;
2432                 shift = i % RTE_RETA_GROUP_SIZE;
2433                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2434
2435                 if (!mask)
2436                         continue;
2437
2438                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2439                                     shift);
2440                 for (j = 0; j < 4; j++) {
2441                         if (!(mask & (0x1 << j)))
2442                                 continue;
2443                         reta_conf->reta[shift + j] =
2444                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2445                 }
2446         }
2447         return 0;
2448 }
2449
2450 static int
2451 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2452                         struct rte_eth_rss_conf *rss_conf)
2453 {
2454         uint32_t update;
2455         uint32_t cfg_rss_ctrl = 0;
2456         uint8_t key;
2457         uint64_t rss_hf;
2458         int i;
2459         struct nfp_net_hw *hw;
2460
2461         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462
2463         rss_hf = rss_conf->rss_hf;
2464
2465         /* Checking if RSS is enabled */
2466         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2467                 if (rss_hf != 0) { /* Enable RSS? */
2468                         RTE_LOG(ERR, PMD, "RSS unsupported\n");
2469                         return -EINVAL;
2470                 }
2471                 return 0; /* Nothing to do */
2472         }
2473
2474         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2475                 RTE_LOG(ERR, PMD, "hash key too long\n");
2476                 return -EINVAL;
2477         }
2478
2479         if (rss_hf & ETH_RSS_IPV4)
2480                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2481                                 NFP_NET_CFG_RSS_IPV4_TCP |
2482                                 NFP_NET_CFG_RSS_IPV4_UDP;
2483
2484         if (rss_hf & ETH_RSS_IPV6)
2485                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2486                                 NFP_NET_CFG_RSS_IPV6_TCP |
2487                                 NFP_NET_CFG_RSS_IPV6_UDP;
2488
2489         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2490         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2491
2492         /* configuring where to apply the RSS hash */
2493         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2494
2495         /* Writing the key byte a byte */
2496         for (i = 0; i < rss_conf->rss_key_len; i++) {
2497                 memcpy(&key, &rss_conf->rss_key[i], 1);
2498                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2499         }
2500
2501         /* Writing the key size */
2502         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2503
2504         update = NFP_NET_CFG_UPDATE_RSS;
2505
2506         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2507                 return -EIO;
2508
2509         return 0;
2510 }
2511
2512 static int
2513 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2514                           struct rte_eth_rss_conf *rss_conf)
2515 {
2516         uint64_t rss_hf;
2517         uint32_t cfg_rss_ctrl;
2518         uint8_t key;
2519         int i;
2520         struct nfp_net_hw *hw;
2521
2522         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523
2524         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2525                 return -EINVAL;
2526
2527         rss_hf = rss_conf->rss_hf;
2528         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2529
2530         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2531                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2532
2533         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2534                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2535
2536         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2537                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2538
2539         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2540                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2541
2542         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2543                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2544
2545         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2546                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2547
2548         /* Reading the key size */
2549         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2550
2551         /* Reading the key byte a byte */
2552         for (i = 0; i < rss_conf->rss_key_len; i++) {
2553                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2554                 memcpy(&rss_conf->rss_key[i], &key, 1);
2555         }
2556
2557         return 0;
2558 }
2559
2560 /* Initialise and register driver with DPDK Application */
2561 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2562         .dev_configure          = nfp_net_configure,
2563         .dev_start              = nfp_net_start,
2564         .dev_stop               = nfp_net_stop,
2565         .dev_close              = nfp_net_close,
2566         .promiscuous_enable     = nfp_net_promisc_enable,
2567         .promiscuous_disable    = nfp_net_promisc_disable,
2568         .link_update            = nfp_net_link_update,
2569         .stats_get              = nfp_net_stats_get,
2570         .stats_reset            = nfp_net_stats_reset,
2571         .dev_infos_get          = nfp_net_infos_get,
2572         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2573         .mtu_set                = nfp_net_dev_mtu_set,
2574         .vlan_offload_set       = nfp_net_vlan_offload_set,
2575         .reta_update            = nfp_net_reta_update,
2576         .reta_query             = nfp_net_reta_query,
2577         .rss_hash_update        = nfp_net_rss_hash_update,
2578         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2579         .rx_queue_setup         = nfp_net_rx_queue_setup,
2580         .rx_queue_release       = nfp_net_rx_queue_release,
2581         .rx_queue_count         = nfp_net_rx_queue_count,
2582         .tx_queue_setup         = nfp_net_tx_queue_setup,
2583         .tx_queue_release       = nfp_net_tx_queue_release,
2584         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2585         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2586 };
2587
2588 /*
2589  * All eth_dev created got its private data, but before nfp_net_init, that
2590  * private data is referencing private data for all the PF ports. This is due
2591  * to how the vNIC bars are mapped based on first port, so all ports need info
2592  * about port 0 private data. Inside nfp_net_init the private data pointer is
2593  * changed to the right address for each port once the bars have been mapped.
2594  *
2595  * This functions helps to find out which port and therefore which offset
2596  * inside the private data array to use.
2597  */
2598 static int
2599 get_pf_port_number(char *name)
2600 {
2601         char *pf_str = name;
2602         int size = 0;
2603
2604         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2605                 pf_str++;
2606
2607         if (size == 30)
2608                 /*
2609                  * This should not happen at all and it would mean major
2610                  * implementation fault.
2611                  */
2612                 rte_panic("nfp_net: problem with pf device name\n");
2613
2614         /* Expecting _portX with X within [0,7] */
2615         pf_str += 5;
2616
2617         return (int)strtol(pf_str, NULL, 10);
2618 }
2619
2620 static int
2621 nfp_net_init(struct rte_eth_dev *eth_dev)
2622 {
2623         struct rte_pci_device *pci_dev;
2624         struct nfp_net_hw *hw, *hwport0;
2625
2626         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2627         uint32_t start_q;
2628         int stride = 4;
2629
2630         nspu_desc_t *nspu_desc = NULL;
2631         uint64_t bar_offset;
2632         int port = 0;
2633
2634         PMD_INIT_FUNC_TRACE();
2635
2636         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2637
2638         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2639             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2640                 port = get_pf_port_number(eth_dev->data->name);
2641                 if (port < 0 || port > 7) {
2642                         RTE_LOG(ERR, PMD, "Port value is wrong\n");
2643                         return -ENODEV;
2644                 }
2645
2646                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2647
2648                 /* This points to port 0 private data */
2649                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2650
2651                 /* This points to the specific port private data */
2652                 hw = &hwport0[port];
2653                 hw->pf_port_idx = port;
2654         } else {
2655                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2656                 hwport0 = 0;
2657         }
2658
2659         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2660         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2661         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2662
2663         /* For secondary processes, the primary has done all the work */
2664         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2665                 return 0;
2666
2667         rte_eth_copy_pci_info(eth_dev, pci_dev);
2668         /* hotplug is not possible with multiport PF */
2669         if (!hw->pf_multiport_enabled)
2670                 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2671
2672         hw->device_id = pci_dev->id.device_id;
2673         hw->vendor_id = pci_dev->id.vendor_id;
2674         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2675         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2676
2677         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2678                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2679                      pci_dev->addr.domain, pci_dev->addr.bus,
2680                      pci_dev->addr.devid, pci_dev->addr.function);
2681
2682         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2683         if (hw->ctrl_bar == NULL) {
2684                 RTE_LOG(ERR, PMD,
2685                         "hw->ctrl_bar is NULL. BAR0 not configured\n");
2686                 return -ENODEV;
2687         }
2688
2689         if (hw->is_pf && port == 0) {
2690                 nspu_desc = hw->nspu_desc;
2691
2692                 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2693                         /*
2694                          * A firmware should be there after PF probe so this
2695                          * should not happen.
2696                          */
2697                         RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2698                         return -ENODEV;
2699                 }
2700
2701                 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2702                 hw->ctrl_bar += bar_offset;
2703                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2704         }
2705
2706         if (port > 0) {
2707                 if (!hwport0->ctrl_bar)
2708                         return -ENODEV;
2709
2710                 /* address based on port0 offset */
2711                 hw->ctrl_bar = hwport0->ctrl_bar +
2712                                (port * NFP_PF_CSR_SLICE_SIZE);
2713         }
2714
2715         PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2716
2717         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2718         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2719
2720         /* Work out where in the BAR the queues start. */
2721         switch (pci_dev->id.device_id) {
2722         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2723         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2724         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2725                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2726                 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2727                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2728                 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2729                 break;
2730         default:
2731                 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2732                 return -ENODEV;
2733         }
2734
2735         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2736         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2737
2738         if (hw->is_pf && port == 0) {
2739                 /* configure access to tx/rx vNIC BARs */
2740                 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2741                 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2742                                     bar_offset);
2743                 hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2744
2745                 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2746                 hwport0->hw_queues += bar_offset;
2747
2748                 /* Lets seize the chance to read eth table from hw */
2749                 if (nfp_nsp_eth_read_table(nspu_desc, &hw->eth_table))
2750                         return -ENODEV;
2751         }
2752
2753         if (hw->is_pf) {
2754                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2755                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2756                 eth_dev->data->dev_private = hw;
2757         } else {
2758                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2759                              tx_bar_off;
2760                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2761                              rx_bar_off;
2762         }
2763
2764         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2765                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2766
2767         nfp_net_cfg_queue_setup(hw);
2768
2769         /* Get some of the read-only fields from the config BAR */
2770         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2771         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2772         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2773         hw->mtu = hw->max_mtu;
2774
2775         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2776                 hw->rx_offset = NFP_NET_RX_OFFSET;
2777         else
2778                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2779
2780         PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2781                      hw->ver, hw->max_mtu);
2782         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2783                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2784                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2785                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2786                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2787                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2788                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2789                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2790                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2791                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2792                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2793                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "");
2794
2795         hw->ctrl = 0;
2796
2797         hw->stride_rx = stride;
2798         hw->stride_tx = stride;
2799
2800         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2801                      hw->max_rx_queues, hw->max_tx_queues);
2802
2803         /* Initializing spinlock for reconfigs */
2804         rte_spinlock_init(&hw->reconfig_lock);
2805
2806         /* Allocating memory for mac addr */
2807         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2808         if (eth_dev->data->mac_addrs == NULL) {
2809                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2810                 return -ENOMEM;
2811         }
2812
2813         if (hw->is_pf) {
2814                 nfp_net_pf_read_mac(hwport0, port);
2815                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2816         } else {
2817                 nfp_net_vf_read_mac(hw);
2818         }
2819
2820         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2821                 /* Using random mac addresses for VFs */
2822                 eth_random_addr(&hw->mac_addr[0]);
2823                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2824         }
2825
2826         /* Copying mac address to DPDK eth_dev struct */
2827         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2828                         &eth_dev->data->mac_addrs[0]);
2829
2830         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2831                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2832                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2833                      pci_dev->id.device_id,
2834                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2835                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2836
2837         /* Registering LSC interrupt handler */
2838         rte_intr_callback_register(&pci_dev->intr_handle,
2839                                    nfp_net_dev_interrupt_handler,
2840                                    (void *)eth_dev);
2841
2842         /* Telling the firmware about the LSC interrupt entry */
2843         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2844
2845         /* Recording current stats counters values */
2846         nfp_net_stats_reset(eth_dev);
2847
2848         return 0;
2849 }
2850
2851 static int
2852 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2853                   nfpu_desc_t *nfpu_desc, void **priv)
2854 {
2855         struct rte_eth_dev *eth_dev;
2856         struct nfp_net_hw *hw;
2857         char *port_name;
2858         int ret;
2859
2860         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2861         if (!port_name)
2862                 return -ENOMEM;
2863
2864         if (ports > 1)
2865                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2866         else
2867                 sprintf(port_name, "%s", dev->device.name);
2868
2869         eth_dev = rte_eth_dev_allocate(port_name);
2870         if (!eth_dev)
2871                 return -ENOMEM;
2872
2873         if (port == 0) {
2874                 *priv = rte_zmalloc(port_name,
2875                                     sizeof(struct nfp_net_adapter) * ports,
2876                                     RTE_CACHE_LINE_SIZE);
2877                 if (!*priv) {
2878                         rte_eth_dev_release_port(eth_dev);
2879                         return -ENOMEM;
2880                 }
2881         }
2882
2883         eth_dev->data->dev_private = *priv;
2884
2885         /*
2886          * dev_private pointing to port0 dev_private because we need
2887          * to configure vNIC bars based on port0 at nfp_net_init.
2888          * Then dev_private is adjusted per port.
2889          */
2890         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2891         hw->nspu_desc = nfpu_desc->nspu;
2892         hw->nfpu_desc = nfpu_desc;
2893         hw->is_pf = 1;
2894         if (ports > 1)
2895                 hw->pf_multiport_enabled = 1;
2896
2897         eth_dev->device = &dev->device;
2898         rte_eth_copy_pci_info(eth_dev, dev);
2899
2900         ret = nfp_net_init(eth_dev);
2901
2902         if (ret)
2903                 rte_eth_dev_release_port(eth_dev);
2904
2905         rte_free(port_name);
2906
2907         return ret;
2908 }
2909
2910 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2911                             struct rte_pci_device *dev)
2912 {
2913         nfpu_desc_t *nfpu_desc;
2914         nspu_desc_t *nspu_desc;
2915         uint64_t offset_symbol;
2916         uint8_t *bar_offset;
2917         int major, minor;
2918         int total_ports;
2919         void *priv = 0;
2920         int ret = -ENODEV;
2921         int i;
2922
2923         if (!dev)
2924                 return ret;
2925
2926         nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2927         if (!nfpu_desc)
2928                 return -ENOMEM;
2929
2930         if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2931                 RTE_LOG(ERR, PMD,
2932                         "nfpu_open failed\n");
2933                 goto nfpu_error;
2934         }
2935
2936         nspu_desc = nfpu_desc->nspu;
2937
2938
2939         /* Check NSP ABI version */
2940         if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2941                 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2942                 goto error;
2943         }
2944         PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2945
2946         if ((major == 0) && (minor < 20)) {
2947                 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2948                 goto error;
2949         }
2950
2951         ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
2952                                &offset_symbol);
2953         if (ret)
2954                 goto error;
2955
2956         bar_offset = (uint8_t *)dev->mem_resource[0].addr;
2957         bar_offset += offset_symbol;
2958         total_ports = (uint32_t)*bar_offset;
2959         PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
2960
2961         if (total_ports <= 0 || total_ports > 8) {
2962                 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
2963                 ret = -ENODEV;
2964                 goto error;
2965         }
2966
2967         for (i = 0; i < total_ports; i++) {
2968                 ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
2969                 if (ret)
2970                         goto error;
2971         }
2972
2973         return 0;
2974
2975 error:
2976         nfpu_close(nfpu_desc);
2977 nfpu_error:
2978         rte_free(nfpu_desc);
2979
2980         return ret;
2981 }
2982
2983 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
2984         {
2985                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2986                                PCI_DEVICE_ID_NFP4000_PF_NIC)
2987         },
2988         {
2989                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2990                                PCI_DEVICE_ID_NFP6000_PF_NIC)
2991         },
2992         {
2993                 .vendor_id = 0,
2994         },
2995 };
2996
2997 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
2998         {
2999                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3000                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3001         },
3002         {
3003                 .vendor_id = 0,
3004         },
3005 };
3006
3007 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3008         struct rte_pci_device *pci_dev)
3009 {
3010         return rte_eth_dev_pci_generic_probe(pci_dev,
3011                 sizeof(struct nfp_net_adapter), nfp_net_init);
3012 }
3013
3014 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3015 {
3016         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3017 }
3018
3019 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3020         .id_table = pci_id_nfp_pf_net_map,
3021         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3022         .probe = nfp_pf_pci_probe,
3023         .remove = eth_nfp_pci_remove,
3024 };
3025
3026 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3027         .id_table = pci_id_nfp_vf_net_map,
3028         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3029         .probe = eth_nfp_pci_probe,
3030         .remove = eth_nfp_pci_remove,
3031 };
3032
3033 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3034 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3035 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3036 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3037 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3038 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3039
3040 /*
3041  * Local variables:
3042  * c-file-style: "Linux"
3043  * indent-tabs-mode: t
3044  * End:
3045  */