2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
59 #include "nfp_net_pmd.h"
60 #include "nfp_net_logs.h"
61 #include "nfp_net_ctrl.h"
64 static void nfp_net_close(struct rte_eth_dev *dev);
65 static int nfp_net_configure(struct rte_eth_dev *dev);
66 static void nfp_net_dev_interrupt_handler(void *param);
67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
70 struct rte_eth_dev_info *dev_info);
71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
80 static void nfp_net_rx_queue_release(void *rxq);
81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
82 uint16_t nb_desc, unsigned int socket_id,
83 const struct rte_eth_rxconf *rx_conf,
84 struct rte_mempool *mp);
85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
86 static void nfp_net_tx_queue_release(void *txq);
87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_txconf *tx_conf);
90 static int nfp_net_start(struct rte_eth_dev *dev);
91 static void nfp_net_stats_get(struct rte_eth_dev *dev,
92 struct rte_eth_stats *stats);
93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
94 static void nfp_net_stop(struct rte_eth_dev *dev);
95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
99 * The offset of the queue controller queues in the PCIe Target. These
100 * happen to be at the same offset on the NFP6000 and the NFP3200 so
101 * we use a single macro here.
103 #define NFP_PCIE_QUEUE(_q) (0x800 * ((_q) & 0xff))
105 /* Maximum value which can be added to a queue with one transaction */
106 #define NFP_QCP_MAX_ADD 0x7f
108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
109 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
113 NFP_QCP_READ_PTR = 0,
118 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
119 * @q: Base address for queue structure
120 * @ptr: Add to the Read or Write pointer
121 * @val: Value to add to the queue pointer
123 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
130 if (ptr == NFP_QCP_READ_PTR)
131 off = NFP_QCP_QUEUE_ADD_RPTR;
133 off = NFP_QCP_QUEUE_ADD_WPTR;
135 while (val > NFP_QCP_MAX_ADD) {
136 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
137 val -= NFP_QCP_MAX_ADD;
140 nn_writel(rte_cpu_to_le_32(val), q + off);
144 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
145 * @q: Base address for queue structure
146 * @ptr: Read or Write pointer
148 static inline uint32_t
149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
154 if (ptr == NFP_QCP_READ_PTR)
155 off = NFP_QCP_QUEUE_STS_LO;
157 off = NFP_QCP_QUEUE_STS_HI;
159 val = rte_cpu_to_le_32(nn_readl(q + off));
161 if (ptr == NFP_QCP_READ_PTR)
162 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
164 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
168 * Functions to read/write from/to Config BAR
169 * Performs any endian conversion necessary.
171 static inline uint8_t
172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
174 return nn_readb(hw->ctrl_bar + off);
178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
180 nn_writeb(val, hw->ctrl_bar + off);
183 static inline uint32_t
184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
186 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
192 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
195 static inline uint64_t
196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
198 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
204 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
208 * Atomically reads link status information from global structure rte_eth_dev.
211 * - Pointer to the structure rte_eth_dev to read from.
212 * - Pointer to the buffer to be saved with the link status.
215 * - On success, zero.
216 * - On failure, negative value.
219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
220 struct rte_eth_link *link)
222 struct rte_eth_link *dst = link;
223 struct rte_eth_link *src = &dev->data->dev_link;
225 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
226 *(uint64_t *)src) == 0)
233 * Atomically writes the link status information into global
234 * structure rte_eth_dev.
237 * - Pointer to the structure rte_eth_dev to read from.
238 * - Pointer to the buffer to be saved with the link status.
241 * - On success, zero.
242 * - On failure, negative value.
245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
246 struct rte_eth_link *link)
248 struct rte_eth_link *dst = &dev->data->dev_link;
249 struct rte_eth_link *src = link;
251 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
252 *(uint64_t *)src) == 0)
259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
263 if (rxq->rxbufs == NULL)
266 for (i = 0; i < rxq->rx_count; i++) {
267 if (rxq->rxbufs[i].mbuf) {
268 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
269 rxq->rxbufs[i].mbuf = NULL;
275 nfp_net_rx_queue_release(void *rx_queue)
277 struct nfp_net_rxq *rxq = rx_queue;
280 nfp_net_rx_queue_release_mbufs(rxq);
281 rte_free(rxq->rxbufs);
287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
289 nfp_net_rx_queue_release_mbufs(rxq);
295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
299 if (txq->txbufs == NULL)
302 for (i = 0; i < txq->tx_count; i++) {
303 if (txq->txbufs[i].mbuf) {
304 rte_pktmbuf_free(txq->txbufs[i].mbuf);
305 txq->txbufs[i].mbuf = NULL;
311 nfp_net_tx_queue_release(void *tx_queue)
313 struct nfp_net_txq *txq = tx_queue;
316 nfp_net_tx_queue_release_mbufs(txq);
317 rte_free(txq->txbufs);
323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
325 nfp_net_tx_queue_release_mbufs(txq);
331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
335 struct timespec wait;
337 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
340 if (hw->qcp_cfg == NULL)
341 rte_panic("Bad configuration queue pointer\n");
343 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
346 wait.tv_nsec = 1000000;
348 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
350 /* Poll update field, waiting for NFP to ack the config */
351 for (cnt = 0; ; cnt++) {
352 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
355 if (new & NFP_NET_CFG_UPDATE_ERR) {
356 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
359 if (cnt >= NFP_NET_POLL_TIMEOUT) {
360 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
361 " %dms", update, cnt);
362 rte_panic("Exiting\n");
364 nanosleep(&wait, 0); /* waiting for a 1ms */
366 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
371 * Reconfigure the NIC
372 * @nn: device to reconfigure
373 * @ctrl: The value for the ctrl field in the BAR config
374 * @update: The value for the update field in the BAR config
376 * Write the update word to the BAR and ping the reconfig queue. Then poll
377 * until the firmware has acknowledged the update by zeroing the update word.
380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
384 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
387 rte_spinlock_lock(&hw->reconfig_lock);
389 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
390 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
394 err = __nfp_net_reconfig(hw, update);
396 rte_spinlock_unlock(&hw->reconfig_lock);
402 * Reconfig errors imply situations where they can be handled.
403 * Otherwise, rte_panic is called inside __nfp_net_reconfig
405 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
411 * Configure an Ethernet device. This function must be invoked first
412 * before any other function in the Ethernet API. This function can
413 * also be re-invoked when a device is in the stopped state.
416 nfp_net_configure(struct rte_eth_dev *dev)
418 struct rte_eth_conf *dev_conf;
419 struct rte_eth_rxmode *rxmode;
420 struct rte_eth_txmode *txmode;
421 uint32_t new_ctrl = 0;
423 struct nfp_net_hw *hw;
425 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
428 * A DPDK app sends info about how many queues to use and how
429 * those queues need to be configured. This is used by the
430 * DPDK core and it makes sure no more queues than those
431 * advertised by the driver are requested. This function is
432 * called after that internal process
435 PMD_INIT_LOG(DEBUG, "Configure");
437 dev_conf = &dev->data->dev_conf;
438 rxmode = &dev_conf->rxmode;
439 txmode = &dev_conf->txmode;
441 /* Checking TX mode */
442 if (txmode->mq_mode) {
443 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
447 /* Checking RX mode */
448 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
449 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
450 update = NFP_NET_CFG_UPDATE_RSS;
451 new_ctrl = NFP_NET_CFG_CTRL_RSS;
453 PMD_INIT_LOG(INFO, "RSS not supported");
458 if (rxmode->split_hdr_size) {
459 PMD_INIT_LOG(INFO, "rxmode does not support split header");
463 if (rxmode->hw_ip_checksum) {
464 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
465 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
467 PMD_INIT_LOG(INFO, "RXCSUM not supported");
472 if (rxmode->hw_vlan_filter) {
473 PMD_INIT_LOG(INFO, "VLAN filter not supported");
477 if (rxmode->hw_vlan_strip) {
478 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
479 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
481 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
486 if (rxmode->hw_vlan_extend) {
487 PMD_INIT_LOG(INFO, "VLAN extended not supported");
491 /* Supporting VLAN insertion by default */
492 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
493 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
495 if (rxmode->jumbo_frame)
496 /* this is handled in rte_eth_dev_configure */
498 if (rxmode->hw_strip_crc) {
499 PMD_INIT_LOG(INFO, "strip CRC not supported");
503 if (rxmode->enable_scatter) {
504 PMD_INIT_LOG(INFO, "Scatter not supported");
511 update |= NFP_NET_CFG_UPDATE_GEN;
513 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
514 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
523 nfp_net_enable_queues(struct rte_eth_dev *dev)
525 struct nfp_net_hw *hw;
526 uint64_t enabled_queues = 0;
529 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
531 /* Enabling the required TX queues in the device */
532 for (i = 0; i < dev->data->nb_tx_queues; i++)
533 enabled_queues |= (1 << i);
535 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
539 /* Enabling the required RX queues in the device */
540 for (i = 0; i < dev->data->nb_rx_queues; i++)
541 enabled_queues |= (1 << i);
543 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
547 nfp_net_disable_queues(struct rte_eth_dev *dev)
549 struct nfp_net_hw *hw;
550 uint32_t new_ctrl, update = 0;
552 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
554 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
555 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
557 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
558 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
559 NFP_NET_CFG_UPDATE_MSIX;
561 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
562 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
564 /* If an error when reconfig we avoid to change hw state */
565 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
572 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
576 for (i = 0; i < dev->data->nb_rx_queues; i++) {
577 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
584 nfp_net_params_setup(struct nfp_net_hw *hw)
586 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
587 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
591 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
593 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
596 static void nfp_net_read_mac(struct nfp_net_hw *hw)
600 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
601 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
603 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
604 memcpy(&hw->mac_addr[4], &tmp, 2);
608 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
610 uint32_t mac0 = *(uint32_t *)mac;
613 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
616 mac1 = *(uint16_t *)mac;
617 nn_writew(rte_cpu_to_be_16(mac1),
618 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
622 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
623 struct rte_intr_handle *intr_handle)
625 struct nfp_net_hw *hw;
628 if (!intr_handle->intr_vec) {
629 intr_handle->intr_vec =
630 rte_zmalloc("intr_vec",
631 dev->data->nb_rx_queues * sizeof(int), 0);
632 if (!intr_handle->intr_vec) {
633 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
634 " intr_vec", dev->data->nb_rx_queues);
639 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
641 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
642 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
643 /* UIO just supports one queue and no LSC*/
644 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
645 intr_handle->intr_vec[0] = 0;
647 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
648 for (i = 0; i < dev->data->nb_rx_queues; i++) {
650 * The first msix vector is reserved for non
653 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
654 intr_handle->intr_vec[i] = i + 1;
655 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
656 intr_handle->intr_vec[i]);
660 /* Avoiding TX interrupts */
661 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
666 nfp_net_start(struct rte_eth_dev *dev)
668 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
669 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
670 uint32_t new_ctrl, update = 0;
671 struct nfp_net_hw *hw;
672 uint32_t intr_vector;
675 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
677 PMD_INIT_LOG(DEBUG, "Start");
679 /* Disabling queues just in case... */
680 nfp_net_disable_queues(dev);
682 /* Writing configuration parameters in the device */
683 nfp_net_params_setup(hw);
685 /* Enabling the required queues in the device */
686 nfp_net_enable_queues(dev);
688 /* check and configure queue intr-vector mapping */
689 if (dev->data->dev_conf.intr_conf.rxq != 0) {
690 if (hw->pf_multiport_enabled) {
691 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
692 "with NFP multiport PF");
695 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
697 * Better not to share LSC with RX interrupts.
698 * Unregistering LSC interrupt handler
700 rte_intr_callback_unregister(&pci_dev->intr_handle,
701 nfp_net_dev_interrupt_handler, (void *)dev);
703 if (dev->data->nb_rx_queues > 1) {
704 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
705 "supports 1 queue with UIO");
709 intr_vector = dev->data->nb_rx_queues;
710 if (rte_intr_efd_enable(intr_handle, intr_vector))
713 nfp_configure_rx_interrupt(dev, intr_handle);
714 update = NFP_NET_CFG_UPDATE_MSIX;
717 rte_intr_enable(intr_handle);
720 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
722 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
724 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
725 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
727 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
728 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
732 * Allocating rte mbuffs for configured rx queues.
733 * This requires queues being enabled before
735 if (nfp_net_rx_freelist_setup(dev) < 0) {
746 * An error returned by this function should mean the app
747 * exiting and then the system releasing all the memory
748 * allocated even memory coming from hugepages.
750 * The device could be enabled at this point with some queues
751 * ready for getting packets. This is true if the call to
752 * nfp_net_rx_freelist_setup() succeeds for some queues but
753 * fails for subsequent queues.
755 * This should make the app exiting but better if we tell the
758 nfp_net_disable_queues(dev);
763 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
765 nfp_net_stop(struct rte_eth_dev *dev)
769 PMD_INIT_LOG(DEBUG, "Stop");
771 nfp_net_disable_queues(dev);
774 for (i = 0; i < dev->data->nb_tx_queues; i++) {
775 nfp_net_reset_tx_queue(
776 (struct nfp_net_txq *)dev->data->tx_queues[i]);
779 for (i = 0; i < dev->data->nb_rx_queues; i++) {
780 nfp_net_reset_rx_queue(
781 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
785 /* Reset and stop device. The device can not be restarted. */
787 nfp_net_close(struct rte_eth_dev *dev)
789 struct nfp_net_hw *hw;
790 struct rte_pci_device *pci_dev;
792 PMD_INIT_LOG(DEBUG, "Close");
794 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
795 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
798 * We assume that the DPDK application is stopping all the
799 * threads/queues before calling the device close function.
804 rte_intr_disable(&pci_dev->intr_handle);
805 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
807 /* unregister callback func from eal lib */
808 rte_intr_callback_unregister(&pci_dev->intr_handle,
809 nfp_net_dev_interrupt_handler,
813 * The ixgbe PMD driver disables the pcie master on the
814 * device. The i40e does not...
819 nfp_net_promisc_enable(struct rte_eth_dev *dev)
821 uint32_t new_ctrl, update = 0;
822 struct nfp_net_hw *hw;
824 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
826 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
828 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
829 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
833 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
834 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
838 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
839 update = NFP_NET_CFG_UPDATE_GEN;
842 * DPDK sets promiscuous mode on just after this call assuming
843 * it can not fail ...
845 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
852 nfp_net_promisc_disable(struct rte_eth_dev *dev)
854 uint32_t new_ctrl, update = 0;
855 struct nfp_net_hw *hw;
857 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
859 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
860 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
864 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
865 update = NFP_NET_CFG_UPDATE_GEN;
868 * DPDK sets promiscuous mode off just before this call
869 * assuming it can not fail ...
871 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
878 * return 0 means link status changed, -1 means not changed
880 * Wait to complete is needed as it can take up to 9 seconds to get the Link
884 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
886 struct nfp_net_hw *hw;
887 struct rte_eth_link link, old;
888 uint32_t nn_link_status;
890 static const uint32_t ls_to_ethtool[] = {
891 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
892 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
893 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
894 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
895 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
896 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
897 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
898 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
901 PMD_DRV_LOG(DEBUG, "Link update\n");
903 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
905 memset(&old, 0, sizeof(old));
906 nfp_net_dev_atomic_read_link_status(dev, &old);
908 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
910 memset(&link, 0, sizeof(struct rte_eth_link));
912 if (nn_link_status & NFP_NET_CFG_STS_LINK)
913 link.link_status = ETH_LINK_UP;
915 link.link_duplex = ETH_LINK_FULL_DUPLEX;
917 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
918 NFP_NET_CFG_STS_LINK_RATE_MASK;
920 if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
921 ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
922 (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
923 /* We really do not know the speed wil old firmware */
924 link.link_speed = ETH_SPEED_NUM_NONE;
926 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
927 link.link_speed = ETH_SPEED_NUM_NONE;
929 link.link_speed = ls_to_ethtool[nn_link_status];
932 if (old.link_status != link.link_status) {
933 nfp_net_dev_atomic_write_link_status(dev, &link);
934 if (link.link_status)
935 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
937 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
945 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
948 struct nfp_net_hw *hw;
949 struct rte_eth_stats nfp_dev_stats;
951 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
953 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
955 /* reading per RX ring stats */
956 for (i = 0; i < dev->data->nb_rx_queues; i++) {
957 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
960 nfp_dev_stats.q_ipackets[i] =
961 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
963 nfp_dev_stats.q_ipackets[i] -=
964 hw->eth_stats_base.q_ipackets[i];
966 nfp_dev_stats.q_ibytes[i] =
967 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
969 nfp_dev_stats.q_ibytes[i] -=
970 hw->eth_stats_base.q_ibytes[i];
973 /* reading per TX ring stats */
974 for (i = 0; i < dev->data->nb_tx_queues; i++) {
975 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
978 nfp_dev_stats.q_opackets[i] =
979 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
981 nfp_dev_stats.q_opackets[i] -=
982 hw->eth_stats_base.q_opackets[i];
984 nfp_dev_stats.q_obytes[i] =
985 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
987 nfp_dev_stats.q_obytes[i] -=
988 hw->eth_stats_base.q_obytes[i];
991 nfp_dev_stats.ipackets =
992 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
994 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
996 nfp_dev_stats.ibytes =
997 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
999 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1001 nfp_dev_stats.opackets =
1002 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1004 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1006 nfp_dev_stats.obytes =
1007 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1009 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1011 /* reading general device stats */
1012 nfp_dev_stats.ierrors =
1013 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1015 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1017 nfp_dev_stats.oerrors =
1018 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1020 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1022 /* RX ring mbuf allocation failures */
1023 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1025 nfp_dev_stats.imissed =
1026 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1028 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1031 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1035 nfp_net_stats_reset(struct rte_eth_dev *dev)
1038 struct nfp_net_hw *hw;
1040 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043 * hw->eth_stats_base records the per counter starting point.
1044 * Lets update it now
1047 /* reading per RX ring stats */
1048 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1049 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1052 hw->eth_stats_base.q_ipackets[i] =
1053 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1055 hw->eth_stats_base.q_ibytes[i] =
1056 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1059 /* reading per TX ring stats */
1060 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1061 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1064 hw->eth_stats_base.q_opackets[i] =
1065 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1067 hw->eth_stats_base.q_obytes[i] =
1068 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1071 hw->eth_stats_base.ipackets =
1072 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1074 hw->eth_stats_base.ibytes =
1075 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1077 hw->eth_stats_base.opackets =
1078 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1080 hw->eth_stats_base.obytes =
1081 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1083 /* reading general device stats */
1084 hw->eth_stats_base.ierrors =
1085 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1087 hw->eth_stats_base.oerrors =
1088 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1090 /* RX ring mbuf allocation failures */
1091 dev->data->rx_mbuf_alloc_failed = 0;
1093 hw->eth_stats_base.imissed =
1094 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1098 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1100 struct nfp_net_hw *hw;
1102 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1104 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1105 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1106 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1107 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1108 dev_info->max_rx_pktlen = hw->mtu;
1109 /* Next should change when PF support is implemented */
1110 dev_info->max_mac_addrs = 1;
1112 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1113 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1115 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1116 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1117 DEV_RX_OFFLOAD_UDP_CKSUM |
1118 DEV_RX_OFFLOAD_TCP_CKSUM;
1120 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1121 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1123 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1124 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1125 DEV_TX_OFFLOAD_UDP_CKSUM |
1126 DEV_TX_OFFLOAD_TCP_CKSUM;
1128 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1130 .pthresh = DEFAULT_RX_PTHRESH,
1131 .hthresh = DEFAULT_RX_HTHRESH,
1132 .wthresh = DEFAULT_RX_WTHRESH,
1134 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1138 dev_info->default_txconf = (struct rte_eth_txconf) {
1140 .pthresh = DEFAULT_TX_PTHRESH,
1141 .hthresh = DEFAULT_TX_HTHRESH,
1142 .wthresh = DEFAULT_TX_WTHRESH,
1144 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1145 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1146 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1147 ETH_TXQ_FLAGS_NOOFFLOADS,
1150 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1151 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1153 dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1154 ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1155 ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1157 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1158 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1161 static const uint32_t *
1162 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1164 static const uint32_t ptypes[] = {
1165 /* refers to nfp_net_set_hash() */
1166 RTE_PTYPE_INNER_L3_IPV4,
1167 RTE_PTYPE_INNER_L3_IPV6,
1168 RTE_PTYPE_INNER_L3_IPV6_EXT,
1169 RTE_PTYPE_INNER_L4_MASK,
1173 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1179 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1181 struct nfp_net_rxq *rxq;
1182 struct nfp_net_rx_desc *rxds;
1186 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1193 * Other PMDs are just checking the DD bit in intervals of 4
1194 * descriptors and counting all four if the first has the DD
1195 * bit on. Of course, this is not accurate but can be good for
1196 * performance. But ideally that should be done in descriptors
1197 * chunks belonging to the same cache line
1200 while (count < rxq->rx_count) {
1201 rxds = &rxq->rxds[idx];
1202 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1209 if ((idx) == rxq->rx_count)
1217 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1219 struct rte_pci_device *pci_dev;
1220 struct nfp_net_hw *hw;
1223 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1226 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1229 /* Make sure all updates are written before un-masking */
1231 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1232 NFP_NET_CFG_ICR_UNMASKED);
1237 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1239 struct rte_pci_device *pci_dev;
1240 struct nfp_net_hw *hw;
1243 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1244 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1246 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1249 /* Make sure all updates are written before un-masking */
1251 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1256 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1258 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1259 struct rte_eth_link link;
1261 memset(&link, 0, sizeof(link));
1262 nfp_net_dev_atomic_read_link_status(dev, &link);
1263 if (link.link_status)
1264 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1265 (int)(dev->data->port_id), (unsigned)link.link_speed,
1266 link.link_duplex == ETH_LINK_FULL_DUPLEX
1267 ? "full-duplex" : "half-duplex");
1269 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1270 (int)(dev->data->port_id));
1272 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1273 pci_dev->addr.domain, pci_dev->addr.bus,
1274 pci_dev->addr.devid, pci_dev->addr.function);
1277 /* Interrupt configuration and handling */
1280 * nfp_net_irq_unmask - Unmask an interrupt
1282 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1283 * clear the ICR for the entry.
1286 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1288 struct nfp_net_hw *hw;
1289 struct rte_pci_device *pci_dev;
1291 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1292 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1294 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1295 /* If MSI-X auto-masking is used, clear the entry */
1297 rte_intr_enable(&pci_dev->intr_handle);
1299 /* Make sure all updates are written before un-masking */
1301 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1302 NFP_NET_CFG_ICR_UNMASKED);
1307 nfp_net_dev_interrupt_handler(void *param)
1310 struct rte_eth_link link;
1311 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1313 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1315 /* get the link status */
1316 memset(&link, 0, sizeof(link));
1317 nfp_net_dev_atomic_read_link_status(dev, &link);
1319 nfp_net_link_update(dev, 0);
1322 if (!link.link_status) {
1323 /* handle it 1 sec later, wait it being stable */
1324 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1325 /* likely to down */
1327 /* handle it 4 sec later, wait it being stable */
1328 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1331 if (rte_eal_alarm_set(timeout * 1000,
1332 nfp_net_dev_interrupt_delayed_handler,
1334 RTE_LOG(ERR, PMD, "Error setting alarm");
1336 nfp_net_irq_unmask(dev);
1341 * Interrupt handler which shall be registered for alarm callback for delayed
1342 * handling specific interrupt to wait for the stable nic state. As the NIC
1343 * interrupt state is not stable for nfp after link is just down, it needs
1344 * to wait 4 seconds to get the stable status.
1346 * @param handle Pointer to interrupt handle.
1347 * @param param The address of parameter (struct rte_eth_dev *)
1352 nfp_net_dev_interrupt_delayed_handler(void *param)
1354 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1356 nfp_net_link_update(dev, 0);
1357 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1359 nfp_net_dev_link_status_print(dev);
1362 nfp_net_irq_unmask(dev);
1366 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1368 struct nfp_net_hw *hw;
1370 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1372 /* check that mtu is within the allowed range */
1373 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1376 /* switch to jumbo mode if needed */
1377 if ((uint32_t)mtu > ETHER_MAX_LEN)
1378 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1380 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1382 /* update max frame size */
1383 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1385 /* writing to configuration space */
1386 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1394 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1395 uint16_t queue_idx, uint16_t nb_desc,
1396 unsigned int socket_id,
1397 const struct rte_eth_rxconf *rx_conf,
1398 struct rte_mempool *mp)
1400 const struct rte_memzone *tz;
1401 struct nfp_net_rxq *rxq;
1402 struct nfp_net_hw *hw;
1404 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406 PMD_INIT_FUNC_TRACE();
1408 /* Validating number of descriptors */
1409 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1410 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1411 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1412 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1417 * Free memory prior to re-allocation if needed. This is the case after
1418 * calling nfp_net_stop
1420 if (dev->data->rx_queues[queue_idx]) {
1421 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1422 dev->data->rx_queues[queue_idx] = NULL;
1425 /* Allocating rx queue data structure */
1426 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1427 RTE_CACHE_LINE_SIZE, socket_id);
1431 /* Hw queues mapping based on firmware confifguration */
1432 rxq->qidx = queue_idx;
1433 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1434 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1435 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1436 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1439 * Tracking mbuf size for detecting a potential mbuf overflow due to
1443 rxq->mbuf_size = rxq->mem_pool->elt_size;
1444 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1445 hw->flbufsz = rxq->mbuf_size;
1447 rxq->rx_count = nb_desc;
1448 rxq->port_id = dev->data->port_id;
1449 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1450 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1452 rxq->drop_en = rx_conf->rx_drop_en;
1455 * Allocate RX ring hardware descriptors. A memzone large enough to
1456 * handle the maximum ring size is allocated in order to allow for
1457 * resizing in later calls to the queue setup function.
1459 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1460 sizeof(struct nfp_net_rx_desc) *
1461 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1465 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1466 nfp_net_rx_queue_release(rxq);
1470 /* Saving physical and virtual addresses for the RX ring */
1471 rxq->dma = (uint64_t)tz->phys_addr;
1472 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1474 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1475 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1476 sizeof(*rxq->rxbufs) * nb_desc,
1477 RTE_CACHE_LINE_SIZE, socket_id);
1478 if (rxq->rxbufs == NULL) {
1479 nfp_net_rx_queue_release(rxq);
1483 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1484 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1486 nfp_net_reset_rx_queue(rxq);
1488 dev->data->rx_queues[queue_idx] = rxq;
1492 * Telling the HW about the physical address of the RX ring and number
1493 * of descriptors in log2 format
1495 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1496 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1502 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1504 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1508 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1511 for (i = 0; i < rxq->rx_count; i++) {
1512 struct nfp_net_rx_desc *rxd;
1513 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1516 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1517 (unsigned)rxq->qidx);
1521 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1523 rxd = &rxq->rxds[i];
1525 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1526 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1528 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1531 /* Make sure all writes are flushed before telling the hardware */
1534 /* Not advertising the whole ring as the firmware gets confused if so */
1535 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1538 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1544 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1545 uint16_t nb_desc, unsigned int socket_id,
1546 const struct rte_eth_txconf *tx_conf)
1548 const struct rte_memzone *tz;
1549 struct nfp_net_txq *txq;
1550 uint16_t tx_free_thresh;
1551 struct nfp_net_hw *hw;
1553 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555 PMD_INIT_FUNC_TRACE();
1557 /* Validating number of descriptors */
1558 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1559 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1560 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1561 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1565 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1566 tx_conf->tx_free_thresh :
1567 DEFAULT_TX_FREE_THRESH);
1569 if (tx_free_thresh > (nb_desc)) {
1571 "tx_free_thresh must be less than the number of TX "
1572 "descriptors. (tx_free_thresh=%u port=%d "
1573 "queue=%d)\n", (unsigned int)tx_free_thresh,
1574 (int)dev->data->port_id, (int)queue_idx);
1579 * Free memory prior to re-allocation if needed. This is the case after
1580 * calling nfp_net_stop
1582 if (dev->data->tx_queues[queue_idx]) {
1583 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1585 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1586 dev->data->tx_queues[queue_idx] = NULL;
1589 /* Allocating tx queue data structure */
1590 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1591 RTE_CACHE_LINE_SIZE, socket_id);
1593 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1598 * Allocate TX ring hardware descriptors. A memzone large enough to
1599 * handle the maximum ring size is allocated in order to allow for
1600 * resizing in later calls to the queue setup function.
1602 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1603 sizeof(struct nfp_net_tx_desc) *
1604 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1607 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1608 nfp_net_tx_queue_release(txq);
1612 txq->tx_count = nb_desc;
1613 txq->tx_free_thresh = tx_free_thresh;
1614 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1615 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1616 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1618 /* queue mapping based on firmware configuration */
1619 txq->qidx = queue_idx;
1620 txq->tx_qcidx = queue_idx * hw->stride_tx;
1621 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1623 txq->port_id = dev->data->port_id;
1624 txq->txq_flags = tx_conf->txq_flags;
1626 /* Saving physical and virtual addresses for the TX ring */
1627 txq->dma = (uint64_t)tz->phys_addr;
1628 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1630 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1631 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1632 sizeof(*txq->txbufs) * nb_desc,
1633 RTE_CACHE_LINE_SIZE, socket_id);
1634 if (txq->txbufs == NULL) {
1635 nfp_net_tx_queue_release(txq);
1638 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1639 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1641 nfp_net_reset_tx_queue(txq);
1643 dev->data->tx_queues[queue_idx] = txq;
1647 * Telling the HW about the physical address of the TX ring and number
1648 * of descriptors in log2 format
1650 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1651 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1656 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1658 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1659 struct rte_mbuf *mb)
1662 struct nfp_net_hw *hw = txq->hw;
1664 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1667 ol_flags = mb->ol_flags;
1669 if (!(ol_flags & PKT_TX_TCP_SEG))
1672 txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1673 txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1674 txd->flags = PCIE_DESC_TX_LSO;
1683 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1685 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1686 struct rte_mbuf *mb)
1689 struct nfp_net_hw *hw = txq->hw;
1691 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1694 ol_flags = mb->ol_flags;
1696 /* IPv6 does not need checksum */
1697 if (ol_flags & PKT_TX_IP_CKSUM)
1698 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1700 switch (ol_flags & PKT_TX_L4_MASK) {
1701 case PKT_TX_UDP_CKSUM:
1702 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1704 case PKT_TX_TCP_CKSUM:
1705 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1709 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1710 txd->flags |= PCIE_DESC_TX_CSUM;
1713 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1715 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1716 struct rte_mbuf *mb)
1718 struct nfp_net_hw *hw = rxq->hw;
1720 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1723 /* If IPv4 and IP checksum error, fail */
1724 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1725 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1726 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1728 /* If neither UDP nor TCP return */
1729 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1730 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1733 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1734 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1735 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1737 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1738 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1739 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1742 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1743 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1745 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1748 * nfp_net_set_hash - Set mbuf hash data
1750 * The RSS hash and hash-type are pre-pended to the packet data.
1751 * Extract and decode it and set the mbuf fields.
1754 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1755 struct rte_mbuf *mbuf)
1757 struct nfp_net_hw *hw = rxq->hw;
1758 uint8_t *meta_offset;
1761 uint32_t hash_type = 0;
1763 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1766 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1767 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1770 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1771 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1773 } else if (NFP_DESC_META_LEN(rxd)) {
1776 * <---- 32 bit ----->
1781 * ====================
1784 * Field type word contains up to 8 4bit field types
1785 * A 4bit field type refers to a data field word
1786 * A data field word can have several 4bit field types
1788 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1789 meta_offset -= NFP_DESC_META_LEN(rxd);
1790 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1792 /* NFP PMD just supports metadata for hashing */
1793 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1794 case NFP_NET_META_HASH:
1795 /* next field type is about the hash type */
1796 meta_info >>= NFP_NET_META_FIELD_SIZE;
1797 /* hash value is in the data field */
1798 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1799 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1802 /* Unsupported metadata can be a performance issue */
1809 mbuf->hash.rss = hash;
1810 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1812 switch (hash_type) {
1813 case NFP_NET_RSS_IPV4:
1814 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1816 case NFP_NET_RSS_IPV6:
1817 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1819 case NFP_NET_RSS_IPV6_EX:
1820 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1823 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1828 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1830 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1833 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1838 * There are some decissions to take:
1839 * 1) How to check DD RX descriptors bit
1840 * 2) How and when to allocate new mbufs
1842 * Current implementation checks just one single DD bit each loop. As each
1843 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1844 * a single cache line instead. Tests with this change have not shown any
1845 * performance improvement but it requires further investigation. For example,
1846 * depending on which descriptor is next, the number of descriptors could be
1847 * less than 8 for just checking those in the same cache line. This implies
1848 * extra work which could be counterproductive by itself. Indeed, last firmware
1849 * changes are just doing this: writing several descriptors with the DD bit
1850 * for saving PCIe bandwidth and DMA operations from the NFP.
1852 * Mbuf allocation is done when a new packet is received. Then the descriptor
1853 * is automatically linked with the new mbuf and the old one is given to the
1854 * user. The main drawback with this design is mbuf allocation is heavier than
1855 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1856 * cache point of view it does not seem allocating the mbuf early on as we are
1857 * doing now have any benefit at all. Again, tests with this change have not
1858 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1859 * so looking at the implications of this type of allocation should be studied
1864 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1866 struct nfp_net_rxq *rxq;
1867 struct nfp_net_rx_desc *rxds;
1868 struct nfp_net_rx_buff *rxb;
1869 struct nfp_net_hw *hw;
1870 struct rte_mbuf *mb;
1871 struct rte_mbuf *new_mb;
1877 if (unlikely(rxq == NULL)) {
1879 * DPDK just checks the queue is lower than max queues
1880 * enabled. But the queue needs to be configured
1882 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1890 while (avail < nb_pkts) {
1891 rxb = &rxq->rxbufs[rxq->rd_p];
1892 if (unlikely(rxb == NULL)) {
1893 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1898 * Memory barrier to ensure that we won't do other
1899 * reads before the DD bit.
1903 rxds = &rxq->rxds[rxq->rd_p];
1904 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1908 * We got a packet. Let's alloc a new mbuff for refilling the
1909 * free descriptor ring as soon as possible
1911 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1912 if (unlikely(new_mb == NULL)) {
1913 RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1914 "queue_id=%u\n", (unsigned)rxq->port_id,
1915 (unsigned)rxq->qidx);
1916 nfp_net_mbuf_alloc_failed(rxq);
1923 * Grab the mbuff and refill the descriptor with the
1924 * previously allocated mbuff
1929 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1930 rxds->rxd.data_len, rxq->mbuf_size);
1932 /* Size of this segment */
1933 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1934 /* Size of the whole packet. We just support 1 segment */
1935 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1937 if (unlikely((mb->data_len + hw->rx_offset) >
1940 * This should not happen and the user has the
1941 * responsibility of avoiding it. But we have
1942 * to give some info about the error
1944 RTE_LOG_DP(ERR, PMD,
1945 "mbuf overflow likely due to the RX offset.\n"
1946 "\t\tYour mbuf size should have extra space for"
1947 " RX offset=%u bytes.\n"
1948 "\t\tCurrently you just have %u bytes available"
1949 " but the received packet is %u bytes long",
1951 rxq->mbuf_size - hw->rx_offset,
1956 /* Filling the received mbuff with packet info */
1958 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1960 mb->data_off = RTE_PKTMBUF_HEADROOM +
1961 NFP_DESC_META_LEN(rxds);
1963 /* No scatter mode supported */
1967 /* Checking the RSS flag */
1968 nfp_net_set_hash(rxq, rxds, mb);
1970 /* Checking the checksum flag */
1971 nfp_net_rx_cksum(rxq, rxds, mb);
1973 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1974 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1975 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1976 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1979 /* Adding the mbuff to the mbuff array passed by the app */
1980 rx_pkts[avail++] = mb;
1982 /* Now resetting and updating the descriptor */
1985 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1987 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1988 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1991 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
1998 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1999 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
2001 nb_hold += rxq->nb_rx_hold;
2004 * FL descriptors needs to be written before incrementing the
2005 * FL queue WR pointer
2008 if (nb_hold > rxq->rx_free_thresh) {
2009 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2010 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
2011 (unsigned)nb_hold, (unsigned)avail);
2012 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2015 rxq->nb_rx_hold = nb_hold;
2021 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2023 * @txq: TX queue to work with
2024 * Returns number of descriptors freed
2027 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2032 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2033 " status\n", txq->qidx);
2035 /* Work out how many packets have been sent */
2036 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2038 if (qcp_rd_p == txq->rd_p) {
2039 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2040 "packets (%u, %u)\n", txq->qidx,
2041 qcp_rd_p, txq->rd_p);
2045 if (qcp_rd_p > txq->rd_p)
2046 todo = qcp_rd_p - txq->rd_p;
2048 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2050 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2051 qcp_rd_p, txq->rd_p, txq->rd_p);
2057 if (unlikely(txq->rd_p >= txq->tx_count))
2058 txq->rd_p -= txq->tx_count;
2063 /* Leaving always free descriptors for avoiding wrapping confusion */
2065 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2067 if (txq->wr_p >= txq->rd_p)
2068 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2070 return txq->rd_p - txq->wr_p - 8;
2074 * nfp_net_txq_full - Check if the TX queue free descriptors
2075 * is below tx_free_threshold
2077 * @txq: TX queue to check
2079 * This function uses the host copy* of read/write pointers
2082 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2084 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2088 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2090 struct nfp_net_txq *txq;
2091 struct nfp_net_hw *hw;
2092 struct nfp_net_tx_desc *txds, txd;
2093 struct rte_mbuf *pkt;
2095 int pkt_size, dma_size;
2096 uint16_t free_descs, issued_descs;
2097 struct rte_mbuf **lmbuf;
2102 txds = &txq->txds[txq->wr_p];
2104 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2105 txq->qidx, txq->wr_p, nb_pkts);
2107 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2108 nfp_net_tx_free_bufs(txq);
2110 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2111 if (unlikely(free_descs == 0))
2118 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2119 txq->qidx, nb_pkts);
2120 /* Sending packets */
2121 while ((i < nb_pkts) && free_descs) {
2122 /* Grabbing the mbuf linked to the current descriptor */
2123 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2124 /* Warming the cache for releasing the mbuf later on */
2125 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2127 pkt = *(tx_pkts + i);
2129 if (unlikely((pkt->nb_segs > 1) &&
2130 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2131 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2132 rte_panic("Multisegment packet unsupported\n");
2135 /* Checking if we have enough descriptors */
2136 if (unlikely(pkt->nb_segs > free_descs))
2140 * Checksum and VLAN flags just in the first descriptor for a
2141 * multisegment packet, but TSO info needs to be in all of them.
2143 txd.data_len = pkt->pkt_len;
2144 nfp_net_tx_tso(txq, &txd, pkt);
2145 nfp_net_tx_cksum(txq, &txd, pkt);
2147 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2148 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2149 txd.flags |= PCIE_DESC_TX_VLAN;
2150 txd.vlan = pkt->vlan_tci;
2154 * mbuf data_len is the data in one segment and pkt_len data
2155 * in the whole packet. When the packet is just one segment,
2156 * then data_len = pkt_len
2158 pkt_size = pkt->pkt_len;
2161 /* Copying TSO, VLAN and cksum info */
2164 /* Releasing mbuf used by this descriptor previously*/
2166 rte_pktmbuf_free_seg(*lmbuf);
2169 * Linking mbuf with descriptor for being released
2170 * next time descriptor is used
2174 dma_size = pkt->data_len;
2175 dma_addr = rte_mbuf_data_dma_addr(pkt);
2176 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2177 "%" PRIx64 "\n", dma_addr);
2179 /* Filling descriptors fields */
2180 txds->dma_len = dma_size;
2181 txds->data_len = txd.data_len;
2182 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2183 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2184 ASSERT(free_descs > 0);
2188 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2191 pkt_size -= dma_size;
2194 txds->offset_eop |= PCIE_DESC_TX_EOP;
2196 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2199 /* Referencing next free TX descriptor */
2200 txds = &txq->txds[txq->wr_p];
2201 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2208 /* Increment write pointers. Force memory write before we let HW know */
2210 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2216 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2218 uint32_t new_ctrl, update;
2219 struct nfp_net_hw *hw;
2221 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2224 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2225 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2226 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2227 " ETH_VLAN_EXTEND_OFFLOAD");
2229 /* Enable vlan strip if it is not configured yet */
2230 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2231 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2232 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2234 /* Disable vlan strip just if it is configured */
2235 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2236 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2237 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2242 update = NFP_NET_CFG_UPDATE_GEN;
2244 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2247 hw->ctrl = new_ctrl;
2250 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2252 nfp_net_reta_update(struct rte_eth_dev *dev,
2253 struct rte_eth_rss_reta_entry64 *reta_conf,
2256 uint32_t reta, mask;
2260 struct nfp_net_hw *hw =
2261 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2263 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2266 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2267 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2268 "(%d) doesn't match the number hardware can supported "
2269 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2274 * Update Redirection Table. There are 128 8bit-entries which can be
2275 * manage as 32 32bit-entries
2277 for (i = 0; i < reta_size; i += 4) {
2278 /* Handling 4 RSS entries per loop */
2279 idx = i / RTE_RETA_GROUP_SIZE;
2280 shift = i % RTE_RETA_GROUP_SIZE;
2281 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2287 /* If all 4 entries were set, don't need read RETA register */
2289 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2291 for (j = 0; j < 4; j++) {
2292 if (!(mask & (0x1 << j)))
2295 /* Clearing the entry bits */
2296 reta &= ~(0xFF << (8 * j));
2297 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2299 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2303 update = NFP_NET_CFG_UPDATE_RSS;
2305 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2311 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2313 nfp_net_reta_query(struct rte_eth_dev *dev,
2314 struct rte_eth_rss_reta_entry64 *reta_conf,
2320 struct nfp_net_hw *hw;
2322 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2324 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2327 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2328 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2329 "(%d) doesn't match the number hardware can supported "
2330 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2335 * Reading Redirection Table. There are 128 8bit-entries which can be
2336 * manage as 32 32bit-entries
2338 for (i = 0; i < reta_size; i += 4) {
2339 /* Handling 4 RSS entries per loop */
2340 idx = i / RTE_RETA_GROUP_SIZE;
2341 shift = i % RTE_RETA_GROUP_SIZE;
2342 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2347 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2349 for (j = 0; j < 4; j++) {
2350 if (!(mask & (0x1 << j)))
2352 reta_conf->reta[shift + j] =
2353 (uint8_t)((reta >> (8 * j)) & 0xF);
2360 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2361 struct rte_eth_rss_conf *rss_conf)
2364 uint32_t cfg_rss_ctrl = 0;
2368 struct nfp_net_hw *hw;
2370 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372 rss_hf = rss_conf->rss_hf;
2374 /* Checking if RSS is enabled */
2375 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2376 if (rss_hf != 0) { /* Enable RSS? */
2377 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2380 return 0; /* Nothing to do */
2383 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2384 RTE_LOG(ERR, PMD, "hash key too long\n");
2388 if (rss_hf & ETH_RSS_IPV4)
2389 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2390 NFP_NET_CFG_RSS_IPV4_TCP |
2391 NFP_NET_CFG_RSS_IPV4_UDP;
2393 if (rss_hf & ETH_RSS_IPV6)
2394 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2395 NFP_NET_CFG_RSS_IPV6_TCP |
2396 NFP_NET_CFG_RSS_IPV6_UDP;
2398 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2399 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2401 /* configuring where to apply the RSS hash */
2402 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2404 /* Writing the key byte a byte */
2405 for (i = 0; i < rss_conf->rss_key_len; i++) {
2406 memcpy(&key, &rss_conf->rss_key[i], 1);
2407 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2410 /* Writing the key size */
2411 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2413 update = NFP_NET_CFG_UPDATE_RSS;
2415 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2422 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2423 struct rte_eth_rss_conf *rss_conf)
2426 uint32_t cfg_rss_ctrl;
2429 struct nfp_net_hw *hw;
2431 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2433 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2436 rss_hf = rss_conf->rss_hf;
2437 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2439 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2440 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2442 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2443 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2445 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2446 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2448 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2449 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2451 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2452 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2454 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2455 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2457 /* Reading the key size */
2458 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2460 /* Reading the key byte a byte */
2461 for (i = 0; i < rss_conf->rss_key_len; i++) {
2462 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2463 memcpy(&rss_conf->rss_key[i], &key, 1);
2469 /* Initialise and register driver with DPDK Application */
2470 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2471 .dev_configure = nfp_net_configure,
2472 .dev_start = nfp_net_start,
2473 .dev_stop = nfp_net_stop,
2474 .dev_close = nfp_net_close,
2475 .promiscuous_enable = nfp_net_promisc_enable,
2476 .promiscuous_disable = nfp_net_promisc_disable,
2477 .link_update = nfp_net_link_update,
2478 .stats_get = nfp_net_stats_get,
2479 .stats_reset = nfp_net_stats_reset,
2480 .dev_infos_get = nfp_net_infos_get,
2481 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2482 .mtu_set = nfp_net_dev_mtu_set,
2483 .vlan_offload_set = nfp_net_vlan_offload_set,
2484 .reta_update = nfp_net_reta_update,
2485 .reta_query = nfp_net_reta_query,
2486 .rss_hash_update = nfp_net_rss_hash_update,
2487 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2488 .rx_queue_setup = nfp_net_rx_queue_setup,
2489 .rx_queue_release = nfp_net_rx_queue_release,
2490 .rx_queue_count = nfp_net_rx_queue_count,
2491 .tx_queue_setup = nfp_net_tx_queue_setup,
2492 .tx_queue_release = nfp_net_tx_queue_release,
2493 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2494 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2498 * All eth_dev created got its private data, but before nfp_net_init, that
2499 * private data is referencing private data for all the PF ports. This is due
2500 * to how the vNIC bars are mapped based on first port, so all ports need info
2501 * about port 0 private data. Inside nfp_net_init the private data pointer is
2502 * changed to the right address for each port once the bars have been mapped.
2504 * This functions helps to find out which port and therefore which offset
2505 * inside the private data array to use.
2508 get_pf_port_number(char *name)
2510 char *pf_str = name;
2513 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2518 * This should not happen at all and it would mean major
2519 * implementation fault.
2521 rte_panic("nfp_net: problem with pf device name\n");
2523 /* Expecting _portX with X within [0,7] */
2526 return (int)strtol(pf_str, NULL, 10);
2530 nfp_net_init(struct rte_eth_dev *eth_dev)
2532 struct rte_pci_device *pci_dev;
2533 struct nfp_net_hw *hw, *hwport0;
2535 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2539 nspu_desc_t *nspu_desc = NULL;
2540 uint64_t bar_offset;
2543 PMD_INIT_FUNC_TRACE();
2545 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2547 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2548 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2549 port = get_pf_port_number(eth_dev->data->name);
2550 if (port < 0 || port > 7) {
2551 RTE_LOG(ERR, PMD, "Port value is wrong\n");
2555 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2557 /* This points to port 0 private data */
2558 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2560 /* This points to the specific port private data */
2561 hw = &hwport0[port];
2562 hw->pf_port_idx = port;
2564 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2568 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2569 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2570 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2572 /* For secondary processes, the primary has done all the work */
2573 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2576 rte_eth_copy_pci_info(eth_dev, pci_dev);
2577 /* hotplug is not possible with multiport PF */
2578 if (!hw->pf_multiport_enabled)
2579 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2581 hw->device_id = pci_dev->id.device_id;
2582 hw->vendor_id = pci_dev->id.vendor_id;
2583 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2584 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2586 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2587 pci_dev->id.vendor_id, pci_dev->id.device_id,
2588 pci_dev->addr.domain, pci_dev->addr.bus,
2589 pci_dev->addr.devid, pci_dev->addr.function);
2591 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2592 if (hw->ctrl_bar == NULL) {
2594 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2598 if (hw->is_pf && port == 0) {
2599 nspu_desc = hw->nspu_desc;
2601 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2603 * A firmware should be there after PF probe so this
2604 * should not happen.
2606 RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2610 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2611 hw->ctrl_bar += bar_offset;
2612 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2616 if (!hwport0->ctrl_bar)
2619 /* address based on port0 offset */
2620 hw->ctrl_bar = hwport0->ctrl_bar +
2621 (port * NFP_PF_CSR_SLICE_SIZE);
2624 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2626 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2627 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2629 /* Work out where in the BAR the queues start. */
2630 switch (pci_dev->id.device_id) {
2631 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2632 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2633 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2634 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2635 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2636 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2637 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2640 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2644 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2645 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2647 if (hw->is_pf && port == 0) {
2648 /* configure access to tx/rx vNIC BARs */
2649 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2650 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2652 hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2654 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2655 hwport0->hw_queues += bar_offset;
2659 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2660 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2661 eth_dev->data->dev_private = hw;
2663 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2665 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2669 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2670 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2672 nfp_net_cfg_queue_setup(hw);
2674 /* Get some of the read-only fields from the config BAR */
2675 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2676 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2677 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2678 hw->mtu = hw->max_mtu;
2680 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2681 hw->rx_offset = NFP_NET_RX_OFFSET;
2683 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2685 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2686 hw->ver, hw->max_mtu);
2687 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2688 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2689 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2690 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2691 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2692 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2693 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2694 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2695 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2696 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2700 hw->stride_rx = stride;
2701 hw->stride_tx = stride;
2703 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2704 hw->max_rx_queues, hw->max_tx_queues);
2706 /* Initializing spinlock for reconfigs */
2707 rte_spinlock_init(&hw->reconfig_lock);
2709 /* Allocating memory for mac addr */
2710 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2711 if (eth_dev->data->mac_addrs == NULL) {
2712 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2716 nfp_net_read_mac(hw);
2718 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2719 /* Using random mac addresses for VFs */
2720 eth_random_addr(&hw->mac_addr[0]);
2721 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2724 /* Copying mac address to DPDK eth_dev struct */
2725 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2726 ð_dev->data->mac_addrs[0]);
2728 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2729 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2730 eth_dev->data->port_id, pci_dev->id.vendor_id,
2731 pci_dev->id.device_id,
2732 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2733 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2735 /* Registering LSC interrupt handler */
2736 rte_intr_callback_register(&pci_dev->intr_handle,
2737 nfp_net_dev_interrupt_handler,
2740 /* Telling the firmware about the LSC interrupt entry */
2741 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2743 /* Recording current stats counters values */
2744 nfp_net_stats_reset(eth_dev);
2750 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2751 nfpu_desc_t *nfpu_desc, void **priv)
2753 struct rte_eth_dev *eth_dev;
2754 struct nfp_net_hw *hw;
2758 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2763 sprintf(port_name, "%s_port%d", dev->device.name, port);
2765 sprintf(port_name, "%s", dev->device.name);
2767 eth_dev = rte_eth_dev_allocate(port_name);
2772 *priv = rte_zmalloc(port_name,
2773 sizeof(struct nfp_net_adapter) * ports,
2774 RTE_CACHE_LINE_SIZE);
2776 rte_eth_dev_release_port(eth_dev);
2781 eth_dev->data->dev_private = *priv;
2784 * dev_private pointing to port0 dev_private because we need
2785 * to configure vNIC bars based on port0 at nfp_net_init.
2786 * Then dev_private is adjusted per port.
2788 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2789 hw->nspu_desc = nfpu_desc->nspu;
2790 hw->nfpu_desc = nfpu_desc;
2793 hw->pf_multiport_enabled = 1;
2795 eth_dev->device = &dev->device;
2796 rte_eth_copy_pci_info(eth_dev, dev);
2798 ret = nfp_net_init(eth_dev);
2801 rte_eth_dev_release_port(eth_dev);
2803 rte_free(port_name);
2808 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2809 struct rte_pci_device *dev)
2811 nfpu_desc_t *nfpu_desc;
2812 nspu_desc_t *nspu_desc;
2813 uint64_t offset_symbol;
2814 uint8_t *bar_offset;
2824 nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2828 if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2830 "nfpu_open failed\n");
2834 nspu_desc = nfpu_desc->nspu;
2837 /* Check NSP ABI version */
2838 if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2839 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2842 PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2844 if ((major == 0) && (minor < 20)) {
2845 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2849 ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
2854 bar_offset = (uint8_t *)dev->mem_resource[0].addr;
2855 bar_offset += offset_symbol;
2856 total_ports = (uint32_t)*bar_offset;
2857 PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
2859 if (total_ports <= 0 || total_ports > 8) {
2860 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
2865 for (i = 0; i < total_ports; i++) {
2866 ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
2874 nfpu_close(nfpu_desc);
2876 rte_free(nfpu_desc);
2881 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
2883 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2884 PCI_DEVICE_ID_NFP4000_PF_NIC)
2887 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2888 PCI_DEVICE_ID_NFP6000_PF_NIC)
2895 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
2897 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2898 PCI_DEVICE_ID_NFP6000_VF_NIC)
2905 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2906 struct rte_pci_device *pci_dev)
2908 return rte_eth_dev_pci_generic_probe(pci_dev,
2909 sizeof(struct nfp_net_adapter), nfp_net_init);
2912 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
2914 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2917 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
2918 .id_table = pci_id_nfp_pf_net_map,
2919 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2920 .probe = nfp_pf_pci_probe,
2921 .remove = eth_nfp_pci_remove,
2924 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
2925 .id_table = pci_id_nfp_vf_net_map,
2926 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2927 .probe = eth_nfp_pci_probe,
2928 .remove = eth_nfp_pci_remove,
2931 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
2932 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
2933 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
2934 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
2935 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
2936 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
2940 * c-file-style: "Linux"
2941 * indent-tabs-mode: t