drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014, 2015 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfp_nfpu.h"
  59 #include "nfp_net_pmd.h"
  60 #include "nfp_net_logs.h"
  61 #include "nfp_net_ctrl.h"
  62
  63 /* Prototypes */
  64 static void nfp_net_close(struct rte_eth_dev *dev);
  65 static int nfp_net_configure(struct rte_eth_dev *dev);
  66 static void nfp_net_dev_interrupt_handler(void *param);
  67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  70                               struct rte_eth_dev_info *dev_info);
  71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  77                                        uint16_t queue_idx);
  78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  79                                   uint16_t nb_pkts);
  80 static void nfp_net_rx_queue_release(void *rxq);
  81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  82                                   uint16_t nb_desc, unsigned int socket_id,
  83                                   const struct rte_eth_rxconf *rx_conf,
  84                                   struct rte_mempool *mp);
  85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  86 static void nfp_net_tx_queue_release(void *txq);
  87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_txconf *tx_conf);
  90 static int nfp_net_start(struct rte_eth_dev *dev);
  91 static void nfp_net_stats_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_stats *stats);
  93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
  94 static void nfp_net_stop(struct rte_eth_dev *dev);
  95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  96                                   uint16_t nb_pkts);
  97
  98 /*
  99  * The offset of the queue controller queues in the PCIe Target. These
 100  * happen to be at the same offset on the NFP6000 and the NFP3200 so
 101  * we use a single macro here.
 102  */
 103 #define NFP_PCIE_QUEUE(_q)      (0x800 * ((_q) & 0xff))
 104
 105 /* Maximum value which can be added to a queue with one transaction */
 106 #define NFP_QCP_MAX_ADD 0x7f
 107
 108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 109         (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
 110
 111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 112 enum nfp_qcp_ptr {
 113         NFP_QCP_READ_PTR = 0,
 114         NFP_QCP_WRITE_PTR
 115 };
 116
 117 /*
 118  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 119  * @q: Base address for queue structure
 120  * @ptr: Add to the Read or Write pointer
 121  * @val: Value to add to the queue pointer
 122  *
 123  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 124  */
 125 static inline void
 126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 127 {
 128         uint32_t off;
 129
 130         if (ptr == NFP_QCP_READ_PTR)
 131                 off = NFP_QCP_QUEUE_ADD_RPTR;
 132         else
 133                 off = NFP_QCP_QUEUE_ADD_WPTR;
 134
 135         while (val > NFP_QCP_MAX_ADD) {
 136                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 137                 val -= NFP_QCP_MAX_ADD;
 138         }
 139
 140         nn_writel(rte_cpu_to_le_32(val), q + off);
 141 }
 142
 143 /*
 144  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 145  * @q:  Base address for queue structure
 146  * @ptr: Read or Write pointer
 147  */
 148 static inline uint32_t
 149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 150 {
 151         uint32_t off;
 152         uint32_t val;
 153
 154         if (ptr == NFP_QCP_READ_PTR)
 155                 off = NFP_QCP_QUEUE_STS_LO;
 156         else
 157                 off = NFP_QCP_QUEUE_STS_HI;
 158
 159         val = rte_cpu_to_le_32(nn_readl(q + off));
 160
 161         if (ptr == NFP_QCP_READ_PTR)
 162                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 163         else
 164                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 165 }
 166
 167 /*
 168  * Functions to read/write from/to Config BAR
 169  * Performs any endian conversion necessary.
 170  */
 171 static inline uint8_t
 172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 173 {
 174         return nn_readb(hw->ctrl_bar + off);
 175 }
 176
 177 static inline void
 178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 179 {
 180         nn_writeb(val, hw->ctrl_bar + off);
 181 }
 182
 183 static inline uint32_t
 184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 185 {
 186         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 187 }
 188
 189 static inline void
 190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 191 {
 192         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 193 }
 194
 195 static inline uint64_t
 196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 197 {
 198         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 199 }
 200
 201 static inline void
 202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 203 {
 204         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 205 }
 206
 207 /*
 208  * Atomically reads link status information from global structure rte_eth_dev.
 209  *
 210  * @param dev
 211  *   - Pointer to the structure rte_eth_dev to read from.
 212  *   - Pointer to the buffer to be saved with the link status.
 213  *
 214  * @return
 215  *   - On success, zero.
 216  *   - On failure, negative value.
 217  */
 218 static inline int
 219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 220                                     struct rte_eth_link *link)
 221 {
 222         struct rte_eth_link *dst = link;
 223         struct rte_eth_link *src = &dev->data->dev_link;
 224
 225         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 226                                 *(uint64_t *)src) == 0)
 227                 return -1;
 228
 229         return 0;
 230 }
 231
 232 /*
 233  * Atomically writes the link status information into global
 234  * structure rte_eth_dev.
 235  *
 236  * @param dev
 237  *   - Pointer to the structure rte_eth_dev to read from.
 238  *   - Pointer to the buffer to be saved with the link status.
 239  *
 240  * @return
 241  *   - On success, zero.
 242  *   - On failure, negative value.
 243  */
 244 static inline int
 245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 246                                      struct rte_eth_link *link)
 247 {
 248         struct rte_eth_link *dst = &dev->data->dev_link;
 249         struct rte_eth_link *src = link;
 250
 251         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 252                                 *(uint64_t *)src) == 0)
 253                 return -1;
 254
 255         return 0;
 256 }
 257
 258 static void
 259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 260 {
 261         unsigned i;
 262
 263         if (rxq->rxbufs == NULL)
 264                 return;
 265
 266         for (i = 0; i < rxq->rx_count; i++) {
 267                 if (rxq->rxbufs[i].mbuf) {
 268                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 269                         rxq->rxbufs[i].mbuf = NULL;
 270                 }
 271         }
 272 }
 273
 274 static void
 275 nfp_net_rx_queue_release(void *rx_queue)
 276 {
 277         struct nfp_net_rxq *rxq = rx_queue;
 278
 279         if (rxq) {
 280                 nfp_net_rx_queue_release_mbufs(rxq);
 281                 rte_free(rxq->rxbufs);
 282                 rte_free(rxq);
 283         }
 284 }
 285
 286 static void
 287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 288 {
 289         nfp_net_rx_queue_release_mbufs(rxq);
 290         rxq->rd_p = 0;
 291         rxq->nb_rx_hold = 0;
 292 }
 293
 294 static void
 295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 296 {
 297         unsigned i;
 298
 299         if (txq->txbufs == NULL)
 300                 return;
 301
 302         for (i = 0; i < txq->tx_count; i++) {
 303                 if (txq->txbufs[i].mbuf) {
 304                         rte_pktmbuf_free(txq->txbufs[i].mbuf);
 305                         txq->txbufs[i].mbuf = NULL;
 306                 }
 307         }
 308 }
 309
 310 static void
 311 nfp_net_tx_queue_release(void *tx_queue)
 312 {
 313         struct nfp_net_txq *txq = tx_queue;
 314
 315         if (txq) {
 316                 nfp_net_tx_queue_release_mbufs(txq);
 317                 rte_free(txq->txbufs);
 318                 rte_free(txq);
 319         }
 320 }
 321
 322 static void
 323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 324 {
 325         nfp_net_tx_queue_release_mbufs(txq);
 326         txq->wr_p = 0;
 327         txq->rd_p = 0;
 328 }
 329
 330 static int
 331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 332 {
 333         int cnt;
 334         uint32_t new;
 335         struct timespec wait;
 336
 337         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
 338                     hw->qcp_cfg);
 339
 340         if (hw->qcp_cfg == NULL)
 341                 rte_panic("Bad configuration queue pointer\n");
 342
 343         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 344
 345         wait.tv_sec = 0;
 346         wait.tv_nsec = 1000000;
 347
 348         PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
 349
 350         /* Poll update field, waiting for NFP to ack the config */
 351         for (cnt = 0; ; cnt++) {
 352                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 353                 if (new == 0)
 354                         break;
 355                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 356                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 357                         return -1;
 358                 }
 359                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 360                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 361                                           " %dms", update, cnt);
 362                         rte_panic("Exiting\n");
 363                 }
 364                 nanosleep(&wait, 0); /* waiting for a 1ms */
 365         }
 366         PMD_DRV_LOG(DEBUG, "Ack DONE\n");
 367         return 0;
 368 }
 369
 370 /*
 371  * Reconfigure the NIC
 372  * @nn:    device to reconfigure
 373  * @ctrl:    The value for the ctrl field in the BAR config
 374  * @update:  The value for the update field in the BAR config
 375  *
 376  * Write the update word to the BAR and ping the reconfig queue. Then poll
 377  * until the firmware has acknowledged the update by zeroing the update word.
 378  */
 379 static int
 380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 381 {
 382         uint32_t err;
 383
 384         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
 385                     ctrl, update);
 386
 387         rte_spinlock_lock(&hw->reconfig_lock);
 388
 389         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 390         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 391
 392         rte_wmb();
 393
 394         err = __nfp_net_reconfig(hw, update);
 395
 396         rte_spinlock_unlock(&hw->reconfig_lock);
 397
 398         if (!err)
 399                 return 0;
 400
 401         /*
 402          * Reconfig errors imply situations where they can be handled.
 403          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 404          */
 405         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 406                      ctrl, update);
 407         return -EIO;
 408 }
 409
 410 /*
 411  * Configure an Ethernet device. This function must be invoked first
 412  * before any other function in the Ethernet API. This function can
 413  * also be re-invoked when a device is in the stopped state.
 414  */
 415 static int
 416 nfp_net_configure(struct rte_eth_dev *dev)
 417 {
 418         struct rte_eth_conf *dev_conf;
 419         struct rte_eth_rxmode *rxmode;
 420         struct rte_eth_txmode *txmode;
 421         uint32_t new_ctrl = 0;
 422         uint32_t update = 0;
 423         struct nfp_net_hw *hw;
 424
 425         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 426
 427         /*
 428          * A DPDK app sends info about how many queues to use and how
 429          * those queues need to be configured. This is used by the
 430          * DPDK core and it makes sure no more queues than those
 431          * advertised by the driver are requested. This function is
 432          * called after that internal process
 433          */
 434
 435         PMD_INIT_LOG(DEBUG, "Configure");
 436
 437         dev_conf = &dev->data->dev_conf;
 438         rxmode = &dev_conf->rxmode;
 439         txmode = &dev_conf->txmode;
 440
 441         /* Checking TX mode */
 442         if (txmode->mq_mode) {
 443                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 444                 return -EINVAL;
 445         }
 446
 447         /* Checking RX mode */
 448         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 449                 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
 450                         update = NFP_NET_CFG_UPDATE_RSS;
 451                         new_ctrl = NFP_NET_CFG_CTRL_RSS;
 452                 } else {
 453                         PMD_INIT_LOG(INFO, "RSS not supported");
 454                         return -EINVAL;
 455                 }
 456         }
 457
 458         if (rxmode->split_hdr_size) {
 459                 PMD_INIT_LOG(INFO, "rxmode does not support split header");
 460                 return -EINVAL;
 461         }
 462
 463         if (rxmode->hw_ip_checksum) {
 464                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
 465                         new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 466                 } else {
 467                         PMD_INIT_LOG(INFO, "RXCSUM not supported");
 468                         return -EINVAL;
 469                 }
 470         }
 471
 472         if (rxmode->hw_vlan_filter) {
 473                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
 474                 return -EINVAL;
 475         }
 476
 477         if (rxmode->hw_vlan_strip) {
 478                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
 479                         new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 480                 } else {
 481                         PMD_INIT_LOG(INFO, "hw vlan strip not supported");
 482                         return -EINVAL;
 483                 }
 484         }
 485
 486         if (rxmode->hw_vlan_extend) {
 487                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
 488                 return -EINVAL;
 489         }
 490
 491         /* Supporting VLAN insertion by default */
 492         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
 493                 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 494
 495         if (rxmode->jumbo_frame)
 496                 /* this is handled in rte_eth_dev_configure */
 497
 498         if (rxmode->hw_strip_crc) {
 499                 PMD_INIT_LOG(INFO, "strip CRC not supported");
 500                 return -EINVAL;
 501         }
 502
 503         if (rxmode->enable_scatter) {
 504                 PMD_INIT_LOG(INFO, "Scatter not supported");
 505                 return -EINVAL;
 506         }
 507
 508         if (!new_ctrl)
 509                 return 0;
 510
 511         update |= NFP_NET_CFG_UPDATE_GEN;
 512
 513         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 514         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 515                 return -EIO;
 516
 517         hw->ctrl = new_ctrl;
 518
 519         return 0;
 520 }
 521
 522 static void
 523 nfp_net_enable_queues(struct rte_eth_dev *dev)
 524 {
 525         struct nfp_net_hw *hw;
 526         uint64_t enabled_queues = 0;
 527         int i;
 528
 529         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 530
 531         /* Enabling the required TX queues in the device */
 532         for (i = 0; i < dev->data->nb_tx_queues; i++)
 533                 enabled_queues |= (1 << i);
 534
 535         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 536
 537         enabled_queues = 0;
 538
 539         /* Enabling the required RX queues in the device */
 540         for (i = 0; i < dev->data->nb_rx_queues; i++)
 541                 enabled_queues |= (1 << i);
 542
 543         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 544 }
 545
 546 static void
 547 nfp_net_disable_queues(struct rte_eth_dev *dev)
 548 {
 549         struct nfp_net_hw *hw;
 550         uint32_t new_ctrl, update = 0;
 551
 552         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 553
 554         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 555         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 556
 557         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 558         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 559                  NFP_NET_CFG_UPDATE_MSIX;
 560
 561         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 562                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 563
 564         /* If an error when reconfig we avoid to change hw state */
 565         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 566                 return;
 567
 568         hw->ctrl = new_ctrl;
 569 }
 570
 571 static int
 572 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 573 {
 574         int i;
 575
 576         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 577                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 578                         return -1;
 579         }
 580         return 0;
 581 }
 582
 583 static void
 584 nfp_net_params_setup(struct nfp_net_hw *hw)
 585 {
 586         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 587         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 588 }
 589
 590 static void
 591 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 592 {
 593         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 594 }
 595
 596 #define ETH_ADDR_LEN    6
 597
 598 static void
 599 nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src)
 600 {
 601         int i;
 602
 603         for (i = 0; i < ETH_ADDR_LEN; i++)
 604                 dst[ETH_ADDR_LEN - i - 1] = src[i];
 605 }
 606
 607 static int
 608 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 609 {
 610         union eth_table_entry *entry;
 611         int idx, i;
 612
 613         idx = port;
 614         entry = hw->eth_table;
 615
 616         /* Reading NFP ethernet table obtained before */
 617         for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
 618                 if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
 619                         /* port not in use */
 620                         entry++;
 621                         continue;
 622                 }
 623                 if (idx == 0)
 624                         break;
 625                 idx--;
 626                 entry++;
 627         }
 628
 629         if (i == NSP_ETH_MAX_COUNT)
 630                 return -EINVAL;
 631
 632         /*
 633          * hw points to port0 private data. We need hw now pointing to
 634          * right port.
 635          */
 636         hw += port;
 637         nfp_eth_copy_mac_reverse((uint8_t *)&hw->mac_addr,
 638                                  (uint8_t *)&entry->mac_addr);
 639
 640         return 0;
 641 }
 642
 643 static void
 644 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 645 {
 646         uint32_t tmp;
 647
 648         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 649         memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
 650
 651         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 652         memcpy(&hw->mac_addr[4], &tmp, 2);
 653 }
 654
 655 static void
 656 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 657 {
 658         uint32_t mac0 = *(uint32_t *)mac;
 659         uint16_t mac1;
 660
 661         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 662
 663         mac += 4;
 664         mac1 = *(uint16_t *)mac;
 665         nn_writew(rte_cpu_to_be_16(mac1),
 666                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 667 }
 668
 669 static int
 670 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 671                            struct rte_intr_handle *intr_handle)
 672 {
 673         struct nfp_net_hw *hw;
 674         int i;
 675
 676         if (!intr_handle->intr_vec) {
 677                 intr_handle->intr_vec =
 678                         rte_zmalloc("intr_vec",
 679                                     dev->data->nb_rx_queues * sizeof(int), 0);
 680                 if (!intr_handle->intr_vec) {
 681                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 682                                      " intr_vec", dev->data->nb_rx_queues);
 683                         return -ENOMEM;
 684                 }
 685         }
 686
 687         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 688
 689         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 690                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 691                 /* UIO just supports one queue and no LSC*/
 692                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 693                 intr_handle->intr_vec[0] = 0;
 694         } else {
 695                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 696                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 697                         /*
 698                          * The first msix vector is reserved for non
 699                          * efd interrupts
 700                         */
 701                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 702                         intr_handle->intr_vec[i] = i + 1;
 703                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
 704                                             intr_handle->intr_vec[i]);
 705                 }
 706         }
 707
 708         /* Avoiding TX interrupts */
 709         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 710         return 0;
 711 }
 712
 713 static int
 714 nfp_net_start(struct rte_eth_dev *dev)
 715 {
 716         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 717         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 718         uint32_t new_ctrl, update = 0;
 719         struct nfp_net_hw *hw;
 720         uint32_t intr_vector;
 721         int ret;
 722
 723         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 724
 725         PMD_INIT_LOG(DEBUG, "Start");
 726
 727         /* Disabling queues just in case... */
 728         nfp_net_disable_queues(dev);
 729
 730         /* Writing configuration parameters in the device */
 731         nfp_net_params_setup(hw);
 732
 733         /* Enabling the required queues in the device */
 734         nfp_net_enable_queues(dev);
 735
 736         /* check and configure queue intr-vector mapping */
 737         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 738                 if (hw->pf_multiport_enabled) {
 739                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 740                                           "with NFP multiport PF");
 741                                 return -EINVAL;
 742                 }
 743                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 744                         /*
 745                          * Better not to share LSC with RX interrupts.
 746                          * Unregistering LSC interrupt handler
 747                          */
 748                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 749                                 nfp_net_dev_interrupt_handler, (void *)dev);
 750
 751                         if (dev->data->nb_rx_queues > 1) {
 752                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 753                                              "supports 1 queue with UIO");
 754                                 return -EIO;
 755                         }
 756                 }
 757                 intr_vector = dev->data->nb_rx_queues;
 758                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 759                         return -1;
 760
 761                 nfp_configure_rx_interrupt(dev, intr_handle);
 762                 update = NFP_NET_CFG_UPDATE_MSIX;
 763         }
 764
 765         rte_intr_enable(intr_handle);
 766
 767         /* Enable device */
 768         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
 769
 770         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 771
 772         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 773                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 774
 775         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 776         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 777                 return -EIO;
 778
 779         /*
 780          * Allocating rte mbuffs for configured rx queues.
 781          * This requires queues being enabled before
 782          */
 783         if (nfp_net_rx_freelist_setup(dev) < 0) {
 784                 ret = -ENOMEM;
 785                 goto error;
 786         }
 787
 788         if (hw->is_pf)
 789                 /* Configure the physical port up */
 790                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1);
 791
 792         hw->ctrl = new_ctrl;
 793
 794         return 0;
 795
 796 error:
 797         /*
 798          * An error returned by this function should mean the app
 799          * exiting and then the system releasing all the memory
 800          * allocated even memory coming from hugepages.
 801          *
 802          * The device could be enabled at this point with some queues
 803          * ready for getting packets. This is true if the call to
 804          * nfp_net_rx_freelist_setup() succeeds for some queues but
 805          * fails for subsequent queues.
 806          *
 807          * This should make the app exiting but better if we tell the
 808          * device first.
 809          */
 810         nfp_net_disable_queues(dev);
 811
 812         return ret;
 813 }
 814
 815 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 816 static void
 817 nfp_net_stop(struct rte_eth_dev *dev)
 818 {
 819         int i;
 820         struct nfp_net_hw *hw;
 821
 822         PMD_INIT_LOG(DEBUG, "Stop");
 823
 824         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 825
 826         nfp_net_disable_queues(dev);
 827
 828         /* Clear queues */
 829         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 830                 nfp_net_reset_tx_queue(
 831                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 832         }
 833
 834         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 835                 nfp_net_reset_rx_queue(
 836                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 837         }
 838
 839         if (hw->is_pf)
 840                 /* Configure the physical port down */
 841                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0);
 842 }
 843
 844 /* Reset and stop device. The device can not be restarted. */
 845 static void
 846 nfp_net_close(struct rte_eth_dev *dev)
 847 {
 848         struct nfp_net_hw *hw;
 849         struct rte_pci_device *pci_dev;
 850         int i;
 851
 852         PMD_INIT_LOG(DEBUG, "Close");
 853
 854         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 855         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 856
 857         /*
 858          * We assume that the DPDK application is stopping all the
 859          * threads/queues before calling the device close function.
 860          */
 861
 862         nfp_net_disable_queues(dev);
 863
 864         /* Clear queues */
 865         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 866                 nfp_net_reset_tx_queue(
 867                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 868         }
 869
 870         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 871                 nfp_net_reset_rx_queue(
 872                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 873         }
 874
 875         rte_intr_disable(&pci_dev->intr_handle);
 876         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 877
 878         /* unregister callback func from eal lib */
 879         rte_intr_callback_unregister(&pci_dev->intr_handle,
 880                                      nfp_net_dev_interrupt_handler,
 881                                      (void *)dev);
 882
 883         /*
 884          * The ixgbe PMD driver disables the pcie master on the
 885          * device. The i40e does not...
 886          */
 887 }
 888
 889 static void
 890 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 891 {
 892         uint32_t new_ctrl, update = 0;
 893         struct nfp_net_hw *hw;
 894
 895         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
 896
 897         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 898
 899         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 900                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 901                 return;
 902         }
 903
 904         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 905                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
 906                 return;
 907         }
 908
 909         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 910         update = NFP_NET_CFG_UPDATE_GEN;
 911
 912         /*
 913          * DPDK sets promiscuous mode on just after this call assuming
 914          * it can not fail ...
 915          */
 916         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 917                 return;
 918
 919         hw->ctrl = new_ctrl;
 920 }
 921
 922 static void
 923 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 924 {
 925         uint32_t new_ctrl, update = 0;
 926         struct nfp_net_hw *hw;
 927
 928         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 929
 930         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 931                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
 932                 return;
 933         }
 934
 935         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 936         update = NFP_NET_CFG_UPDATE_GEN;
 937
 938         /*
 939          * DPDK sets promiscuous mode off just before this call
 940          * assuming it can not fail ...
 941          */
 942         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 943                 return;
 944
 945         hw->ctrl = new_ctrl;
 946 }
 947
 948 /*
 949  * return 0 means link status changed, -1 means not changed
 950  *
 951  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 952  * status.
 953  */
 954 static int
 955 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 956 {
 957         struct nfp_net_hw *hw;
 958         struct rte_eth_link link, old;
 959         uint32_t nn_link_status;
 960
 961         static const uint32_t ls_to_ethtool[] = {
 962                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 963                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 964                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 965                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 966                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 967                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 968                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 969                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 970         };
 971
 972         PMD_DRV_LOG(DEBUG, "Link update\n");
 973
 974         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 975
 976         memset(&old, 0, sizeof(old));
 977         nfp_net_dev_atomic_read_link_status(dev, &old);
 978
 979         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 980
 981         memset(&link, 0, sizeof(struct rte_eth_link));
 982
 983         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 984                 link.link_status = ETH_LINK_UP;
 985
 986         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 987
 988         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 989                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 990
 991         if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
 992             ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
 993             (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
 994                 /* We really do not know the speed wil old firmware */
 995                 link.link_speed = ETH_SPEED_NUM_NONE;
 996         else {
 997                 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 998                         link.link_speed = ETH_SPEED_NUM_NONE;
 999                 else
1000                         link.link_speed = ls_to_ethtool[nn_link_status];
1001         }
1002
1003         if (old.link_status != link.link_status) {
1004                 nfp_net_dev_atomic_write_link_status(dev, &link);
1005                 if (link.link_status)
1006                         PMD_DRV_LOG(INFO, "NIC Link is Up\n");
1007                 else
1008                         PMD_DRV_LOG(INFO, "NIC Link is Down\n");
1009                 return 0;
1010         }
1011
1012         return -1;
1013 }
1014
1015 static void
1016 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1017 {
1018         int i;
1019         struct nfp_net_hw *hw;
1020         struct rte_eth_stats nfp_dev_stats;
1021
1022         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1023
1024         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1025
1026         /* reading per RX ring stats */
1027         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1028                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1029                         break;
1030
1031                 nfp_dev_stats.q_ipackets[i] =
1032                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1033
1034                 nfp_dev_stats.q_ipackets[i] -=
1035                         hw->eth_stats_base.q_ipackets[i];
1036
1037                 nfp_dev_stats.q_ibytes[i] =
1038                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1039
1040                 nfp_dev_stats.q_ibytes[i] -=
1041                         hw->eth_stats_base.q_ibytes[i];
1042         }
1043
1044         /* reading per TX ring stats */
1045         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1046                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1047                         break;
1048
1049                 nfp_dev_stats.q_opackets[i] =
1050                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1051
1052                 nfp_dev_stats.q_opackets[i] -=
1053                         hw->eth_stats_base.q_opackets[i];
1054
1055                 nfp_dev_stats.q_obytes[i] =
1056                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1057
1058                 nfp_dev_stats.q_obytes[i] -=
1059                         hw->eth_stats_base.q_obytes[i];
1060         }
1061
1062         nfp_dev_stats.ipackets =
1063                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1064
1065         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1066
1067         nfp_dev_stats.ibytes =
1068                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1069
1070         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1071
1072         nfp_dev_stats.opackets =
1073                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1074
1075         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1076
1077         nfp_dev_stats.obytes =
1078                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1079
1080         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1081
1082         /* reading general device stats */
1083         nfp_dev_stats.ierrors =
1084                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1085
1086         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1087
1088         nfp_dev_stats.oerrors =
1089                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1090
1091         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1092
1093         /* RX ring mbuf allocation failures */
1094         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1095
1096         nfp_dev_stats.imissed =
1097                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1098
1099         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1100
1101         if (stats)
1102                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1103 }
1104
1105 static void
1106 nfp_net_stats_reset(struct rte_eth_dev *dev)
1107 {
1108         int i;
1109         struct nfp_net_hw *hw;
1110
1111         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112
1113         /*
1114          * hw->eth_stats_base records the per counter starting point.
1115          * Lets update it now
1116          */
1117
1118         /* reading per RX ring stats */
1119         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1120                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1121                         break;
1122
1123                 hw->eth_stats_base.q_ipackets[i] =
1124                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1125
1126                 hw->eth_stats_base.q_ibytes[i] =
1127                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1128         }
1129
1130         /* reading per TX ring stats */
1131         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1132                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1133                         break;
1134
1135                 hw->eth_stats_base.q_opackets[i] =
1136                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1137
1138                 hw->eth_stats_base.q_obytes[i] =
1139                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1140         }
1141
1142         hw->eth_stats_base.ipackets =
1143                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1144
1145         hw->eth_stats_base.ibytes =
1146                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1147
1148         hw->eth_stats_base.opackets =
1149                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1150
1151         hw->eth_stats_base.obytes =
1152                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1153
1154         /* reading general device stats */
1155         hw->eth_stats_base.ierrors =
1156                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1157
1158         hw->eth_stats_base.oerrors =
1159                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1160
1161         /* RX ring mbuf allocation failures */
1162         dev->data->rx_mbuf_alloc_failed = 0;
1163
1164         hw->eth_stats_base.imissed =
1165                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1166 }
1167
1168 static void
1169 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1170 {
1171         struct nfp_net_hw *hw;
1172
1173         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1174
1175         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1176         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1177         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1178         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1179         dev_info->max_rx_pktlen = hw->mtu;
1180         /* Next should change when PF support is implemented */
1181         dev_info->max_mac_addrs = 1;
1182
1183         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1184                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1185
1186         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1187                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1188                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1189                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1190
1191         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1192                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1193
1194         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1195                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1196                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1197                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1198
1199         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1200                 .rx_thresh = {
1201                         .pthresh = DEFAULT_RX_PTHRESH,
1202                         .hthresh = DEFAULT_RX_HTHRESH,
1203                         .wthresh = DEFAULT_RX_WTHRESH,
1204                 },
1205                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1206                 .rx_drop_en = 0,
1207         };
1208
1209         dev_info->default_txconf = (struct rte_eth_txconf) {
1210                 .tx_thresh = {
1211                         .pthresh = DEFAULT_TX_PTHRESH,
1212                         .hthresh = DEFAULT_TX_HTHRESH,
1213                         .wthresh = DEFAULT_TX_WTHRESH,
1214                 },
1215                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1216                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1217                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1218                              ETH_TXQ_FLAGS_NOOFFLOADS,
1219         };
1220
1221         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1222         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1223
1224         dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1225                                ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1226                                ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1227
1228         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1229                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1230 }
1231
1232 static const uint32_t *
1233 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1234 {
1235         static const uint32_t ptypes[] = {
1236                 /* refers to nfp_net_set_hash() */
1237                 RTE_PTYPE_INNER_L3_IPV4,
1238                 RTE_PTYPE_INNER_L3_IPV6,
1239                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1240                 RTE_PTYPE_INNER_L4_MASK,
1241                 RTE_PTYPE_UNKNOWN
1242         };
1243
1244         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1245                 return ptypes;
1246         return NULL;
1247 }
1248
1249 static uint32_t
1250 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1251 {
1252         struct nfp_net_rxq *rxq;
1253         struct nfp_net_rx_desc *rxds;
1254         uint32_t idx;
1255         uint32_t count;
1256
1257         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1258
1259         idx = rxq->rd_p;
1260
1261         count = 0;
1262
1263         /*
1264          * Other PMDs are just checking the DD bit in intervals of 4
1265          * descriptors and counting all four if the first has the DD
1266          * bit on. Of course, this is not accurate but can be good for
1267          * performance. But ideally that should be done in descriptors
1268          * chunks belonging to the same cache line
1269          */
1270
1271         while (count < rxq->rx_count) {
1272                 rxds = &rxq->rxds[idx];
1273                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1274                         break;
1275
1276                 count++;
1277                 idx++;
1278
1279                 /* Wrapping? */
1280                 if ((idx) == rxq->rx_count)
1281                         idx = 0;
1282         }
1283
1284         return count;
1285 }
1286
1287 static int
1288 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1289 {
1290         struct rte_pci_device *pci_dev;
1291         struct nfp_net_hw *hw;
1292         int base = 0;
1293
1294         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1295         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296
1297         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1298                 base = 1;
1299
1300         /* Make sure all updates are written before un-masking */
1301         rte_wmb();
1302         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1303                       NFP_NET_CFG_ICR_UNMASKED);
1304         return 0;
1305 }
1306
1307 static int
1308 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1309 {
1310         struct rte_pci_device *pci_dev;
1311         struct nfp_net_hw *hw;
1312         int base = 0;
1313
1314         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1316
1317         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1318                 base = 1;
1319
1320         /* Make sure all updates are written before un-masking */
1321         rte_wmb();
1322         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1323         return 0;
1324 }
1325
1326 static void
1327 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1328 {
1329         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1330         struct rte_eth_link link;
1331
1332         memset(&link, 0, sizeof(link));
1333         nfp_net_dev_atomic_read_link_status(dev, &link);
1334         if (link.link_status)
1335                 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1336                         (int)(dev->data->port_id), (unsigned)link.link_speed,
1337                         link.link_duplex == ETH_LINK_FULL_DUPLEX
1338                         ? "full-duplex" : "half-duplex");
1339         else
1340                 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1341                         (int)(dev->data->port_id));
1342
1343         RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1344                 pci_dev->addr.domain, pci_dev->addr.bus,
1345                 pci_dev->addr.devid, pci_dev->addr.function);
1346 }
1347
1348 /* Interrupt configuration and handling */
1349
1350 /*
1351  * nfp_net_irq_unmask - Unmask an interrupt
1352  *
1353  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1354  * clear the ICR for the entry.
1355  */
1356 static void
1357 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1358 {
1359         struct nfp_net_hw *hw;
1360         struct rte_pci_device *pci_dev;
1361
1362         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1363         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1364
1365         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1366                 /* If MSI-X auto-masking is used, clear the entry */
1367                 rte_wmb();
1368                 rte_intr_enable(&pci_dev->intr_handle);
1369         } else {
1370                 /* Make sure all updates are written before un-masking */
1371                 rte_wmb();
1372                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1373                               NFP_NET_CFG_ICR_UNMASKED);
1374         }
1375 }
1376
1377 static void
1378 nfp_net_dev_interrupt_handler(void *param)
1379 {
1380         int64_t timeout;
1381         struct rte_eth_link link;
1382         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1383
1384         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1385
1386         /* get the link status */
1387         memset(&link, 0, sizeof(link));
1388         nfp_net_dev_atomic_read_link_status(dev, &link);
1389
1390         nfp_net_link_update(dev, 0);
1391
1392         /* likely to up */
1393         if (!link.link_status) {
1394                 /* handle it 1 sec later, wait it being stable */
1395                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1396                 /* likely to down */
1397         } else {
1398                 /* handle it 4 sec later, wait it being stable */
1399                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1400         }
1401
1402         if (rte_eal_alarm_set(timeout * 1000,
1403                               nfp_net_dev_interrupt_delayed_handler,
1404                               (void *)dev) < 0) {
1405                 RTE_LOG(ERR, PMD, "Error setting alarm");
1406                 /* Unmasking */
1407                 nfp_net_irq_unmask(dev);
1408         }
1409 }
1410
1411 /*
1412  * Interrupt handler which shall be registered for alarm callback for delayed
1413  * handling specific interrupt to wait for the stable nic state. As the NIC
1414  * interrupt state is not stable for nfp after link is just down, it needs
1415  * to wait 4 seconds to get the stable status.
1416  *
1417  * @param handle   Pointer to interrupt handle.
1418  * @param param    The address of parameter (struct rte_eth_dev *)
1419  *
1420  * @return  void
1421  */
1422 static void
1423 nfp_net_dev_interrupt_delayed_handler(void *param)
1424 {
1425         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1426
1427         nfp_net_link_update(dev, 0);
1428         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1429
1430         nfp_net_dev_link_status_print(dev);
1431
1432         /* Unmasking */
1433         nfp_net_irq_unmask(dev);
1434 }
1435
1436 static int
1437 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1438 {
1439         struct nfp_net_hw *hw;
1440
1441         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1442
1443         /* check that mtu is within the allowed range */
1444         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1445                 return -EINVAL;
1446
1447         /* switch to jumbo mode if needed */
1448         if ((uint32_t)mtu > ETHER_MAX_LEN)
1449                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1450         else
1451                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1452
1453         /* update max frame size */
1454         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1455
1456         /* writing to configuration space */
1457         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1458
1459         hw->mtu = mtu;
1460
1461         return 0;
1462 }
1463
1464 static int
1465 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1466                        uint16_t queue_idx, uint16_t nb_desc,
1467                        unsigned int socket_id,
1468                        const struct rte_eth_rxconf *rx_conf,
1469                        struct rte_mempool *mp)
1470 {
1471         const struct rte_memzone *tz;
1472         struct nfp_net_rxq *rxq;
1473         struct nfp_net_hw *hw;
1474
1475         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1476
1477         PMD_INIT_FUNC_TRACE();
1478
1479         /* Validating number of descriptors */
1480         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1481             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1482             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1483                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1484                 return -EINVAL;
1485         }
1486
1487         /*
1488          * Free memory prior to re-allocation if needed. This is the case after
1489          * calling nfp_net_stop
1490          */
1491         if (dev->data->rx_queues[queue_idx]) {
1492                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1493                 dev->data->rx_queues[queue_idx] = NULL;
1494         }
1495
1496         /* Allocating rx queue data structure */
1497         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1498                                  RTE_CACHE_LINE_SIZE, socket_id);
1499         if (rxq == NULL)
1500                 return -ENOMEM;
1501
1502         /* Hw queues mapping based on firmware confifguration */
1503         rxq->qidx = queue_idx;
1504         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1505         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1506         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1507         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1508
1509         /*
1510          * Tracking mbuf size for detecting a potential mbuf overflow due to
1511          * RX offset
1512          */
1513         rxq->mem_pool = mp;
1514         rxq->mbuf_size = rxq->mem_pool->elt_size;
1515         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1516         hw->flbufsz = rxq->mbuf_size;
1517
1518         rxq->rx_count = nb_desc;
1519         rxq->port_id = dev->data->port_id;
1520         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1521         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1522                                   : ETHER_CRC_LEN);
1523         rxq->drop_en = rx_conf->rx_drop_en;
1524
1525         /*
1526          * Allocate RX ring hardware descriptors. A memzone large enough to
1527          * handle the maximum ring size is allocated in order to allow for
1528          * resizing in later calls to the queue setup function.
1529          */
1530         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1531                                    sizeof(struct nfp_net_rx_desc) *
1532                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1533                                    socket_id);
1534
1535         if (tz == NULL) {
1536                 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1537                 nfp_net_rx_queue_release(rxq);
1538                 return -ENOMEM;
1539         }
1540
1541         /* Saving physical and virtual addresses for the RX ring */
1542         rxq->dma = (uint64_t)tz->phys_addr;
1543         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1544
1545         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1546         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1547                                          sizeof(*rxq->rxbufs) * nb_desc,
1548                                          RTE_CACHE_LINE_SIZE, socket_id);
1549         if (rxq->rxbufs == NULL) {
1550                 nfp_net_rx_queue_release(rxq);
1551                 return -ENOMEM;
1552         }
1553
1554         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1555                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1556
1557         nfp_net_reset_rx_queue(rxq);
1558
1559         dev->data->rx_queues[queue_idx] = rxq;
1560         rxq->hw = hw;
1561
1562         /*
1563          * Telling the HW about the physical address of the RX ring and number
1564          * of descriptors in log2 format
1565          */
1566         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1567         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1568
1569         return 0;
1570 }
1571
1572 static int
1573 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1574 {
1575         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1576         uint64_t dma_addr;
1577         unsigned i;
1578
1579         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1580                    rxq->rx_count);
1581
1582         for (i = 0; i < rxq->rx_count; i++) {
1583                 struct nfp_net_rx_desc *rxd;
1584                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1585
1586                 if (mbuf == NULL) {
1587                         RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1588                                 (unsigned)rxq->qidx);
1589                         return -ENOMEM;
1590                 }
1591
1592                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1593
1594                 rxd = &rxq->rxds[i];
1595                 rxd->fld.dd = 0;
1596                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1597                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1598                 rxe[i].mbuf = mbuf;
1599                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1600         }
1601
1602         /* Make sure all writes are flushed before telling the hardware */
1603         rte_wmb();
1604
1605         /* Not advertising the whole ring as the firmware gets confused if so */
1606         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1607                    rxq->rx_count - 1);
1608
1609         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1610
1611         return 0;
1612 }
1613
1614 static int
1615 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1616                        uint16_t nb_desc, unsigned int socket_id,
1617                        const struct rte_eth_txconf *tx_conf)
1618 {
1619         const struct rte_memzone *tz;
1620         struct nfp_net_txq *txq;
1621         uint16_t tx_free_thresh;
1622         struct nfp_net_hw *hw;
1623
1624         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1625
1626         PMD_INIT_FUNC_TRACE();
1627
1628         /* Validating number of descriptors */
1629         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1630             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1631             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1632                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1633                 return -EINVAL;
1634         }
1635
1636         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1637                                     tx_conf->tx_free_thresh :
1638                                     DEFAULT_TX_FREE_THRESH);
1639
1640         if (tx_free_thresh > (nb_desc)) {
1641                 RTE_LOG(ERR, PMD,
1642                         "tx_free_thresh must be less than the number of TX "
1643                         "descriptors. (tx_free_thresh=%u port=%d "
1644                         "queue=%d)\n", (unsigned int)tx_free_thresh,
1645                         (int)dev->data->port_id, (int)queue_idx);
1646                 return -(EINVAL);
1647         }
1648
1649         /*
1650          * Free memory prior to re-allocation if needed. This is the case after
1651          * calling nfp_net_stop
1652          */
1653         if (dev->data->tx_queues[queue_idx]) {
1654                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1655                            queue_idx);
1656                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1657                 dev->data->tx_queues[queue_idx] = NULL;
1658         }
1659
1660         /* Allocating tx queue data structure */
1661         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1662                                  RTE_CACHE_LINE_SIZE, socket_id);
1663         if (txq == NULL) {
1664                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1665                 return -ENOMEM;
1666         }
1667
1668         /*
1669          * Allocate TX ring hardware descriptors. A memzone large enough to
1670          * handle the maximum ring size is allocated in order to allow for
1671          * resizing in later calls to the queue setup function.
1672          */
1673         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1674                                    sizeof(struct nfp_net_tx_desc) *
1675                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1676                                    socket_id);
1677         if (tz == NULL) {
1678                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1679                 nfp_net_tx_queue_release(txq);
1680                 return -ENOMEM;
1681         }
1682
1683         txq->tx_count = nb_desc;
1684         txq->tx_free_thresh = tx_free_thresh;
1685         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1686         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1687         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1688
1689         /* queue mapping based on firmware configuration */
1690         txq->qidx = queue_idx;
1691         txq->tx_qcidx = queue_idx * hw->stride_tx;
1692         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1693
1694         txq->port_id = dev->data->port_id;
1695         txq->txq_flags = tx_conf->txq_flags;
1696
1697         /* Saving physical and virtual addresses for the TX ring */
1698         txq->dma = (uint64_t)tz->phys_addr;
1699         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1700
1701         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1702         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1703                                          sizeof(*txq->txbufs) * nb_desc,
1704                                          RTE_CACHE_LINE_SIZE, socket_id);
1705         if (txq->txbufs == NULL) {
1706                 nfp_net_tx_queue_release(txq);
1707                 return -ENOMEM;
1708         }
1709         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1710                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1711
1712         nfp_net_reset_tx_queue(txq);
1713
1714         dev->data->tx_queues[queue_idx] = txq;
1715         txq->hw = hw;
1716
1717         /*
1718          * Telling the HW about the physical address of the TX ring and number
1719          * of descriptors in log2 format
1720          */
1721         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1722         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1723
1724         return 0;
1725 }
1726
1727 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1728 static inline void
1729 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1730                struct rte_mbuf *mb)
1731 {
1732         uint64_t ol_flags;
1733         struct nfp_net_hw *hw = txq->hw;
1734
1735         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1736                 goto clean_txd;
1737
1738         ol_flags = mb->ol_flags;
1739
1740         if (!(ol_flags & PKT_TX_TCP_SEG))
1741                 goto clean_txd;
1742
1743         txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1744         txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1745         txd->flags = PCIE_DESC_TX_LSO;
1746         return;
1747
1748 clean_txd:
1749         txd->flags = 0;
1750         txd->l4_offset = 0;
1751         txd->lso = 0;
1752 }
1753
1754 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1755 static inline void
1756 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1757                  struct rte_mbuf *mb)
1758 {
1759         uint64_t ol_flags;
1760         struct nfp_net_hw *hw = txq->hw;
1761
1762         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1763                 return;
1764
1765         ol_flags = mb->ol_flags;
1766
1767         /* IPv6 does not need checksum */
1768         if (ol_flags & PKT_TX_IP_CKSUM)
1769                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1770
1771         switch (ol_flags & PKT_TX_L4_MASK) {
1772         case PKT_TX_UDP_CKSUM:
1773                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1774                 break;
1775         case PKT_TX_TCP_CKSUM:
1776                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1777                 break;
1778         }
1779
1780         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1781                 txd->flags |= PCIE_DESC_TX_CSUM;
1782 }
1783
1784 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1785 static inline void
1786 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1787                  struct rte_mbuf *mb)
1788 {
1789         struct nfp_net_hw *hw = rxq->hw;
1790
1791         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1792                 return;
1793
1794         /* If IPv4 and IP checksum error, fail */
1795         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1796             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1797                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1798
1799         /* If neither UDP nor TCP return */
1800         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1801             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1802                 return;
1803
1804         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1805             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1806                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1807
1808         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1809             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1810                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1811 }
1812
1813 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1814 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1815
1816 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1817
1818 /*
1819  * nfp_net_set_hash - Set mbuf hash data
1820  *
1821  * The RSS hash and hash-type are pre-pended to the packet data.
1822  * Extract and decode it and set the mbuf fields.
1823  */
1824 static inline void
1825 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1826                  struct rte_mbuf *mbuf)
1827 {
1828         struct nfp_net_hw *hw = rxq->hw;
1829         uint8_t *meta_offset;
1830         uint32_t meta_info;
1831         uint32_t hash = 0;
1832         uint32_t hash_type = 0;
1833
1834         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1835                 return;
1836
1837         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1838                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1839                         return;
1840
1841                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1842                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1843
1844         } else if (NFP_DESC_META_LEN(rxd)) {
1845                 /*
1846                  * new metadata api:
1847                  * <----  32 bit  ----->
1848                  * m    field type word
1849                  * e     data field #2
1850                  * t     data field #1
1851                  * a     data field #0
1852                  * ====================
1853                  *    packet data
1854                  *
1855                  * Field type word contains up to 8 4bit field types
1856                  * A 4bit field type refers to a data field word
1857                  * A data field word can have several 4bit field types
1858                  */
1859                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1860                 meta_offset -= NFP_DESC_META_LEN(rxd);
1861                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1862                 meta_offset += 4;
1863                 /* NFP PMD just supports metadata for hashing */
1864                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1865                 case NFP_NET_META_HASH:
1866                         /* next field type is about the hash type */
1867                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1868                         /* hash value is in the data field */
1869                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1870                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1871                         break;
1872                 default:
1873                         /* Unsupported metadata can be a performance issue */
1874                         return;
1875                 }
1876         } else {
1877                 return;
1878         }
1879
1880         mbuf->hash.rss = hash;
1881         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1882
1883         switch (hash_type) {
1884         case NFP_NET_RSS_IPV4:
1885                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1886                 break;
1887         case NFP_NET_RSS_IPV6:
1888                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1889                 break;
1890         case NFP_NET_RSS_IPV6_EX:
1891                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1892                 break;
1893         default:
1894                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1895         }
1896 }
1897
1898 static inline void
1899 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1900 {
1901         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1902 }
1903
1904 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1905
1906 /*
1907  * RX path design:
1908  *
1909  * There are some decissions to take:
1910  * 1) How to check DD RX descriptors bit
1911  * 2) How and when to allocate new mbufs
1912  *
1913  * Current implementation checks just one single DD bit each loop. As each
1914  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1915  * a single cache line instead. Tests with this change have not shown any
1916  * performance improvement but it requires further investigation. For example,
1917  * depending on which descriptor is next, the number of descriptors could be
1918  * less than 8 for just checking those in the same cache line. This implies
1919  * extra work which could be counterproductive by itself. Indeed, last firmware
1920  * changes are just doing this: writing several descriptors with the DD bit
1921  * for saving PCIe bandwidth and DMA operations from the NFP.
1922  *
1923  * Mbuf allocation is done when a new packet is received. Then the descriptor
1924  * is automatically linked with the new mbuf and the old one is given to the
1925  * user. The main drawback with this design is mbuf allocation is heavier than
1926  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1927  * cache point of view it does not seem allocating the mbuf early on as we are
1928  * doing now have any benefit at all. Again, tests with this change have not
1929  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1930  * so looking at the implications of this type of allocation should be studied
1931  * deeply
1932  */
1933
1934 static uint16_t
1935 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1936 {
1937         struct nfp_net_rxq *rxq;
1938         struct nfp_net_rx_desc *rxds;
1939         struct nfp_net_rx_buff *rxb;
1940         struct nfp_net_hw *hw;
1941         struct rte_mbuf *mb;
1942         struct rte_mbuf *new_mb;
1943         uint16_t nb_hold;
1944         uint64_t dma_addr;
1945         int avail;
1946
1947         rxq = rx_queue;
1948         if (unlikely(rxq == NULL)) {
1949                 /*
1950                  * DPDK just checks the queue is lower than max queues
1951                  * enabled. But the queue needs to be configured
1952                  */
1953                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1954                 return -EINVAL;
1955         }
1956
1957         hw = rxq->hw;
1958         avail = 0;
1959         nb_hold = 0;
1960
1961         while (avail < nb_pkts) {
1962                 rxb = &rxq->rxbufs[rxq->rd_p];
1963                 if (unlikely(rxb == NULL)) {
1964                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1965                         break;
1966                 }
1967
1968                 /*
1969                  * Memory barrier to ensure that we won't do other
1970                  * reads before the DD bit.
1971                  */
1972                 rte_rmb();
1973
1974                 rxds = &rxq->rxds[rxq->rd_p];
1975                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1976                         break;
1977
1978                 /*
1979                  * We got a packet. Let's alloc a new mbuff for refilling the
1980                  * free descriptor ring as soon as possible
1981                  */
1982                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1983                 if (unlikely(new_mb == NULL)) {
1984                         RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1985                                 "queue_id=%u\n", (unsigned)rxq->port_id,
1986                                 (unsigned)rxq->qidx);
1987                         nfp_net_mbuf_alloc_failed(rxq);
1988                         break;
1989                 }
1990
1991                 nb_hold++;
1992
1993                 /*
1994                  * Grab the mbuff and refill the descriptor with the
1995                  * previously allocated mbuff
1996                  */
1997                 mb = rxb->mbuf;
1998                 rxb->mbuf = new_mb;
1999
2000                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
2001                            rxds->rxd.data_len, rxq->mbuf_size);
2002
2003                 /* Size of this segment */
2004                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2005                 /* Size of the whole packet. We just support 1 segment */
2006                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2007
2008                 if (unlikely((mb->data_len + hw->rx_offset) >
2009                              rxq->mbuf_size)) {
2010                         /*
2011                          * This should not happen and the user has the
2012                          * responsibility of avoiding it. But we have
2013                          * to give some info about the error
2014                          */
2015                         RTE_LOG_DP(ERR, PMD,
2016                                 "mbuf overflow likely due to the RX offset.\n"
2017                                 "\t\tYour mbuf size should have extra space for"
2018                                 " RX offset=%u bytes.\n"
2019                                 "\t\tCurrently you just have %u bytes available"
2020                                 " but the received packet is %u bytes long",
2021                                 hw->rx_offset,
2022                                 rxq->mbuf_size - hw->rx_offset,
2023                                 mb->data_len);
2024                         return -EINVAL;
2025                 }
2026
2027                 /* Filling the received mbuff with packet info */
2028                 if (hw->rx_offset)
2029                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2030                 else
2031                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2032                                        NFP_DESC_META_LEN(rxds);
2033
2034                 /* No scatter mode supported */
2035                 mb->nb_segs = 1;
2036                 mb->next = NULL;
2037
2038                 /* Checking the RSS flag */
2039                 nfp_net_set_hash(rxq, rxds, mb);
2040
2041                 /* Checking the checksum flag */
2042                 nfp_net_rx_cksum(rxq, rxds, mb);
2043
2044                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2045                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2046                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2047                         mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
2048                 }
2049
2050                 /* Adding the mbuff to the mbuff array passed by the app */
2051                 rx_pkts[avail++] = mb;
2052
2053                 /* Now resetting and updating the descriptor */
2054                 rxds->vals[0] = 0;
2055                 rxds->vals[1] = 0;
2056                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2057                 rxds->fld.dd = 0;
2058                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2059                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2060
2061                 rxq->rd_p++;
2062                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2063                         rxq->rd_p = 0;
2064         }
2065
2066         if (nb_hold == 0)
2067                 return nb_hold;
2068
2069         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received\n",
2070                    (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
2071
2072         nb_hold += rxq->nb_rx_hold;
2073
2074         /*
2075          * FL descriptors needs to be written before incrementing the
2076          * FL queue WR pointer
2077          */
2078         rte_wmb();
2079         if (nb_hold > rxq->rx_free_thresh) {
2080                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2081                            (unsigned)rxq->port_id, (unsigned)rxq->qidx,
2082                            (unsigned)nb_hold, (unsigned)avail);
2083                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2084                 nb_hold = 0;
2085         }
2086         rxq->nb_rx_hold = nb_hold;
2087
2088         return avail;
2089 }
2090
2091 /*
2092  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2093  * status
2094  * @txq: TX queue to work with
2095  * Returns number of descriptors freed
2096  */
2097 int
2098 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2099 {
2100         uint32_t qcp_rd_p;
2101         int todo;
2102
2103         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2104                    " status\n", txq->qidx);
2105
2106         /* Work out how many packets have been sent */
2107         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2108
2109         if (qcp_rd_p == txq->rd_p) {
2110                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2111                            "packets (%u, %u)\n", txq->qidx,
2112                            qcp_rd_p, txq->rd_p);
2113                 return 0;
2114         }
2115
2116         if (qcp_rd_p > txq->rd_p)
2117                 todo = qcp_rd_p - txq->rd_p;
2118         else
2119                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2120
2121         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2122                    qcp_rd_p, txq->rd_p, txq->rd_p);
2123
2124         if (todo == 0)
2125                 return todo;
2126
2127         txq->rd_p += todo;
2128         if (unlikely(txq->rd_p >= txq->tx_count))
2129                 txq->rd_p -= txq->tx_count;
2130
2131         return todo;
2132 }
2133
2134 /* Leaving always free descriptors for avoiding wrapping confusion */
2135 static inline
2136 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2137 {
2138         if (txq->wr_p >= txq->rd_p)
2139                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2140         else
2141                 return txq->rd_p - txq->wr_p - 8;
2142 }
2143
2144 /*
2145  * nfp_net_txq_full - Check if the TX queue free descriptors
2146  * is below tx_free_threshold
2147  *
2148  * @txq: TX queue to check
2149  *
2150  * This function uses the host copy* of read/write pointers
2151  */
2152 static inline
2153 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2154 {
2155         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2156 }
2157
2158 static uint16_t
2159 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2160 {
2161         struct nfp_net_txq *txq;
2162         struct nfp_net_hw *hw;
2163         struct nfp_net_tx_desc *txds, txd;
2164         struct rte_mbuf *pkt;
2165         uint64_t dma_addr;
2166         int pkt_size, dma_size;
2167         uint16_t free_descs, issued_descs;
2168         struct rte_mbuf **lmbuf;
2169         int i;
2170
2171         txq = tx_queue;
2172         hw = txq->hw;
2173         txds = &txq->txds[txq->wr_p];
2174
2175         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2176                    txq->qidx, txq->wr_p, nb_pkts);
2177
2178         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2179                 nfp_net_tx_free_bufs(txq);
2180
2181         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2182         if (unlikely(free_descs == 0))
2183                 return 0;
2184
2185         pkt = *tx_pkts;
2186
2187         i = 0;
2188         issued_descs = 0;
2189         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2190                    txq->qidx, nb_pkts);
2191         /* Sending packets */
2192         while ((i < nb_pkts) && free_descs) {
2193                 /* Grabbing the mbuf linked to the current descriptor */
2194                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2195                 /* Warming the cache for releasing the mbuf later on */
2196                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2197
2198                 pkt = *(tx_pkts + i);
2199
2200                 if (unlikely((pkt->nb_segs > 1) &&
2201                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2202                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2203                         rte_panic("Multisegment packet unsupported\n");
2204                 }
2205
2206                 /* Checking if we have enough descriptors */
2207                 if (unlikely(pkt->nb_segs > free_descs))
2208                         goto xmit_end;
2209
2210                 /*
2211                  * Checksum and VLAN flags just in the first descriptor for a
2212                  * multisegment packet, but TSO info needs to be in all of them.
2213                  */
2214                 txd.data_len = pkt->pkt_len;
2215                 nfp_net_tx_tso(txq, &txd, pkt);
2216                 nfp_net_tx_cksum(txq, &txd, pkt);
2217
2218                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2219                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2220                         txd.flags |= PCIE_DESC_TX_VLAN;
2221                         txd.vlan = pkt->vlan_tci;
2222                 }
2223
2224                 /*
2225                  * mbuf data_len is the data in one segment and pkt_len data
2226                  * in the whole packet. When the packet is just one segment,
2227                  * then data_len = pkt_len
2228                  */
2229                 pkt_size = pkt->pkt_len;
2230
2231                 while (pkt) {
2232                         /* Copying TSO, VLAN and cksum info */
2233                         *txds = txd;
2234
2235                         /* Releasing mbuf used by this descriptor previously*/
2236                         if (*lmbuf)
2237                                 rte_pktmbuf_free_seg(*lmbuf);
2238
2239                         /*
2240                          * Linking mbuf with descriptor for being released
2241                          * next time descriptor is used
2242                          */
2243                         *lmbuf = pkt;
2244
2245                         dma_size = pkt->data_len;
2246                         dma_addr = rte_mbuf_data_dma_addr(pkt);
2247                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2248                                    "%" PRIx64 "\n", dma_addr);
2249
2250                         /* Filling descriptors fields */
2251                         txds->dma_len = dma_size;
2252                         txds->data_len = txd.data_len;
2253                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2254                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2255                         ASSERT(free_descs > 0);
2256                         free_descs--;
2257
2258                         txq->wr_p++;
2259                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2260                                 txq->wr_p = 0;
2261
2262                         pkt_size -= dma_size;
2263                         if (!pkt_size)
2264                                 /* End of packet */
2265                                 txds->offset_eop |= PCIE_DESC_TX_EOP;
2266                         else
2267                                 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2268
2269                         pkt = pkt->next;
2270                         /* Referencing next free TX descriptor */
2271                         txds = &txq->txds[txq->wr_p];
2272                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2273                         issued_descs++;
2274                 }
2275                 i++;
2276         }
2277
2278 xmit_end:
2279         /* Increment write pointers. Force memory write before we let HW know */
2280         rte_wmb();
2281         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2282
2283         return i;
2284 }
2285
2286 static void
2287 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2288 {
2289         uint32_t new_ctrl, update;
2290         struct nfp_net_hw *hw;
2291
2292         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2293         new_ctrl = 0;
2294
2295         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2296             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2297                 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2298                         " ETH_VLAN_EXTEND_OFFLOAD");
2299
2300         /* Enable vlan strip if it is not configured yet */
2301         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2302             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2303                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2304
2305         /* Disable vlan strip just if it is configured */
2306         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2307             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2308                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2309
2310         if (new_ctrl == 0)
2311                 return;
2312
2313         update = NFP_NET_CFG_UPDATE_GEN;
2314
2315         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2316                 return;
2317
2318         hw->ctrl = new_ctrl;
2319 }
2320
2321 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2322 static int
2323 nfp_net_reta_update(struct rte_eth_dev *dev,
2324                     struct rte_eth_rss_reta_entry64 *reta_conf,
2325                     uint16_t reta_size)
2326 {
2327         uint32_t reta, mask;
2328         int i, j;
2329         int idx, shift;
2330         uint32_t update;
2331         struct nfp_net_hw *hw =
2332                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2333
2334         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2335                 return -EINVAL;
2336
2337         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2338                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2339                         "(%d) doesn't match the number hardware can supported "
2340                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2341                 return -EINVAL;
2342         }
2343
2344         /*
2345          * Update Redirection Table. There are 128 8bit-entries which can be
2346          * manage as 32 32bit-entries
2347          */
2348         for (i = 0; i < reta_size; i += 4) {
2349                 /* Handling 4 RSS entries per loop */
2350                 idx = i / RTE_RETA_GROUP_SIZE;
2351                 shift = i % RTE_RETA_GROUP_SIZE;
2352                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2353
2354                 if (!mask)
2355                         continue;
2356
2357                 reta = 0;
2358                 /* If all 4 entries were set, don't need read RETA register */
2359                 if (mask != 0xF)
2360                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2361
2362                 for (j = 0; j < 4; j++) {
2363                         if (!(mask & (0x1 << j)))
2364                                 continue;
2365                         if (mask != 0xF)
2366                                 /* Clearing the entry bits */
2367                                 reta &= ~(0xFF << (8 * j));
2368                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2369                 }
2370                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2371                               reta);
2372         }
2373
2374         update = NFP_NET_CFG_UPDATE_RSS;
2375
2376         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2377                 return -EIO;
2378
2379         return 0;
2380 }
2381
2382  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2383 static int
2384 nfp_net_reta_query(struct rte_eth_dev *dev,
2385                    struct rte_eth_rss_reta_entry64 *reta_conf,
2386                    uint16_t reta_size)
2387 {
2388         uint8_t i, j, mask;
2389         int idx, shift;
2390         uint32_t reta;
2391         struct nfp_net_hw *hw;
2392
2393         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394
2395         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2396                 return -EINVAL;
2397
2398         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2399                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2400                         "(%d) doesn't match the number hardware can supported "
2401                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2402                 return -EINVAL;
2403         }
2404
2405         /*
2406          * Reading Redirection Table. There are 128 8bit-entries which can be
2407          * manage as 32 32bit-entries
2408          */
2409         for (i = 0; i < reta_size; i += 4) {
2410                 /* Handling 4 RSS entries per loop */
2411                 idx = i / RTE_RETA_GROUP_SIZE;
2412                 shift = i % RTE_RETA_GROUP_SIZE;
2413                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2414
2415                 if (!mask)
2416                         continue;
2417
2418                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2419                                     shift);
2420                 for (j = 0; j < 4; j++) {
2421                         if (!(mask & (0x1 << j)))
2422                                 continue;
2423                         reta_conf->reta[shift + j] =
2424                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2425                 }
2426         }
2427         return 0;
2428 }
2429
2430 static int
2431 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2432                         struct rte_eth_rss_conf *rss_conf)
2433 {
2434         uint32_t update;
2435         uint32_t cfg_rss_ctrl = 0;
2436         uint8_t key;
2437         uint64_t rss_hf;
2438         int i;
2439         struct nfp_net_hw *hw;
2440
2441         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2442
2443         rss_hf = rss_conf->rss_hf;
2444
2445         /* Checking if RSS is enabled */
2446         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2447                 if (rss_hf != 0) { /* Enable RSS? */
2448                         RTE_LOG(ERR, PMD, "RSS unsupported\n");
2449                         return -EINVAL;
2450                 }
2451                 return 0; /* Nothing to do */
2452         }
2453
2454         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2455                 RTE_LOG(ERR, PMD, "hash key too long\n");
2456                 return -EINVAL;
2457         }
2458
2459         if (rss_hf & ETH_RSS_IPV4)
2460                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2461                                 NFP_NET_CFG_RSS_IPV4_TCP |
2462                                 NFP_NET_CFG_RSS_IPV4_UDP;
2463
2464         if (rss_hf & ETH_RSS_IPV6)
2465                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2466                                 NFP_NET_CFG_RSS_IPV6_TCP |
2467                                 NFP_NET_CFG_RSS_IPV6_UDP;
2468
2469         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2470         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2471
2472         /* configuring where to apply the RSS hash */
2473         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2474
2475         /* Writing the key byte a byte */
2476         for (i = 0; i < rss_conf->rss_key_len; i++) {
2477                 memcpy(&key, &rss_conf->rss_key[i], 1);
2478                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2479         }
2480
2481         /* Writing the key size */
2482         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2483
2484         update = NFP_NET_CFG_UPDATE_RSS;
2485
2486         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2487                 return -EIO;
2488
2489         return 0;
2490 }
2491
2492 static int
2493 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2494                           struct rte_eth_rss_conf *rss_conf)
2495 {
2496         uint64_t rss_hf;
2497         uint32_t cfg_rss_ctrl;
2498         uint8_t key;
2499         int i;
2500         struct nfp_net_hw *hw;
2501
2502         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2503
2504         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2505                 return -EINVAL;
2506
2507         rss_hf = rss_conf->rss_hf;
2508         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2509
2510         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2511                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2512
2513         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2514                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2515
2516         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2517                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2518
2519         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2520                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2521
2522         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2523                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2524
2525         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2526                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2527
2528         /* Reading the key size */
2529         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2530
2531         /* Reading the key byte a byte */
2532         for (i = 0; i < rss_conf->rss_key_len; i++) {
2533                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2534                 memcpy(&rss_conf->rss_key[i], &key, 1);
2535         }
2536
2537         return 0;
2538 }
2539
2540 /* Initialise and register driver with DPDK Application */
2541 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2542         .dev_configure          = nfp_net_configure,
2543         .dev_start              = nfp_net_start,
2544         .dev_stop               = nfp_net_stop,
2545         .dev_close              = nfp_net_close,
2546         .promiscuous_enable     = nfp_net_promisc_enable,
2547         .promiscuous_disable    = nfp_net_promisc_disable,
2548         .link_update            = nfp_net_link_update,
2549         .stats_get              = nfp_net_stats_get,
2550         .stats_reset            = nfp_net_stats_reset,
2551         .dev_infos_get          = nfp_net_infos_get,
2552         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2553         .mtu_set                = nfp_net_dev_mtu_set,
2554         .vlan_offload_set       = nfp_net_vlan_offload_set,
2555         .reta_update            = nfp_net_reta_update,
2556         .reta_query             = nfp_net_reta_query,
2557         .rss_hash_update        = nfp_net_rss_hash_update,
2558         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2559         .rx_queue_setup         = nfp_net_rx_queue_setup,
2560         .rx_queue_release       = nfp_net_rx_queue_release,
2561         .rx_queue_count         = nfp_net_rx_queue_count,
2562         .tx_queue_setup         = nfp_net_tx_queue_setup,
2563         .tx_queue_release       = nfp_net_tx_queue_release,
2564         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2565         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2566 };
2567
2568 /*
2569  * All eth_dev created got its private data, but before nfp_net_init, that
2570  * private data is referencing private data for all the PF ports. This is due
2571  * to how the vNIC bars are mapped based on first port, so all ports need info
2572  * about port 0 private data. Inside nfp_net_init the private data pointer is
2573  * changed to the right address for each port once the bars have been mapped.
2574  *
2575  * This functions helps to find out which port and therefore which offset
2576  * inside the private data array to use.
2577  */
2578 static int
2579 get_pf_port_number(char *name)
2580 {
2581         char *pf_str = name;
2582         int size = 0;
2583
2584         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2585                 pf_str++;
2586
2587         if (size == 30)
2588                 /*
2589                  * This should not happen at all and it would mean major
2590                  * implementation fault.
2591                  */
2592                 rte_panic("nfp_net: problem with pf device name\n");
2593
2594         /* Expecting _portX with X within [0,7] */
2595         pf_str += 5;
2596
2597         return (int)strtol(pf_str, NULL, 10);
2598 }
2599
2600 static int
2601 nfp_net_init(struct rte_eth_dev *eth_dev)
2602 {
2603         struct rte_pci_device *pci_dev;
2604         struct nfp_net_hw *hw, *hwport0;
2605
2606         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2607         uint32_t start_q;
2608         int stride = 4;
2609
2610         nspu_desc_t *nspu_desc = NULL;
2611         uint64_t bar_offset;
2612         int port = 0;
2613
2614         PMD_INIT_FUNC_TRACE();
2615
2616         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2617
2618         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2619             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2620                 port = get_pf_port_number(eth_dev->data->name);
2621                 if (port < 0 || port > 7) {
2622                         RTE_LOG(ERR, PMD, "Port value is wrong\n");
2623                         return -ENODEV;
2624                 }
2625
2626                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2627
2628                 /* This points to port 0 private data */
2629                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2630
2631                 /* This points to the specific port private data */
2632                 hw = &hwport0[port];
2633                 hw->pf_port_idx = port;
2634         } else {
2635                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2636                 hwport0 = 0;
2637         }
2638
2639         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2640         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2641         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2642
2643         /* For secondary processes, the primary has done all the work */
2644         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2645                 return 0;
2646
2647         rte_eth_copy_pci_info(eth_dev, pci_dev);
2648         /* hotplug is not possible with multiport PF */
2649         if (!hw->pf_multiport_enabled)
2650                 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2651
2652         hw->device_id = pci_dev->id.device_id;
2653         hw->vendor_id = pci_dev->id.vendor_id;
2654         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2655         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2656
2657         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2658                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2659                      pci_dev->addr.domain, pci_dev->addr.bus,
2660                      pci_dev->addr.devid, pci_dev->addr.function);
2661
2662         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2663         if (hw->ctrl_bar == NULL) {
2664                 RTE_LOG(ERR, PMD,
2665                         "hw->ctrl_bar is NULL. BAR0 not configured\n");
2666                 return -ENODEV;
2667         }
2668
2669         if (hw->is_pf && port == 0) {
2670                 nspu_desc = hw->nspu_desc;
2671
2672                 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2673                         /*
2674                          * A firmware should be there after PF probe so this
2675                          * should not happen.
2676                          */
2677                         RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2678                         return -ENODEV;
2679                 }
2680
2681                 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2682                 hw->ctrl_bar += bar_offset;
2683                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2684         }
2685
2686         if (port > 0) {
2687                 if (!hwport0->ctrl_bar)
2688                         return -ENODEV;
2689
2690                 /* address based on port0 offset */
2691                 hw->ctrl_bar = hwport0->ctrl_bar +
2692                                (port * NFP_PF_CSR_SLICE_SIZE);
2693         }
2694
2695         PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2696
2697         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2698         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2699
2700         /* Work out where in the BAR the queues start. */
2701         switch (pci_dev->id.device_id) {
2702         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2703         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2704         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2705                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2706                 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2707                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2708                 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2709                 break;
2710         default:
2711                 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2712                 return -ENODEV;
2713         }
2714
2715         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2716         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2717
2718         if (hw->is_pf && port == 0) {
2719                 /* configure access to tx/rx vNIC BARs */
2720                 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2721                 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2722                                     bar_offset);
2723                 hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2724
2725                 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2726                 hwport0->hw_queues += bar_offset;
2727
2728                 /* Lets seize the chance to read eth table from hw */
2729                 if (nfp_nsp_eth_read_table(nspu_desc, &hw->eth_table))
2730                         return -ENODEV;
2731         }
2732
2733         if (hw->is_pf) {
2734                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2735                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2736                 eth_dev->data->dev_private = hw;
2737         } else {
2738                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2739                              tx_bar_off;
2740                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2741                              rx_bar_off;
2742         }
2743
2744         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2745                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2746
2747         nfp_net_cfg_queue_setup(hw);
2748
2749         /* Get some of the read-only fields from the config BAR */
2750         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2751         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2752         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2753         hw->mtu = hw->max_mtu;
2754
2755         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2756                 hw->rx_offset = NFP_NET_RX_OFFSET;
2757         else
2758                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2759
2760         PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2761                      hw->ver, hw->max_mtu);
2762         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2763                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2764                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2765                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2766                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2767                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2768                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2769                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2770                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2771                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "");
2772
2773         hw->ctrl = 0;
2774
2775         hw->stride_rx = stride;
2776         hw->stride_tx = stride;
2777
2778         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2779                      hw->max_rx_queues, hw->max_tx_queues);
2780
2781         /* Initializing spinlock for reconfigs */
2782         rte_spinlock_init(&hw->reconfig_lock);
2783
2784         /* Allocating memory for mac addr */
2785         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2786         if (eth_dev->data->mac_addrs == NULL) {
2787                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2788                 return -ENOMEM;
2789         }
2790
2791         if (hw->is_pf)
2792                 nfp_net_pf_read_mac(hwport0, port);
2793         else
2794                 nfp_net_vf_read_mac(hw);
2795
2796         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2797                 /* Using random mac addresses for VFs */
2798                 eth_random_addr(&hw->mac_addr[0]);
2799                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2800         }
2801
2802         /* Copying mac address to DPDK eth_dev struct */
2803         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2804                         &eth_dev->data->mac_addrs[0]);
2805
2806         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2807                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2808                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2809                      pci_dev->id.device_id,
2810                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2811                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2812
2813         /* Registering LSC interrupt handler */
2814         rte_intr_callback_register(&pci_dev->intr_handle,
2815                                    nfp_net_dev_interrupt_handler,
2816                                    (void *)eth_dev);
2817
2818         /* Telling the firmware about the LSC interrupt entry */
2819         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2820
2821         /* Recording current stats counters values */
2822         nfp_net_stats_reset(eth_dev);
2823
2824         return 0;
2825 }
2826
2827 static int
2828 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2829                   nfpu_desc_t *nfpu_desc, void **priv)
2830 {
2831         struct rte_eth_dev *eth_dev;
2832         struct nfp_net_hw *hw;
2833         char *port_name;
2834         int ret;
2835
2836         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2837         if (!port_name)
2838                 return -ENOMEM;
2839
2840         if (ports > 1)
2841                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2842         else
2843                 sprintf(port_name, "%s", dev->device.name);
2844
2845         eth_dev = rte_eth_dev_allocate(port_name);
2846         if (!eth_dev)
2847                 return -ENOMEM;
2848
2849         if (port == 0) {
2850                 *priv = rte_zmalloc(port_name,
2851                                     sizeof(struct nfp_net_adapter) * ports,
2852                                     RTE_CACHE_LINE_SIZE);
2853                 if (!*priv) {
2854                         rte_eth_dev_release_port(eth_dev);
2855                         return -ENOMEM;
2856                 }
2857         }
2858
2859         eth_dev->data->dev_private = *priv;
2860
2861         /*
2862          * dev_private pointing to port0 dev_private because we need
2863          * to configure vNIC bars based on port0 at nfp_net_init.
2864          * Then dev_private is adjusted per port.
2865          */
2866         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2867         hw->nspu_desc = nfpu_desc->nspu;
2868         hw->nfpu_desc = nfpu_desc;
2869         hw->is_pf = 1;
2870         if (ports > 1)
2871                 hw->pf_multiport_enabled = 1;
2872
2873         eth_dev->device = &dev->device;
2874         rte_eth_copy_pci_info(eth_dev, dev);
2875
2876         ret = nfp_net_init(eth_dev);
2877
2878         if (ret)
2879                 rte_eth_dev_release_port(eth_dev);
2880
2881         rte_free(port_name);
2882
2883         return ret;
2884 }
2885
2886 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2887                             struct rte_pci_device *dev)
2888 {
2889         nfpu_desc_t *nfpu_desc;
2890         nspu_desc_t *nspu_desc;
2891         uint64_t offset_symbol;
2892         uint8_t *bar_offset;
2893         int major, minor;
2894         int total_ports;
2895         void *priv = 0;
2896         int ret = -ENODEV;
2897         int i;
2898
2899         if (!dev)
2900                 return ret;
2901
2902         nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2903         if (!nfpu_desc)
2904                 return -ENOMEM;
2905
2906         if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2907                 RTE_LOG(ERR, PMD,
2908                         "nfpu_open failed\n");
2909                 goto nfpu_error;
2910         }
2911
2912         nspu_desc = nfpu_desc->nspu;
2913
2914
2915         /* Check NSP ABI version */
2916         if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2917                 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2918                 goto error;
2919         }
2920         PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2921
2922         if ((major == 0) && (minor < 20)) {
2923                 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2924                 goto error;
2925         }
2926
2927         ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
2928                                &offset_symbol);
2929         if (ret)
2930                 goto error;
2931
2932         bar_offset = (uint8_t *)dev->mem_resource[0].addr;
2933         bar_offset += offset_symbol;
2934         total_ports = (uint32_t)*bar_offset;
2935         PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
2936
2937         if (total_ports <= 0 || total_ports > 8) {
2938                 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
2939                 ret = -ENODEV;
2940                 goto error;
2941         }
2942
2943         for (i = 0; i < total_ports; i++) {
2944                 ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
2945                 if (ret)
2946                         goto error;
2947         }
2948
2949         return 0;
2950
2951 error:
2952         nfpu_close(nfpu_desc);
2953 nfpu_error:
2954         rte_free(nfpu_desc);
2955
2956         return ret;
2957 }
2958
2959 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
2960         {
2961                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2962                                PCI_DEVICE_ID_NFP4000_PF_NIC)
2963         },
2964         {
2965                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2966                                PCI_DEVICE_ID_NFP6000_PF_NIC)
2967         },
2968         {
2969                 .vendor_id = 0,
2970         },
2971 };
2972
2973 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
2974         {
2975                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2976                                PCI_DEVICE_ID_NFP6000_VF_NIC)
2977         },
2978         {
2979                 .vendor_id = 0,
2980         },
2981 };
2982
2983 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2984         struct rte_pci_device *pci_dev)
2985 {
2986         return rte_eth_dev_pci_generic_probe(pci_dev,
2987                 sizeof(struct nfp_net_adapter), nfp_net_init);
2988 }
2989
2990 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
2991 {
2992         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2993 }
2994
2995 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
2996         .id_table = pci_id_nfp_pf_net_map,
2997         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2998         .probe = nfp_pf_pci_probe,
2999         .remove = eth_nfp_pci_remove,
3000 };
3001
3002 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3003         .id_table = pci_id_nfp_vf_net_map,
3004         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3005         .probe = eth_nfp_pci_probe,
3006         .remove = eth_nfp_pci_remove,
3007 };
3008
3009 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3010 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3011 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3012 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3013 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3014 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3015
3016 /*
3017  * Local variables:
3018  * c-file-style: "Linux"
3019  * indent-tabs-mode: t
3020  * End:
3021  */