1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
9 * vim:shiftwidth=8:noexpandtab
11 * @file dpdk/pmd/nfp_net.c
13 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
19 #include <rte_debug.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
23 #include <rte_ether.h>
24 #include <rte_malloc.h>
25 #include <rte_memzone.h>
26 #include <rte_mempool.h>
27 #include <rte_version.h>
28 #include <rte_string_fns.h>
29 #include <rte_alarm.h>
30 #include <rte_spinlock.h>
31 #include <rte_service_component.h>
33 #include "eal_firmware.h"
35 #include "nfpcore/nfp_cpp.h"
36 #include "nfpcore/nfp_nffw.h"
37 #include "nfpcore/nfp_hwinfo.h"
38 #include "nfpcore/nfp_mip.h"
39 #include "nfpcore/nfp_rtsym.h"
40 #include "nfpcore/nfp_nsp.h"
42 #include "nfp_net_pmd.h"
43 #include "nfp_net_logs.h"
44 #include "nfp_net_ctrl.h"
46 #include <sys/types.h>
47 #include <sys/socket.h>
51 #include <sys/ioctl.h>
55 static int nfp_net_close(struct rte_eth_dev *dev);
56 static int nfp_net_configure(struct rte_eth_dev *dev);
57 static void nfp_net_dev_interrupt_handler(void *param);
58 static void nfp_net_dev_interrupt_delayed_handler(void *param);
59 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
60 static int nfp_net_infos_get(struct rte_eth_dev *dev,
61 struct rte_eth_dev_info *dev_info);
62 static int nfp_net_init(struct rte_eth_dev *eth_dev);
63 static int nfp_pf_init(struct rte_eth_dev *eth_dev);
64 static int nfp_pci_uninit(struct rte_eth_dev *eth_dev);
65 static int nfp_init_phyports(struct nfp_pf_dev *pf_dev);
66 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
67 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
68 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
69 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
70 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
72 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
74 static void nfp_net_rx_queue_release(void *rxq);
75 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
76 uint16_t nb_desc, unsigned int socket_id,
77 const struct rte_eth_rxconf *rx_conf,
78 struct rte_mempool *mp);
79 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
80 static void nfp_net_tx_queue_release(void *txq);
81 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
82 uint16_t nb_desc, unsigned int socket_id,
83 const struct rte_eth_txconf *tx_conf);
84 static int nfp_net_start(struct rte_eth_dev *dev);
85 static int nfp_net_stats_get(struct rte_eth_dev *dev,
86 struct rte_eth_stats *stats);
87 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
88 static int nfp_net_stop(struct rte_eth_dev *dev);
89 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
92 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
93 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
94 struct rte_eth_rss_conf *rss_conf);
95 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
96 struct rte_eth_rss_reta_entry64 *reta_conf,
98 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
99 struct rte_eth_rss_conf *rss_conf);
100 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
101 struct rte_ether_addr *mac_addr);
102 static int32_t nfp_cpp_bridge_service_func(void *args);
103 static int nfp_fw_setup(struct rte_pci_device *dev,
105 struct nfp_eth_table *nfp_eth_table,
106 struct nfp_hwinfo *hwinfo);
109 /* The offset of the queue controller queues in the PCIe Target */
110 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
112 /* Maximum value which can be added to a queue with one transaction */
113 #define NFP_QCP_MAX_ADD 0x7f
115 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
116 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
118 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
120 NFP_QCP_READ_PTR = 0,
125 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
126 * @q: Base address for queue structure
127 * @ptr: Add to the Read or Write pointer
128 * @val: Value to add to the queue pointer
130 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
133 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
137 if (ptr == NFP_QCP_READ_PTR)
138 off = NFP_QCP_QUEUE_ADD_RPTR;
140 off = NFP_QCP_QUEUE_ADD_WPTR;
142 while (val > NFP_QCP_MAX_ADD) {
143 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
144 val -= NFP_QCP_MAX_ADD;
147 nn_writel(rte_cpu_to_le_32(val), q + off);
151 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
152 * @q: Base address for queue structure
153 * @ptr: Read or Write pointer
155 static inline uint32_t
156 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
161 if (ptr == NFP_QCP_READ_PTR)
162 off = NFP_QCP_QUEUE_STS_LO;
164 off = NFP_QCP_QUEUE_STS_HI;
166 val = rte_cpu_to_le_32(nn_readl(q + off));
168 if (ptr == NFP_QCP_READ_PTR)
169 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
171 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
175 * Functions to read/write from/to Config BAR
176 * Performs any endian conversion necessary.
178 static inline uint8_t
179 nn_cfg_readb(struct nfp_net_hw *hw, int off)
181 return nn_readb(hw->ctrl_bar + off);
185 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
187 nn_writeb(val, hw->ctrl_bar + off);
190 static inline uint32_t
191 nn_cfg_readl(struct nfp_net_hw *hw, int off)
193 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
197 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
199 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
202 static inline uint64_t
203 nn_cfg_readq(struct nfp_net_hw *hw, int off)
205 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
209 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
211 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
215 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
219 if (rxq->rxbufs == NULL)
222 for (i = 0; i < rxq->rx_count; i++) {
223 if (rxq->rxbufs[i].mbuf) {
224 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
225 rxq->rxbufs[i].mbuf = NULL;
231 nfp_net_rx_queue_release(void *rx_queue)
233 struct nfp_net_rxq *rxq = rx_queue;
236 nfp_net_rx_queue_release_mbufs(rxq);
237 rte_free(rxq->rxbufs);
243 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
245 nfp_net_rx_queue_release_mbufs(rxq);
251 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
255 if (txq->txbufs == NULL)
258 for (i = 0; i < txq->tx_count; i++) {
259 if (txq->txbufs[i].mbuf) {
260 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
261 txq->txbufs[i].mbuf = NULL;
267 nfp_net_tx_queue_release(void *tx_queue)
269 struct nfp_net_txq *txq = tx_queue;
272 nfp_net_tx_queue_release_mbufs(txq);
273 rte_free(txq->txbufs);
279 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
281 nfp_net_tx_queue_release_mbufs(txq);
287 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
291 struct timespec wait;
293 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
296 if (hw->qcp_cfg == NULL)
297 rte_panic("Bad configuration queue pointer\n");
299 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
302 wait.tv_nsec = 1000000;
304 PMD_DRV_LOG(DEBUG, "Polling for update ack...");
306 /* Poll update field, waiting for NFP to ack the config */
307 for (cnt = 0; ; cnt++) {
308 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
311 if (new & NFP_NET_CFG_UPDATE_ERR) {
312 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
315 if (cnt >= NFP_NET_POLL_TIMEOUT) {
316 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
317 " %dms", update, cnt);
318 rte_panic("Exiting\n");
320 nanosleep(&wait, 0); /* waiting for a 1ms */
322 PMD_DRV_LOG(DEBUG, "Ack DONE");
327 * Reconfigure the NIC
328 * @nn: device to reconfigure
329 * @ctrl: The value for the ctrl field in the BAR config
330 * @update: The value for the update field in the BAR config
332 * Write the update word to the BAR and ping the reconfig queue. Then poll
333 * until the firmware has acknowledged the update by zeroing the update word.
336 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
340 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
343 rte_spinlock_lock(&hw->reconfig_lock);
345 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
346 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
350 err = __nfp_net_reconfig(hw, update);
352 rte_spinlock_unlock(&hw->reconfig_lock);
358 * Reconfig errors imply situations where they can be handled.
359 * Otherwise, rte_panic is called inside __nfp_net_reconfig
361 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
367 * Configure an Ethernet device. This function must be invoked first
368 * before any other function in the Ethernet API. This function can
369 * also be re-invoked when a device is in the stopped state.
372 nfp_net_configure(struct rte_eth_dev *dev)
374 struct rte_eth_conf *dev_conf;
375 struct rte_eth_rxmode *rxmode;
376 struct rte_eth_txmode *txmode;
377 struct nfp_net_hw *hw;
379 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
382 * A DPDK app sends info about how many queues to use and how
383 * those queues need to be configured. This is used by the
384 * DPDK core and it makes sure no more queues than those
385 * advertised by the driver are requested. This function is
386 * called after that internal process
389 PMD_INIT_LOG(DEBUG, "Configure");
391 dev_conf = &dev->data->dev_conf;
392 rxmode = &dev_conf->rxmode;
393 txmode = &dev_conf->txmode;
395 if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
396 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
398 /* Checking TX mode */
399 if (txmode->mq_mode) {
400 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
404 /* Checking RX mode */
405 if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
406 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
407 PMD_INIT_LOG(INFO, "RSS not supported");
415 nfp_net_enable_queues(struct rte_eth_dev *dev)
417 struct nfp_net_hw *hw;
418 uint64_t enabled_queues = 0;
421 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
423 /* Enabling the required TX queues in the device */
424 for (i = 0; i < dev->data->nb_tx_queues; i++)
425 enabled_queues |= (1 << i);
427 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
431 /* Enabling the required RX queues in the device */
432 for (i = 0; i < dev->data->nb_rx_queues; i++)
433 enabled_queues |= (1 << i);
435 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
439 nfp_net_disable_queues(struct rte_eth_dev *dev)
441 struct nfp_net_hw *hw;
442 uint32_t new_ctrl, update = 0;
444 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
446 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
447 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
449 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
450 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
451 NFP_NET_CFG_UPDATE_MSIX;
453 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
454 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
456 /* If an error when reconfig we avoid to change hw state */
457 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
464 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
468 for (i = 0; i < dev->data->nb_rx_queues; i++) {
469 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
476 nfp_net_params_setup(struct nfp_net_hw *hw)
478 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
479 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
483 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
485 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
488 #define ETH_ADDR_LEN 6
491 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
495 for (i = 0; i < ETH_ADDR_LEN; i++)
500 nfp_net_pf_read_mac(struct nfp_pf_dev *pf_dev, int port)
502 struct nfp_eth_table *nfp_eth_table;
503 struct nfp_net_hw *hw = NULL;
505 /* Grab a pointer to the correct physical port */
506 hw = pf_dev->ports[port];
508 nfp_eth_table = nfp_eth_read_ports(pf_dev->cpp);
510 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
511 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
518 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
522 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
523 memcpy(&hw->mac_addr[0], &tmp, 4);
525 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
526 memcpy(&hw->mac_addr[4], &tmp, 2);
530 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
532 uint32_t mac0 = *(uint32_t *)mac;
535 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
538 mac1 = *(uint16_t *)mac;
539 nn_writew(rte_cpu_to_be_16(mac1),
540 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
544 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
546 struct nfp_net_hw *hw;
547 uint32_t update, ctrl;
549 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
550 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
551 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
552 PMD_INIT_LOG(INFO, "MAC address unable to change when"
557 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
558 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
561 /* Writing new MAC to the specific port BAR address */
562 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
564 /* Signal the NIC about the change */
565 update = NFP_NET_CFG_UPDATE_MACADDR;
567 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
568 (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
569 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
570 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
571 PMD_INIT_LOG(INFO, "MAC address update failed");
578 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
579 struct rte_intr_handle *intr_handle)
581 struct nfp_net_hw *hw;
584 if (!intr_handle->intr_vec) {
585 intr_handle->intr_vec =
586 rte_zmalloc("intr_vec",
587 dev->data->nb_rx_queues * sizeof(int), 0);
588 if (!intr_handle->intr_vec) {
589 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
590 " intr_vec", dev->data->nb_rx_queues);
595 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
597 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
598 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
599 /* UIO just supports one queue and no LSC*/
600 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
601 intr_handle->intr_vec[0] = 0;
603 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
604 for (i = 0; i < dev->data->nb_rx_queues; i++) {
606 * The first msix vector is reserved for non
609 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
610 intr_handle->intr_vec[i] = i + 1;
611 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
612 intr_handle->intr_vec[i]);
616 /* Avoiding TX interrupts */
617 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
622 nfp_check_offloads(struct rte_eth_dev *dev)
624 struct nfp_net_hw *hw;
625 struct rte_eth_conf *dev_conf;
626 struct rte_eth_rxmode *rxmode;
627 struct rte_eth_txmode *txmode;
630 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
632 dev_conf = &dev->data->dev_conf;
633 rxmode = &dev_conf->rxmode;
634 txmode = &dev_conf->txmode;
636 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
637 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
638 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
641 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
642 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
643 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
646 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
647 hw->mtu = rxmode->max_rx_pkt_len;
649 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
650 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
653 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
654 ctrl |= NFP_NET_CFG_CTRL_L2BC;
657 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
658 ctrl |= NFP_NET_CFG_CTRL_L2MC;
660 /* TX checksum offload */
661 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
662 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
663 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
664 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
667 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
668 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
669 ctrl |= NFP_NET_CFG_CTRL_LSO;
671 ctrl |= NFP_NET_CFG_CTRL_LSO2;
675 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
676 ctrl |= NFP_NET_CFG_CTRL_GATHER;
682 nfp_net_start(struct rte_eth_dev *dev)
684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
686 uint32_t new_ctrl, update = 0;
687 struct nfp_net_hw *hw;
688 struct nfp_pf_dev *pf_dev;
689 struct rte_eth_conf *dev_conf;
690 struct rte_eth_rxmode *rxmode;
691 uint32_t intr_vector;
694 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
695 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(dev->data->dev_private);
697 PMD_INIT_LOG(DEBUG, "Start");
699 /* Disabling queues just in case... */
700 nfp_net_disable_queues(dev);
702 /* Enabling the required queues in the device */
703 nfp_net_enable_queues(dev);
705 /* check and configure queue intr-vector mapping */
706 if (dev->data->dev_conf.intr_conf.rxq != 0) {
707 if (pf_dev->multiport) {
708 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
709 "with NFP multiport PF");
712 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
714 * Better not to share LSC with RX interrupts.
715 * Unregistering LSC interrupt handler
717 rte_intr_callback_unregister(&pci_dev->intr_handle,
718 nfp_net_dev_interrupt_handler, (void *)dev);
720 if (dev->data->nb_rx_queues > 1) {
721 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
722 "supports 1 queue with UIO");
726 intr_vector = dev->data->nb_rx_queues;
727 if (rte_intr_efd_enable(intr_handle, intr_vector))
730 nfp_configure_rx_interrupt(dev, intr_handle);
731 update = NFP_NET_CFG_UPDATE_MSIX;
734 rte_intr_enable(intr_handle);
736 new_ctrl = nfp_check_offloads(dev);
738 /* Writing configuration parameters in the device */
739 nfp_net_params_setup(hw);
741 dev_conf = &dev->data->dev_conf;
742 rxmode = &dev_conf->rxmode;
744 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
745 nfp_net_rss_config_default(dev);
746 update |= NFP_NET_CFG_UPDATE_RSS;
747 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
751 new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
753 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
755 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
756 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
758 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
759 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
763 * Allocating rte mbufs for configured rx queues.
764 * This requires queues being enabled before
766 if (nfp_net_rx_freelist_setup(dev) < 0) {
771 if (hw->is_phyport) {
772 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
773 /* Configure the physical port up */
774 nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 1);
776 nfp_eth_set_configured(dev->process_private,
786 * An error returned by this function should mean the app
787 * exiting and then the system releasing all the memory
788 * allocated even memory coming from hugepages.
790 * The device could be enabled at this point with some queues
791 * ready for getting packets. This is true if the call to
792 * nfp_net_rx_freelist_setup() succeeds for some queues but
793 * fails for subsequent queues.
795 * This should make the app exiting but better if we tell the
798 nfp_net_disable_queues(dev);
803 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
805 nfp_net_stop(struct rte_eth_dev *dev)
808 struct nfp_net_hw *hw;
810 PMD_INIT_LOG(DEBUG, "Stop");
812 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
814 nfp_net_disable_queues(dev);
817 for (i = 0; i < dev->data->nb_tx_queues; i++) {
818 nfp_net_reset_tx_queue(
819 (struct nfp_net_txq *)dev->data->tx_queues[i]);
822 for (i = 0; i < dev->data->nb_rx_queues; i++) {
823 nfp_net_reset_rx_queue(
824 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
827 if (hw->is_phyport) {
828 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
829 /* Configure the physical port down */
830 nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 0);
832 nfp_eth_set_configured(dev->process_private,
839 /* Set the link up. */
841 nfp_net_set_link_up(struct rte_eth_dev *dev)
843 struct nfp_net_hw *hw;
845 PMD_DRV_LOG(DEBUG, "Set link up");
847 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
852 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
853 /* Configure the physical port down */
854 return nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 1);
856 return nfp_eth_set_configured(dev->process_private,
860 /* Set the link down. */
862 nfp_net_set_link_down(struct rte_eth_dev *dev)
864 struct nfp_net_hw *hw;
866 PMD_DRV_LOG(DEBUG, "Set link down");
868 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
873 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
874 /* Configure the physical port down */
875 return nfp_eth_set_configured(hw->cpp, hw->nfp_idx, 0);
877 return nfp_eth_set_configured(dev->process_private,
881 /* Reset and stop device. The device can not be restarted. */
883 nfp_net_close(struct rte_eth_dev *dev)
885 struct nfp_net_hw *hw;
886 struct rte_pci_device *pci_dev;
889 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
892 PMD_INIT_LOG(DEBUG, "Close");
894 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
895 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
898 * We assume that the DPDK application is stopping all the
899 * threads/queues before calling the device close function.
902 nfp_net_disable_queues(dev);
905 for (i = 0; i < dev->data->nb_tx_queues; i++) {
906 nfp_net_reset_tx_queue(
907 (struct nfp_net_txq *)dev->data->tx_queues[i]);
910 for (i = 0; i < dev->data->nb_rx_queues; i++) {
911 nfp_net_reset_rx_queue(
912 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
915 /* Only free PF resources after all physical ports have been closed */
916 if (pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC ||
917 pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC) {
918 struct nfp_pf_dev *pf_dev;
919 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(dev->data->dev_private);
921 /* Mark this port as unused and free device priv resources*/
922 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
923 pf_dev->ports[hw->idx] = NULL;
924 rte_eth_dev_release_port(dev);
926 for (i = 0; i < pf_dev->total_phyports; i++) {
927 /* Check to see if ports are still in use */
928 if (pf_dev->ports[i])
932 /* Now it is safe to free all PF resources */
933 PMD_INIT_LOG(INFO, "Freeing PF resources");
934 nfp_cpp_area_free(pf_dev->ctrl_area);
935 nfp_cpp_area_free(pf_dev->hwqueues_area);
936 free(pf_dev->hwinfo);
937 free(pf_dev->sym_tbl);
938 nfp_cpp_free(pf_dev->cpp);
942 rte_intr_disable(&pci_dev->intr_handle);
944 /* unregister callback func from eal lib */
945 rte_intr_callback_unregister(&pci_dev->intr_handle,
946 nfp_net_dev_interrupt_handler,
950 * The ixgbe PMD driver disables the pcie master on the
951 * device. The i40e does not...
958 nfp_net_promisc_enable(struct rte_eth_dev *dev)
960 uint32_t new_ctrl, update = 0;
961 struct nfp_net_hw *hw;
964 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
966 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
968 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
969 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
973 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
974 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
978 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
979 update = NFP_NET_CFG_UPDATE_GEN;
982 * DPDK sets promiscuous mode on just after this call assuming
983 * it can not fail ...
985 ret = nfp_net_reconfig(hw, new_ctrl, update);
995 nfp_net_promisc_disable(struct rte_eth_dev *dev)
997 uint32_t new_ctrl, update = 0;
998 struct nfp_net_hw *hw;
1001 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1003 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
1004 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
1008 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
1009 update = NFP_NET_CFG_UPDATE_GEN;
1012 * DPDK sets promiscuous mode off just before this call
1013 * assuming it can not fail ...
1015 ret = nfp_net_reconfig(hw, new_ctrl, update);
1019 hw->ctrl = new_ctrl;
1025 * return 0 means link status changed, -1 means not changed
1027 * Wait to complete is needed as it can take up to 9 seconds to get the Link
1031 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1033 struct nfp_net_hw *hw;
1034 struct rte_eth_link link;
1035 uint32_t nn_link_status;
1038 static const uint32_t ls_to_ethtool[] = {
1039 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
1040 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
1041 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
1042 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
1043 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
1044 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
1045 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
1046 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
1049 PMD_DRV_LOG(DEBUG, "Link update");
1051 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1053 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1055 memset(&link, 0, sizeof(struct rte_eth_link));
1057 if (nn_link_status & NFP_NET_CFG_STS_LINK)
1058 link.link_status = ETH_LINK_UP;
1060 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1062 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1063 NFP_NET_CFG_STS_LINK_RATE_MASK;
1065 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1066 link.link_speed = ETH_SPEED_NUM_NONE;
1068 link.link_speed = ls_to_ethtool[nn_link_status];
1070 ret = rte_eth_linkstatus_set(dev, &link);
1072 if (link.link_status)
1073 PMD_DRV_LOG(INFO, "NIC Link is Up");
1075 PMD_DRV_LOG(INFO, "NIC Link is Down");
1081 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1084 struct nfp_net_hw *hw;
1085 struct rte_eth_stats nfp_dev_stats;
1087 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1091 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1093 /* reading per RX ring stats */
1094 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1095 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1098 nfp_dev_stats.q_ipackets[i] =
1099 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1101 nfp_dev_stats.q_ipackets[i] -=
1102 hw->eth_stats_base.q_ipackets[i];
1104 nfp_dev_stats.q_ibytes[i] =
1105 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1107 nfp_dev_stats.q_ibytes[i] -=
1108 hw->eth_stats_base.q_ibytes[i];
1111 /* reading per TX ring stats */
1112 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1113 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1116 nfp_dev_stats.q_opackets[i] =
1117 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1119 nfp_dev_stats.q_opackets[i] -=
1120 hw->eth_stats_base.q_opackets[i];
1122 nfp_dev_stats.q_obytes[i] =
1123 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1125 nfp_dev_stats.q_obytes[i] -=
1126 hw->eth_stats_base.q_obytes[i];
1129 nfp_dev_stats.ipackets =
1130 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1132 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1134 nfp_dev_stats.ibytes =
1135 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1137 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1139 nfp_dev_stats.opackets =
1140 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1142 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1144 nfp_dev_stats.obytes =
1145 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1147 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1149 /* reading general device stats */
1150 nfp_dev_stats.ierrors =
1151 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1153 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1155 nfp_dev_stats.oerrors =
1156 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1158 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1160 /* RX ring mbuf allocation failures */
1161 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1163 nfp_dev_stats.imissed =
1164 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1166 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1169 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1176 nfp_net_stats_reset(struct rte_eth_dev *dev)
1179 struct nfp_net_hw *hw;
1181 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1184 * hw->eth_stats_base records the per counter starting point.
1185 * Lets update it now
1188 /* reading per RX ring stats */
1189 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1190 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1193 hw->eth_stats_base.q_ipackets[i] =
1194 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1196 hw->eth_stats_base.q_ibytes[i] =
1197 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1200 /* reading per TX ring stats */
1201 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1202 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1205 hw->eth_stats_base.q_opackets[i] =
1206 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1208 hw->eth_stats_base.q_obytes[i] =
1209 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1212 hw->eth_stats_base.ipackets =
1213 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1215 hw->eth_stats_base.ibytes =
1216 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1218 hw->eth_stats_base.opackets =
1219 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1221 hw->eth_stats_base.obytes =
1222 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1224 /* reading general device stats */
1225 hw->eth_stats_base.ierrors =
1226 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1228 hw->eth_stats_base.oerrors =
1229 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1231 /* RX ring mbuf allocation failures */
1232 dev->data->rx_mbuf_alloc_failed = 0;
1234 hw->eth_stats_base.imissed =
1235 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1241 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1243 struct nfp_net_hw *hw;
1245 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1247 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1248 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1249 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1250 dev_info->max_rx_pktlen = hw->max_mtu;
1251 /* Next should change when PF support is implemented */
1252 dev_info->max_mac_addrs = 1;
1254 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1255 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1257 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1258 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1259 DEV_RX_OFFLOAD_UDP_CKSUM |
1260 DEV_RX_OFFLOAD_TCP_CKSUM;
1262 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1263 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1265 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1266 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1267 DEV_TX_OFFLOAD_UDP_CKSUM |
1268 DEV_TX_OFFLOAD_TCP_CKSUM;
1270 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1271 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1273 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1274 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1276 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1278 .pthresh = DEFAULT_RX_PTHRESH,
1279 .hthresh = DEFAULT_RX_HTHRESH,
1280 .wthresh = DEFAULT_RX_WTHRESH,
1282 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1286 dev_info->default_txconf = (struct rte_eth_txconf) {
1288 .pthresh = DEFAULT_TX_PTHRESH,
1289 .hthresh = DEFAULT_TX_HTHRESH,
1290 .wthresh = DEFAULT_TX_WTHRESH,
1292 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1293 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1296 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1297 .nb_max = NFP_NET_MAX_RX_DESC,
1298 .nb_min = NFP_NET_MIN_RX_DESC,
1299 .nb_align = NFP_ALIGN_RING_DESC,
1302 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1303 .nb_max = NFP_NET_MAX_TX_DESC,
1304 .nb_min = NFP_NET_MIN_TX_DESC,
1305 .nb_align = NFP_ALIGN_RING_DESC,
1306 .nb_seg_max = NFP_TX_MAX_SEG,
1307 .nb_mtu_seg_max = NFP_TX_MAX_MTU_SEG,
1310 /* All NFP devices support jumbo frames */
1311 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1313 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
1314 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_RSS_HASH;
1316 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1317 ETH_RSS_NONFRAG_IPV4_TCP |
1318 ETH_RSS_NONFRAG_IPV4_UDP |
1320 ETH_RSS_NONFRAG_IPV6_TCP |
1321 ETH_RSS_NONFRAG_IPV6_UDP;
1323 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1324 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1327 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1328 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1329 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1334 static const uint32_t *
1335 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1337 static const uint32_t ptypes[] = {
1338 /* refers to nfp_net_set_hash() */
1339 RTE_PTYPE_INNER_L3_IPV4,
1340 RTE_PTYPE_INNER_L3_IPV6,
1341 RTE_PTYPE_INNER_L3_IPV6_EXT,
1342 RTE_PTYPE_INNER_L4_MASK,
1346 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1352 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1354 struct nfp_net_rxq *rxq;
1355 struct nfp_net_rx_desc *rxds;
1359 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1366 * Other PMDs are just checking the DD bit in intervals of 4
1367 * descriptors and counting all four if the first has the DD
1368 * bit on. Of course, this is not accurate but can be good for
1369 * performance. But ideally that should be done in descriptors
1370 * chunks belonging to the same cache line
1373 while (count < rxq->rx_count) {
1374 rxds = &rxq->rxds[idx];
1375 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1382 if ((idx) == rxq->rx_count)
1390 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1392 struct rte_pci_device *pci_dev;
1393 struct nfp_net_hw *hw;
1396 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1399 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1402 /* Make sure all updates are written before un-masking */
1404 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1405 NFP_NET_CFG_ICR_UNMASKED);
1410 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1412 struct rte_pci_device *pci_dev;
1413 struct nfp_net_hw *hw;
1416 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1419 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1422 /* Make sure all updates are written before un-masking */
1424 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1429 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1431 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1432 struct rte_eth_link link;
1434 rte_eth_linkstatus_get(dev, &link);
1435 if (link.link_status)
1436 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1437 dev->data->port_id, link.link_speed,
1438 link.link_duplex == ETH_LINK_FULL_DUPLEX
1439 ? "full-duplex" : "half-duplex");
1441 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1442 dev->data->port_id);
1444 PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
1445 pci_dev->addr.domain, pci_dev->addr.bus,
1446 pci_dev->addr.devid, pci_dev->addr.function);
1449 /* Interrupt configuration and handling */
1452 * nfp_net_irq_unmask - Unmask an interrupt
1454 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1455 * clear the ICR for the entry.
1458 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1460 struct nfp_net_hw *hw;
1461 struct rte_pci_device *pci_dev;
1463 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1464 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1466 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1467 /* If MSI-X auto-masking is used, clear the entry */
1469 rte_intr_ack(&pci_dev->intr_handle);
1471 /* Make sure all updates are written before un-masking */
1473 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1474 NFP_NET_CFG_ICR_UNMASKED);
1479 nfp_net_dev_interrupt_handler(void *param)
1482 struct rte_eth_link link;
1483 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1485 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1487 rte_eth_linkstatus_get(dev, &link);
1489 nfp_net_link_update(dev, 0);
1492 if (!link.link_status) {
1493 /* handle it 1 sec later, wait it being stable */
1494 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1495 /* likely to down */
1497 /* handle it 4 sec later, wait it being stable */
1498 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1501 if (rte_eal_alarm_set(timeout * 1000,
1502 nfp_net_dev_interrupt_delayed_handler,
1504 PMD_INIT_LOG(ERR, "Error setting alarm");
1506 nfp_net_irq_unmask(dev);
1511 * Interrupt handler which shall be registered for alarm callback for delayed
1512 * handling specific interrupt to wait for the stable nic state. As the NIC
1513 * interrupt state is not stable for nfp after link is just down, it needs
1514 * to wait 4 seconds to get the stable status.
1516 * @param handle Pointer to interrupt handle.
1517 * @param param The address of parameter (struct rte_eth_dev *)
1522 nfp_net_dev_interrupt_delayed_handler(void *param)
1524 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1526 nfp_net_link_update(dev, 0);
1527 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1529 nfp_net_dev_link_status_print(dev);
1532 nfp_net_irq_unmask(dev);
1536 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1538 struct nfp_net_hw *hw;
1540 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1542 /* check that mtu is within the allowed range */
1543 if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1546 /* mtu setting is forbidden if port is started */
1547 if (dev->data->dev_started) {
1548 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1549 dev->data->port_id);
1553 /* switch to jumbo mode if needed */
1554 if ((uint32_t)mtu > RTE_ETHER_MTU)
1555 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1557 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1559 /* update max frame size */
1560 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1562 /* writing to configuration space */
1563 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1571 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1572 uint16_t queue_idx, uint16_t nb_desc,
1573 unsigned int socket_id,
1574 const struct rte_eth_rxconf *rx_conf,
1575 struct rte_mempool *mp)
1577 const struct rte_memzone *tz;
1578 struct nfp_net_rxq *rxq;
1579 struct nfp_net_hw *hw;
1580 uint32_t rx_desc_sz;
1582 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584 PMD_INIT_FUNC_TRACE();
1586 /* Validating number of descriptors */
1587 rx_desc_sz = nb_desc * sizeof(struct nfp_net_rx_desc);
1588 if (rx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1589 nb_desc > NFP_NET_MAX_RX_DESC ||
1590 nb_desc < NFP_NET_MIN_RX_DESC) {
1591 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1596 * Free memory prior to re-allocation if needed. This is the case after
1597 * calling nfp_net_stop
1599 if (dev->data->rx_queues[queue_idx]) {
1600 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1601 dev->data->rx_queues[queue_idx] = NULL;
1604 /* Allocating rx queue data structure */
1605 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1606 RTE_CACHE_LINE_SIZE, socket_id);
1610 /* Hw queues mapping based on firmware configuration */
1611 rxq->qidx = queue_idx;
1612 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1613 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1614 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1615 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1618 * Tracking mbuf size for detecting a potential mbuf overflow due to
1622 rxq->mbuf_size = rxq->mem_pool->elt_size;
1623 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1624 hw->flbufsz = rxq->mbuf_size;
1626 rxq->rx_count = nb_desc;
1627 rxq->port_id = dev->data->port_id;
1628 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1629 rxq->drop_en = rx_conf->rx_drop_en;
1632 * Allocate RX ring hardware descriptors. A memzone large enough to
1633 * handle the maximum ring size is allocated in order to allow for
1634 * resizing in later calls to the queue setup function.
1636 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1637 sizeof(struct nfp_net_rx_desc) *
1638 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1642 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1643 nfp_net_rx_queue_release(rxq);
1647 /* Saving physical and virtual addresses for the RX ring */
1648 rxq->dma = (uint64_t)tz->iova;
1649 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1651 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1652 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1653 sizeof(*rxq->rxbufs) * nb_desc,
1654 RTE_CACHE_LINE_SIZE, socket_id);
1655 if (rxq->rxbufs == NULL) {
1656 nfp_net_rx_queue_release(rxq);
1660 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1661 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1663 nfp_net_reset_rx_queue(rxq);
1665 dev->data->rx_queues[queue_idx] = rxq;
1669 * Telling the HW about the physical address of the RX ring and number
1670 * of descriptors in log2 format
1672 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1673 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1679 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1681 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1685 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1688 for (i = 0; i < rxq->rx_count; i++) {
1689 struct nfp_net_rx_desc *rxd;
1690 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1693 PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1694 (unsigned)rxq->qidx);
1698 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1700 rxd = &rxq->rxds[i];
1702 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1703 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1705 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1708 /* Make sure all writes are flushed before telling the hardware */
1711 /* Not advertising the whole ring as the firmware gets confused if so */
1712 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1715 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1721 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1722 uint16_t nb_desc, unsigned int socket_id,
1723 const struct rte_eth_txconf *tx_conf)
1725 const struct rte_memzone *tz;
1726 struct nfp_net_txq *txq;
1727 uint16_t tx_free_thresh;
1728 struct nfp_net_hw *hw;
1729 uint32_t tx_desc_sz;
1731 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1733 PMD_INIT_FUNC_TRACE();
1735 /* Validating number of descriptors */
1736 tx_desc_sz = nb_desc * sizeof(struct nfp_net_tx_desc);
1737 if (tx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1738 nb_desc > NFP_NET_MAX_TX_DESC ||
1739 nb_desc < NFP_NET_MIN_TX_DESC) {
1740 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1744 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1745 tx_conf->tx_free_thresh :
1746 DEFAULT_TX_FREE_THRESH);
1748 if (tx_free_thresh > (nb_desc)) {
1750 "tx_free_thresh must be less than the number of TX "
1751 "descriptors. (tx_free_thresh=%u port=%d "
1752 "queue=%d)", (unsigned int)tx_free_thresh,
1753 dev->data->port_id, (int)queue_idx);
1758 * Free memory prior to re-allocation if needed. This is the case after
1759 * calling nfp_net_stop
1761 if (dev->data->tx_queues[queue_idx]) {
1762 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1764 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1765 dev->data->tx_queues[queue_idx] = NULL;
1768 /* Allocating tx queue data structure */
1769 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1770 RTE_CACHE_LINE_SIZE, socket_id);
1772 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1777 * Allocate TX ring hardware descriptors. A memzone large enough to
1778 * handle the maximum ring size is allocated in order to allow for
1779 * resizing in later calls to the queue setup function.
1781 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1782 sizeof(struct nfp_net_tx_desc) *
1783 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1786 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1787 nfp_net_tx_queue_release(txq);
1791 txq->tx_count = nb_desc;
1792 txq->tx_free_thresh = tx_free_thresh;
1793 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1794 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1795 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1797 /* queue mapping based on firmware configuration */
1798 txq->qidx = queue_idx;
1799 txq->tx_qcidx = queue_idx * hw->stride_tx;
1800 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1802 txq->port_id = dev->data->port_id;
1804 /* Saving physical and virtual addresses for the TX ring */
1805 txq->dma = (uint64_t)tz->iova;
1806 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1808 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1809 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1810 sizeof(*txq->txbufs) * nb_desc,
1811 RTE_CACHE_LINE_SIZE, socket_id);
1812 if (txq->txbufs == NULL) {
1813 nfp_net_tx_queue_release(txq);
1816 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1817 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1819 nfp_net_reset_tx_queue(txq);
1821 dev->data->tx_queues[queue_idx] = txq;
1825 * Telling the HW about the physical address of the TX ring and number
1826 * of descriptors in log2 format
1828 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1829 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1834 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1836 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1837 struct rte_mbuf *mb)
1840 struct nfp_net_hw *hw = txq->hw;
1842 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1845 ol_flags = mb->ol_flags;
1847 if (!(ol_flags & PKT_TX_TCP_SEG))
1850 txd->l3_offset = mb->l2_len;
1851 txd->l4_offset = mb->l2_len + mb->l3_len;
1852 txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1853 txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1854 txd->flags = PCIE_DESC_TX_LSO;
1861 txd->lso_hdrlen = 0;
1865 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1867 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1868 struct rte_mbuf *mb)
1871 struct nfp_net_hw *hw = txq->hw;
1873 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1876 ol_flags = mb->ol_flags;
1878 /* IPv6 does not need checksum */
1879 if (ol_flags & PKT_TX_IP_CKSUM)
1880 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1882 switch (ol_flags & PKT_TX_L4_MASK) {
1883 case PKT_TX_UDP_CKSUM:
1884 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1886 case PKT_TX_TCP_CKSUM:
1887 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1891 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1892 txd->flags |= PCIE_DESC_TX_CSUM;
1895 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1897 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1898 struct rte_mbuf *mb)
1900 struct nfp_net_hw *hw = rxq->hw;
1902 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1905 /* If IPv4 and IP checksum error, fail */
1906 if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1907 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1908 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1910 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1912 /* If neither UDP nor TCP return */
1913 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1914 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1917 if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1918 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1920 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1923 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1924 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1926 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1929 * nfp_net_set_hash - Set mbuf hash data
1931 * The RSS hash and hash-type are pre-pended to the packet data.
1932 * Extract and decode it and set the mbuf fields.
1935 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1936 struct rte_mbuf *mbuf)
1938 struct nfp_net_hw *hw = rxq->hw;
1939 uint8_t *meta_offset;
1942 uint32_t hash_type = 0;
1944 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1947 /* this is true for new firmwares */
1948 if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1949 (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1950 NFP_DESC_META_LEN(rxd))) {
1953 * <---- 32 bit ----->
1958 * ====================
1961 * Field type word contains up to 8 4bit field types
1962 * A 4bit field type refers to a data field word
1963 * A data field word can have several 4bit field types
1965 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1966 meta_offset -= NFP_DESC_META_LEN(rxd);
1967 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1969 /* NFP PMD just supports metadata for hashing */
1970 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1971 case NFP_NET_META_HASH:
1972 /* next field type is about the hash type */
1973 meta_info >>= NFP_NET_META_FIELD_SIZE;
1974 /* hash value is in the data field */
1975 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1976 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1979 /* Unsupported metadata can be a performance issue */
1983 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1986 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1987 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1990 mbuf->hash.rss = hash;
1991 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1993 switch (hash_type) {
1994 case NFP_NET_RSS_IPV4:
1995 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1997 case NFP_NET_RSS_IPV6:
1998 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
2000 case NFP_NET_RSS_IPV6_EX:
2001 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2003 case NFP_NET_RSS_IPV4_TCP:
2004 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2006 case NFP_NET_RSS_IPV6_TCP:
2007 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2009 case NFP_NET_RSS_IPV4_UDP:
2010 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2012 case NFP_NET_RSS_IPV6_UDP:
2013 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2016 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
2021 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
2023 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
2026 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
2031 * There are some decisions to take:
2032 * 1) How to check DD RX descriptors bit
2033 * 2) How and when to allocate new mbufs
2035 * Current implementation checks just one single DD bit each loop. As each
2036 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
2037 * a single cache line instead. Tests with this change have not shown any
2038 * performance improvement but it requires further investigation. For example,
2039 * depending on which descriptor is next, the number of descriptors could be
2040 * less than 8 for just checking those in the same cache line. This implies
2041 * extra work which could be counterproductive by itself. Indeed, last firmware
2042 * changes are just doing this: writing several descriptors with the DD bit
2043 * for saving PCIe bandwidth and DMA operations from the NFP.
2045 * Mbuf allocation is done when a new packet is received. Then the descriptor
2046 * is automatically linked with the new mbuf and the old one is given to the
2047 * user. The main drawback with this design is mbuf allocation is heavier than
2048 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2049 * cache point of view it does not seem allocating the mbuf early on as we are
2050 * doing now have any benefit at all. Again, tests with this change have not
2051 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2052 * so looking at the implications of this type of allocation should be studied
2057 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2059 struct nfp_net_rxq *rxq;
2060 struct nfp_net_rx_desc *rxds;
2061 struct nfp_net_rx_buff *rxb;
2062 struct nfp_net_hw *hw;
2063 struct rte_mbuf *mb;
2064 struct rte_mbuf *new_mb;
2070 if (unlikely(rxq == NULL)) {
2072 * DPDK just checks the queue is lower than max queues
2073 * enabled. But the queue needs to be configured
2075 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2083 while (avail < nb_pkts) {
2084 rxb = &rxq->rxbufs[rxq->rd_p];
2085 if (unlikely(rxb == NULL)) {
2086 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2090 rxds = &rxq->rxds[rxq->rd_p];
2091 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2095 * Memory barrier to ensure that we won't do other
2096 * reads before the DD bit.
2101 * We got a packet. Let's alloc a new mbuf for refilling the
2102 * free descriptor ring as soon as possible
2104 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2105 if (unlikely(new_mb == NULL)) {
2106 RTE_LOG_DP(DEBUG, PMD,
2107 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2108 rxq->port_id, (unsigned int)rxq->qidx);
2109 nfp_net_mbuf_alloc_failed(rxq);
2116 * Grab the mbuf and refill the descriptor with the
2117 * previously allocated mbuf
2122 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2123 rxds->rxd.data_len, rxq->mbuf_size);
2125 /* Size of this segment */
2126 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2127 /* Size of the whole packet. We just support 1 segment */
2128 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2130 if (unlikely((mb->data_len + hw->rx_offset) >
2133 * This should not happen and the user has the
2134 * responsibility of avoiding it. But we have
2135 * to give some info about the error
2137 RTE_LOG_DP(ERR, PMD,
2138 "mbuf overflow likely due to the RX offset.\n"
2139 "\t\tYour mbuf size should have extra space for"
2140 " RX offset=%u bytes.\n"
2141 "\t\tCurrently you just have %u bytes available"
2142 " but the received packet is %u bytes long",
2144 rxq->mbuf_size - hw->rx_offset,
2149 /* Filling the received mbuf with packet info */
2151 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2153 mb->data_off = RTE_PKTMBUF_HEADROOM +
2154 NFP_DESC_META_LEN(rxds);
2156 /* No scatter mode supported */
2160 mb->port = rxq->port_id;
2162 /* Checking the RSS flag */
2163 nfp_net_set_hash(rxq, rxds, mb);
2165 /* Checking the checksum flag */
2166 nfp_net_rx_cksum(rxq, rxds, mb);
2168 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2169 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2170 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2171 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2174 /* Adding the mbuf to the mbuf array passed by the app */
2175 rx_pkts[avail++] = mb;
2177 /* Now resetting and updating the descriptor */
2180 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2182 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2183 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2186 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2193 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received",
2194 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2196 nb_hold += rxq->nb_rx_hold;
2199 * FL descriptors needs to be written before incrementing the
2200 * FL queue WR pointer
2203 if (nb_hold > rxq->rx_free_thresh) {
2204 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2205 rxq->port_id, (unsigned int)rxq->qidx,
2206 (unsigned)nb_hold, (unsigned)avail);
2207 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2210 rxq->nb_rx_hold = nb_hold;
2216 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2218 * @txq: TX queue to work with
2219 * Returns number of descriptors freed
2222 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2227 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2228 " status", txq->qidx);
2230 /* Work out how many packets have been sent */
2231 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2233 if (qcp_rd_p == txq->rd_p) {
2234 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2235 "packets (%u, %u)", txq->qidx,
2236 qcp_rd_p, txq->rd_p);
2240 if (qcp_rd_p > txq->rd_p)
2241 todo = qcp_rd_p - txq->rd_p;
2243 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2245 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2246 qcp_rd_p, txq->rd_p, txq->rd_p);
2252 if (unlikely(txq->rd_p >= txq->tx_count))
2253 txq->rd_p -= txq->tx_count;
2258 /* Leaving always free descriptors for avoiding wrapping confusion */
2260 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2262 if (txq->wr_p >= txq->rd_p)
2263 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2265 return txq->rd_p - txq->wr_p - 8;
2269 * nfp_net_txq_full - Check if the TX queue free descriptors
2270 * is below tx_free_threshold
2272 * @txq: TX queue to check
2274 * This function uses the host copy* of read/write pointers
2277 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2279 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2283 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2285 struct nfp_net_txq *txq;
2286 struct nfp_net_hw *hw;
2287 struct nfp_net_tx_desc *txds, txd;
2288 struct rte_mbuf *pkt;
2290 int pkt_size, dma_size;
2291 uint16_t free_descs, issued_descs;
2292 struct rte_mbuf **lmbuf;
2297 txds = &txq->txds[txq->wr_p];
2299 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2300 txq->qidx, txq->wr_p, nb_pkts);
2302 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2303 nfp_net_tx_free_bufs(txq);
2305 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2306 if (unlikely(free_descs == 0))
2313 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2314 txq->qidx, nb_pkts);
2315 /* Sending packets */
2316 while ((i < nb_pkts) && free_descs) {
2317 /* Grabbing the mbuf linked to the current descriptor */
2318 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2319 /* Warming the cache for releasing the mbuf later on */
2320 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2322 pkt = *(tx_pkts + i);
2324 if (unlikely((pkt->nb_segs > 1) &&
2325 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2326 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2327 rte_panic("Multisegment packet unsupported\n");
2330 /* Checking if we have enough descriptors */
2331 if (unlikely(pkt->nb_segs > free_descs))
2335 * Checksum and VLAN flags just in the first descriptor for a
2336 * multisegment packet, but TSO info needs to be in all of them.
2338 txd.data_len = pkt->pkt_len;
2339 nfp_net_tx_tso(txq, &txd, pkt);
2340 nfp_net_tx_cksum(txq, &txd, pkt);
2342 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2343 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2344 txd.flags |= PCIE_DESC_TX_VLAN;
2345 txd.vlan = pkt->vlan_tci;
2349 * mbuf data_len is the data in one segment and pkt_len data
2350 * in the whole packet. When the packet is just one segment,
2351 * then data_len = pkt_len
2353 pkt_size = pkt->pkt_len;
2356 /* Copying TSO, VLAN and cksum info */
2359 /* Releasing mbuf used by this descriptor previously*/
2361 rte_pktmbuf_free_seg(*lmbuf);
2364 * Linking mbuf with descriptor for being released
2365 * next time descriptor is used
2369 dma_size = pkt->data_len;
2370 dma_addr = rte_mbuf_data_iova(pkt);
2371 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2372 "%" PRIx64 "", dma_addr);
2374 /* Filling descriptors fields */
2375 txds->dma_len = dma_size;
2376 txds->data_len = txd.data_len;
2377 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2378 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2379 ASSERT(free_descs > 0);
2383 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2386 pkt_size -= dma_size;
2389 * Making the EOP, packets with just one segment
2392 if (likely(!pkt_size))
2393 txds->offset_eop = PCIE_DESC_TX_EOP;
2395 txds->offset_eop = 0;
2398 /* Referencing next free TX descriptor */
2399 txds = &txq->txds[txq->wr_p];
2400 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2407 /* Increment write pointers. Force memory write before we let HW know */
2409 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2415 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2417 uint32_t new_ctrl, update;
2418 struct nfp_net_hw *hw;
2421 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2424 /* Enable vlan strip if it is not configured yet */
2425 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2426 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2427 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2429 /* Disable vlan strip just if it is configured */
2430 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2431 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2432 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2437 update = NFP_NET_CFG_UPDATE_GEN;
2439 ret = nfp_net_reconfig(hw, new_ctrl, update);
2441 hw->ctrl = new_ctrl;
2447 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2448 struct rte_eth_rss_reta_entry64 *reta_conf,
2451 uint32_t reta, mask;
2454 struct nfp_net_hw *hw =
2455 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2458 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2459 "(%d) doesn't match the number hardware can supported "
2460 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2465 * Update Redirection Table. There are 128 8bit-entries which can be
2466 * manage as 32 32bit-entries
2468 for (i = 0; i < reta_size; i += 4) {
2469 /* Handling 4 RSS entries per loop */
2470 idx = i / RTE_RETA_GROUP_SIZE;
2471 shift = i % RTE_RETA_GROUP_SIZE;
2472 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2478 /* If all 4 entries were set, don't need read RETA register */
2480 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2482 for (j = 0; j < 4; j++) {
2483 if (!(mask & (0x1 << j)))
2486 /* Clearing the entry bits */
2487 reta &= ~(0xFF << (8 * j));
2488 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2490 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2496 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2498 nfp_net_reta_update(struct rte_eth_dev *dev,
2499 struct rte_eth_rss_reta_entry64 *reta_conf,
2502 struct nfp_net_hw *hw =
2503 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2507 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2510 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2514 update = NFP_NET_CFG_UPDATE_RSS;
2516 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2522 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2524 nfp_net_reta_query(struct rte_eth_dev *dev,
2525 struct rte_eth_rss_reta_entry64 *reta_conf,
2531 struct nfp_net_hw *hw;
2533 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2538 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2539 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2540 "(%d) doesn't match the number hardware can supported "
2541 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2546 * Reading Redirection Table. There are 128 8bit-entries which can be
2547 * manage as 32 32bit-entries
2549 for (i = 0; i < reta_size; i += 4) {
2550 /* Handling 4 RSS entries per loop */
2551 idx = i / RTE_RETA_GROUP_SIZE;
2552 shift = i % RTE_RETA_GROUP_SIZE;
2553 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2558 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2560 for (j = 0; j < 4; j++) {
2561 if (!(mask & (0x1 << j)))
2563 reta_conf[idx].reta[shift + j] =
2564 (uint8_t)((reta >> (8 * j)) & 0xF);
2571 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2572 struct rte_eth_rss_conf *rss_conf)
2574 struct nfp_net_hw *hw;
2576 uint32_t cfg_rss_ctrl = 0;
2580 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2582 /* Writing the key byte a byte */
2583 for (i = 0; i < rss_conf->rss_key_len; i++) {
2584 memcpy(&key, &rss_conf->rss_key[i], 1);
2585 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2588 rss_hf = rss_conf->rss_hf;
2590 if (rss_hf & ETH_RSS_IPV4)
2591 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2593 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2594 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2596 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2597 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2599 if (rss_hf & ETH_RSS_IPV6)
2600 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2602 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2603 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2605 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2606 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2608 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2609 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2611 /* configuring where to apply the RSS hash */
2612 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2614 /* Writing the key size */
2615 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2621 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2622 struct rte_eth_rss_conf *rss_conf)
2626 struct nfp_net_hw *hw;
2628 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2630 rss_hf = rss_conf->rss_hf;
2632 /* Checking if RSS is enabled */
2633 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2634 if (rss_hf != 0) { /* Enable RSS? */
2635 PMD_DRV_LOG(ERR, "RSS unsupported");
2638 return 0; /* Nothing to do */
2641 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2642 PMD_DRV_LOG(ERR, "hash key too long");
2646 nfp_net_rss_hash_write(dev, rss_conf);
2648 update = NFP_NET_CFG_UPDATE_RSS;
2650 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2657 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2658 struct rte_eth_rss_conf *rss_conf)
2661 uint32_t cfg_rss_ctrl;
2664 struct nfp_net_hw *hw;
2666 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2671 rss_hf = rss_conf->rss_hf;
2672 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2674 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2675 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2677 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2678 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2680 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2681 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2683 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2684 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2686 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2687 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2689 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2690 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2692 /* Propagate current RSS hash functions to caller */
2693 rss_conf->rss_hf = rss_hf;
2695 /* Reading the key size */
2696 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2698 /* Reading the key byte a byte */
2699 for (i = 0; i < rss_conf->rss_key_len; i++) {
2700 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2701 memcpy(&rss_conf->rss_key[i], &key, 1);
2708 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2710 struct rte_eth_conf *dev_conf;
2711 struct rte_eth_rss_conf rss_conf;
2712 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2713 uint16_t rx_queues = dev->data->nb_rx_queues;
2717 PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2720 nfp_reta_conf[0].mask = ~0x0;
2721 nfp_reta_conf[1].mask = ~0x0;
2724 for (i = 0; i < 0x40; i += 8) {
2725 for (j = i; j < (i + 8); j++) {
2726 nfp_reta_conf[0].reta[j] = queue;
2727 nfp_reta_conf[1].reta[j] = queue++;
2731 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2735 dev_conf = &dev->data->dev_conf;
2737 PMD_DRV_LOG(INFO, "wrong rss conf");
2740 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2742 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2748 /* Initialise and register driver with DPDK Application */
2749 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2750 .dev_configure = nfp_net_configure,
2751 .dev_start = nfp_net_start,
2752 .dev_stop = nfp_net_stop,
2753 .dev_set_link_up = nfp_net_set_link_up,
2754 .dev_set_link_down = nfp_net_set_link_down,
2755 .dev_close = nfp_net_close,
2756 .promiscuous_enable = nfp_net_promisc_enable,
2757 .promiscuous_disable = nfp_net_promisc_disable,
2758 .link_update = nfp_net_link_update,
2759 .stats_get = nfp_net_stats_get,
2760 .stats_reset = nfp_net_stats_reset,
2761 .dev_infos_get = nfp_net_infos_get,
2762 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2763 .mtu_set = nfp_net_dev_mtu_set,
2764 .mac_addr_set = nfp_set_mac_addr,
2765 .vlan_offload_set = nfp_net_vlan_offload_set,
2766 .reta_update = nfp_net_reta_update,
2767 .reta_query = nfp_net_reta_query,
2768 .rss_hash_update = nfp_net_rss_hash_update,
2769 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2770 .rx_queue_setup = nfp_net_rx_queue_setup,
2771 .rx_queue_release = nfp_net_rx_queue_release,
2772 .tx_queue_setup = nfp_net_tx_queue_setup,
2773 .tx_queue_release = nfp_net_tx_queue_release,
2774 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2775 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2780 nfp_net_init(struct rte_eth_dev *eth_dev)
2782 struct rte_pci_device *pci_dev;
2783 struct nfp_pf_dev *pf_dev;
2784 struct nfp_net_hw *hw;
2786 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2792 PMD_INIT_FUNC_TRACE();
2794 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2796 /* Use backpointer here to the PF of this eth_dev */
2797 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(eth_dev->data->dev_private);
2799 /* NFP can not handle DMA addresses requiring more than 40 bits */
2800 if (rte_mem_check_dma_mask(40)) {
2801 RTE_LOG(ERR, PMD, "device %s can not be used:",
2802 pci_dev->device.name);
2803 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2807 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2808 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2809 port = ((struct nfp_net_hw *)eth_dev->data->dev_private)->idx;
2810 if (port < 0 || port > 7) {
2811 PMD_DRV_LOG(ERR, "Port value is wrong");
2815 /* Use PF array of physical ports to get pointer to
2816 * this specific port
2818 hw = pf_dev->ports[port];
2820 PMD_INIT_LOG(DEBUG, "Working with physical port number: %d, "
2821 "NFP internal port number: %d",
2825 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2828 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2829 eth_dev->rx_queue_count = nfp_net_rx_queue_count;
2830 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2831 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2833 /* For secondary processes, the primary has done all the work */
2834 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2837 rte_eth_copy_pci_info(eth_dev, pci_dev);
2839 hw->device_id = pci_dev->id.device_id;
2840 hw->vendor_id = pci_dev->id.vendor_id;
2841 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2842 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2844 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2845 pci_dev->id.vendor_id, pci_dev->id.device_id,
2846 pci_dev->addr.domain, pci_dev->addr.bus,
2847 pci_dev->addr.devid, pci_dev->addr.function);
2849 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2850 if (hw->ctrl_bar == NULL) {
2852 "hw->ctrl_bar is NULL. BAR0 not configured");
2856 if (hw->is_phyport) {
2858 hw->ctrl_bar = pf_dev->ctrl_bar;
2860 if (!pf_dev->ctrl_bar)
2862 /* Use port offset in pf ctrl_bar for this
2865 hw->ctrl_bar = pf_dev->ctrl_bar +
2866 (port * NFP_PF_CSR_SLICE_SIZE);
2870 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2872 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2873 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2875 /* Work out where in the BAR the queues start. */
2876 switch (pci_dev->id.device_id) {
2877 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2878 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2879 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2880 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2881 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2882 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2883 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2886 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2888 goto dev_err_ctrl_map;
2891 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2892 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2894 if (hw->is_phyport) {
2895 hw->tx_bar = pf_dev->hw_queues + tx_bar_off;
2896 hw->rx_bar = pf_dev->hw_queues + rx_bar_off;
2897 eth_dev->data->dev_private = hw;
2899 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2901 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2905 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2906 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2908 nfp_net_cfg_queue_setup(hw);
2910 /* Get some of the read-only fields from the config BAR */
2911 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2912 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2913 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2914 hw->mtu = RTE_ETHER_MTU;
2916 /* VLAN insertion is incompatible with LSOv2 */
2917 if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2918 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2920 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2921 hw->rx_offset = NFP_NET_RX_OFFSET;
2923 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2925 PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2926 NFD_CFG_MAJOR_VERSION_of(hw->ver),
2927 NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2929 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2930 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2931 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2932 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2933 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2934 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2935 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2936 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2937 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2938 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2939 hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "",
2940 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2941 hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "",
2942 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "",
2943 hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : "");
2947 hw->stride_rx = stride;
2948 hw->stride_tx = stride;
2950 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2951 hw->max_rx_queues, hw->max_tx_queues);
2953 /* Initializing spinlock for reconfigs */
2954 rte_spinlock_init(&hw->reconfig_lock);
2956 /* Allocating memory for mac addr */
2957 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2958 RTE_ETHER_ADDR_LEN, 0);
2959 if (eth_dev->data->mac_addrs == NULL) {
2960 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2962 goto dev_err_queues_map;
2965 if (hw->is_phyport) {
2966 nfp_net_pf_read_mac(pf_dev, port);
2967 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2969 nfp_net_vf_read_mac(hw);
2972 if (!rte_is_valid_assigned_ether_addr(
2973 (struct rte_ether_addr *)&hw->mac_addr)) {
2974 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2976 /* Using random mac addresses for VFs */
2977 rte_eth_random_addr(&hw->mac_addr[0]);
2978 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2981 /* Copying mac address to DPDK eth_dev struct */
2982 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2983 ð_dev->data->mac_addrs[0]);
2985 if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2986 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2988 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2990 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2991 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2992 eth_dev->data->port_id, pci_dev->id.vendor_id,
2993 pci_dev->id.device_id,
2994 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2995 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2997 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2998 /* Registering LSC interrupt handler */
2999 rte_intr_callback_register(&pci_dev->intr_handle,
3000 nfp_net_dev_interrupt_handler,
3002 /* Telling the firmware about the LSC interrupt entry */
3003 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3004 /* Recording current stats counters values */
3005 nfp_net_stats_reset(eth_dev);
3011 nfp_cpp_area_free(hw->hwqueues_area);
3013 nfp_cpp_area_free(hw->ctrl_area);
3018 #define NFP_CPP_MEMIO_BOUNDARY (1 << 20)
3021 * Serving a write request to NFP from host programs. The request
3022 * sends the write size and the CPP target. The bridge makes use
3023 * of CPP interface handler configured by the PMD setup.
3026 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3028 struct nfp_cpp_area *area;
3029 off_t offset, nfp_offset;
3030 uint32_t cpp_id, pos, len;
3031 uint32_t tmpbuf[16];
3032 size_t count, curlen, totlen = 0;
3035 PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3036 sizeof(off_t), sizeof(size_t));
3038 /* Reading the count param */
3039 err = recv(sockfd, &count, sizeof(off_t), 0);
3040 if (err != sizeof(off_t))
3045 /* Reading the offset param */
3046 err = recv(sockfd, &offset, sizeof(off_t), 0);
3047 if (err != sizeof(off_t))
3050 /* Obtain target's CPP ID and offset in target */
3051 cpp_id = (offset >> 40) << 8;
3052 nfp_offset = offset & ((1ull << 40) - 1);
3054 PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3056 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3057 cpp_id, nfp_offset);
3059 /* Adjust length if not aligned */
3060 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3061 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3062 curlen = NFP_CPP_MEMIO_BOUNDARY -
3063 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3067 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3068 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3069 nfp_offset, curlen);
3071 RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3075 /* mapping the target */
3076 err = nfp_cpp_area_acquire(area);
3078 RTE_LOG(ERR, PMD, "area acquire failed\n");
3079 nfp_cpp_area_free(area);
3083 for (pos = 0; pos < curlen; pos += len) {
3085 if (len > sizeof(tmpbuf))
3086 len = sizeof(tmpbuf);
3088 PMD_CPP_LOG(DEBUG, "%s: Receive %u of %zu\n", __func__,
3090 err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3091 if (err != (int)len) {
3093 "%s: error when receiving, %d of %zu\n",
3094 __func__, err, count);
3095 nfp_cpp_area_release(area);
3096 nfp_cpp_area_free(area);
3099 err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3101 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3102 nfp_cpp_area_release(area);
3103 nfp_cpp_area_free(area);
3110 nfp_cpp_area_release(area);
3111 nfp_cpp_area_free(area);
3114 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3115 NFP_CPP_MEMIO_BOUNDARY : count;
3122 * Serving a read request to NFP from host programs. The request
3123 * sends the read size and the CPP target. The bridge makes use
3124 * of CPP interface handler configured by the PMD setup. The read
3125 * data is sent to the requester using the same socket.
3128 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3130 struct nfp_cpp_area *area;
3131 off_t offset, nfp_offset;
3132 uint32_t cpp_id, pos, len;
3133 uint32_t tmpbuf[16];
3134 size_t count, curlen, totlen = 0;
3137 PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3138 sizeof(off_t), sizeof(size_t));
3140 /* Reading the count param */
3141 err = recv(sockfd, &count, sizeof(off_t), 0);
3142 if (err != sizeof(off_t))
3147 /* Reading the offset param */
3148 err = recv(sockfd, &offset, sizeof(off_t), 0);
3149 if (err != sizeof(off_t))
3152 /* Obtain target's CPP ID and offset in target */
3153 cpp_id = (offset >> 40) << 8;
3154 nfp_offset = offset & ((1ull << 40) - 1);
3156 PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3158 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3159 cpp_id, nfp_offset);
3161 /* Adjust length if not aligned */
3162 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3163 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3164 curlen = NFP_CPP_MEMIO_BOUNDARY -
3165 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3169 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3170 nfp_offset, curlen);
3172 RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3176 err = nfp_cpp_area_acquire(area);
3178 RTE_LOG(ERR, PMD, "area acquire failed\n");
3179 nfp_cpp_area_free(area);
3183 for (pos = 0; pos < curlen; pos += len) {
3185 if (len > sizeof(tmpbuf))
3186 len = sizeof(tmpbuf);
3188 err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3190 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3191 nfp_cpp_area_release(area);
3192 nfp_cpp_area_free(area);
3195 PMD_CPP_LOG(DEBUG, "%s: sending %u of %zu\n", __func__,
3198 err = send(sockfd, tmpbuf, len, 0);
3199 if (err != (int)len) {
3201 "%s: error when sending: %d of %zu\n",
3202 __func__, err, count);
3203 nfp_cpp_area_release(area);
3204 nfp_cpp_area_free(area);
3211 nfp_cpp_area_release(area);
3212 nfp_cpp_area_free(area);
3215 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3216 NFP_CPP_MEMIO_BOUNDARY : count;
3221 #define NFP_IOCTL 'n'
3222 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3224 * Serving a ioctl command from host NFP tools. This usually goes to
3225 * a kernel driver char driver but it is not available when the PF is
3226 * bound to the PMD. Currently just one ioctl command is served and it
3227 * does not require any CPP access at all.
3230 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3232 uint32_t cmd, ident_size, tmp;
3235 /* Reading now the IOCTL command */
3236 err = recv(sockfd, &cmd, 4, 0);
3238 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3242 /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3243 if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3244 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3248 err = recv(sockfd, &ident_size, 4, 0);
3250 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3254 tmp = nfp_cpp_model(cpp);
3256 PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3258 err = send(sockfd, &tmp, 4, 0);
3260 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3264 tmp = cpp->interface;
3266 PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3268 err = send(sockfd, &tmp, 4, 0);
3270 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3277 #define NFP_BRIDGE_OP_READ 20
3278 #define NFP_BRIDGE_OP_WRITE 30
3279 #define NFP_BRIDGE_OP_IOCTL 40
3282 * This is the code to be executed by a service core. The CPP bridge interface
3283 * is based on a unix socket and requests usually received by a kernel char
3284 * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3285 * can be executed with a wrapper library and LD_LIBRARY being completely
3286 * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3290 nfp_cpp_bridge_service_func(void *args)
3292 struct sockaddr address;
3293 struct nfp_cpp *cpp = args;
3294 int sockfd, datafd, op, ret;
3296 unlink("/tmp/nfp_cpp");
3297 sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3299 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3304 memset(&address, 0, sizeof(struct sockaddr));
3306 address.sa_family = AF_UNIX;
3307 strcpy(address.sa_data, "/tmp/nfp_cpp");
3309 ret = bind(sockfd, (const struct sockaddr *)&address,
3310 sizeof(struct sockaddr));
3312 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3318 ret = listen(sockfd, 20);
3320 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3327 datafd = accept(sockfd, NULL, NULL);
3329 RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3331 RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3337 ret = recv(datafd, &op, 4, 0);
3339 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3344 PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3346 if (op == NFP_BRIDGE_OP_READ)
3347 nfp_cpp_bridge_serve_read(datafd, cpp);
3349 if (op == NFP_BRIDGE_OP_WRITE)
3350 nfp_cpp_bridge_serve_write(datafd, cpp);
3352 if (op == NFP_BRIDGE_OP_IOCTL)
3353 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3365 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
3368 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3370 struct nfp_cpp *cpp = nsp->cpp;
3376 /* Looking for firmware file in order of priority */
3378 /* First try to find a firmware image specific for this device */
3379 snprintf(serial, sizeof(serial),
3380 "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3381 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3382 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3383 cpp->interface & 0xff);
3385 snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3387 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3388 if (rte_firmware_read(fw_name, &fw_buf, &fsize) == 0)
3391 /* Then try the PCI name */
3392 snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3394 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3395 if (rte_firmware_read(fw_name, &fw_buf, &fsize) == 0)
3398 /* Finally try the card type and media */
3399 snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3400 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3401 if (rte_firmware_read(fw_name, &fw_buf, &fsize) < 0) {
3402 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3407 PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %zu",
3410 PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3411 nfp_nsp_load_fw(nsp, fw_buf, fsize);
3412 PMD_DRV_LOG(INFO, "Done");
3419 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3420 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3422 struct nfp_nsp *nsp;
3423 const char *nfp_fw_model;
3424 char card_desc[100];
3427 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3430 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3432 PMD_DRV_LOG(ERR, "firmware model NOT found");
3436 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3437 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3438 nfp_eth_table->count);
3442 PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3443 nfp_eth_table->count);
3445 PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3447 snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3448 nfp_fw_model, nfp_eth_table->count,
3449 nfp_eth_table->ports[0].speed / 1000);
3451 nsp = nfp_nsp_open(cpp);
3453 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3457 nfp_nsp_device_soft_reset(nsp);
3458 err = nfp_fw_upload(dev, nsp, card_desc);
3464 static int nfp_init_phyports(struct nfp_pf_dev *pf_dev)
3466 struct nfp_net_hw *hw;
3467 struct rte_eth_dev *eth_dev;
3468 struct nfp_eth_table *nfp_eth_table = NULL;
3472 nfp_eth_table = nfp_eth_read_ports(pf_dev->cpp);
3473 if (!nfp_eth_table) {
3474 PMD_INIT_LOG(ERR, "Error reading NFP ethernet table");
3479 /* Loop through all physical ports on PF */
3480 for (i = 0; i < pf_dev->total_phyports; i++) {
3481 const unsigned int numa_node = rte_socket_id();
3482 char port_name[RTE_ETH_NAME_MAX_LEN];
3484 snprintf(port_name, sizeof(port_name), "%s_port%d",
3485 pf_dev->pci_dev->device.name, i);
3487 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3488 eth_dev = rte_eth_dev_attach_secondary(port_name);
3491 "secondary process attach failed, "
3492 "ethdev doesn't exist");
3497 eth_dev->process_private = pf_dev->cpp;
3501 /* First port has already been initialized */
3503 eth_dev = pf_dev->eth_dev;
3504 goto skip_dev_alloc;
3507 /* Allocate a eth_dev for remaining ports */
3508 eth_dev = rte_eth_dev_allocate(port_name);
3514 /* Allocate memory for remaining ports */
3515 eth_dev->data->dev_private =
3516 rte_zmalloc_socket(port_name, sizeof(struct nfp_net_hw),
3517 RTE_CACHE_LINE_SIZE, numa_node);
3518 if (!eth_dev->data->dev_private) {
3520 rte_eth_dev_release_port(eth_dev);
3525 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3527 /* Add this device to the PF's array of physical ports */
3528 pf_dev->ports[i] = hw;
3530 hw->pf_dev = pf_dev;
3531 hw->cpp = pf_dev->cpp;
3532 hw->eth_dev = eth_dev;
3534 hw->nfp_idx = nfp_eth_table->ports[i].index;
3535 hw->is_phyport = true;
3538 eth_dev->device = &pf_dev->pci_dev->device;
3540 /* ctrl/tx/rx BAR mappings and remaining init happens in
3543 ret = nfp_net_init(eth_dev);
3550 rte_eth_dev_probing_finish(eth_dev);
3552 } /* End loop, all ports on this PF */
3554 goto eth_table_cleanup;
3557 for (i = 0; i < pf_dev->total_phyports; i++) {
3558 if (pf_dev->ports[i] && pf_dev->ports[i]->eth_dev) {
3559 struct rte_eth_dev *tmp_dev;
3560 tmp_dev = pf_dev->ports[i]->eth_dev;
3561 rte_eth_dev_release_port(tmp_dev);
3562 pf_dev->ports[i] = NULL;
3566 free(nfp_eth_table);
3571 static int nfp_pf_init(struct rte_eth_dev *eth_dev)
3573 struct rte_pci_device *pci_dev;
3574 struct nfp_net_hw *hw = NULL;
3575 struct nfp_pf_dev *pf_dev = NULL;
3576 struct nfp_cpp *cpp;
3577 struct nfp_hwinfo *hwinfo;
3578 struct nfp_rtsym_table *sym_tbl;
3579 struct nfp_eth_table *nfp_eth_table = NULL;
3580 struct rte_service_spec service;
3581 char name[RTE_ETH_NAME_MAX_LEN];
3586 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3587 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev);
3593 * When device bound to UIO, the device could be used, by mistake,
3594 * by two DPDK apps, and the UIO driver does not avoid it. This
3595 * could lead to a serious problem when configuring the NFP CPP
3596 * interface. Here we avoid this telling to the CPP init code to
3597 * use a lock file if UIO is being used.
3599 if (pci_dev->kdrv == RTE_PCI_KDRV_VFIO)
3600 cpp = nfp_cpp_from_device_name(pci_dev, 0);
3602 cpp = nfp_cpp_from_device_name(pci_dev, 1);
3605 PMD_INIT_LOG(ERR, "A CPP handle can not be obtained");
3610 hwinfo = nfp_hwinfo_read(cpp);
3612 PMD_INIT_LOG(ERR, "Error reading hwinfo table");
3617 nfp_eth_table = nfp_eth_read_ports(cpp);
3618 if (!nfp_eth_table) {
3619 PMD_INIT_LOG(ERR, "Error reading NFP ethernet table");
3621 goto hwinfo_cleanup;
3624 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3625 if (nfp_fw_setup(pci_dev, cpp, nfp_eth_table, hwinfo)) {
3626 PMD_INIT_LOG(ERR, "Error when uploading firmware");
3628 goto eth_table_cleanup;
3632 /* Now the symbol table should be there */
3633 sym_tbl = nfp_rtsym_table_read(cpp);
3635 PMD_INIT_LOG(ERR, "Something is wrong with the firmware"
3638 goto eth_table_cleanup;
3641 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3642 if (total_ports != (int)nfp_eth_table->count) {
3643 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3645 goto sym_tbl_cleanup;
3648 PMD_INIT_LOG(INFO, "Total physical ports: %d", total_ports);
3650 if (total_ports <= 0 || total_ports > 8) {
3651 PMD_INIT_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3653 goto sym_tbl_cleanup;
3655 /* Allocate memory for the PF "device" */
3656 snprintf(name, sizeof(name), "nfp_pf%d", eth_dev->data->port_id);
3657 pf_dev = rte_zmalloc(name, sizeof(*pf_dev), 0);
3660 goto sym_tbl_cleanup;
3663 /* Populate the newly created PF device */
3665 pf_dev->hwinfo = hwinfo;
3666 pf_dev->sym_tbl = sym_tbl;
3667 pf_dev->total_phyports = total_ports;
3669 if (total_ports > 1)
3670 pf_dev->multiport = true;
3672 pf_dev->pci_dev = pci_dev;
3674 /* The first eth_dev is part of the PF struct */
3675 pf_dev->eth_dev = eth_dev;
3677 /* Map the symbol table */
3678 pf_dev->ctrl_bar = nfp_rtsym_map(pf_dev->sym_tbl, "_pf0_net_bar0",
3679 pf_dev->total_phyports * 32768,
3680 &pf_dev->ctrl_area);
3681 if (!pf_dev->ctrl_bar) {
3682 PMD_INIT_LOG(ERR, "nfp_rtsym_map fails for _pf0_net_ctrl_bar");
3687 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", pf_dev->ctrl_bar);
3689 /* configure access to tx/rx vNIC BARs */
3690 pf_dev->hw_queues = nfp_cpp_map_area(pf_dev->cpp, 0, 0,
3692 NFP_QCP_QUEUE_AREA_SZ,
3693 &pf_dev->hwqueues_area);
3694 if (!pf_dev->hw_queues) {
3695 PMD_INIT_LOG(ERR, "nfp_rtsym_map fails for net.qc");
3697 goto ctrl_area_cleanup;
3700 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p", pf_dev->hw_queues);
3702 /* Initialize and prep physical ports now
3703 * This will loop through all physical ports
3705 ret = nfp_init_phyports(pf_dev);
3707 PMD_INIT_LOG(ERR, "Could not create physical ports");
3708 goto hwqueues_cleanup;
3712 * The rte_service needs to be created just once per PMD.
3713 * And the cpp handler needs to be linked to the service.
3714 * Secondary processes will be used for debugging DPDK apps
3715 * when requiring to use the CPP interface for accessing NFP
3716 * components. And the cpp handler for secondary processes is
3717 * available at this point.
3719 memset(&service, 0, sizeof(struct rte_service_spec));
3720 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3721 service.callback = nfp_cpp_bridge_service_func;
3722 service.callback_userdata = (void *)cpp;
3724 if (rte_service_component_register(&service,
3725 &hw->nfp_cpp_service_id))
3726 RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3728 RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3733 nfp_cpp_area_free(pf_dev->hwqueues_area);
3735 nfp_cpp_area_free(pf_dev->ctrl_area);
3741 free(nfp_eth_table);
3748 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3749 struct rte_pci_device *dev)
3751 return rte_eth_dev_pci_generic_probe(dev,
3752 sizeof(struct nfp_net_hw), nfp_pf_init);
3755 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3757 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3758 PCI_DEVICE_ID_NFP4000_PF_NIC)
3761 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3762 PCI_DEVICE_ID_NFP6000_PF_NIC)
3769 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3771 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3772 PCI_DEVICE_ID_NFP6000_VF_NIC)
3779 static int nfp_pci_uninit(struct rte_eth_dev *eth_dev)
3781 struct rte_pci_device *pci_dev;
3784 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3786 if (pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC ||
3787 pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC) {
3788 /* Free up all physical ports under PF */
3789 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3790 rte_eth_dev_close(port_id);
3792 * Ports can be closed and freed but hotplugging is not
3793 * currently supported
3798 /* VF cleanup, just free private port data */
3799 return nfp_net_close(eth_dev);
3802 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3803 struct rte_pci_device *pci_dev)
3805 return rte_eth_dev_pci_generic_probe(pci_dev,
3806 sizeof(struct nfp_net_adapter), nfp_net_init);
3809 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3811 return rte_eth_dev_pci_generic_remove(pci_dev, nfp_pci_uninit);
3814 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3815 .id_table = pci_id_nfp_pf_net_map,
3816 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3817 .probe = nfp_pf_pci_probe,
3818 .remove = eth_nfp_pci_remove,
3821 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3822 .id_table = pci_id_nfp_vf_net_map,
3823 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3824 .probe = eth_nfp_pci_probe,
3825 .remove = eth_nfp_pci_remove,
3828 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3829 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3830 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3831 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3832 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3833 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3834 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_init, init, NOTICE);
3835 RTE_LOG_REGISTER_SUFFIX(nfp_logtype_driver, driver, NOTICE);
3838 * c-file-style: "Linux"
3839 * indent-tabs-mode: t