2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev_driver.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
57 #include <rte_service_component.h>
59 #include "nfpcore/nfp_cpp.h"
60 #include "nfpcore/nfp_nffw.h"
61 #include "nfpcore/nfp_hwinfo.h"
62 #include "nfpcore/nfp_mip.h"
63 #include "nfpcore/nfp_rtsym.h"
64 #include "nfpcore/nfp_nsp.h"
66 #include "nfp_net_pmd.h"
67 #include "nfp_net_logs.h"
68 #include "nfp_net_ctrl.h"
70 #include <sys/types.h>
71 #include <sys/socket.h>
75 #include <sys/ioctl.h>
79 static void nfp_net_close(struct rte_eth_dev *dev);
80 static int nfp_net_configure(struct rte_eth_dev *dev);
81 static void nfp_net_dev_interrupt_handler(void *param);
82 static void nfp_net_dev_interrupt_delayed_handler(void *param);
83 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
84 static int nfp_net_infos_get(struct rte_eth_dev *dev,
85 struct rte_eth_dev_info *dev_info);
86 static int nfp_net_init(struct rte_eth_dev *eth_dev);
87 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
88 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
89 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
90 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
91 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
93 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
95 static void nfp_net_rx_queue_release(void *rxq);
96 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
97 uint16_t nb_desc, unsigned int socket_id,
98 const struct rte_eth_rxconf *rx_conf,
99 struct rte_mempool *mp);
100 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
101 static void nfp_net_tx_queue_release(void *txq);
102 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
103 uint16_t nb_desc, unsigned int socket_id,
104 const struct rte_eth_txconf *tx_conf);
105 static int nfp_net_start(struct rte_eth_dev *dev);
106 static int nfp_net_stats_get(struct rte_eth_dev *dev,
107 struct rte_eth_stats *stats);
108 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
109 static void nfp_net_stop(struct rte_eth_dev *dev);
110 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
113 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
114 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
115 struct rte_eth_rss_conf *rss_conf);
116 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
117 struct rte_eth_rss_reta_entry64 *reta_conf,
119 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
120 struct rte_eth_rss_conf *rss_conf);
121 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
122 struct rte_ether_addr *mac_addr);
124 /* The offset of the queue controller queues in the PCIe Target */
125 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
127 /* Maximum value which can be added to a queue with one transaction */
128 #define NFP_QCP_MAX_ADD 0x7f
130 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
131 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
133 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
135 NFP_QCP_READ_PTR = 0,
140 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
141 * @q: Base address for queue structure
142 * @ptr: Add to the Read or Write pointer
143 * @val: Value to add to the queue pointer
145 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
148 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
152 if (ptr == NFP_QCP_READ_PTR)
153 off = NFP_QCP_QUEUE_ADD_RPTR;
155 off = NFP_QCP_QUEUE_ADD_WPTR;
157 while (val > NFP_QCP_MAX_ADD) {
158 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
159 val -= NFP_QCP_MAX_ADD;
162 nn_writel(rte_cpu_to_le_32(val), q + off);
166 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
167 * @q: Base address for queue structure
168 * @ptr: Read or Write pointer
170 static inline uint32_t
171 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
176 if (ptr == NFP_QCP_READ_PTR)
177 off = NFP_QCP_QUEUE_STS_LO;
179 off = NFP_QCP_QUEUE_STS_HI;
181 val = rte_cpu_to_le_32(nn_readl(q + off));
183 if (ptr == NFP_QCP_READ_PTR)
184 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
186 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
190 * Functions to read/write from/to Config BAR
191 * Performs any endian conversion necessary.
193 static inline uint8_t
194 nn_cfg_readb(struct nfp_net_hw *hw, int off)
196 return nn_readb(hw->ctrl_bar + off);
200 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
202 nn_writeb(val, hw->ctrl_bar + off);
205 static inline uint32_t
206 nn_cfg_readl(struct nfp_net_hw *hw, int off)
208 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
212 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
214 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
217 static inline uint64_t
218 nn_cfg_readq(struct nfp_net_hw *hw, int off)
220 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
224 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
226 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
230 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
234 if (rxq->rxbufs == NULL)
237 for (i = 0; i < rxq->rx_count; i++) {
238 if (rxq->rxbufs[i].mbuf) {
239 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
240 rxq->rxbufs[i].mbuf = NULL;
246 nfp_net_rx_queue_release(void *rx_queue)
248 struct nfp_net_rxq *rxq = rx_queue;
251 nfp_net_rx_queue_release_mbufs(rxq);
252 rte_free(rxq->rxbufs);
258 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
260 nfp_net_rx_queue_release_mbufs(rxq);
266 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
270 if (txq->txbufs == NULL)
273 for (i = 0; i < txq->tx_count; i++) {
274 if (txq->txbufs[i].mbuf) {
275 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
276 txq->txbufs[i].mbuf = NULL;
282 nfp_net_tx_queue_release(void *tx_queue)
284 struct nfp_net_txq *txq = tx_queue;
287 nfp_net_tx_queue_release_mbufs(txq);
288 rte_free(txq->txbufs);
294 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
296 nfp_net_tx_queue_release_mbufs(txq);
302 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
306 struct timespec wait;
308 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
311 if (hw->qcp_cfg == NULL)
312 rte_panic("Bad configuration queue pointer\n");
314 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
317 wait.tv_nsec = 1000000;
319 PMD_DRV_LOG(DEBUG, "Polling for update ack...");
321 /* Poll update field, waiting for NFP to ack the config */
322 for (cnt = 0; ; cnt++) {
323 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
326 if (new & NFP_NET_CFG_UPDATE_ERR) {
327 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
330 if (cnt >= NFP_NET_POLL_TIMEOUT) {
331 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
332 " %dms", update, cnt);
333 rte_panic("Exiting\n");
335 nanosleep(&wait, 0); /* waiting for a 1ms */
337 PMD_DRV_LOG(DEBUG, "Ack DONE");
342 * Reconfigure the NIC
343 * @nn: device to reconfigure
344 * @ctrl: The value for the ctrl field in the BAR config
345 * @update: The value for the update field in the BAR config
347 * Write the update word to the BAR and ping the reconfig queue. Then poll
348 * until the firmware has acknowledged the update by zeroing the update word.
351 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
355 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
358 rte_spinlock_lock(&hw->reconfig_lock);
360 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
361 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
365 err = __nfp_net_reconfig(hw, update);
367 rte_spinlock_unlock(&hw->reconfig_lock);
373 * Reconfig errors imply situations where they can be handled.
374 * Otherwise, rte_panic is called inside __nfp_net_reconfig
376 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
382 * Configure an Ethernet device. This function must be invoked first
383 * before any other function in the Ethernet API. This function can
384 * also be re-invoked when a device is in the stopped state.
387 nfp_net_configure(struct rte_eth_dev *dev)
389 struct rte_eth_conf *dev_conf;
390 struct rte_eth_rxmode *rxmode;
391 struct rte_eth_txmode *txmode;
392 struct nfp_net_hw *hw;
394 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
397 * A DPDK app sends info about how many queues to use and how
398 * those queues need to be configured. This is used by the
399 * DPDK core and it makes sure no more queues than those
400 * advertised by the driver are requested. This function is
401 * called after that internal process
404 PMD_INIT_LOG(DEBUG, "Configure");
406 dev_conf = &dev->data->dev_conf;
407 rxmode = &dev_conf->rxmode;
408 txmode = &dev_conf->txmode;
410 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
412 /* Checking TX mode */
413 if (txmode->mq_mode) {
414 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
418 /* Checking RX mode */
419 if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
420 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
421 PMD_INIT_LOG(INFO, "RSS not supported");
429 nfp_net_enable_queues(struct rte_eth_dev *dev)
431 struct nfp_net_hw *hw;
432 uint64_t enabled_queues = 0;
435 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
437 /* Enabling the required TX queues in the device */
438 for (i = 0; i < dev->data->nb_tx_queues; i++)
439 enabled_queues |= (1 << i);
441 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
445 /* Enabling the required RX queues in the device */
446 for (i = 0; i < dev->data->nb_rx_queues; i++)
447 enabled_queues |= (1 << i);
449 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
453 nfp_net_disable_queues(struct rte_eth_dev *dev)
455 struct nfp_net_hw *hw;
456 uint32_t new_ctrl, update = 0;
458 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
460 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
461 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
463 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
464 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
465 NFP_NET_CFG_UPDATE_MSIX;
467 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
468 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
470 /* If an error when reconfig we avoid to change hw state */
471 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
478 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
482 for (i = 0; i < dev->data->nb_rx_queues; i++) {
483 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
490 nfp_net_params_setup(struct nfp_net_hw *hw)
492 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
493 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
497 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
499 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
502 #define ETH_ADDR_LEN 6
505 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
509 for (i = 0; i < ETH_ADDR_LEN; i++)
514 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
516 struct nfp_eth_table *nfp_eth_table;
518 nfp_eth_table = nfp_eth_read_ports(hw->cpp);
520 * hw points to port0 private data. We need hw now pointing to
524 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
525 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
532 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
536 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
537 memcpy(&hw->mac_addr[0], &tmp, 4);
539 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
540 memcpy(&hw->mac_addr[4], &tmp, 2);
544 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
546 uint32_t mac0 = *(uint32_t *)mac;
549 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
552 mac1 = *(uint16_t *)mac;
553 nn_writew(rte_cpu_to_be_16(mac1),
554 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
558 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
560 struct nfp_net_hw *hw;
561 uint32_t update, ctrl;
563 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
564 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
565 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
566 PMD_INIT_LOG(INFO, "MAC address unable to change when"
571 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
572 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
575 /* Writing new MAC to the specific port BAR address */
576 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
578 /* Signal the NIC about the change */
579 update = NFP_NET_CFG_UPDATE_MACADDR;
581 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
582 (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
583 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
584 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
585 PMD_INIT_LOG(INFO, "MAC address update failed");
592 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
593 struct rte_intr_handle *intr_handle)
595 struct nfp_net_hw *hw;
598 if (!intr_handle->intr_vec) {
599 intr_handle->intr_vec =
600 rte_zmalloc("intr_vec",
601 dev->data->nb_rx_queues * sizeof(int), 0);
602 if (!intr_handle->intr_vec) {
603 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
604 " intr_vec", dev->data->nb_rx_queues);
609 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
611 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
612 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
613 /* UIO just supports one queue and no LSC*/
614 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
615 intr_handle->intr_vec[0] = 0;
617 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
618 for (i = 0; i < dev->data->nb_rx_queues; i++) {
620 * The first msix vector is reserved for non
623 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
624 intr_handle->intr_vec[i] = i + 1;
625 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
626 intr_handle->intr_vec[i]);
630 /* Avoiding TX interrupts */
631 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
636 nfp_check_offloads(struct rte_eth_dev *dev)
638 struct nfp_net_hw *hw;
639 struct rte_eth_conf *dev_conf;
640 struct rte_eth_rxmode *rxmode;
641 struct rte_eth_txmode *txmode;
644 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
646 dev_conf = &dev->data->dev_conf;
647 rxmode = &dev_conf->rxmode;
648 txmode = &dev_conf->txmode;
650 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
651 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
652 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
655 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
656 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
657 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
660 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
661 hw->mtu = rxmode->max_rx_pkt_len;
663 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
664 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
667 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
668 ctrl |= NFP_NET_CFG_CTRL_L2BC;
671 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
672 ctrl |= NFP_NET_CFG_CTRL_L2MC;
674 /* TX checksum offload */
675 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
676 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
677 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
678 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
681 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
682 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
683 ctrl |= NFP_NET_CFG_CTRL_LSO;
685 ctrl |= NFP_NET_CFG_CTRL_LSO2;
689 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
690 ctrl |= NFP_NET_CFG_CTRL_GATHER;
696 nfp_net_start(struct rte_eth_dev *dev)
698 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
699 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
700 uint32_t new_ctrl, update = 0;
701 struct nfp_net_hw *hw;
702 struct rte_eth_conf *dev_conf;
703 struct rte_eth_rxmode *rxmode;
704 uint32_t intr_vector;
707 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
709 PMD_INIT_LOG(DEBUG, "Start");
711 /* Disabling queues just in case... */
712 nfp_net_disable_queues(dev);
714 /* Enabling the required queues in the device */
715 nfp_net_enable_queues(dev);
717 /* check and configure queue intr-vector mapping */
718 if (dev->data->dev_conf.intr_conf.rxq != 0) {
719 if (hw->pf_multiport_enabled) {
720 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
721 "with NFP multiport PF");
724 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
726 * Better not to share LSC with RX interrupts.
727 * Unregistering LSC interrupt handler
729 rte_intr_callback_unregister(&pci_dev->intr_handle,
730 nfp_net_dev_interrupt_handler, (void *)dev);
732 if (dev->data->nb_rx_queues > 1) {
733 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
734 "supports 1 queue with UIO");
738 intr_vector = dev->data->nb_rx_queues;
739 if (rte_intr_efd_enable(intr_handle, intr_vector))
742 nfp_configure_rx_interrupt(dev, intr_handle);
743 update = NFP_NET_CFG_UPDATE_MSIX;
746 rte_intr_enable(intr_handle);
748 new_ctrl = nfp_check_offloads(dev);
750 /* Writing configuration parameters in the device */
751 nfp_net_params_setup(hw);
753 dev_conf = &dev->data->dev_conf;
754 rxmode = &dev_conf->rxmode;
756 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
757 nfp_net_rss_config_default(dev);
758 update |= NFP_NET_CFG_UPDATE_RSS;
759 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
763 new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
765 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
767 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
768 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
770 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
771 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
775 * Allocating rte mbufs for configured rx queues.
776 * This requires queues being enabled before
778 if (nfp_net_rx_freelist_setup(dev) < 0) {
784 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
785 /* Configure the physical port up */
786 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
788 nfp_eth_set_configured(dev->process_private,
798 * An error returned by this function should mean the app
799 * exiting and then the system releasing all the memory
800 * allocated even memory coming from hugepages.
802 * The device could be enabled at this point with some queues
803 * ready for getting packets. This is true if the call to
804 * nfp_net_rx_freelist_setup() succeeds for some queues but
805 * fails for subsequent queues.
807 * This should make the app exiting but better if we tell the
810 nfp_net_disable_queues(dev);
815 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
817 nfp_net_stop(struct rte_eth_dev *dev)
820 struct nfp_net_hw *hw;
822 PMD_INIT_LOG(DEBUG, "Stop");
824 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
826 nfp_net_disable_queues(dev);
829 for (i = 0; i < dev->data->nb_tx_queues; i++) {
830 nfp_net_reset_tx_queue(
831 (struct nfp_net_txq *)dev->data->tx_queues[i]);
834 for (i = 0; i < dev->data->nb_rx_queues; i++) {
835 nfp_net_reset_rx_queue(
836 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
840 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
841 /* Configure the physical port down */
842 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
844 nfp_eth_set_configured(dev->process_private,
849 /* Set the link up. */
851 nfp_net_set_link_up(struct rte_eth_dev *dev)
853 struct nfp_net_hw *hw;
855 PMD_DRV_LOG(DEBUG, "Set link up");
857 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
862 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
863 /* Configure the physical port down */
864 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
866 return nfp_eth_set_configured(dev->process_private,
870 /* Set the link down. */
872 nfp_net_set_link_down(struct rte_eth_dev *dev)
874 struct nfp_net_hw *hw;
876 PMD_DRV_LOG(DEBUG, "Set link down");
878 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
883 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
884 /* Configure the physical port down */
885 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
887 return nfp_eth_set_configured(dev->process_private,
891 /* Reset and stop device. The device can not be restarted. */
893 nfp_net_close(struct rte_eth_dev *dev)
895 struct nfp_net_hw *hw;
896 struct rte_pci_device *pci_dev;
899 PMD_INIT_LOG(DEBUG, "Close");
901 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
902 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
905 * We assume that the DPDK application is stopping all the
906 * threads/queues before calling the device close function.
909 nfp_net_disable_queues(dev);
912 for (i = 0; i < dev->data->nb_tx_queues; i++) {
913 nfp_net_reset_tx_queue(
914 (struct nfp_net_txq *)dev->data->tx_queues[i]);
917 for (i = 0; i < dev->data->nb_rx_queues; i++) {
918 nfp_net_reset_rx_queue(
919 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
922 rte_intr_disable(&pci_dev->intr_handle);
923 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
925 /* unregister callback func from eal lib */
926 rte_intr_callback_unregister(&pci_dev->intr_handle,
927 nfp_net_dev_interrupt_handler,
931 * The ixgbe PMD driver disables the pcie master on the
932 * device. The i40e does not...
937 nfp_net_promisc_enable(struct rte_eth_dev *dev)
939 uint32_t new_ctrl, update = 0;
940 struct nfp_net_hw *hw;
943 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
945 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
947 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
948 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
952 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
953 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
957 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
958 update = NFP_NET_CFG_UPDATE_GEN;
961 * DPDK sets promiscuous mode on just after this call assuming
962 * it can not fail ...
964 ret = nfp_net_reconfig(hw, new_ctrl, update);
974 nfp_net_promisc_disable(struct rte_eth_dev *dev)
976 uint32_t new_ctrl, update = 0;
977 struct nfp_net_hw *hw;
980 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
982 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
983 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
987 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
988 update = NFP_NET_CFG_UPDATE_GEN;
991 * DPDK sets promiscuous mode off just before this call
992 * assuming it can not fail ...
994 ret = nfp_net_reconfig(hw, new_ctrl, update);
1004 * return 0 means link status changed, -1 means not changed
1006 * Wait to complete is needed as it can take up to 9 seconds to get the Link
1010 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1012 struct nfp_net_hw *hw;
1013 struct rte_eth_link link;
1014 uint32_t nn_link_status;
1017 static const uint32_t ls_to_ethtool[] = {
1018 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
1019 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
1020 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
1021 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
1022 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
1023 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
1024 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
1025 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
1028 PMD_DRV_LOG(DEBUG, "Link update");
1030 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1034 memset(&link, 0, sizeof(struct rte_eth_link));
1036 if (nn_link_status & NFP_NET_CFG_STS_LINK)
1037 link.link_status = ETH_LINK_UP;
1039 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1041 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1042 NFP_NET_CFG_STS_LINK_RATE_MASK;
1044 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1045 link.link_speed = ETH_SPEED_NUM_NONE;
1047 link.link_speed = ls_to_ethtool[nn_link_status];
1049 ret = rte_eth_linkstatus_set(dev, &link);
1051 if (link.link_status)
1052 PMD_DRV_LOG(INFO, "NIC Link is Up");
1054 PMD_DRV_LOG(INFO, "NIC Link is Down");
1060 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1063 struct nfp_net_hw *hw;
1064 struct rte_eth_stats nfp_dev_stats;
1066 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1068 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1070 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1072 /* reading per RX ring stats */
1073 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1074 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1077 nfp_dev_stats.q_ipackets[i] =
1078 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1080 nfp_dev_stats.q_ipackets[i] -=
1081 hw->eth_stats_base.q_ipackets[i];
1083 nfp_dev_stats.q_ibytes[i] =
1084 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1086 nfp_dev_stats.q_ibytes[i] -=
1087 hw->eth_stats_base.q_ibytes[i];
1090 /* reading per TX ring stats */
1091 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1092 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1095 nfp_dev_stats.q_opackets[i] =
1096 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1098 nfp_dev_stats.q_opackets[i] -=
1099 hw->eth_stats_base.q_opackets[i];
1101 nfp_dev_stats.q_obytes[i] =
1102 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1104 nfp_dev_stats.q_obytes[i] -=
1105 hw->eth_stats_base.q_obytes[i];
1108 nfp_dev_stats.ipackets =
1109 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1111 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1113 nfp_dev_stats.ibytes =
1114 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1116 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1118 nfp_dev_stats.opackets =
1119 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1121 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1123 nfp_dev_stats.obytes =
1124 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1126 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1128 /* reading general device stats */
1129 nfp_dev_stats.ierrors =
1130 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1132 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1134 nfp_dev_stats.oerrors =
1135 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1137 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1139 /* RX ring mbuf allocation failures */
1140 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1142 nfp_dev_stats.imissed =
1143 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1145 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1148 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1155 nfp_net_stats_reset(struct rte_eth_dev *dev)
1158 struct nfp_net_hw *hw;
1160 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1163 * hw->eth_stats_base records the per counter starting point.
1164 * Lets update it now
1167 /* reading per RX ring stats */
1168 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1169 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1172 hw->eth_stats_base.q_ipackets[i] =
1173 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1175 hw->eth_stats_base.q_ibytes[i] =
1176 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1179 /* reading per TX ring stats */
1180 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1181 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1184 hw->eth_stats_base.q_opackets[i] =
1185 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1187 hw->eth_stats_base.q_obytes[i] =
1188 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1191 hw->eth_stats_base.ipackets =
1192 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1194 hw->eth_stats_base.ibytes =
1195 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1197 hw->eth_stats_base.opackets =
1198 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1200 hw->eth_stats_base.obytes =
1201 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1203 /* reading general device stats */
1204 hw->eth_stats_base.ierrors =
1205 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1207 hw->eth_stats_base.oerrors =
1208 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1210 /* RX ring mbuf allocation failures */
1211 dev->data->rx_mbuf_alloc_failed = 0;
1213 hw->eth_stats_base.imissed =
1214 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1220 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1222 struct nfp_net_hw *hw;
1224 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1226 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1227 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1228 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1229 dev_info->max_rx_pktlen = hw->max_mtu;
1230 /* Next should change when PF support is implemented */
1231 dev_info->max_mac_addrs = 1;
1233 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1234 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1236 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1237 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1238 DEV_RX_OFFLOAD_UDP_CKSUM |
1239 DEV_RX_OFFLOAD_TCP_CKSUM;
1241 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME |
1242 DEV_RX_OFFLOAD_RSS_HASH;
1244 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1245 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1247 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1248 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1249 DEV_TX_OFFLOAD_UDP_CKSUM |
1250 DEV_TX_OFFLOAD_TCP_CKSUM;
1252 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1253 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1255 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1256 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1258 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1260 .pthresh = DEFAULT_RX_PTHRESH,
1261 .hthresh = DEFAULT_RX_HTHRESH,
1262 .wthresh = DEFAULT_RX_WTHRESH,
1264 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1268 dev_info->default_txconf = (struct rte_eth_txconf) {
1270 .pthresh = DEFAULT_TX_PTHRESH,
1271 .hthresh = DEFAULT_TX_HTHRESH,
1272 .wthresh = DEFAULT_TX_WTHRESH,
1274 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1275 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1278 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1279 ETH_RSS_NONFRAG_IPV4_TCP |
1280 ETH_RSS_NONFRAG_IPV4_UDP |
1282 ETH_RSS_NONFRAG_IPV6_TCP |
1283 ETH_RSS_NONFRAG_IPV6_UDP;
1285 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1286 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1288 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1289 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1290 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1295 static const uint32_t *
1296 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1298 static const uint32_t ptypes[] = {
1299 /* refers to nfp_net_set_hash() */
1300 RTE_PTYPE_INNER_L3_IPV4,
1301 RTE_PTYPE_INNER_L3_IPV6,
1302 RTE_PTYPE_INNER_L3_IPV6_EXT,
1303 RTE_PTYPE_INNER_L4_MASK,
1307 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1313 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1315 struct nfp_net_rxq *rxq;
1316 struct nfp_net_rx_desc *rxds;
1320 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1327 * Other PMDs are just checking the DD bit in intervals of 4
1328 * descriptors and counting all four if the first has the DD
1329 * bit on. Of course, this is not accurate but can be good for
1330 * performance. But ideally that should be done in descriptors
1331 * chunks belonging to the same cache line
1334 while (count < rxq->rx_count) {
1335 rxds = &rxq->rxds[idx];
1336 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1343 if ((idx) == rxq->rx_count)
1351 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1353 struct rte_pci_device *pci_dev;
1354 struct nfp_net_hw *hw;
1357 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1358 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1360 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1363 /* Make sure all updates are written before un-masking */
1365 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1366 NFP_NET_CFG_ICR_UNMASKED);
1371 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1373 struct rte_pci_device *pci_dev;
1374 struct nfp_net_hw *hw;
1377 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1380 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1383 /* Make sure all updates are written before un-masking */
1385 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1390 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1392 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1393 struct rte_eth_link link;
1395 rte_eth_linkstatus_get(dev, &link);
1396 if (link.link_status)
1397 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1398 dev->data->port_id, link.link_speed,
1399 link.link_duplex == ETH_LINK_FULL_DUPLEX
1400 ? "full-duplex" : "half-duplex");
1402 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1403 dev->data->port_id);
1405 PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1406 pci_dev->addr.domain, pci_dev->addr.bus,
1407 pci_dev->addr.devid, pci_dev->addr.function);
1410 /* Interrupt configuration and handling */
1413 * nfp_net_irq_unmask - Unmask an interrupt
1415 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1416 * clear the ICR for the entry.
1419 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1421 struct nfp_net_hw *hw;
1422 struct rte_pci_device *pci_dev;
1424 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1425 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1427 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1428 /* If MSI-X auto-masking is used, clear the entry */
1430 rte_intr_ack(&pci_dev->intr_handle);
1432 /* Make sure all updates are written before un-masking */
1434 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1435 NFP_NET_CFG_ICR_UNMASKED);
1440 nfp_net_dev_interrupt_handler(void *param)
1443 struct rte_eth_link link;
1444 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1446 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1448 rte_eth_linkstatus_get(dev, &link);
1450 nfp_net_link_update(dev, 0);
1453 if (!link.link_status) {
1454 /* handle it 1 sec later, wait it being stable */
1455 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1456 /* likely to down */
1458 /* handle it 4 sec later, wait it being stable */
1459 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1462 if (rte_eal_alarm_set(timeout * 1000,
1463 nfp_net_dev_interrupt_delayed_handler,
1465 PMD_INIT_LOG(ERR, "Error setting alarm");
1467 nfp_net_irq_unmask(dev);
1472 * Interrupt handler which shall be registered for alarm callback for delayed
1473 * handling specific interrupt to wait for the stable nic state. As the NIC
1474 * interrupt state is not stable for nfp after link is just down, it needs
1475 * to wait 4 seconds to get the stable status.
1477 * @param handle Pointer to interrupt handle.
1478 * @param param The address of parameter (struct rte_eth_dev *)
1483 nfp_net_dev_interrupt_delayed_handler(void *param)
1485 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1487 nfp_net_link_update(dev, 0);
1488 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1490 nfp_net_dev_link_status_print(dev);
1493 nfp_net_irq_unmask(dev);
1497 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1499 struct nfp_net_hw *hw;
1501 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503 /* check that mtu is within the allowed range */
1504 if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1507 /* mtu setting is forbidden if port is started */
1508 if (dev->data->dev_started) {
1509 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1510 dev->data->port_id);
1514 /* switch to jumbo mode if needed */
1515 if ((uint32_t)mtu > RTE_ETHER_MAX_LEN)
1516 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1518 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1520 /* update max frame size */
1521 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1523 /* writing to configuration space */
1524 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1532 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1533 uint16_t queue_idx, uint16_t nb_desc,
1534 unsigned int socket_id,
1535 const struct rte_eth_rxconf *rx_conf,
1536 struct rte_mempool *mp)
1538 const struct rte_memzone *tz;
1539 struct nfp_net_rxq *rxq;
1540 struct nfp_net_hw *hw;
1542 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1544 PMD_INIT_FUNC_TRACE();
1546 /* Validating number of descriptors */
1547 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1548 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1549 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1550 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1555 * Free memory prior to re-allocation if needed. This is the case after
1556 * calling nfp_net_stop
1558 if (dev->data->rx_queues[queue_idx]) {
1559 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1560 dev->data->rx_queues[queue_idx] = NULL;
1563 /* Allocating rx queue data structure */
1564 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1565 RTE_CACHE_LINE_SIZE, socket_id);
1569 /* Hw queues mapping based on firmware configuration */
1570 rxq->qidx = queue_idx;
1571 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1572 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1573 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1574 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1577 * Tracking mbuf size for detecting a potential mbuf overflow due to
1581 rxq->mbuf_size = rxq->mem_pool->elt_size;
1582 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1583 hw->flbufsz = rxq->mbuf_size;
1585 rxq->rx_count = nb_desc;
1586 rxq->port_id = dev->data->port_id;
1587 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1588 rxq->drop_en = rx_conf->rx_drop_en;
1591 * Allocate RX ring hardware descriptors. A memzone large enough to
1592 * handle the maximum ring size is allocated in order to allow for
1593 * resizing in later calls to the queue setup function.
1595 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1596 sizeof(struct nfp_net_rx_desc) *
1597 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1601 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1602 nfp_net_rx_queue_release(rxq);
1606 /* Saving physical and virtual addresses for the RX ring */
1607 rxq->dma = (uint64_t)tz->iova;
1608 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1610 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1611 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1612 sizeof(*rxq->rxbufs) * nb_desc,
1613 RTE_CACHE_LINE_SIZE, socket_id);
1614 if (rxq->rxbufs == NULL) {
1615 nfp_net_rx_queue_release(rxq);
1619 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1620 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1622 nfp_net_reset_rx_queue(rxq);
1624 dev->data->rx_queues[queue_idx] = rxq;
1628 * Telling the HW about the physical address of the RX ring and number
1629 * of descriptors in log2 format
1631 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1632 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1638 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1640 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1644 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1647 for (i = 0; i < rxq->rx_count; i++) {
1648 struct nfp_net_rx_desc *rxd;
1649 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1652 PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1653 (unsigned)rxq->qidx);
1657 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1659 rxd = &rxq->rxds[i];
1661 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1662 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1664 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1667 /* Make sure all writes are flushed before telling the hardware */
1670 /* Not advertising the whole ring as the firmware gets confused if so */
1671 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1674 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1680 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1681 uint16_t nb_desc, unsigned int socket_id,
1682 const struct rte_eth_txconf *tx_conf)
1684 const struct rte_memzone *tz;
1685 struct nfp_net_txq *txq;
1686 uint16_t tx_free_thresh;
1687 struct nfp_net_hw *hw;
1689 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691 PMD_INIT_FUNC_TRACE();
1693 /* Validating number of descriptors */
1694 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1695 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1696 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1697 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1701 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1702 tx_conf->tx_free_thresh :
1703 DEFAULT_TX_FREE_THRESH);
1705 if (tx_free_thresh > (nb_desc)) {
1707 "tx_free_thresh must be less than the number of TX "
1708 "descriptors. (tx_free_thresh=%u port=%d "
1709 "queue=%d)", (unsigned int)tx_free_thresh,
1710 dev->data->port_id, (int)queue_idx);
1715 * Free memory prior to re-allocation if needed. This is the case after
1716 * calling nfp_net_stop
1718 if (dev->data->tx_queues[queue_idx]) {
1719 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1721 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1722 dev->data->tx_queues[queue_idx] = NULL;
1725 /* Allocating tx queue data structure */
1726 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1727 RTE_CACHE_LINE_SIZE, socket_id);
1729 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1734 * Allocate TX ring hardware descriptors. A memzone large enough to
1735 * handle the maximum ring size is allocated in order to allow for
1736 * resizing in later calls to the queue setup function.
1738 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1739 sizeof(struct nfp_net_tx_desc) *
1740 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1743 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1744 nfp_net_tx_queue_release(txq);
1748 txq->tx_count = nb_desc;
1749 txq->tx_free_thresh = tx_free_thresh;
1750 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1751 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1752 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1754 /* queue mapping based on firmware configuration */
1755 txq->qidx = queue_idx;
1756 txq->tx_qcidx = queue_idx * hw->stride_tx;
1757 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1759 txq->port_id = dev->data->port_id;
1761 /* Saving physical and virtual addresses for the TX ring */
1762 txq->dma = (uint64_t)tz->iova;
1763 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1765 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1766 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1767 sizeof(*txq->txbufs) * nb_desc,
1768 RTE_CACHE_LINE_SIZE, socket_id);
1769 if (txq->txbufs == NULL) {
1770 nfp_net_tx_queue_release(txq);
1773 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1774 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1776 nfp_net_reset_tx_queue(txq);
1778 dev->data->tx_queues[queue_idx] = txq;
1782 * Telling the HW about the physical address of the TX ring and number
1783 * of descriptors in log2 format
1785 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1786 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1791 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1793 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1794 struct rte_mbuf *mb)
1797 struct nfp_net_hw *hw = txq->hw;
1799 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1802 ol_flags = mb->ol_flags;
1804 if (!(ol_flags & PKT_TX_TCP_SEG))
1807 txd->l3_offset = mb->l2_len;
1808 txd->l4_offset = mb->l2_len + mb->l3_len;
1809 txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1810 txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1811 txd->flags = PCIE_DESC_TX_LSO;
1818 txd->lso_hdrlen = 0;
1822 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1824 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1825 struct rte_mbuf *mb)
1828 struct nfp_net_hw *hw = txq->hw;
1830 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1833 ol_flags = mb->ol_flags;
1835 /* IPv6 does not need checksum */
1836 if (ol_flags & PKT_TX_IP_CKSUM)
1837 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1839 switch (ol_flags & PKT_TX_L4_MASK) {
1840 case PKT_TX_UDP_CKSUM:
1841 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1843 case PKT_TX_TCP_CKSUM:
1844 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1848 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1849 txd->flags |= PCIE_DESC_TX_CSUM;
1852 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1854 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1855 struct rte_mbuf *mb)
1857 struct nfp_net_hw *hw = rxq->hw;
1859 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1862 /* If IPv4 and IP checksum error, fail */
1863 if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1864 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1865 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1867 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1869 /* If neither UDP nor TCP return */
1870 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1871 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1874 if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1875 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1877 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1880 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1881 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1883 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1886 * nfp_net_set_hash - Set mbuf hash data
1888 * The RSS hash and hash-type are pre-pended to the packet data.
1889 * Extract and decode it and set the mbuf fields.
1892 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1893 struct rte_mbuf *mbuf)
1895 struct nfp_net_hw *hw = rxq->hw;
1896 uint8_t *meta_offset;
1899 uint32_t hash_type = 0;
1901 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1904 /* this is true for new firmwares */
1905 if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1906 (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1907 NFP_DESC_META_LEN(rxd))) {
1910 * <---- 32 bit ----->
1915 * ====================
1918 * Field type word contains up to 8 4bit field types
1919 * A 4bit field type refers to a data field word
1920 * A data field word can have several 4bit field types
1922 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1923 meta_offset -= NFP_DESC_META_LEN(rxd);
1924 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1926 /* NFP PMD just supports metadata for hashing */
1927 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1928 case NFP_NET_META_HASH:
1929 /* next field type is about the hash type */
1930 meta_info >>= NFP_NET_META_FIELD_SIZE;
1931 /* hash value is in the data field */
1932 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1933 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1936 /* Unsupported metadata can be a performance issue */
1940 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1943 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1944 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1947 mbuf->hash.rss = hash;
1948 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1950 switch (hash_type) {
1951 case NFP_NET_RSS_IPV4:
1952 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1954 case NFP_NET_RSS_IPV6:
1955 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1957 case NFP_NET_RSS_IPV6_EX:
1958 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1960 case NFP_NET_RSS_IPV4_TCP:
1961 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1963 case NFP_NET_RSS_IPV6_TCP:
1964 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1966 case NFP_NET_RSS_IPV4_UDP:
1967 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1969 case NFP_NET_RSS_IPV6_UDP:
1970 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1973 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1978 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1980 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1983 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1988 * There are some decisions to take:
1989 * 1) How to check DD RX descriptors bit
1990 * 2) How and when to allocate new mbufs
1992 * Current implementation checks just one single DD bit each loop. As each
1993 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1994 * a single cache line instead. Tests with this change have not shown any
1995 * performance improvement but it requires further investigation. For example,
1996 * depending on which descriptor is next, the number of descriptors could be
1997 * less than 8 for just checking those in the same cache line. This implies
1998 * extra work which could be counterproductive by itself. Indeed, last firmware
1999 * changes are just doing this: writing several descriptors with the DD bit
2000 * for saving PCIe bandwidth and DMA operations from the NFP.
2002 * Mbuf allocation is done when a new packet is received. Then the descriptor
2003 * is automatically linked with the new mbuf and the old one is given to the
2004 * user. The main drawback with this design is mbuf allocation is heavier than
2005 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2006 * cache point of view it does not seem allocating the mbuf early on as we are
2007 * doing now have any benefit at all. Again, tests with this change have not
2008 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2009 * so looking at the implications of this type of allocation should be studied
2014 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2016 struct nfp_net_rxq *rxq;
2017 struct nfp_net_rx_desc *rxds;
2018 struct nfp_net_rx_buff *rxb;
2019 struct nfp_net_hw *hw;
2020 struct rte_mbuf *mb;
2021 struct rte_mbuf *new_mb;
2027 if (unlikely(rxq == NULL)) {
2029 * DPDK just checks the queue is lower than max queues
2030 * enabled. But the queue needs to be configured
2032 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2040 while (avail < nb_pkts) {
2041 rxb = &rxq->rxbufs[rxq->rd_p];
2042 if (unlikely(rxb == NULL)) {
2043 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2047 rxds = &rxq->rxds[rxq->rd_p];
2048 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2052 * Memory barrier to ensure that we won't do other
2053 * reads before the DD bit.
2058 * We got a packet. Let's alloc a new mbuf for refilling the
2059 * free descriptor ring as soon as possible
2061 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2062 if (unlikely(new_mb == NULL)) {
2063 RTE_LOG_DP(DEBUG, PMD,
2064 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2065 rxq->port_id, (unsigned int)rxq->qidx);
2066 nfp_net_mbuf_alloc_failed(rxq);
2073 * Grab the mbuf and refill the descriptor with the
2074 * previously allocated mbuf
2079 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2080 rxds->rxd.data_len, rxq->mbuf_size);
2082 /* Size of this segment */
2083 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2084 /* Size of the whole packet. We just support 1 segment */
2085 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2087 if (unlikely((mb->data_len + hw->rx_offset) >
2090 * This should not happen and the user has the
2091 * responsibility of avoiding it. But we have
2092 * to give some info about the error
2094 RTE_LOG_DP(ERR, PMD,
2095 "mbuf overflow likely due to the RX offset.\n"
2096 "\t\tYour mbuf size should have extra space for"
2097 " RX offset=%u bytes.\n"
2098 "\t\tCurrently you just have %u bytes available"
2099 " but the received packet is %u bytes long",
2101 rxq->mbuf_size - hw->rx_offset,
2106 /* Filling the received mbuf with packet info */
2108 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2110 mb->data_off = RTE_PKTMBUF_HEADROOM +
2111 NFP_DESC_META_LEN(rxds);
2113 /* No scatter mode supported */
2117 mb->port = rxq->port_id;
2119 /* Checking the RSS flag */
2120 nfp_net_set_hash(rxq, rxds, mb);
2122 /* Checking the checksum flag */
2123 nfp_net_rx_cksum(rxq, rxds, mb);
2125 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2126 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2127 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2128 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2131 /* Adding the mbuf to the mbuf array passed by the app */
2132 rx_pkts[avail++] = mb;
2134 /* Now resetting and updating the descriptor */
2137 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2139 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2140 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2143 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2150 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received",
2151 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2153 nb_hold += rxq->nb_rx_hold;
2156 * FL descriptors needs to be written before incrementing the
2157 * FL queue WR pointer
2160 if (nb_hold > rxq->rx_free_thresh) {
2161 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2162 rxq->port_id, (unsigned int)rxq->qidx,
2163 (unsigned)nb_hold, (unsigned)avail);
2164 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2167 rxq->nb_rx_hold = nb_hold;
2173 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2175 * @txq: TX queue to work with
2176 * Returns number of descriptors freed
2179 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2184 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2185 " status", txq->qidx);
2187 /* Work out how many packets have been sent */
2188 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2190 if (qcp_rd_p == txq->rd_p) {
2191 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2192 "packets (%u, %u)", txq->qidx,
2193 qcp_rd_p, txq->rd_p);
2197 if (qcp_rd_p > txq->rd_p)
2198 todo = qcp_rd_p - txq->rd_p;
2200 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2202 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2203 qcp_rd_p, txq->rd_p, txq->rd_p);
2209 if (unlikely(txq->rd_p >= txq->tx_count))
2210 txq->rd_p -= txq->tx_count;
2215 /* Leaving always free descriptors for avoiding wrapping confusion */
2217 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2219 if (txq->wr_p >= txq->rd_p)
2220 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2222 return txq->rd_p - txq->wr_p - 8;
2226 * nfp_net_txq_full - Check if the TX queue free descriptors
2227 * is below tx_free_threshold
2229 * @txq: TX queue to check
2231 * This function uses the host copy* of read/write pointers
2234 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2236 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2240 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2242 struct nfp_net_txq *txq;
2243 struct nfp_net_hw *hw;
2244 struct nfp_net_tx_desc *txds, txd;
2245 struct rte_mbuf *pkt;
2247 int pkt_size, dma_size;
2248 uint16_t free_descs, issued_descs;
2249 struct rte_mbuf **lmbuf;
2254 txds = &txq->txds[txq->wr_p];
2256 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2257 txq->qidx, txq->wr_p, nb_pkts);
2259 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2260 nfp_net_tx_free_bufs(txq);
2262 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2263 if (unlikely(free_descs == 0))
2270 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2271 txq->qidx, nb_pkts);
2272 /* Sending packets */
2273 while ((i < nb_pkts) && free_descs) {
2274 /* Grabbing the mbuf linked to the current descriptor */
2275 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2276 /* Warming the cache for releasing the mbuf later on */
2277 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2279 pkt = *(tx_pkts + i);
2281 if (unlikely((pkt->nb_segs > 1) &&
2282 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2283 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2284 rte_panic("Multisegment packet unsupported\n");
2287 /* Checking if we have enough descriptors */
2288 if (unlikely(pkt->nb_segs > free_descs))
2292 * Checksum and VLAN flags just in the first descriptor for a
2293 * multisegment packet, but TSO info needs to be in all of them.
2295 txd.data_len = pkt->pkt_len;
2296 nfp_net_tx_tso(txq, &txd, pkt);
2297 nfp_net_tx_cksum(txq, &txd, pkt);
2299 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2300 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2301 txd.flags |= PCIE_DESC_TX_VLAN;
2302 txd.vlan = pkt->vlan_tci;
2306 * mbuf data_len is the data in one segment and pkt_len data
2307 * in the whole packet. When the packet is just one segment,
2308 * then data_len = pkt_len
2310 pkt_size = pkt->pkt_len;
2313 /* Copying TSO, VLAN and cksum info */
2316 /* Releasing mbuf used by this descriptor previously*/
2318 rte_pktmbuf_free_seg(*lmbuf);
2321 * Linking mbuf with descriptor for being released
2322 * next time descriptor is used
2326 dma_size = pkt->data_len;
2327 dma_addr = rte_mbuf_data_iova(pkt);
2328 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2329 "%" PRIx64 "", dma_addr);
2331 /* Filling descriptors fields */
2332 txds->dma_len = dma_size;
2333 txds->data_len = txd.data_len;
2334 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2335 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2336 ASSERT(free_descs > 0);
2340 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2343 pkt_size -= dma_size;
2346 * Making the EOP, packets with just one segment
2349 if (likely(!pkt_size))
2350 txds->offset_eop = PCIE_DESC_TX_EOP;
2352 txds->offset_eop = 0;
2355 /* Referencing next free TX descriptor */
2356 txds = &txq->txds[txq->wr_p];
2357 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2364 /* Increment write pointers. Force memory write before we let HW know */
2366 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2372 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2374 uint32_t new_ctrl, update;
2375 struct nfp_net_hw *hw;
2378 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2381 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2382 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2383 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2384 " ETH_VLAN_EXTEND_OFFLOAD");
2386 /* Enable vlan strip if it is not configured yet */
2387 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2388 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2389 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2391 /* Disable vlan strip just if it is configured */
2392 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2393 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2394 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2399 update = NFP_NET_CFG_UPDATE_GEN;
2401 ret = nfp_net_reconfig(hw, new_ctrl, update);
2403 hw->ctrl = new_ctrl;
2409 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2410 struct rte_eth_rss_reta_entry64 *reta_conf,
2413 uint32_t reta, mask;
2416 struct nfp_net_hw *hw =
2417 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2420 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2421 "(%d) doesn't match the number hardware can supported "
2422 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2427 * Update Redirection Table. There are 128 8bit-entries which can be
2428 * manage as 32 32bit-entries
2430 for (i = 0; i < reta_size; i += 4) {
2431 /* Handling 4 RSS entries per loop */
2432 idx = i / RTE_RETA_GROUP_SIZE;
2433 shift = i % RTE_RETA_GROUP_SIZE;
2434 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2440 /* If all 4 entries were set, don't need read RETA register */
2442 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2444 for (j = 0; j < 4; j++) {
2445 if (!(mask & (0x1 << j)))
2448 /* Clearing the entry bits */
2449 reta &= ~(0xFF << (8 * j));
2450 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2452 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2458 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2460 nfp_net_reta_update(struct rte_eth_dev *dev,
2461 struct rte_eth_rss_reta_entry64 *reta_conf,
2464 struct nfp_net_hw *hw =
2465 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2472 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2476 update = NFP_NET_CFG_UPDATE_RSS;
2478 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2484 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2486 nfp_net_reta_query(struct rte_eth_dev *dev,
2487 struct rte_eth_rss_reta_entry64 *reta_conf,
2493 struct nfp_net_hw *hw;
2495 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2497 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2500 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2501 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2502 "(%d) doesn't match the number hardware can supported "
2503 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2508 * Reading Redirection Table. There are 128 8bit-entries which can be
2509 * manage as 32 32bit-entries
2511 for (i = 0; i < reta_size; i += 4) {
2512 /* Handling 4 RSS entries per loop */
2513 idx = i / RTE_RETA_GROUP_SIZE;
2514 shift = i % RTE_RETA_GROUP_SIZE;
2515 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2520 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2522 for (j = 0; j < 4; j++) {
2523 if (!(mask & (0x1 << j)))
2525 reta_conf[idx].reta[shift + j] =
2526 (uint8_t)((reta >> (8 * j)) & 0xF);
2533 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2534 struct rte_eth_rss_conf *rss_conf)
2536 struct nfp_net_hw *hw;
2538 uint32_t cfg_rss_ctrl = 0;
2542 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2544 /* Writing the key byte a byte */
2545 for (i = 0; i < rss_conf->rss_key_len; i++) {
2546 memcpy(&key, &rss_conf->rss_key[i], 1);
2547 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2550 rss_hf = rss_conf->rss_hf;
2552 if (rss_hf & ETH_RSS_IPV4)
2553 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2555 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2556 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2558 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2559 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2561 if (rss_hf & ETH_RSS_IPV6)
2562 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2564 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2565 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2567 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2568 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2570 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2571 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2573 /* configuring where to apply the RSS hash */
2574 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2576 /* Writing the key size */
2577 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2583 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2584 struct rte_eth_rss_conf *rss_conf)
2588 struct nfp_net_hw *hw;
2590 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2592 rss_hf = rss_conf->rss_hf;
2594 /* Checking if RSS is enabled */
2595 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2596 if (rss_hf != 0) { /* Enable RSS? */
2597 PMD_DRV_LOG(ERR, "RSS unsupported");
2600 return 0; /* Nothing to do */
2603 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2604 PMD_DRV_LOG(ERR, "hash key too long");
2608 nfp_net_rss_hash_write(dev, rss_conf);
2610 update = NFP_NET_CFG_UPDATE_RSS;
2612 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2619 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2620 struct rte_eth_rss_conf *rss_conf)
2623 uint32_t cfg_rss_ctrl;
2626 struct nfp_net_hw *hw;
2628 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2630 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2633 rss_hf = rss_conf->rss_hf;
2634 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2636 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2637 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2639 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2640 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2642 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2643 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2645 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2646 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2648 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2649 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2651 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2652 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2654 /* Reading the key size */
2655 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2657 /* Reading the key byte a byte */
2658 for (i = 0; i < rss_conf->rss_key_len; i++) {
2659 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2660 memcpy(&rss_conf->rss_key[i], &key, 1);
2667 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2669 struct rte_eth_conf *dev_conf;
2670 struct rte_eth_rss_conf rss_conf;
2671 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2672 uint16_t rx_queues = dev->data->nb_rx_queues;
2676 PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2679 nfp_reta_conf[0].mask = ~0x0;
2680 nfp_reta_conf[1].mask = ~0x0;
2683 for (i = 0; i < 0x40; i += 8) {
2684 for (j = i; j < (i + 8); j++) {
2685 nfp_reta_conf[0].reta[j] = queue;
2686 nfp_reta_conf[1].reta[j] = queue++;
2690 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2694 dev_conf = &dev->data->dev_conf;
2696 PMD_DRV_LOG(INFO, "wrong rss conf");
2699 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2701 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2707 /* Initialise and register driver with DPDK Application */
2708 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2709 .dev_configure = nfp_net_configure,
2710 .dev_start = nfp_net_start,
2711 .dev_stop = nfp_net_stop,
2712 .dev_set_link_up = nfp_net_set_link_up,
2713 .dev_set_link_down = nfp_net_set_link_down,
2714 .dev_close = nfp_net_close,
2715 .promiscuous_enable = nfp_net_promisc_enable,
2716 .promiscuous_disable = nfp_net_promisc_disable,
2717 .link_update = nfp_net_link_update,
2718 .stats_get = nfp_net_stats_get,
2719 .stats_reset = nfp_net_stats_reset,
2720 .dev_infos_get = nfp_net_infos_get,
2721 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2722 .mtu_set = nfp_net_dev_mtu_set,
2723 .mac_addr_set = nfp_set_mac_addr,
2724 .vlan_offload_set = nfp_net_vlan_offload_set,
2725 .reta_update = nfp_net_reta_update,
2726 .reta_query = nfp_net_reta_query,
2727 .rss_hash_update = nfp_net_rss_hash_update,
2728 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2729 .rx_queue_setup = nfp_net_rx_queue_setup,
2730 .rx_queue_release = nfp_net_rx_queue_release,
2731 .rx_queue_count = nfp_net_rx_queue_count,
2732 .tx_queue_setup = nfp_net_tx_queue_setup,
2733 .tx_queue_release = nfp_net_tx_queue_release,
2734 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2735 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2739 * All eth_dev created got its private data, but before nfp_net_init, that
2740 * private data is referencing private data for all the PF ports. This is due
2741 * to how the vNIC bars are mapped based on first port, so all ports need info
2742 * about port 0 private data. Inside nfp_net_init the private data pointer is
2743 * changed to the right address for each port once the bars have been mapped.
2745 * This functions helps to find out which port and therefore which offset
2746 * inside the private data array to use.
2749 get_pf_port_number(char *name)
2751 char *pf_str = name;
2754 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2759 * This should not happen at all and it would mean major
2760 * implementation fault.
2762 rte_panic("nfp_net: problem with pf device name\n");
2764 /* Expecting _portX with X within [0,7] */
2767 return (int)strtol(pf_str, NULL, 10);
2771 nfp_net_init(struct rte_eth_dev *eth_dev)
2773 struct rte_pci_device *pci_dev;
2774 struct nfp_net_hw *hw, *hwport0;
2776 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2782 PMD_INIT_FUNC_TRACE();
2784 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2786 /* NFP can not handle DMA addresses requiring more than 40 bits */
2787 if (rte_mem_check_dma_mask(40)) {
2788 RTE_LOG(ERR, PMD, "device %s can not be used:",
2789 pci_dev->device.name);
2790 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2794 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2795 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2796 port = get_pf_port_number(eth_dev->data->name);
2797 if (port < 0 || port > 7) {
2798 PMD_DRV_LOG(ERR, "Port value is wrong");
2802 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2804 /* This points to port 0 private data */
2805 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2807 /* This points to the specific port private data */
2808 hw = &hwport0[port];
2810 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2814 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2815 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2816 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2818 /* For secondary processes, the primary has done all the work */
2819 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2822 rte_eth_copy_pci_info(eth_dev, pci_dev);
2824 hw->device_id = pci_dev->id.device_id;
2825 hw->vendor_id = pci_dev->id.vendor_id;
2826 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2827 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2829 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2830 pci_dev->id.vendor_id, pci_dev->id.device_id,
2831 pci_dev->addr.domain, pci_dev->addr.bus,
2832 pci_dev->addr.devid, pci_dev->addr.function);
2834 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2835 if (hw->ctrl_bar == NULL) {
2837 "hw->ctrl_bar is NULL. BAR0 not configured");
2841 if (hw->is_pf && port == 0) {
2842 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2843 hw->total_ports * 32768,
2845 if (!hw->ctrl_bar) {
2846 printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2850 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2854 if (!hwport0->ctrl_bar)
2857 /* address based on port0 offset */
2858 hw->ctrl_bar = hwport0->ctrl_bar +
2859 (port * NFP_PF_CSR_SLICE_SIZE);
2862 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2864 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2865 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2867 /* Work out where in the BAR the queues start. */
2868 switch (pci_dev->id.device_id) {
2869 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2870 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2871 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2872 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2873 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2874 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2875 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2878 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2880 goto dev_err_ctrl_map;
2883 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2884 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2886 if (hw->is_pf && port == 0) {
2887 /* configure access to tx/rx vNIC BARs */
2888 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2890 NFP_QCP_QUEUE_AREA_SZ,
2891 &hw->hwqueues_area);
2893 if (!hwport0->hw_queues) {
2894 printf("nfp_rtsym_map fails for net.qc");
2896 goto dev_err_ctrl_map;
2899 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2900 hwport0->hw_queues);
2904 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2905 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2906 eth_dev->data->dev_private = hw;
2908 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2910 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2914 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2915 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2917 nfp_net_cfg_queue_setup(hw);
2919 /* Get some of the read-only fields from the config BAR */
2920 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2921 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2922 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2923 hw->mtu = RTE_ETHER_MTU;
2925 /* VLAN insertion is incompatible with LSOv2 */
2926 if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2927 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2929 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2930 hw->rx_offset = NFP_NET_RX_OFFSET;
2932 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2934 PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2935 NFD_CFG_MAJOR_VERSION_of(hw->ver),
2936 NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2938 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2939 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2940 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2941 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2942 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2943 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2944 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2945 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2946 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2947 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2948 hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "",
2949 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2950 hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "",
2951 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "",
2952 hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : "");
2956 hw->stride_rx = stride;
2957 hw->stride_tx = stride;
2959 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2960 hw->max_rx_queues, hw->max_tx_queues);
2962 /* Initializing spinlock for reconfigs */
2963 rte_spinlock_init(&hw->reconfig_lock);
2965 /* Allocating memory for mac addr */
2966 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2967 RTE_ETHER_ADDR_LEN, 0);
2968 if (eth_dev->data->mac_addrs == NULL) {
2969 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2971 goto dev_err_queues_map;
2975 nfp_net_pf_read_mac(hwport0, port);
2976 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2978 nfp_net_vf_read_mac(hw);
2981 if (!rte_is_valid_assigned_ether_addr(
2982 (struct rte_ether_addr *)&hw->mac_addr)) {
2983 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2985 /* Using random mac addresses for VFs */
2986 rte_eth_random_addr(&hw->mac_addr[0]);
2987 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2990 /* Copying mac address to DPDK eth_dev struct */
2991 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2992 ð_dev->data->mac_addrs[0]);
2994 if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2995 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2997 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2998 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2999 eth_dev->data->port_id, pci_dev->id.vendor_id,
3000 pci_dev->id.device_id,
3001 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
3002 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
3004 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3005 /* Registering LSC interrupt handler */
3006 rte_intr_callback_register(&pci_dev->intr_handle,
3007 nfp_net_dev_interrupt_handler,
3009 /* Telling the firmware about the LSC interrupt entry */
3010 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3011 /* Recording current stats counters values */
3012 nfp_net_stats_reset(eth_dev);
3018 nfp_cpp_area_free(hw->hwqueues_area);
3020 nfp_cpp_area_free(hw->ctrl_area);
3025 #define NFP_CPP_MEMIO_BOUNDARY (1 << 20)
3028 * Serving a write request to NFP from host programs. The request
3029 * sends the write size and the CPP target. The bridge makes use
3030 * of CPP interface handler configured by the PMD setup.
3033 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3035 struct nfp_cpp_area *area;
3036 off_t offset, nfp_offset;
3037 uint32_t cpp_id, pos, len;
3038 uint32_t tmpbuf[16];
3039 size_t count, curlen, totlen = 0;
3042 PMD_CPP_LOG(DEBUG, "%s: offset size %lu, count_size: %lu\n", __func__,
3043 sizeof(off_t), sizeof(size_t));
3045 /* Reading the count param */
3046 err = recv(sockfd, &count, sizeof(off_t), 0);
3047 if (err != sizeof(off_t))
3052 /* Reading the offset param */
3053 err = recv(sockfd, &offset, sizeof(off_t), 0);
3054 if (err != sizeof(off_t))
3057 /* Obtain target's CPP ID and offset in target */
3058 cpp_id = (offset >> 40) << 8;
3059 nfp_offset = offset & ((1ull << 40) - 1);
3061 PMD_CPP_LOG(DEBUG, "%s: count %lu and offset %ld\n", __func__, count,
3063 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %ld\n", __func__,
3064 cpp_id, nfp_offset);
3066 /* Adjust length if not aligned */
3067 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3068 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3069 curlen = NFP_CPP_MEMIO_BOUNDARY -
3070 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3074 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3075 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3076 nfp_offset, curlen);
3078 RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3082 /* mapping the target */
3083 err = nfp_cpp_area_acquire(area);
3085 RTE_LOG(ERR, PMD, "area acquire failed\n");
3086 nfp_cpp_area_free(area);
3090 for (pos = 0; pos < curlen; pos += len) {
3092 if (len > sizeof(tmpbuf))
3093 len = sizeof(tmpbuf);
3095 PMD_CPP_LOG(DEBUG, "%s: Receive %u of %lu\n", __func__,
3097 err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3098 if (err != (int)len) {
3100 "%s: error when receiving, %d of %lu\n",
3101 __func__, err, count);
3102 nfp_cpp_area_release(area);
3103 nfp_cpp_area_free(area);
3106 err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3108 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3109 nfp_cpp_area_release(area);
3110 nfp_cpp_area_free(area);
3117 nfp_cpp_area_release(area);
3118 nfp_cpp_area_free(area);
3121 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3122 NFP_CPP_MEMIO_BOUNDARY : count;
3129 * Serving a read request to NFP from host programs. The request
3130 * sends the read size and the CPP target. The bridge makes use
3131 * of CPP interface handler configured by the PMD setup. The read
3132 * data is sent to the requester using the same socket.
3135 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3137 struct nfp_cpp_area *area;
3138 off_t offset, nfp_offset;
3139 uint32_t cpp_id, pos, len;
3140 uint32_t tmpbuf[16];
3141 size_t count, curlen, totlen = 0;
3144 PMD_CPP_LOG(DEBUG, "%s: offset size %lu, count_size: %lu\n", __func__,
3145 sizeof(off_t), sizeof(size_t));
3147 /* Reading the count param */
3148 err = recv(sockfd, &count, sizeof(off_t), 0);
3149 if (err != sizeof(off_t))
3154 /* Reading the offset param */
3155 err = recv(sockfd, &offset, sizeof(off_t), 0);
3156 if (err != sizeof(off_t))
3159 /* Obtain target's CPP ID and offset in target */
3160 cpp_id = (offset >> 40) << 8;
3161 nfp_offset = offset & ((1ull << 40) - 1);
3163 PMD_CPP_LOG(DEBUG, "%s: count %lu and offset %ld\n", __func__, count,
3165 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %ld\n", __func__,
3166 cpp_id, nfp_offset);
3168 /* Adjust length if not aligned */
3169 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3170 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3171 curlen = NFP_CPP_MEMIO_BOUNDARY -
3172 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3176 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3177 nfp_offset, curlen);
3179 RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3183 err = nfp_cpp_area_acquire(area);
3185 RTE_LOG(ERR, PMD, "area acquire failed\n");
3186 nfp_cpp_area_free(area);
3190 for (pos = 0; pos < curlen; pos += len) {
3192 if (len > sizeof(tmpbuf))
3193 len = sizeof(tmpbuf);
3195 err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3197 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3198 nfp_cpp_area_release(area);
3199 nfp_cpp_area_free(area);
3202 PMD_CPP_LOG(DEBUG, "%s: sending %u of %lu\n", __func__,
3205 err = send(sockfd, tmpbuf, len, 0);
3206 if (err != (int)len) {
3208 "%s: error when sending: %d of %lu\n",
3209 __func__, err, count);
3210 nfp_cpp_area_release(area);
3211 nfp_cpp_area_free(area);
3218 nfp_cpp_area_release(area);
3219 nfp_cpp_area_free(area);
3222 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3223 NFP_CPP_MEMIO_BOUNDARY : count;
3228 #define NFP_IOCTL 'n'
3229 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3231 * Serving a ioctl command from host NFP tools. This usually goes to
3232 * a kernel driver char driver but it is not available when the PF is
3233 * bound to the PMD. Currently just one ioctl command is served and it
3234 * does not require any CPP access at all.
3237 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3239 uint32_t cmd, ident_size, tmp;
3242 /* Reading now the IOCTL command */
3243 err = recv(sockfd, &cmd, 4, 0);
3245 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3249 /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3250 if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3251 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3255 err = recv(sockfd, &ident_size, 4, 0);
3257 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3261 tmp = nfp_cpp_model(cpp);
3263 PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3265 err = send(sockfd, &tmp, 4, 0);
3267 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3271 tmp = cpp->interface;
3273 PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3275 err = send(sockfd, &tmp, 4, 0);
3277 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3284 #define NFP_BRIDGE_OP_READ 20
3285 #define NFP_BRIDGE_OP_WRITE 30
3286 #define NFP_BRIDGE_OP_IOCTL 40
3289 * This is the code to be executed by a service core. The CPP bridge interface
3290 * is based on a unix socket and requests usually received by a kernel char
3291 * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3292 * can be executed with a wrapper library and LD_LIBRARY being completely
3293 * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3297 nfp_cpp_bridge_service_func(void *args)
3299 struct sockaddr address;
3300 struct nfp_cpp *cpp = args;
3301 int sockfd, datafd, op, ret;
3303 unlink("/tmp/nfp_cpp");
3304 sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3306 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3311 memset(&address, 0, sizeof(struct sockaddr));
3313 address.sa_family = AF_UNIX;
3314 strcpy(address.sa_data, "/tmp/nfp_cpp");
3316 ret = bind(sockfd, (const struct sockaddr *)&address,
3317 sizeof(struct sockaddr));
3319 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3325 ret = listen(sockfd, 20);
3327 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3334 datafd = accept(sockfd, NULL, NULL);
3336 RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3338 RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3344 ret = recv(datafd, &op, 4, 0);
3346 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3351 PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3353 if (op == NFP_BRIDGE_OP_READ)
3354 nfp_cpp_bridge_serve_read(datafd, cpp);
3356 if (op == NFP_BRIDGE_OP_WRITE)
3357 nfp_cpp_bridge_serve_write(datafd, cpp);
3359 if (op == NFP_BRIDGE_OP_IOCTL)
3360 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3373 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3374 struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3375 int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3377 struct rte_eth_dev *eth_dev;
3378 struct nfp_net_hw *hw = NULL;
3380 struct rte_service_spec service;
3383 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3388 snprintf(port_name, 100, "%s_port%d", dev->device.name, port);
3390 strlcat(port_name, dev->device.name, 100);
3393 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3394 eth_dev = rte_eth_dev_allocate(port_name);
3396 rte_free(port_name);
3400 *priv = rte_zmalloc(port_name,
3401 sizeof(struct nfp_net_adapter) *
3402 ports, RTE_CACHE_LINE_SIZE);
3404 rte_free(port_name);
3405 rte_eth_dev_release_port(eth_dev);
3409 eth_dev->data->dev_private = *priv;
3412 * dev_private pointing to port0 dev_private because we need
3413 * to configure vNIC bars based on port0 at nfp_net_init.
3414 * Then dev_private is adjusted per port.
3416 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3418 hw->hwinfo = hwinfo;
3419 hw->sym_tbl = sym_tbl;
3420 hw->pf_port_idx = phys_port;
3423 hw->pf_multiport_enabled = 1;
3425 hw->total_ports = ports;
3427 eth_dev = rte_eth_dev_attach_secondary(port_name);
3429 RTE_LOG(ERR, EAL, "secondary process attach failed, "
3430 "ethdev doesn't exist");
3431 rte_free(port_name);
3434 eth_dev->process_private = cpp;
3437 eth_dev->device = &dev->device;
3438 rte_eth_copy_pci_info(eth_dev, dev);
3440 retval = nfp_net_init(eth_dev);
3446 rte_eth_dev_probing_finish(eth_dev);
3449 rte_free(port_name);
3453 * The rte_service needs to be created just once per PMD.
3454 * And the cpp handler needs to be linked to the service.
3455 * Secondary processes will be used for debugging DPDK apps
3456 * when requiring to use the CPP interface for accessing NFP
3457 * components. And the cpp handler for secondary processes is
3458 * available at this point.
3460 memset(&service, 0, sizeof(struct rte_service_spec));
3461 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3462 service.callback = nfp_cpp_bridge_service_func;
3463 service.callback_userdata = (void *)cpp;
3465 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
3467 if (rte_service_component_register(&service,
3468 &hw->nfp_cpp_service_id))
3469 RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3471 RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3477 rte_free(port_name);
3478 /* free ports private data if primary process */
3479 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3480 rte_free(eth_dev->data->dev_private);
3482 rte_eth_dev_release_port(eth_dev);
3487 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
3490 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3492 struct nfp_cpp *cpp = nsp->cpp;
3497 struct stat file_stat;
3500 /* Looking for firmware file in order of priority */
3502 /* First try to find a firmware image specific for this device */
3503 snprintf(serial, sizeof(serial),
3504 "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3505 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3506 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3507 cpp->interface & 0xff);
3509 snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3512 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3513 fw_f = open(fw_name, O_RDONLY);
3517 /* Then try the PCI name */
3518 snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3521 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3522 fw_f = open(fw_name, O_RDONLY);
3526 /* Finally try the card type and media */
3527 snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3528 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3529 fw_f = open(fw_name, O_RDONLY);
3531 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3536 if (fstat(fw_f, &file_stat) < 0) {
3537 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3542 fsize = file_stat.st_size;
3543 PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3544 fw_name, (uint64_t)fsize);
3546 fw_buf = malloc((size_t)fsize);
3548 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3552 memset(fw_buf, 0, fsize);
3554 bytes = read(fw_f, fw_buf, fsize);
3555 if (bytes != fsize) {
3556 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3557 "Just %" PRIu64 " of %" PRIu64 " bytes read",
3558 (uint64_t)bytes, (uint64_t)fsize);
3564 PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3565 nfp_nsp_load_fw(nsp, fw_buf, bytes);
3566 PMD_DRV_LOG(INFO, "Done");
3575 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3576 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3578 struct nfp_nsp *nsp;
3579 const char *nfp_fw_model;
3580 char card_desc[100];
3583 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3586 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3588 PMD_DRV_LOG(ERR, "firmware model NOT found");
3592 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3593 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3594 nfp_eth_table->count);
3598 PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3599 nfp_eth_table->count);
3601 PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3603 snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3604 nfp_fw_model, nfp_eth_table->count,
3605 nfp_eth_table->ports[0].speed / 1000);
3607 nsp = nfp_nsp_open(cpp);
3609 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3613 nfp_nsp_device_soft_reset(nsp);
3614 err = nfp_fw_upload(dev, nsp, card_desc);
3620 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3621 struct rte_pci_device *dev)
3623 struct nfp_cpp *cpp;
3624 struct nfp_hwinfo *hwinfo;
3625 struct nfp_rtsym_table *sym_tbl;
3626 struct nfp_eth_table *nfp_eth_table = NULL;
3637 * When device bound to UIO, the device could be used, by mistake,
3638 * by two DPDK apps, and the UIO driver does not avoid it. This
3639 * could lead to a serious problem when configuring the NFP CPP
3640 * interface. Here we avoid this telling to the CPP init code to
3641 * use a lock file if UIO is being used.
3643 if (dev->kdrv == RTE_KDRV_VFIO)
3644 cpp = nfp_cpp_from_device_name(dev, 0);
3646 cpp = nfp_cpp_from_device_name(dev, 1);
3649 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3654 hwinfo = nfp_hwinfo_read(cpp);
3656 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3660 nfp_eth_table = nfp_eth_read_ports(cpp);
3661 if (!nfp_eth_table) {
3662 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3666 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3667 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3668 PMD_DRV_LOG(INFO, "Error when uploading firmware");
3674 /* Now the symbol table should be there */
3675 sym_tbl = nfp_rtsym_table_read(cpp);
3677 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3683 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3684 if (total_ports != (int)nfp_eth_table->count) {
3685 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3689 PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3691 if (total_ports <= 0 || total_ports > 8) {
3692 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3697 for (i = 0; i < total_ports; i++) {
3698 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3699 nfp_eth_table->ports[i].index,
3706 free(nfp_eth_table);
3710 int nfp_logtype_init;
3711 int nfp_logtype_driver;
3713 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3715 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3716 PCI_DEVICE_ID_NFP4000_PF_NIC)
3719 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3720 PCI_DEVICE_ID_NFP6000_PF_NIC)
3727 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3729 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3730 PCI_DEVICE_ID_NFP6000_VF_NIC)
3737 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3738 struct rte_pci_device *pci_dev)
3740 return rte_eth_dev_pci_generic_probe(pci_dev,
3741 sizeof(struct nfp_net_adapter), nfp_net_init);
3744 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3746 struct rte_eth_dev *eth_dev;
3747 struct nfp_net_hw *hw, *hwport0;
3750 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3751 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3752 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3753 port = get_pf_port_number(eth_dev->data->name);
3755 * hotplug is not possible with multiport PF although freeing
3756 * data structures can be done for first port.
3760 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3761 hw = &hwport0[port];
3762 nfp_cpp_area_free(hw->ctrl_area);
3763 nfp_cpp_area_free(hw->hwqueues_area);
3766 nfp_cpp_free(hw->cpp);
3768 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3770 /* hotplug is not possible with multiport PF */
3771 if (hw->pf_multiport_enabled)
3773 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3776 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3777 .id_table = pci_id_nfp_pf_net_map,
3778 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3779 .probe = nfp_pf_pci_probe,
3780 .remove = eth_nfp_pci_remove,
3783 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3784 .id_table = pci_id_nfp_vf_net_map,
3785 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3786 .probe = eth_nfp_pci_probe,
3787 .remove = eth_nfp_pci_remove,
3790 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3791 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3792 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3793 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3794 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3795 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3797 RTE_INIT(nfp_init_log)
3799 nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3800 if (nfp_logtype_init >= 0)
3801 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3802 nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3803 if (nfp_logtype_driver >= 0)
3804 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3808 * c-file-style: "Linux"
3809 * indent-tabs-mode: t