2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
47 #include <rte_debug.h>
48 #include <rte_ethdev.h>
50 #include <rte_ether.h>
51 #include <rte_malloc.h>
52 #include <rte_memzone.h>
53 #include <rte_mempool.h>
54 #include <rte_version.h>
55 #include <rte_string_fns.h>
56 #include <rte_alarm.h>
57 #include <rte_spinlock.h>
59 #include "nfp_net_pmd.h"
60 #include "nfp_net_logs.h"
61 #include "nfp_net_ctrl.h"
64 static void nfp_net_close(struct rte_eth_dev *dev);
65 static int nfp_net_configure(struct rte_eth_dev *dev);
66 static void nfp_net_dev_interrupt_handler(struct rte_intr_handle *handle,
68 static void nfp_net_dev_interrupt_delayed_handler(void *param);
69 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
70 static void nfp_net_infos_get(struct rte_eth_dev *dev,
71 struct rte_eth_dev_info *dev_info);
72 static int nfp_net_init(struct rte_eth_dev *eth_dev);
73 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
74 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
75 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
76 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
77 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
79 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
81 static void nfp_net_rx_queue_release(void *rxq);
82 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
83 uint16_t nb_desc, unsigned int socket_id,
84 const struct rte_eth_rxconf *rx_conf,
85 struct rte_mempool *mp);
86 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
87 static void nfp_net_tx_queue_release(void *txq);
88 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
89 uint16_t nb_desc, unsigned int socket_id,
90 const struct rte_eth_txconf *tx_conf);
91 static int nfp_net_start(struct rte_eth_dev *dev);
92 static void nfp_net_stats_get(struct rte_eth_dev *dev,
93 struct rte_eth_stats *stats);
94 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
95 static void nfp_net_stop(struct rte_eth_dev *dev);
96 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
100 * The offset of the queue controller queues in the PCIe Target. These
101 * happen to be at the same offset on the NFP6000 and the NFP3200 so
102 * we use a single macro here.
104 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
106 /* Maximum value which can be added to a queue with one transaction */
107 #define NFP_QCP_MAX_ADD 0x7f
109 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
110 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
112 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
114 NFP_QCP_READ_PTR = 0,
119 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
120 * @q: Base address for queue structure
121 * @ptr: Add to the Read or Write pointer
122 * @val: Value to add to the queue pointer
124 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
127 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
131 if (ptr == NFP_QCP_READ_PTR)
132 off = NFP_QCP_QUEUE_ADD_RPTR;
134 off = NFP_QCP_QUEUE_ADD_WPTR;
136 while (val > NFP_QCP_MAX_ADD) {
137 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
138 val -= NFP_QCP_MAX_ADD;
141 nn_writel(rte_cpu_to_le_32(val), q + off);
145 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
146 * @q: Base address for queue structure
147 * @ptr: Read or Write pointer
149 static inline uint32_t
150 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
155 if (ptr == NFP_QCP_READ_PTR)
156 off = NFP_QCP_QUEUE_STS_LO;
158 off = NFP_QCP_QUEUE_STS_HI;
160 val = rte_cpu_to_le_32(nn_readl(q + off));
162 if (ptr == NFP_QCP_READ_PTR)
163 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
165 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
169 * Functions to read/write from/to Config BAR
170 * Performs any endian conversion necessary.
172 static inline uint8_t
173 nn_cfg_readb(struct nfp_net_hw *hw, int off)
175 return nn_readb(hw->ctrl_bar + off);
179 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
181 nn_writeb(val, hw->ctrl_bar + off);
184 static inline uint32_t
185 nn_cfg_readl(struct nfp_net_hw *hw, int off)
187 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
191 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
193 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
196 static inline uint64_t
197 nn_cfg_readq(struct nfp_net_hw *hw, int off)
199 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
203 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
205 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
208 /* Creating memzone for hardware rings. */
209 static const struct rte_memzone *
210 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
211 uint16_t queue_id, uint32_t ring_size, int socket_id)
213 char z_name[RTE_MEMZONE_NAMESIZE];
214 const struct rte_memzone *mz;
216 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
217 dev->driver->pci_drv.name,
218 ring_name, dev->data->port_id, queue_id);
220 mz = rte_memzone_lookup(z_name);
224 return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
229 * Atomically reads link status information from global structure rte_eth_dev.
232 * - Pointer to the structure rte_eth_dev to read from.
233 * - Pointer to the buffer to be saved with the link status.
236 * - On success, zero.
237 * - On failure, negative value.
240 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
241 struct rte_eth_link *link)
243 struct rte_eth_link *dst = link;
244 struct rte_eth_link *src = &dev->data->dev_link;
246 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
247 *(uint64_t *)src) == 0)
254 * Atomically writes the link status information into global
255 * structure rte_eth_dev.
258 * - Pointer to the structure rte_eth_dev to read from.
259 * - Pointer to the buffer to be saved with the link status.
262 * - On success, zero.
263 * - On failure, negative value.
266 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
267 struct rte_eth_link *link)
269 struct rte_eth_link *dst = &dev->data->dev_link;
270 struct rte_eth_link *src = link;
272 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
273 *(uint64_t *)src) == 0)
280 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
284 if (rxq->rxbufs == NULL)
287 for (i = 0; i < rxq->rx_count; i++) {
288 if (rxq->rxbufs[i].mbuf) {
289 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
290 rxq->rxbufs[i].mbuf = NULL;
296 nfp_net_rx_queue_release(void *rx_queue)
298 struct nfp_net_rxq *rxq = rx_queue;
301 nfp_net_rx_queue_release_mbufs(rxq);
302 rte_free(rxq->rxbufs);
308 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
310 nfp_net_rx_queue_release_mbufs(rxq);
317 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
321 if (txq->txbufs == NULL)
324 for (i = 0; i < txq->tx_count; i++) {
325 if (txq->txbufs[i].mbuf) {
326 rte_pktmbuf_free(txq->txbufs[i].mbuf);
327 txq->txbufs[i].mbuf = NULL;
333 nfp_net_tx_queue_release(void *tx_queue)
335 struct nfp_net_txq *txq = tx_queue;
338 nfp_net_tx_queue_release_mbufs(txq);
339 rte_free(txq->txbufs);
345 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
347 nfp_net_tx_queue_release_mbufs(txq);
355 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
359 struct timespec wait;
361 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
364 if (hw->qcp_cfg == NULL)
365 rte_panic("Bad configuration queue pointer\n");
367 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
370 wait.tv_nsec = 1000000;
372 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
374 /* Poll update field, waiting for NFP to ack the config */
375 for (cnt = 0; ; cnt++) {
376 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
379 if (new & NFP_NET_CFG_UPDATE_ERR) {
380 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x\n", new);
383 if (cnt >= NFP_NET_POLL_TIMEOUT) {
384 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
385 " %dms\n", update, cnt);
386 rte_panic("Exiting\n");
388 nanosleep(&wait, 0); /* waiting for a 1ms */
390 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
395 * Reconfigure the NIC
396 * @nn: device to reconfigure
397 * @ctrl: The value for the ctrl field in the BAR config
398 * @update: The value for the update field in the BAR config
400 * Write the update word to the BAR and ping the reconfig queue. Then poll
401 * until the firmware has acknowledged the update by zeroing the update word.
404 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
408 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
411 rte_spinlock_lock(&hw->reconfig_lock);
413 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
414 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
418 err = __nfp_net_reconfig(hw, update);
420 rte_spinlock_unlock(&hw->reconfig_lock);
426 * Reconfig errors imply situations where they can be handled.
427 * Otherwise, rte_panic is called inside __nfp_net_reconfig
429 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x\n",
435 * Configure an Ethernet device. This function must be invoked first
436 * before any other function in the Ethernet API. This function can
437 * also be re-invoked when a device is in the stopped state.
440 nfp_net_configure(struct rte_eth_dev *dev)
442 struct rte_eth_conf *dev_conf;
443 struct rte_eth_rxmode *rxmode;
444 struct rte_eth_txmode *txmode;
445 uint32_t new_ctrl = 0;
447 struct nfp_net_hw *hw;
449 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
452 * A DPDK app sends info about how many queues to use and how
453 * those queues need to be configured. This is used by the
454 * DPDK core and it makes sure no more queues than those
455 * advertised by the driver are requested. This function is
456 * called after that internal process
459 PMD_INIT_LOG(DEBUG, "Configure\n");
461 dev_conf = &dev->data->dev_conf;
462 rxmode = &dev_conf->rxmode;
463 txmode = &dev_conf->txmode;
465 /* Checking TX mode */
466 if (txmode->mq_mode) {
467 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported\n");
471 /* Checking RX mode */
472 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
473 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
474 update = NFP_NET_CFG_UPDATE_RSS;
475 new_ctrl = NFP_NET_CFG_CTRL_RSS;
477 PMD_INIT_LOG(INFO, "RSS not supported\n");
482 if (rxmode->split_hdr_size) {
483 PMD_INIT_LOG(INFO, "rxmode does not support split header\n");
487 if (rxmode->hw_ip_checksum) {
488 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
489 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
491 PMD_INIT_LOG(INFO, "RXCSUM not supported\n");
496 if (rxmode->hw_vlan_filter) {
497 PMD_INIT_LOG(INFO, "VLAN filter not supported\n");
501 if (rxmode->hw_vlan_strip) {
502 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
503 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
505 PMD_INIT_LOG(INFO, "hw vlan strip not supported\n");
510 if (rxmode->hw_vlan_extend) {
511 PMD_INIT_LOG(INFO, "VLAN extended not supported\n");
515 /* Supporting VLAN insertion by default */
516 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
517 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
519 if (rxmode->jumbo_frame)
520 /* this is handled in rte_eth_dev_configure */
522 if (rxmode->hw_strip_crc) {
523 PMD_INIT_LOG(INFO, "strip CRC not supported\n");
527 if (rxmode->enable_scatter) {
528 PMD_INIT_LOG(INFO, "Scatter not supported\n");
535 update |= NFP_NET_CFG_UPDATE_GEN;
537 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
538 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
547 nfp_net_enable_queues(struct rte_eth_dev *dev)
549 struct nfp_net_hw *hw;
550 uint64_t enabled_queues = 0;
553 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
555 /* Enabling the required TX queues in the device */
556 for (i = 0; i < dev->data->nb_tx_queues; i++)
557 enabled_queues |= (1 << i);
559 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
563 /* Enabling the required RX queues in the device */
564 for (i = 0; i < dev->data->nb_rx_queues; i++)
565 enabled_queues |= (1 << i);
567 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
571 nfp_net_disable_queues(struct rte_eth_dev *dev)
573 struct nfp_net_hw *hw;
574 uint32_t new_ctrl, update = 0;
576 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
578 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
579 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
581 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
582 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
583 NFP_NET_CFG_UPDATE_MSIX;
585 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
586 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
588 /* If an error when reconfig we avoid to change hw state */
589 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
596 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
600 for (i = 0; i < dev->data->nb_rx_queues; i++) {
601 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
608 nfp_net_params_setup(struct nfp_net_hw *hw)
610 uint32_t *mac_address;
612 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
613 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
615 /* A MAC address is 8 bytes long */
616 mac_address = (uint32_t *)(hw->mac_addr);
618 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR,
619 rte_cpu_to_be_32(*mac_address));
620 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR + 4,
621 rte_cpu_to_be_32(*(mac_address + 4)));
625 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
627 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
631 nfp_net_start(struct rte_eth_dev *dev)
633 uint32_t new_ctrl, update = 0;
634 struct nfp_net_hw *hw;
637 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
639 PMD_INIT_LOG(DEBUG, "Start\n");
641 /* Disabling queues just in case... */
642 nfp_net_disable_queues(dev);
644 /* Writing configuration parameters in the device */
645 nfp_net_params_setup(hw);
647 /* Enabling the required queues in the device */
648 nfp_net_enable_queues(dev);
651 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE | NFP_NET_CFG_UPDATE_MSIX;
652 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
654 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
655 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
657 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
658 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
662 * Allocating rte mbuffs for configured rx queues.
663 * This requires queues being enabled before
665 if (nfp_net_rx_freelist_setup(dev) < 0) {
676 * An error returned by this function should mean the app
677 * exiting and then the system releasing all the memory
678 * allocated even memory coming from hugepages.
680 * The device could be enabled at this point with some queues
681 * ready for getting packets. This is true if the call to
682 * nfp_net_rx_freelist_setup() succeeds for some queues but
683 * fails for subsequent queues.
685 * This should make the app exiting but better if we tell the
688 nfp_net_disable_queues(dev);
693 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
695 nfp_net_stop(struct rte_eth_dev *dev)
699 PMD_INIT_LOG(DEBUG, "Stop\n");
701 nfp_net_disable_queues(dev);
704 for (i = 0; i < dev->data->nb_tx_queues; i++) {
705 nfp_net_reset_tx_queue(
706 (struct nfp_net_txq *)dev->data->tx_queues[i]);
709 for (i = 0; i < dev->data->nb_rx_queues; i++) {
710 nfp_net_reset_rx_queue(
711 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
715 /* Reset and stop device. The device can not be restarted. */
717 nfp_net_close(struct rte_eth_dev *dev)
719 struct nfp_net_hw *hw;
721 PMD_INIT_LOG(DEBUG, "Close\n");
723 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
726 * We assume that the DPDK application is stopping all the
727 * threads/queues before calling the device close function.
732 rte_intr_disable(&dev->pci_dev->intr_handle);
733 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
736 * The ixgbe PMD driver disables the pcie master on the
737 * device. The i40e does not...
742 nfp_net_promisc_enable(struct rte_eth_dev *dev)
744 uint32_t new_ctrl, update = 0;
745 struct nfp_net_hw *hw;
747 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
749 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
751 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
752 PMD_INIT_LOG(INFO, "Promiscuous mode not supported\n");
756 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
757 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
761 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
762 update = NFP_NET_CFG_UPDATE_GEN;
765 * DPDK sets promiscuous mode on just after this call assuming
766 * it can not fail ...
768 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
775 nfp_net_promisc_disable(struct rte_eth_dev *dev)
777 uint32_t new_ctrl, update = 0;
778 struct nfp_net_hw *hw;
780 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
782 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
783 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
787 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
788 update = NFP_NET_CFG_UPDATE_GEN;
791 * DPDK sets promiscuous mode off just before this call
792 * assuming it can not fail ...
794 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
801 * return 0 means link status changed, -1 means not changed
803 * Wait to complete is needed as it can take up to 9 seconds to get the Link
807 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
809 struct nfp_net_hw *hw;
810 struct rte_eth_link link, old;
811 uint32_t nn_link_status;
813 PMD_DRV_LOG(DEBUG, "Link update\n");
815 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
817 memset(&old, 0, sizeof(old));
818 nfp_net_dev_atomic_read_link_status(dev, &old);
820 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
822 memset(&link, 0, sizeof(struct rte_eth_link));
824 if (nn_link_status & NFP_NET_CFG_STS_LINK)
825 link.link_status = ETH_LINK_UP;
827 link.link_duplex = ETH_LINK_FULL_DUPLEX;
828 /* Other cards can limit the tx and rx rate per VF */
829 link.link_speed = ETH_SPEED_NUM_40G;
831 if (old.link_status != link.link_status) {
832 nfp_net_dev_atomic_write_link_status(dev, &link);
833 if (link.link_status)
834 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
836 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
844 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
847 struct nfp_net_hw *hw;
848 struct rte_eth_stats nfp_dev_stats;
850 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
852 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
854 /* reading per RX ring stats */
855 for (i = 0; i < dev->data->nb_rx_queues; i++) {
856 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
859 nfp_dev_stats.q_ipackets[i] =
860 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
862 nfp_dev_stats.q_ipackets[i] -=
863 hw->eth_stats_base.q_ipackets[i];
865 nfp_dev_stats.q_ibytes[i] =
866 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
868 nfp_dev_stats.q_ibytes[i] -=
869 hw->eth_stats_base.q_ibytes[i];
872 /* reading per TX ring stats */
873 for (i = 0; i < dev->data->nb_tx_queues; i++) {
874 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
877 nfp_dev_stats.q_opackets[i] =
878 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
880 nfp_dev_stats.q_opackets[i] -=
881 hw->eth_stats_base.q_opackets[i];
883 nfp_dev_stats.q_obytes[i] =
884 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
886 nfp_dev_stats.q_obytes[i] -=
887 hw->eth_stats_base.q_obytes[i];
890 nfp_dev_stats.ipackets =
891 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
893 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
895 nfp_dev_stats.ibytes =
896 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
898 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
900 nfp_dev_stats.opackets =
901 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
903 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
905 nfp_dev_stats.obytes =
906 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
908 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
910 /* reading general device stats */
911 nfp_dev_stats.ierrors =
912 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
914 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
916 nfp_dev_stats.oerrors =
917 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
919 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
921 /* RX ring mbuf allocation failures */
922 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
924 nfp_dev_stats.imissed =
925 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
927 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
930 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
934 nfp_net_stats_reset(struct rte_eth_dev *dev)
937 struct nfp_net_hw *hw;
939 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
942 * hw->eth_stats_base records the per counter starting point.
946 /* reading per RX ring stats */
947 for (i = 0; i < dev->data->nb_rx_queues; i++) {
948 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
951 hw->eth_stats_base.q_ipackets[i] =
952 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
954 hw->eth_stats_base.q_ibytes[i] =
955 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
958 /* reading per TX ring stats */
959 for (i = 0; i < dev->data->nb_tx_queues; i++) {
960 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
963 hw->eth_stats_base.q_opackets[i] =
964 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
966 hw->eth_stats_base.q_obytes[i] =
967 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
970 hw->eth_stats_base.ipackets =
971 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
973 hw->eth_stats_base.ibytes =
974 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
976 hw->eth_stats_base.opackets =
977 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
979 hw->eth_stats_base.obytes =
980 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
982 /* reading general device stats */
983 hw->eth_stats_base.ierrors =
984 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
986 hw->eth_stats_base.oerrors =
987 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
989 /* RX ring mbuf allocation failures */
990 dev->data->rx_mbuf_alloc_failed = 0;
992 hw->eth_stats_base.imissed =
993 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
997 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
999 struct nfp_net_hw *hw;
1001 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1003 dev_info->driver_name = dev->driver->pci_drv.name;
1004 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1005 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1006 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1007 dev_info->max_rx_pktlen = hw->mtu;
1008 /* Next should change when PF support is implemented */
1009 dev_info->max_mac_addrs = 1;
1011 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1012 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1014 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1015 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1016 DEV_RX_OFFLOAD_UDP_CKSUM |
1017 DEV_RX_OFFLOAD_TCP_CKSUM;
1019 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1020 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1022 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1023 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1024 DEV_RX_OFFLOAD_UDP_CKSUM |
1025 DEV_RX_OFFLOAD_TCP_CKSUM;
1027 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1029 .pthresh = DEFAULT_RX_PTHRESH,
1030 .hthresh = DEFAULT_RX_HTHRESH,
1031 .wthresh = DEFAULT_RX_WTHRESH,
1033 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1037 dev_info->default_txconf = (struct rte_eth_txconf) {
1039 .pthresh = DEFAULT_TX_PTHRESH,
1040 .hthresh = DEFAULT_TX_HTHRESH,
1041 .wthresh = DEFAULT_TX_WTHRESH,
1043 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1044 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1045 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1046 ETH_TXQ_FLAGS_NOOFFLOADS,
1049 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1050 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1052 dev_info->speed_capa = ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1055 static const uint32_t *
1056 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1058 static const uint32_t ptypes[] = {
1059 /* refers to nfp_net_set_hash() */
1060 RTE_PTYPE_INNER_L3_IPV4,
1061 RTE_PTYPE_INNER_L3_IPV6,
1062 RTE_PTYPE_INNER_L3_IPV6_EXT,
1063 RTE_PTYPE_INNER_L4_MASK,
1067 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1073 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1075 struct nfp_net_rxq *rxq;
1076 struct nfp_net_rx_desc *rxds;
1080 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1083 PMD_INIT_LOG(ERR, "Bad queue: %u\n", queue_idx);
1087 idx = rxq->rd_p % rxq->rx_count;
1088 rxds = &rxq->rxds[idx];
1093 * Other PMDs are just checking the DD bit in intervals of 4
1094 * descriptors and counting all four if the first has the DD
1095 * bit on. Of course, this is not accurate but can be good for
1096 * perfomance. But ideally that should be done in descriptors
1097 * chunks belonging to the same cache line
1100 while (count < rxq->rx_count) {
1101 rxds = &rxq->rxds[idx];
1102 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1109 if ((idx) == rxq->rx_count)
1117 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1119 struct rte_eth_link link;
1121 memset(&link, 0, sizeof(link));
1122 nfp_net_dev_atomic_read_link_status(dev, &link);
1123 if (link.link_status)
1124 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1125 (int)(dev->data->port_id), (unsigned)link.link_speed,
1126 link.link_duplex == ETH_LINK_FULL_DUPLEX
1127 ? "full-duplex" : "half-duplex");
1129 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1130 (int)(dev->data->port_id));
1132 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1133 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1134 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1137 /* Interrupt configuration and handling */
1140 * nfp_net_irq_unmask - Unmask an interrupt
1142 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1143 * clear the ICR for the entry.
1146 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1148 struct nfp_net_hw *hw;
1150 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1152 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1153 /* If MSI-X auto-masking is used, clear the entry */
1155 rte_intr_enable(&dev->pci_dev->intr_handle);
1157 /* Make sure all updates are written before un-masking */
1159 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1160 NFP_NET_CFG_ICR_UNMASKED);
1165 nfp_net_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1169 struct rte_eth_link link;
1170 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1172 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1174 /* get the link status */
1175 memset(&link, 0, sizeof(link));
1176 nfp_net_dev_atomic_read_link_status(dev, &link);
1178 nfp_net_link_update(dev, 0);
1181 if (!link.link_status) {
1182 /* handle it 1 sec later, wait it being stable */
1183 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1184 /* likely to down */
1186 /* handle it 4 sec later, wait it being stable */
1187 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1190 if (rte_eal_alarm_set(timeout * 1000,
1191 nfp_net_dev_interrupt_delayed_handler,
1193 RTE_LOG(ERR, PMD, "Error setting alarm");
1195 nfp_net_irq_unmask(dev);
1200 * Interrupt handler which shall be registered for alarm callback for delayed
1201 * handling specific interrupt to wait for the stable nic state. As the NIC
1202 * interrupt state is not stable for nfp after link is just down, it needs
1203 * to wait 4 seconds to get the stable status.
1205 * @param handle Pointer to interrupt handle.
1206 * @param param The address of parameter (struct rte_eth_dev *)
1211 nfp_net_dev_interrupt_delayed_handler(void *param)
1213 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1215 nfp_net_link_update(dev, 0);
1216 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1218 nfp_net_dev_link_status_print(dev);
1221 nfp_net_irq_unmask(dev);
1225 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1227 struct nfp_net_hw *hw;
1229 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231 /* check that mtu is within the allowed range */
1232 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1235 /* switch to jumbo mode if needed */
1236 if ((uint32_t)mtu > ETHER_MAX_LEN)
1237 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1239 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1241 /* update max frame size */
1242 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1244 /* writing to configuration space */
1245 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1253 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1254 uint16_t queue_idx, uint16_t nb_desc,
1255 unsigned int socket_id,
1256 const struct rte_eth_rxconf *rx_conf,
1257 struct rte_mempool *mp)
1259 const struct rte_memzone *tz;
1260 struct nfp_net_rxq *rxq;
1261 struct nfp_net_hw *hw;
1263 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1265 PMD_INIT_FUNC_TRACE();
1267 /* Validating number of descriptors */
1268 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1269 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1270 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1271 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1276 * Free memory prior to re-allocation if needed. This is the case after
1277 * calling nfp_net_stop
1279 if (dev->data->rx_queues[queue_idx]) {
1280 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1281 dev->data->rx_queues[queue_idx] = NULL;
1284 /* Allocating rx queue data structure */
1285 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1286 RTE_CACHE_LINE_SIZE, socket_id);
1290 /* Hw queues mapping based on firmware confifguration */
1291 rxq->qidx = queue_idx;
1292 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1293 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1294 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1295 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1298 * Tracking mbuf size for detecting a potential mbuf overflow due to
1302 rxq->mbuf_size = rxq->mem_pool->elt_size;
1303 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1304 hw->flbufsz = rxq->mbuf_size;
1306 rxq->rx_count = nb_desc;
1307 rxq->port_id = dev->data->port_id;
1308 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1309 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1311 rxq->drop_en = rx_conf->rx_drop_en;
1314 * Allocate RX ring hardware descriptors. A memzone large enough to
1315 * handle the maximum ring size is allocated in order to allow for
1316 * resizing in later calls to the queue setup function.
1318 tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1319 sizeof(struct nfp_net_rx_desc) *
1320 NFP_NET_MAX_RX_DESC, socket_id);
1323 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1324 nfp_net_rx_queue_release(rxq);
1328 /* Saving physical and virtual addresses for the RX ring */
1329 rxq->dma = (uint64_t)tz->phys_addr;
1330 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1332 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1333 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1334 sizeof(*rxq->rxbufs) * nb_desc,
1335 RTE_CACHE_LINE_SIZE, socket_id);
1336 if (rxq->rxbufs == NULL) {
1337 nfp_net_rx_queue_release(rxq);
1341 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1342 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1344 nfp_net_reset_rx_queue(rxq);
1346 dev->data->rx_queues[queue_idx] = rxq;
1350 * Telling the HW about the physical address of the RX ring and number
1351 * of descriptors in log2 format
1353 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1354 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1360 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1362 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1366 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1369 for (i = 0; i < rxq->rx_count; i++) {
1370 struct nfp_net_rx_desc *rxd;
1371 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1374 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1375 (unsigned)rxq->qidx);
1379 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1381 rxd = &rxq->rxds[i];
1383 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1384 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1386 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1391 /* Make sure all writes are flushed before telling the hardware */
1394 /* Not advertising the whole ring as the firmware gets confused if so */
1395 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1398 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1404 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1405 uint16_t nb_desc, unsigned int socket_id,
1406 const struct rte_eth_txconf *tx_conf)
1408 const struct rte_memzone *tz;
1409 struct nfp_net_txq *txq;
1410 uint16_t tx_free_thresh;
1411 struct nfp_net_hw *hw;
1413 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415 PMD_INIT_FUNC_TRACE();
1417 /* Validating number of descriptors */
1418 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1419 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1420 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1421 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1425 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1426 tx_conf->tx_free_thresh :
1427 DEFAULT_TX_FREE_THRESH);
1429 if (tx_free_thresh > (nb_desc)) {
1431 "tx_free_thresh must be less than the number of TX "
1432 "descriptors. (tx_free_thresh=%u port=%d "
1433 "queue=%d)\n", (unsigned int)tx_free_thresh,
1434 (int)dev->data->port_id, (int)queue_idx);
1439 * Free memory prior to re-allocation if needed. This is the case after
1440 * calling nfp_net_stop
1442 if (dev->data->tx_queues[queue_idx]) {
1443 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1445 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1446 dev->data->tx_queues[queue_idx] = NULL;
1449 /* Allocating tx queue data structure */
1450 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1451 RTE_CACHE_LINE_SIZE, socket_id);
1453 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1458 * Allocate TX ring hardware descriptors. A memzone large enough to
1459 * handle the maximum ring size is allocated in order to allow for
1460 * resizing in later calls to the queue setup function.
1462 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1463 sizeof(struct nfp_net_tx_desc) *
1464 NFP_NET_MAX_TX_DESC, socket_id);
1466 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1467 nfp_net_tx_queue_release(txq);
1471 txq->tx_count = nb_desc;
1473 txq->tx_free_thresh = tx_free_thresh;
1474 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1475 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1476 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1478 /* queue mapping based on firmware configuration */
1479 txq->qidx = queue_idx;
1480 txq->tx_qcidx = queue_idx * hw->stride_tx;
1481 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1483 txq->port_id = dev->data->port_id;
1484 txq->txq_flags = tx_conf->txq_flags;
1486 /* Saving physical and virtual addresses for the TX ring */
1487 txq->dma = (uint64_t)tz->phys_addr;
1488 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1490 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1491 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1492 sizeof(*txq->txbufs) * nb_desc,
1493 RTE_CACHE_LINE_SIZE, socket_id);
1494 if (txq->txbufs == NULL) {
1495 nfp_net_tx_queue_release(txq);
1498 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1499 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1501 nfp_net_reset_tx_queue(txq);
1503 dev->data->tx_queues[queue_idx] = txq;
1507 * Telling the HW about the physical address of the TX ring and number
1508 * of descriptors in log2 format
1510 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1511 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1516 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1518 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1519 struct rte_mbuf *mb)
1522 struct nfp_net_hw *hw = txq->hw;
1524 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1527 ol_flags = mb->ol_flags;
1529 /* IPv6 does not need checksum */
1530 if (ol_flags & PKT_TX_IP_CKSUM)
1531 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1533 switch (ol_flags & PKT_TX_L4_MASK) {
1534 case PKT_TX_UDP_CKSUM:
1535 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1537 case PKT_TX_TCP_CKSUM:
1538 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1542 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1543 txd->flags |= PCIE_DESC_TX_CSUM;
1546 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1548 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1549 struct rte_mbuf *mb)
1551 struct nfp_net_hw *hw = rxq->hw;
1553 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1556 /* If IPv4 and IP checksum error, fail */
1557 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1558 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1559 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1561 /* If neither UDP nor TCP return */
1562 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1563 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1566 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1567 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1568 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1570 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1571 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1572 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1575 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1576 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1579 * nfp_net_set_hash - Set mbuf hash data
1581 * The RSS hash and hash-type are pre-pended to the packet data.
1582 * Extract and decode it and set the mbuf fields.
1585 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1586 struct rte_mbuf *mbuf)
1590 struct nfp_net_hw *hw = rxq->hw;
1592 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1595 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1598 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1599 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1602 * hash type is sharing the same word with input port info
1607 mbuf->hash.rss = hash;
1608 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1610 switch (hash_type) {
1611 case NFP_NET_RSS_IPV4:
1612 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1614 case NFP_NET_RSS_IPV6:
1615 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1617 case NFP_NET_RSS_IPV6_EX:
1618 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1621 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1625 /* nfp_net_check_port - Set mbuf in_port field */
1627 nfp_net_check_port(struct nfp_net_rx_desc *rxd, struct rte_mbuf *mbuf)
1631 if (!(rxd->rxd.flags & PCIE_DESC_RX_INGRESS_PORT)) {
1636 port = rte_be_to_cpu_32(*(uint32_t *)((uint8_t *)mbuf->buf_addr +
1637 mbuf->data_off - 8));
1640 * hash type is sharing the same word with input port info
1644 port = (uint8_t)(port >> 8);
1649 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1651 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1654 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1659 * There are some decissions to take:
1660 * 1) How to check DD RX descriptors bit
1661 * 2) How and when to allocate new mbufs
1663 * Current implementation checks just one single DD bit each loop. As each
1664 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1665 * a single cache line instead. Tests with this change have not shown any
1666 * performance improvement but it requires further investigation. For example,
1667 * depending on which descriptor is next, the number of descriptors could be
1668 * less than 8 for just checking those in the same cache line. This implies
1669 * extra work which could be counterproductive by itself. Indeed, last firmware
1670 * changes are just doing this: writing several descriptors with the DD bit
1671 * for saving PCIe bandwidth and DMA operations from the NFP.
1673 * Mbuf allocation is done when a new packet is received. Then the descriptor
1674 * is automatically linked with the new mbuf and the old one is given to the
1675 * user. The main drawback with this design is mbuf allocation is heavier than
1676 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1677 * cache point of view it does not seem allocating the mbuf early on as we are
1678 * doing now have any benefit at all. Again, tests with this change have not
1679 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1680 * so looking at the implications of this type of allocation should be studied
1685 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1687 struct nfp_net_rxq *rxq;
1688 struct nfp_net_rx_desc *rxds;
1689 struct nfp_net_rx_buff *rxb;
1690 struct nfp_net_hw *hw;
1691 struct rte_mbuf *mb;
1692 struct rte_mbuf *new_mb;
1699 if (unlikely(rxq == NULL)) {
1701 * DPDK just checks the queue is lower than max queues
1702 * enabled. But the queue needs to be configured
1704 RTE_LOG(ERR, PMD, "RX Bad queue\n");
1712 while (avail < nb_pkts) {
1713 idx = rxq->rd_p % rxq->rx_count;
1715 rxb = &rxq->rxbufs[idx];
1716 if (unlikely(rxb == NULL)) {
1717 RTE_LOG(ERR, PMD, "rxb does not exist!\n");
1722 * Memory barrier to ensure that we won't do other
1723 * reads before the DD bit.
1727 rxds = &rxq->rxds[idx];
1728 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1732 * We got a packet. Let's alloc a new mbuff for refilling the
1733 * free descriptor ring as soon as possible
1735 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1736 if (unlikely(new_mb == NULL)) {
1737 RTE_LOG(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1738 "queue_id=%u\n", (unsigned)rxq->port_id,
1739 (unsigned)rxq->qidx);
1740 nfp_net_mbuf_alloc_failed(rxq);
1747 * Grab the mbuff and refill the descriptor with the
1748 * previously allocated mbuff
1753 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1754 rxds->rxd.data_len, rxq->mbuf_size);
1756 /* Size of this segment */
1757 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1758 /* Size of the whole packet. We just support 1 segment */
1759 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1761 if (unlikely((mb->data_len + hw->rx_offset) >
1764 * This should not happen and the user has the
1765 * responsibility of avoiding it. But we have
1766 * to give some info about the error
1769 "mbuf overflow likely due to the RX offset.\n"
1770 "\t\tYour mbuf size should have extra space for"
1771 " RX offset=%u bytes.\n"
1772 "\t\tCurrently you just have %u bytes available"
1773 " but the received packet is %u bytes long",
1775 rxq->mbuf_size - hw->rx_offset,
1780 /* Filling the received mbuff with packet info */
1782 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1784 mb->data_off = RTE_PKTMBUF_HEADROOM +
1785 NFP_DESC_META_LEN(rxds);
1787 /* No scatter mode supported */
1791 /* Checking the RSS flag */
1792 nfp_net_set_hash(rxq, rxds, mb);
1794 /* Checking the checksum flag */
1795 nfp_net_rx_cksum(rxq, rxds, mb);
1797 /* Checking the port flag */
1798 nfp_net_check_port(rxds, mb);
1800 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1801 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1802 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1803 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1806 /* Adding the mbuff to the mbuff array passed by the app */
1807 rx_pkts[avail++] = mb;
1809 /* Now resetting and updating the descriptor */
1812 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1814 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1815 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1823 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1824 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1826 nb_hold += rxq->nb_rx_hold;
1829 * FL descriptors needs to be written before incrementing the
1830 * FL queue WR pointer
1833 if (nb_hold > rxq->rx_free_thresh) {
1834 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1835 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1836 (unsigned)nb_hold, (unsigned)avail);
1837 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1840 rxq->nb_rx_hold = nb_hold;
1846 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1848 * @txq: TX queue to work with
1849 * Returns number of descriptors freed
1852 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1857 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1858 " status\n", txq->qidx);
1860 /* Work out how many packets have been sent */
1861 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1863 if (qcp_rd_p == txq->qcp_rd_p) {
1864 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1865 "packets (%u, %u)\n", txq->qidx,
1866 qcp_rd_p, txq->qcp_rd_p);
1870 if (qcp_rd_p > txq->qcp_rd_p)
1871 todo = qcp_rd_p - txq->qcp_rd_p;
1873 todo = qcp_rd_p + txq->tx_count - txq->qcp_rd_p;
1875 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->qcp_rd_p: %u, qcp->rd_p: %u\n",
1876 qcp_rd_p, txq->qcp_rd_p, txq->rd_p);
1881 txq->qcp_rd_p += todo;
1882 txq->qcp_rd_p %= txq->tx_count;
1888 /* Leaving always free descriptors for avoiding wrapping confusion */
1889 #define NFP_FREE_TX_DESC(t) (t->tx_count - (t->wr_p - t->rd_p) - 8)
1892 * nfp_net_txq_full - Check if the TX queue free descriptors
1893 * is below tx_free_threshold
1895 * @txq: TX queue to check
1897 * This function uses the host copy* of read/write pointers
1900 int nfp_net_txq_full(struct nfp_net_txq *txq)
1902 return NFP_FREE_TX_DESC(txq) < txq->tx_free_thresh;
1906 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1908 struct nfp_net_txq *txq;
1909 struct nfp_net_hw *hw;
1910 struct nfp_net_tx_desc *txds;
1911 struct rte_mbuf *pkt;
1913 int pkt_size, dma_size;
1914 uint16_t free_descs, issued_descs;
1915 struct rte_mbuf **lmbuf;
1920 txds = &txq->txds[txq->tail];
1922 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
1923 txq->qidx, txq->tail, nb_pkts);
1925 if ((NFP_FREE_TX_DESC(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
1926 nfp_net_tx_free_bufs(txq);
1928 free_descs = (uint16_t)NFP_FREE_TX_DESC(txq);
1929 if (unlikely(free_descs == 0))
1936 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
1937 txq->qidx, nb_pkts);
1938 /* Sending packets */
1939 while ((i < nb_pkts) && free_descs) {
1940 /* Grabbing the mbuf linked to the current descriptor */
1941 lmbuf = &txq->txbufs[txq->tail].mbuf;
1942 /* Warming the cache for releasing the mbuf later on */
1943 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
1945 pkt = *(tx_pkts + i);
1947 if (unlikely((pkt->nb_segs > 1) &&
1948 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
1949 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set\n");
1950 rte_panic("Multisegment packet unsupported\n");
1953 /* Checking if we have enough descriptors */
1954 if (unlikely(pkt->nb_segs > free_descs))
1958 * Checksum and VLAN flags just in the first descriptor for a
1959 * multisegment packet
1961 nfp_net_tx_cksum(txq, txds, pkt);
1963 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
1964 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
1965 txds->flags |= PCIE_DESC_TX_VLAN;
1966 txds->vlan = pkt->vlan_tci;
1969 if (pkt->ol_flags & PKT_TX_TCP_SEG)
1970 rte_panic("TSO is not supported\n");
1973 * mbuf data_len is the data in one segment and pkt_len data
1974 * in the whole packet. When the packet is just one segment,
1975 * then data_len = pkt_len
1977 pkt_size = pkt->pkt_len;
1979 /* Releasing mbuf which was prefetched above */
1981 rte_pktmbuf_free(*lmbuf);
1983 * Linking mbuf with descriptor for being released
1984 * next time descriptor is used
1989 dma_size = pkt->data_len;
1990 dma_addr = rte_mbuf_data_dma_addr(pkt);
1991 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
1992 "%" PRIx64 "\n", dma_addr);
1994 /* Filling descriptors fields */
1995 txds->dma_len = dma_size;
1996 txds->data_len = pkt->pkt_len;
1997 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
1998 txds->dma_addr_lo = (dma_addr & 0xffffffff);
1999 ASSERT(free_descs > 0);
2004 if (unlikely(txq->tail == txq->tx_count)) /* wrapping?*/
2007 pkt_size -= dma_size;
2010 txds->offset_eop |= PCIE_DESC_TX_EOP;
2012 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2015 /* Referencing next free TX descriptor */
2016 txds = &txq->txds[txq->tail];
2023 /* Increment write pointers. Force memory write before we let HW know */
2025 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2031 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2033 uint32_t new_ctrl, update;
2034 struct nfp_net_hw *hw;
2036 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2040 (mask & ETH_VLAN_FILTER_OFFLOAD))
2041 RTE_LOG(INFO, PMD, "Not support for ETH_VLAN_FILTER_OFFLOAD or"
2042 " ETH_VLAN_FILTER_EXTEND");
2044 /* Enable vlan strip if it is not configured yet */
2045 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2046 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2047 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2049 /* Disable vlan strip just if it is configured */
2050 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2051 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2052 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2057 update = NFP_NET_CFG_UPDATE_GEN;
2059 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2062 hw->ctrl = new_ctrl;
2065 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2067 nfp_net_reta_update(struct rte_eth_dev *dev,
2068 struct rte_eth_rss_reta_entry64 *reta_conf,
2071 uint32_t reta, mask;
2075 struct nfp_net_hw *hw =
2076 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2081 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2082 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2083 "(%d) doesn't match the number hardware can supported "
2084 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2089 * Update Redirection Table. There are 128 8bit-entries which can be
2090 * manage as 32 32bit-entries
2092 for (i = 0; i < reta_size; i += 4) {
2093 /* Handling 4 RSS entries per loop */
2094 idx = i / RTE_RETA_GROUP_SIZE;
2095 shift = i % RTE_RETA_GROUP_SIZE;
2096 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2102 /* If all 4 entries were set, don't need read RETA register */
2104 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2106 for (j = 0; j < 4; j++) {
2107 if (!(mask & (0x1 << j)))
2110 /* Clearing the entry bits */
2111 reta &= ~(0xFF << (8 * j));
2112 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2114 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2117 update = NFP_NET_CFG_UPDATE_RSS;
2119 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2125 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2127 nfp_net_reta_query(struct rte_eth_dev *dev,
2128 struct rte_eth_rss_reta_entry64 *reta_conf,
2134 struct nfp_net_hw *hw;
2136 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2138 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2141 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2142 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2143 "(%d) doesn't match the number hardware can supported "
2144 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2149 * Reading Redirection Table. There are 128 8bit-entries which can be
2150 * manage as 32 32bit-entries
2152 for (i = 0; i < reta_size; i += 4) {
2153 /* Handling 4 RSS entries per loop */
2154 idx = i / RTE_RETA_GROUP_SIZE;
2155 shift = i % RTE_RETA_GROUP_SIZE;
2156 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2161 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2162 for (j = 0; j < 4; j++) {
2163 if (!(mask & (0x1 << j)))
2165 reta_conf->reta[shift + j] =
2166 (uint8_t)((reta >> (8 * j)) & 0xF);
2173 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2174 struct rte_eth_rss_conf *rss_conf)
2177 uint32_t cfg_rss_ctrl = 0;
2181 struct nfp_net_hw *hw;
2183 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185 rss_hf = rss_conf->rss_hf;
2187 /* Checking if RSS is enabled */
2188 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2189 if (rss_hf != 0) { /* Enable RSS? */
2190 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2193 return 0; /* Nothing to do */
2196 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2197 RTE_LOG(ERR, PMD, "hash key too long\n");
2201 if (rss_hf & ETH_RSS_IPV4)
2202 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2203 NFP_NET_CFG_RSS_IPV4_TCP |
2204 NFP_NET_CFG_RSS_IPV4_UDP;
2206 if (rss_hf & ETH_RSS_IPV6)
2207 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2208 NFP_NET_CFG_RSS_IPV6_TCP |
2209 NFP_NET_CFG_RSS_IPV6_UDP;
2211 /* configuring where to apply the RSS hash */
2212 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2214 /* Writing the key byte a byte */
2215 for (i = 0; i < rss_conf->rss_key_len; i++) {
2216 memcpy(&key, &rss_conf->rss_key[i], 1);
2217 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2220 /* Writing the key size */
2221 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2223 update = NFP_NET_CFG_UPDATE_RSS;
2225 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2232 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2233 struct rte_eth_rss_conf *rss_conf)
2236 uint32_t cfg_rss_ctrl;
2239 struct nfp_net_hw *hw;
2241 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2243 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2246 rss_hf = rss_conf->rss_hf;
2247 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2249 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2250 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2252 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2253 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2255 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2256 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2258 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2259 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2261 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2262 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2264 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2265 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2267 /* Reading the key size */
2268 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2270 /* Reading the key byte a byte */
2271 for (i = 0; i < rss_conf->rss_key_len; i++) {
2272 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2273 memcpy(&rss_conf->rss_key[i], &key, 1);
2279 /* Initialise and register driver with DPDK Application */
2280 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2281 .dev_configure = nfp_net_configure,
2282 .dev_start = nfp_net_start,
2283 .dev_stop = nfp_net_stop,
2284 .dev_close = nfp_net_close,
2285 .promiscuous_enable = nfp_net_promisc_enable,
2286 .promiscuous_disable = nfp_net_promisc_disable,
2287 .link_update = nfp_net_link_update,
2288 .stats_get = nfp_net_stats_get,
2289 .stats_reset = nfp_net_stats_reset,
2290 .dev_infos_get = nfp_net_infos_get,
2291 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2292 .mtu_set = nfp_net_dev_mtu_set,
2293 .vlan_offload_set = nfp_net_vlan_offload_set,
2294 .reta_update = nfp_net_reta_update,
2295 .reta_query = nfp_net_reta_query,
2296 .rss_hash_update = nfp_net_rss_hash_update,
2297 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2298 .rx_queue_setup = nfp_net_rx_queue_setup,
2299 .rx_queue_release = nfp_net_rx_queue_release,
2300 .rx_queue_count = nfp_net_rx_queue_count,
2301 .tx_queue_setup = nfp_net_tx_queue_setup,
2302 .tx_queue_release = nfp_net_tx_queue_release,
2306 nfp_net_init(struct rte_eth_dev *eth_dev)
2308 struct rte_pci_device *pci_dev;
2309 struct nfp_net_hw *hw;
2311 uint32_t tx_bar_off, rx_bar_off;
2315 PMD_INIT_FUNC_TRACE();
2317 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2319 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2320 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2321 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2323 /* For secondary processes, the primary has done all the work */
2324 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2327 pci_dev = eth_dev->pci_dev;
2328 rte_eth_copy_pci_info(eth_dev, pci_dev);
2330 hw->device_id = pci_dev->id.device_id;
2331 hw->vendor_id = pci_dev->id.vendor_id;
2332 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2333 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2335 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u\n",
2336 pci_dev->id.vendor_id, pci_dev->id.device_id,
2337 pci_dev->addr.domain, pci_dev->addr.bus,
2338 pci_dev->addr.devid, pci_dev->addr.function);
2340 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2341 if (hw->ctrl_bar == NULL) {
2343 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2346 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2347 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2349 /* Work out where in the BAR the queues start. */
2350 switch (pci_dev->id.device_id) {
2351 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2352 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2353 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2354 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2355 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2358 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2362 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x\n", tx_bar_off);
2363 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x\n", rx_bar_off);
2365 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2366 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2368 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p\n",
2369 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2371 nfp_net_cfg_queue_setup(hw);
2373 /* Get some of the read-only fields from the config BAR */
2374 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2375 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2376 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2377 hw->mtu = hw->max_mtu;
2379 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2380 hw->rx_offset = NFP_NET_RX_OFFSET;
2382 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2384 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d\n",
2385 hw->ver, hw->max_mtu);
2386 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s\n", hw->cap,
2387 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2388 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2389 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2390 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2391 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2392 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2393 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2394 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2395 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2397 pci_dev = eth_dev->pci_dev;
2400 hw->stride_rx = stride;
2401 hw->stride_tx = stride;
2403 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u\n",
2404 hw->max_rx_queues, hw->max_tx_queues);
2406 /* Initializing spinlock for reconfigs */
2407 rte_spinlock_init(&hw->reconfig_lock);
2409 /* Allocating memory for mac addr */
2410 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2411 if (eth_dev->data->mac_addrs == NULL) {
2412 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2416 /* Using random mac addresses for VFs */
2417 eth_random_addr(&hw->mac_addr[0]);
2419 /* Copying mac address to DPDK eth_dev struct */
2420 ether_addr_copy(ð_dev->data->mac_addrs[0],
2421 (struct ether_addr *)hw->mac_addr);
2423 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2424 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2425 eth_dev->data->port_id, pci_dev->id.vendor_id,
2426 pci_dev->id.device_id,
2427 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2428 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2430 /* Registering LSC interrupt handler */
2431 rte_intr_callback_register(&pci_dev->intr_handle,
2432 nfp_net_dev_interrupt_handler,
2435 /* enable uio intr after callback register */
2436 rte_intr_enable(&pci_dev->intr_handle);
2438 /* Telling the firmware about the LSC interrupt entry */
2439 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2441 /* Recording current stats counters values */
2442 nfp_net_stats_reset(eth_dev);
2447 static struct rte_pci_id pci_id_nfp_net_map[] = {
2449 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2450 PCI_DEVICE_ID_NFP6000_PF_NIC)
2453 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2454 PCI_DEVICE_ID_NFP6000_VF_NIC)
2461 static struct eth_driver rte_nfp_net_pmd = {
2463 .name = "rte_nfp_net_pmd",
2464 .id_table = pci_id_nfp_net_map,
2465 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2466 RTE_PCI_DRV_DETACHABLE,
2468 .eth_dev_init = nfp_net_init,
2469 .dev_private_size = sizeof(struct nfp_net_adapter),
2473 nfp_net_pmd_init(const char *name __rte_unused,
2474 const char *params __rte_unused)
2476 PMD_INIT_FUNC_TRACE();
2477 PMD_INIT_LOG(INFO, "librte_pmd_nfp_net version %s\n",
2478 NFP_NET_PMD_VERSION);
2480 rte_eth_driver_register(&rte_nfp_net_pmd);
2484 static struct rte_driver rte_nfp_net_driver = {
2486 .init = nfp_net_pmd_init,
2489 PMD_REGISTER_DRIVER(rte_nfp_net_driver, nfp);
2490 DRIVER_REGISTER_PCI_TABLE(nfp, pci_id_nfp_net_map);
2494 * c-file-style: "Linux"
2495 * indent-tabs-mode: t