drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014, 2015 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev_driver.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfp_nfpu.h"
  59 #include "nfp_net_pmd.h"
  60 #include "nfp_net_logs.h"
  61 #include "nfp_net_ctrl.h"
  62
  63 /* Prototypes */
  64 static void nfp_net_close(struct rte_eth_dev *dev);
  65 static int nfp_net_configure(struct rte_eth_dev *dev);
  66 static void nfp_net_dev_interrupt_handler(void *param);
  67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  70                               struct rte_eth_dev_info *dev_info);
  71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  77                                        uint16_t queue_idx);
  78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  79                                   uint16_t nb_pkts);
  80 static void nfp_net_rx_queue_release(void *rxq);
  81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  82                                   uint16_t nb_desc, unsigned int socket_id,
  83                                   const struct rte_eth_rxconf *rx_conf,
  84                                   struct rte_mempool *mp);
  85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  86 static void nfp_net_tx_queue_release(void *txq);
  87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_txconf *tx_conf);
  90 static int nfp_net_start(struct rte_eth_dev *dev);
  91 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_stats *stats);
  93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
  94 static void nfp_net_stop(struct rte_eth_dev *dev);
  95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  96                                   uint16_t nb_pkts);
  97
  98 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
  99 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
 100                                    struct rte_eth_rss_conf *rss_conf);
 101 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
 102                     struct rte_eth_rss_reta_entry64 *reta_conf,
 103                     uint16_t reta_size);
 104 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
 105                         struct rte_eth_rss_conf *rss_conf);
 106
 107 /*
 108  * The offset of the queue controller queues in the PCIe Target. These
 109  * happen to be at the same offset on the NFP6000 and the NFP3200 so
 110  * we use a single macro here.
 111  */
 112 #define NFP_PCIE_QUEUE(_q)      (0x800 * ((_q) & 0xff))
 113
 114 /* Maximum value which can be added to a queue with one transaction */
 115 #define NFP_QCP_MAX_ADD 0x7f
 116
 117 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 118         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 119
 120 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 121 enum nfp_qcp_ptr {
 122         NFP_QCP_READ_PTR = 0,
 123         NFP_QCP_WRITE_PTR
 124 };
 125
 126 /*
 127  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 128  * @q: Base address for queue structure
 129  * @ptr: Add to the Read or Write pointer
 130  * @val: Value to add to the queue pointer
 131  *
 132  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 133  */
 134 static inline void
 135 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 136 {
 137         uint32_t off;
 138
 139         if (ptr == NFP_QCP_READ_PTR)
 140                 off = NFP_QCP_QUEUE_ADD_RPTR;
 141         else
 142                 off = NFP_QCP_QUEUE_ADD_WPTR;
 143
 144         while (val > NFP_QCP_MAX_ADD) {
 145                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 146                 val -= NFP_QCP_MAX_ADD;
 147         }
 148
 149         nn_writel(rte_cpu_to_le_32(val), q + off);
 150 }
 151
 152 /*
 153  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 154  * @q:  Base address for queue structure
 155  * @ptr: Read or Write pointer
 156  */
 157 static inline uint32_t
 158 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 159 {
 160         uint32_t off;
 161         uint32_t val;
 162
 163         if (ptr == NFP_QCP_READ_PTR)
 164                 off = NFP_QCP_QUEUE_STS_LO;
 165         else
 166                 off = NFP_QCP_QUEUE_STS_HI;
 167
 168         val = rte_cpu_to_le_32(nn_readl(q + off));
 169
 170         if (ptr == NFP_QCP_READ_PTR)
 171                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 172         else
 173                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 174 }
 175
 176 /*
 177  * Functions to read/write from/to Config BAR
 178  * Performs any endian conversion necessary.
 179  */
 180 static inline uint8_t
 181 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 182 {
 183         return nn_readb(hw->ctrl_bar + off);
 184 }
 185
 186 static inline void
 187 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 188 {
 189         nn_writeb(val, hw->ctrl_bar + off);
 190 }
 191
 192 static inline uint32_t
 193 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 194 {
 195         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 196 }
 197
 198 static inline void
 199 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 200 {
 201         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 202 }
 203
 204 static inline uint64_t
 205 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 206 {
 207         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 208 }
 209
 210 static inline void
 211 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 212 {
 213         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 214 }
 215
 216 static void
 217 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 218 {
 219         unsigned i;
 220
 221         if (rxq->rxbufs == NULL)
 222                 return;
 223
 224         for (i = 0; i < rxq->rx_count; i++) {
 225                 if (rxq->rxbufs[i].mbuf) {
 226                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 227                         rxq->rxbufs[i].mbuf = NULL;
 228                 }
 229         }
 230 }
 231
 232 static void
 233 nfp_net_rx_queue_release(void *rx_queue)
 234 {
 235         struct nfp_net_rxq *rxq = rx_queue;
 236
 237         if (rxq) {
 238                 nfp_net_rx_queue_release_mbufs(rxq);
 239                 rte_free(rxq->rxbufs);
 240                 rte_free(rxq);
 241         }
 242 }
 243
 244 static void
 245 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 246 {
 247         nfp_net_rx_queue_release_mbufs(rxq);
 248         rxq->rd_p = 0;
 249         rxq->nb_rx_hold = 0;
 250 }
 251
 252 static void
 253 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 254 {
 255         unsigned i;
 256
 257         if (txq->txbufs == NULL)
 258                 return;
 259
 260         for (i = 0; i < txq->tx_count; i++) {
 261                 if (txq->txbufs[i].mbuf) {
 262                         rte_pktmbuf_free(txq->txbufs[i].mbuf);
 263                         txq->txbufs[i].mbuf = NULL;
 264                 }
 265         }
 266 }
 267
 268 static void
 269 nfp_net_tx_queue_release(void *tx_queue)
 270 {
 271         struct nfp_net_txq *txq = tx_queue;
 272
 273         if (txq) {
 274                 nfp_net_tx_queue_release_mbufs(txq);
 275                 rte_free(txq->txbufs);
 276                 rte_free(txq);
 277         }
 278 }
 279
 280 static void
 281 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 282 {
 283         nfp_net_tx_queue_release_mbufs(txq);
 284         txq->wr_p = 0;
 285         txq->rd_p = 0;
 286 }
 287
 288 static int
 289 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 290 {
 291         int cnt;
 292         uint32_t new;
 293         struct timespec wait;
 294
 295         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
 296                     hw->qcp_cfg);
 297
 298         if (hw->qcp_cfg == NULL)
 299                 rte_panic("Bad configuration queue pointer\n");
 300
 301         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 302
 303         wait.tv_sec = 0;
 304         wait.tv_nsec = 1000000;
 305
 306         PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
 307
 308         /* Poll update field, waiting for NFP to ack the config */
 309         for (cnt = 0; ; cnt++) {
 310                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 311                 if (new == 0)
 312                         break;
 313                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 314                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 315                         return -1;
 316                 }
 317                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 318                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 319                                           " %dms", update, cnt);
 320                         rte_panic("Exiting\n");
 321                 }
 322                 nanosleep(&wait, 0); /* waiting for a 1ms */
 323         }
 324         PMD_DRV_LOG(DEBUG, "Ack DONE\n");
 325         return 0;
 326 }
 327
 328 /*
 329  * Reconfigure the NIC
 330  * @nn:    device to reconfigure
 331  * @ctrl:    The value for the ctrl field in the BAR config
 332  * @update:  The value for the update field in the BAR config
 333  *
 334  * Write the update word to the BAR and ping the reconfig queue. Then poll
 335  * until the firmware has acknowledged the update by zeroing the update word.
 336  */
 337 static int
 338 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 339 {
 340         uint32_t err;
 341
 342         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
 343                     ctrl, update);
 344
 345         rte_spinlock_lock(&hw->reconfig_lock);
 346
 347         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 348         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 349
 350         rte_wmb();
 351
 352         err = __nfp_net_reconfig(hw, update);
 353
 354         rte_spinlock_unlock(&hw->reconfig_lock);
 355
 356         if (!err)
 357                 return 0;
 358
 359         /*
 360          * Reconfig errors imply situations where they can be handled.
 361          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 362          */
 363         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 364                      ctrl, update);
 365         return -EIO;
 366 }
 367
 368 /*
 369  * Configure an Ethernet device. This function must be invoked first
 370  * before any other function in the Ethernet API. This function can
 371  * also be re-invoked when a device is in the stopped state.
 372  */
 373 static int
 374 nfp_net_configure(struct rte_eth_dev *dev)
 375 {
 376         struct rte_eth_conf *dev_conf;
 377         struct rte_eth_rxmode *rxmode;
 378         struct rte_eth_txmode *txmode;
 379         uint32_t new_ctrl = 0;
 380         uint32_t update = 0;
 381         struct nfp_net_hw *hw;
 382
 383         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 384
 385         /*
 386          * A DPDK app sends info about how many queues to use and how
 387          * those queues need to be configured. This is used by the
 388          * DPDK core and it makes sure no more queues than those
 389          * advertised by the driver are requested. This function is
 390          * called after that internal process
 391          */
 392
 393         PMD_INIT_LOG(DEBUG, "Configure");
 394
 395         dev_conf = &dev->data->dev_conf;
 396         rxmode = &dev_conf->rxmode;
 397         txmode = &dev_conf->txmode;
 398
 399         /* Checking TX mode */
 400         if (txmode->mq_mode) {
 401                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 402                 return -EINVAL;
 403         }
 404
 405         /* Checking RX mode */
 406         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 407                 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
 408                         update = NFP_NET_CFG_UPDATE_RSS;
 409                         new_ctrl = NFP_NET_CFG_CTRL_RSS;
 410                 } else {
 411                         PMD_INIT_LOG(INFO, "RSS not supported");
 412                         return -EINVAL;
 413                 }
 414         }
 415
 416         if (rxmode->split_hdr_size) {
 417                 PMD_INIT_LOG(INFO, "rxmode does not support split header");
 418                 return -EINVAL;
 419         }
 420
 421         if (rxmode->hw_ip_checksum) {
 422                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
 423                         new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 424                 } else {
 425                         PMD_INIT_LOG(INFO, "RXCSUM not supported");
 426                         return -EINVAL;
 427                 }
 428         }
 429
 430         if (rxmode->hw_vlan_filter) {
 431                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
 432                 return -EINVAL;
 433         }
 434
 435         if (rxmode->hw_vlan_strip) {
 436                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
 437                         new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 438                 } else {
 439                         PMD_INIT_LOG(INFO, "hw vlan strip not supported");
 440                         return -EINVAL;
 441                 }
 442         }
 443
 444         if (rxmode->hw_vlan_extend) {
 445                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
 446                 return -EINVAL;
 447         }
 448
 449         if (rxmode->jumbo_frame)
 450                 hw->mtu = rxmode->max_rx_pkt_len;
 451
 452         if (!rxmode->hw_strip_crc)
 453                 PMD_INIT_LOG(INFO, "HW does strip CRC and it is not configurable");
 454
 455         if (rxmode->enable_scatter) {
 456                 PMD_INIT_LOG(INFO, "Scatter not supported");
 457                 return -EINVAL;
 458         }
 459
 460         /* If next capabilities are supported, configure them by default */
 461
 462         /* VLAN insertion */
 463         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
 464                 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 465
 466         /* L2 broadcast */
 467         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 468                 new_ctrl |= NFP_NET_CFG_CTRL_L2BC;
 469
 470         /* L2 multicast */
 471         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 472                 new_ctrl |= NFP_NET_CFG_CTRL_L2MC;
 473
 474         /* TX checksum offload */
 475         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
 476                 new_ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 477
 478         /* LSO offload */
 479         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 480                 new_ctrl |= NFP_NET_CFG_CTRL_LSO;
 481
 482         /* RX gather */
 483         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
 484                 new_ctrl |= NFP_NET_CFG_CTRL_GATHER;
 485
 486         if (!new_ctrl)
 487                 return 0;
 488
 489         update |= NFP_NET_CFG_UPDATE_GEN;
 490
 491         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 492         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 493                 return -EIO;
 494
 495         hw->ctrl = new_ctrl;
 496
 497         return 0;
 498 }
 499
 500 static void
 501 nfp_net_enable_queues(struct rte_eth_dev *dev)
 502 {
 503         struct nfp_net_hw *hw;
 504         uint64_t enabled_queues = 0;
 505         int i;
 506
 507         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 508
 509         /* Enabling the required TX queues in the device */
 510         for (i = 0; i < dev->data->nb_tx_queues; i++)
 511                 enabled_queues |= (1 << i);
 512
 513         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 514
 515         enabled_queues = 0;
 516
 517         /* Enabling the required RX queues in the device */
 518         for (i = 0; i < dev->data->nb_rx_queues; i++)
 519                 enabled_queues |= (1 << i);
 520
 521         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 522 }
 523
 524 static void
 525 nfp_net_disable_queues(struct rte_eth_dev *dev)
 526 {
 527         struct nfp_net_hw *hw;
 528         uint32_t new_ctrl, update = 0;
 529
 530         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 531
 532         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 533         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 534
 535         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 536         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 537                  NFP_NET_CFG_UPDATE_MSIX;
 538
 539         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 540                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 541
 542         /* If an error when reconfig we avoid to change hw state */
 543         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 544                 return;
 545
 546         hw->ctrl = new_ctrl;
 547 }
 548
 549 static int
 550 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 551 {
 552         int i;
 553
 554         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 555                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 556                         return -1;
 557         }
 558         return 0;
 559 }
 560
 561 static void
 562 nfp_net_params_setup(struct nfp_net_hw *hw)
 563 {
 564         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 565         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 566 }
 567
 568 static void
 569 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 570 {
 571         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 572 }
 573
 574 #define ETH_ADDR_LEN    6
 575
 576 static void
 577 nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src)
 578 {
 579         int i;
 580
 581         for (i = 0; i < ETH_ADDR_LEN; i++)
 582                 dst[ETH_ADDR_LEN - i - 1] = src[i];
 583 }
 584
 585 static int
 586 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 587 {
 588         union eth_table_entry *entry;
 589         int idx, i;
 590
 591         idx = port;
 592         entry = hw->eth_table;
 593
 594         /* Reading NFP ethernet table obtained before */
 595         for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
 596                 if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
 597                         /* port not in use */
 598                         entry++;
 599                         continue;
 600                 }
 601                 if (idx == 0)
 602                         break;
 603                 idx--;
 604                 entry++;
 605         }
 606
 607         if (i == NSP_ETH_MAX_COUNT)
 608                 return -EINVAL;
 609
 610         /*
 611          * hw points to port0 private data. We need hw now pointing to
 612          * right port.
 613          */
 614         hw += port;
 615         nfp_eth_copy_mac_reverse((uint8_t *)&hw->mac_addr,
 616                                  (uint8_t *)&entry->mac_addr);
 617
 618         return 0;
 619 }
 620
 621 static void
 622 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 623 {
 624         uint32_t tmp;
 625
 626         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 627         memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
 628
 629         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 630         memcpy(&hw->mac_addr[4], &tmp, 2);
 631 }
 632
 633 static void
 634 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 635 {
 636         uint32_t mac0 = *(uint32_t *)mac;
 637         uint16_t mac1;
 638
 639         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 640
 641         mac += 4;
 642         mac1 = *(uint16_t *)mac;
 643         nn_writew(rte_cpu_to_be_16(mac1),
 644                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 645 }
 646
 647 static int
 648 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 649                            struct rte_intr_handle *intr_handle)
 650 {
 651         struct nfp_net_hw *hw;
 652         int i;
 653
 654         if (!intr_handle->intr_vec) {
 655                 intr_handle->intr_vec =
 656                         rte_zmalloc("intr_vec",
 657                                     dev->data->nb_rx_queues * sizeof(int), 0);
 658                 if (!intr_handle->intr_vec) {
 659                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 660                                      " intr_vec", dev->data->nb_rx_queues);
 661                         return -ENOMEM;
 662                 }
 663         }
 664
 665         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 666
 667         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 668                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 669                 /* UIO just supports one queue and no LSC*/
 670                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 671                 intr_handle->intr_vec[0] = 0;
 672         } else {
 673                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 674                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 675                         /*
 676                          * The first msix vector is reserved for non
 677                          * efd interrupts
 678                         */
 679                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 680                         intr_handle->intr_vec[i] = i + 1;
 681                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
 682                                             intr_handle->intr_vec[i]);
 683                 }
 684         }
 685
 686         /* Avoiding TX interrupts */
 687         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 688         return 0;
 689 }
 690
 691 static int
 692 nfp_net_start(struct rte_eth_dev *dev)
 693 {
 694         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 695         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 696         struct rte_eth_conf *dev_conf;
 697         struct rte_eth_rxmode *rxmode;
 698         uint32_t new_ctrl, update = 0;
 699         struct nfp_net_hw *hw;
 700         uint32_t intr_vector;
 701         int ret;
 702
 703         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 704
 705         PMD_INIT_LOG(DEBUG, "Start");
 706
 707         /* Disabling queues just in case... */
 708         nfp_net_disable_queues(dev);
 709
 710         /* Writing configuration parameters in the device */
 711         nfp_net_params_setup(hw);
 712
 713         /* Enabling the required queues in the device */
 714         nfp_net_enable_queues(dev);
 715
 716         /* check and configure queue intr-vector mapping */
 717         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 718                 if (hw->pf_multiport_enabled) {
 719                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 720                                           "with NFP multiport PF");
 721                                 return -EINVAL;
 722                 }
 723                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 724                         /*
 725                          * Better not to share LSC with RX interrupts.
 726                          * Unregistering LSC interrupt handler
 727                          */
 728                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 729                                 nfp_net_dev_interrupt_handler, (void *)dev);
 730
 731                         if (dev->data->nb_rx_queues > 1) {
 732                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 733                                              "supports 1 queue with UIO");
 734                                 return -EIO;
 735                         }
 736                 }
 737                 intr_vector = dev->data->nb_rx_queues;
 738                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 739                         return -1;
 740
 741                 nfp_configure_rx_interrupt(dev, intr_handle);
 742                 update = NFP_NET_CFG_UPDATE_MSIX;
 743         }
 744
 745         rte_intr_enable(intr_handle);
 746
 747         dev_conf = &dev->data->dev_conf;
 748         rxmode = &dev_conf->rxmode;
 749
 750         /* Checking RX mode */
 751         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 752                 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
 753                         if (!nfp_net_rss_config_default(dev))
 754                                 update |= NFP_NET_CFG_UPDATE_RSS;
 755                 } else {
 756                         PMD_INIT_LOG(INFO, "RSS not supported");
 757                         return -EINVAL;
 758                 }
 759         }
 760         /* Enable device */
 761         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
 762
 763         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 764
 765         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 766                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 767
 768         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 769         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 770                 return -EIO;
 771
 772         /*
 773          * Allocating rte mbuffs for configured rx queues.
 774          * This requires queues being enabled before
 775          */
 776         if (nfp_net_rx_freelist_setup(dev) < 0) {
 777                 ret = -ENOMEM;
 778                 goto error;
 779         }
 780
 781         if (hw->is_pf)
 782                 /* Configure the physical port up */
 783                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1);
 784
 785         hw->ctrl = new_ctrl;
 786
 787         return 0;
 788
 789 error:
 790         /*
 791          * An error returned by this function should mean the app
 792          * exiting and then the system releasing all the memory
 793          * allocated even memory coming from hugepages.
 794          *
 795          * The device could be enabled at this point with some queues
 796          * ready for getting packets. This is true if the call to
 797          * nfp_net_rx_freelist_setup() succeeds for some queues but
 798          * fails for subsequent queues.
 799          *
 800          * This should make the app exiting but better if we tell the
 801          * device first.
 802          */
 803         nfp_net_disable_queues(dev);
 804
 805         return ret;
 806 }
 807
 808 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 809 static void
 810 nfp_net_stop(struct rte_eth_dev *dev)
 811 {
 812         int i;
 813         struct nfp_net_hw *hw;
 814
 815         PMD_INIT_LOG(DEBUG, "Stop");
 816
 817         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 818
 819         nfp_net_disable_queues(dev);
 820
 821         /* Clear queues */
 822         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 823                 nfp_net_reset_tx_queue(
 824                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 825         }
 826
 827         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 828                 nfp_net_reset_rx_queue(
 829                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 830         }
 831
 832         if (hw->is_pf)
 833                 /* Configure the physical port down */
 834                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0);
 835 }
 836
 837 /* Reset and stop device. The device can not be restarted. */
 838 static void
 839 nfp_net_close(struct rte_eth_dev *dev)
 840 {
 841         struct nfp_net_hw *hw;
 842         struct rte_pci_device *pci_dev;
 843         int i;
 844
 845         PMD_INIT_LOG(DEBUG, "Close");
 846
 847         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 848         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 849
 850         /*
 851          * We assume that the DPDK application is stopping all the
 852          * threads/queues before calling the device close function.
 853          */
 854
 855         nfp_net_disable_queues(dev);
 856
 857         /* Clear queues */
 858         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 859                 nfp_net_reset_tx_queue(
 860                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 861         }
 862
 863         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 864                 nfp_net_reset_rx_queue(
 865                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 866         }
 867
 868         rte_intr_disable(&pci_dev->intr_handle);
 869         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 870
 871         /* unregister callback func from eal lib */
 872         rte_intr_callback_unregister(&pci_dev->intr_handle,
 873                                      nfp_net_dev_interrupt_handler,
 874                                      (void *)dev);
 875
 876         /*
 877          * The ixgbe PMD driver disables the pcie master on the
 878          * device. The i40e does not...
 879          */
 880 }
 881
 882 static void
 883 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 884 {
 885         uint32_t new_ctrl, update = 0;
 886         struct nfp_net_hw *hw;
 887
 888         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
 889
 890         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 891
 892         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 893                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 894                 return;
 895         }
 896
 897         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 898                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
 899                 return;
 900         }
 901
 902         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 903         update = NFP_NET_CFG_UPDATE_GEN;
 904
 905         /*
 906          * DPDK sets promiscuous mode on just after this call assuming
 907          * it can not fail ...
 908          */
 909         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 910                 return;
 911
 912         hw->ctrl = new_ctrl;
 913 }
 914
 915 static void
 916 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 917 {
 918         uint32_t new_ctrl, update = 0;
 919         struct nfp_net_hw *hw;
 920
 921         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 922
 923         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 924                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
 925                 return;
 926         }
 927
 928         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 929         update = NFP_NET_CFG_UPDATE_GEN;
 930
 931         /*
 932          * DPDK sets promiscuous mode off just before this call
 933          * assuming it can not fail ...
 934          */
 935         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 936                 return;
 937
 938         hw->ctrl = new_ctrl;
 939 }
 940
 941 /*
 942  * return 0 means link status changed, -1 means not changed
 943  *
 944  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 945  * status.
 946  */
 947 static int
 948 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 949 {
 950         struct nfp_net_hw *hw;
 951         struct rte_eth_link link;
 952         uint32_t nn_link_status;
 953         int ret;
 954
 955         static const uint32_t ls_to_ethtool[] = {
 956                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 957                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 958                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 959                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 960                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 961                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 962                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 963                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 964         };
 965
 966         PMD_DRV_LOG(DEBUG, "Link update\n");
 967
 968         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 969
 970         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 971
 972         memset(&link, 0, sizeof(struct rte_eth_link));
 973
 974         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 975                 link.link_status = ETH_LINK_UP;
 976
 977         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 978
 979         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 980                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 981
 982         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 983                 link.link_speed = ETH_SPEED_NUM_NONE;
 984         else
 985                 link.link_speed = ls_to_ethtool[nn_link_status];
 986
 987         ret = rte_eth_linkstatus_set(dev, &link);
 988         if (ret == 0) {
 989                 if (link.link_status)
 990                         PMD_DRV_LOG(INFO, "NIC Link is Up\n");
 991                 else
 992                         PMD_DRV_LOG(INFO, "NIC Link is Down\n");
 993         }
 994         return ret;
 995 }
 996
 997 static int
 998 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 999 {
1000         int i;
1001         struct nfp_net_hw *hw;
1002         struct rte_eth_stats nfp_dev_stats;
1003
1004         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1005
1006         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1007
1008         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1009
1010         /* reading per RX ring stats */
1011         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1012                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1013                         break;
1014
1015                 nfp_dev_stats.q_ipackets[i] =
1016                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1017
1018                 nfp_dev_stats.q_ipackets[i] -=
1019                         hw->eth_stats_base.q_ipackets[i];
1020
1021                 nfp_dev_stats.q_ibytes[i] =
1022                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1023
1024                 nfp_dev_stats.q_ibytes[i] -=
1025                         hw->eth_stats_base.q_ibytes[i];
1026         }
1027
1028         /* reading per TX ring stats */
1029         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1030                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1031                         break;
1032
1033                 nfp_dev_stats.q_opackets[i] =
1034                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1035
1036                 nfp_dev_stats.q_opackets[i] -=
1037                         hw->eth_stats_base.q_opackets[i];
1038
1039                 nfp_dev_stats.q_obytes[i] =
1040                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1041
1042                 nfp_dev_stats.q_obytes[i] -=
1043                         hw->eth_stats_base.q_obytes[i];
1044         }
1045
1046         nfp_dev_stats.ipackets =
1047                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1048
1049         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1050
1051         nfp_dev_stats.ibytes =
1052                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1053
1054         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1055
1056         nfp_dev_stats.opackets =
1057                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1058
1059         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1060
1061         nfp_dev_stats.obytes =
1062                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1063
1064         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1065
1066         /* reading general device stats */
1067         nfp_dev_stats.ierrors =
1068                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1069
1070         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1071
1072         nfp_dev_stats.oerrors =
1073                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1074
1075         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1076
1077         /* RX ring mbuf allocation failures */
1078         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1079
1080         nfp_dev_stats.imissed =
1081                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1082
1083         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1084
1085         if (stats) {
1086                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1087                 return 0;
1088         }
1089         return -EINVAL;
1090 }
1091
1092 static void
1093 nfp_net_stats_reset(struct rte_eth_dev *dev)
1094 {
1095         int i;
1096         struct nfp_net_hw *hw;
1097
1098         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1099
1100         /*
1101          * hw->eth_stats_base records the per counter starting point.
1102          * Lets update it now
1103          */
1104
1105         /* reading per RX ring stats */
1106         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1107                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1108                         break;
1109
1110                 hw->eth_stats_base.q_ipackets[i] =
1111                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1112
1113                 hw->eth_stats_base.q_ibytes[i] =
1114                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1115         }
1116
1117         /* reading per TX ring stats */
1118         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1119                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1120                         break;
1121
1122                 hw->eth_stats_base.q_opackets[i] =
1123                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1124
1125                 hw->eth_stats_base.q_obytes[i] =
1126                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1127         }
1128
1129         hw->eth_stats_base.ipackets =
1130                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1131
1132         hw->eth_stats_base.ibytes =
1133                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1134
1135         hw->eth_stats_base.opackets =
1136                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1137
1138         hw->eth_stats_base.obytes =
1139                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1140
1141         /* reading general device stats */
1142         hw->eth_stats_base.ierrors =
1143                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1144
1145         hw->eth_stats_base.oerrors =
1146                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1147
1148         /* RX ring mbuf allocation failures */
1149         dev->data->rx_mbuf_alloc_failed = 0;
1150
1151         hw->eth_stats_base.imissed =
1152                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1153 }
1154
1155 static void
1156 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1157 {
1158         struct nfp_net_hw *hw;
1159
1160         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1161
1162         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1163         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1164         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1165         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1166         dev_info->max_rx_pktlen = hw->max_mtu;
1167         /* Next should change when PF support is implemented */
1168         dev_info->max_mac_addrs = 1;
1169
1170         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1171                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1172
1173         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1174                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1175                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1176                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1177
1178         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1179                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1180
1181         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1182                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1183                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1184                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1185
1186         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1187                 .rx_thresh = {
1188                         .pthresh = DEFAULT_RX_PTHRESH,
1189                         .hthresh = DEFAULT_RX_HTHRESH,
1190                         .wthresh = DEFAULT_RX_WTHRESH,
1191                 },
1192                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1193                 .rx_drop_en = 0,
1194         };
1195
1196         dev_info->default_txconf = (struct rte_eth_txconf) {
1197                 .tx_thresh = {
1198                         .pthresh = DEFAULT_TX_PTHRESH,
1199                         .hthresh = DEFAULT_TX_HTHRESH,
1200                         .wthresh = DEFAULT_TX_WTHRESH,
1201                 },
1202                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1203                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1204                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1205                              ETH_TXQ_FLAGS_NOOFFLOADS,
1206         };
1207
1208         dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1209                                            ETH_RSS_NONFRAG_IPV4_UDP |
1210                                            ETH_RSS_NONFRAG_IPV6_TCP |
1211                                            ETH_RSS_NONFRAG_IPV6_UDP;
1212
1213         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1214         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1215
1216         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1217                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1218                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1219
1220         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1221                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1222 }
1223
1224 static const uint32_t *
1225 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1226 {
1227         static const uint32_t ptypes[] = {
1228                 /* refers to nfp_net_set_hash() */
1229                 RTE_PTYPE_INNER_L3_IPV4,
1230                 RTE_PTYPE_INNER_L3_IPV6,
1231                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1232                 RTE_PTYPE_INNER_L4_MASK,
1233                 RTE_PTYPE_UNKNOWN
1234         };
1235
1236         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1237                 return ptypes;
1238         return NULL;
1239 }
1240
1241 static uint32_t
1242 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1243 {
1244         struct nfp_net_rxq *rxq;
1245         struct nfp_net_rx_desc *rxds;
1246         uint32_t idx;
1247         uint32_t count;
1248
1249         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1250
1251         idx = rxq->rd_p;
1252
1253         count = 0;
1254
1255         /*
1256          * Other PMDs are just checking the DD bit in intervals of 4
1257          * descriptors and counting all four if the first has the DD
1258          * bit on. Of course, this is not accurate but can be good for
1259          * performance. But ideally that should be done in descriptors
1260          * chunks belonging to the same cache line
1261          */
1262
1263         while (count < rxq->rx_count) {
1264                 rxds = &rxq->rxds[idx];
1265                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1266                         break;
1267
1268                 count++;
1269                 idx++;
1270
1271                 /* Wrapping? */
1272                 if ((idx) == rxq->rx_count)
1273                         idx = 0;
1274         }
1275
1276         return count;
1277 }
1278
1279 static int
1280 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1281 {
1282         struct rte_pci_device *pci_dev;
1283         struct nfp_net_hw *hw;
1284         int base = 0;
1285
1286         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1287         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1288
1289         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1290                 base = 1;
1291
1292         /* Make sure all updates are written before un-masking */
1293         rte_wmb();
1294         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1295                       NFP_NET_CFG_ICR_UNMASKED);
1296         return 0;
1297 }
1298
1299 static int
1300 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1301 {
1302         struct rte_pci_device *pci_dev;
1303         struct nfp_net_hw *hw;
1304         int base = 0;
1305
1306         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1308
1309         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1310                 base = 1;
1311
1312         /* Make sure all updates are written before un-masking */
1313         rte_wmb();
1314         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1315         return 0;
1316 }
1317
1318 static void
1319 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1320 {
1321         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1322         struct rte_eth_link link;
1323
1324         rte_eth_linkstatus_get(dev, &link);
1325         if (link.link_status)
1326                 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1327                         dev->data->port_id, link.link_speed,
1328                         link.link_duplex == ETH_LINK_FULL_DUPLEX
1329                         ? "full-duplex" : "half-duplex");
1330         else
1331                 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1332                         dev->data->port_id);
1333
1334         RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1335                 pci_dev->addr.domain, pci_dev->addr.bus,
1336                 pci_dev->addr.devid, pci_dev->addr.function);
1337 }
1338
1339 /* Interrupt configuration and handling */
1340
1341 /*
1342  * nfp_net_irq_unmask - Unmask an interrupt
1343  *
1344  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1345  * clear the ICR for the entry.
1346  */
1347 static void
1348 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1349 {
1350         struct nfp_net_hw *hw;
1351         struct rte_pci_device *pci_dev;
1352
1353         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1355
1356         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1357                 /* If MSI-X auto-masking is used, clear the entry */
1358                 rte_wmb();
1359                 rte_intr_enable(&pci_dev->intr_handle);
1360         } else {
1361                 /* Make sure all updates are written before un-masking */
1362                 rte_wmb();
1363                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1364                               NFP_NET_CFG_ICR_UNMASKED);
1365         }
1366 }
1367
1368 static void
1369 nfp_net_dev_interrupt_handler(void *param)
1370 {
1371         int64_t timeout;
1372         struct rte_eth_link link;
1373         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1374
1375         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1376
1377         rte_eth_linkstatus_get(dev, &link);
1378
1379         nfp_net_link_update(dev, 0);
1380
1381         /* likely to up */
1382         if (!link.link_status) {
1383                 /* handle it 1 sec later, wait it being stable */
1384                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1385                 /* likely to down */
1386         } else {
1387                 /* handle it 4 sec later, wait it being stable */
1388                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1389         }
1390
1391         if (rte_eal_alarm_set(timeout * 1000,
1392                               nfp_net_dev_interrupt_delayed_handler,
1393                               (void *)dev) < 0) {
1394                 RTE_LOG(ERR, PMD, "Error setting alarm");
1395                 /* Unmasking */
1396                 nfp_net_irq_unmask(dev);
1397         }
1398 }
1399
1400 /*
1401  * Interrupt handler which shall be registered for alarm callback for delayed
1402  * handling specific interrupt to wait for the stable nic state. As the NIC
1403  * interrupt state is not stable for nfp after link is just down, it needs
1404  * to wait 4 seconds to get the stable status.
1405  *
1406  * @param handle   Pointer to interrupt handle.
1407  * @param param    The address of parameter (struct rte_eth_dev *)
1408  *
1409  * @return  void
1410  */
1411 static void
1412 nfp_net_dev_interrupt_delayed_handler(void *param)
1413 {
1414         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1415
1416         nfp_net_link_update(dev, 0);
1417         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1418
1419         nfp_net_dev_link_status_print(dev);
1420
1421         /* Unmasking */
1422         nfp_net_irq_unmask(dev);
1423 }
1424
1425 static int
1426 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1427 {
1428         struct nfp_net_hw *hw;
1429
1430         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1431
1432         /* check that mtu is within the allowed range */
1433         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1434                 return -EINVAL;
1435
1436         /* mtu setting is forbidden if port is started */
1437         if (dev->data->dev_started) {
1438                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1439                             dev->data->port_id);
1440                 return -EBUSY;
1441         }
1442
1443         /* switch to jumbo mode if needed */
1444         if ((uint32_t)mtu > ETHER_MAX_LEN)
1445                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1446         else
1447                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1448
1449         /* update max frame size */
1450         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1451
1452         /* writing to configuration space */
1453         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1454
1455         hw->mtu = mtu;
1456
1457         return 0;
1458 }
1459
1460 static int
1461 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1462                        uint16_t queue_idx, uint16_t nb_desc,
1463                        unsigned int socket_id,
1464                        const struct rte_eth_rxconf *rx_conf,
1465                        struct rte_mempool *mp)
1466 {
1467         const struct rte_memzone *tz;
1468         struct nfp_net_rxq *rxq;
1469         struct nfp_net_hw *hw;
1470
1471         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1472
1473         PMD_INIT_FUNC_TRACE();
1474
1475         /* Validating number of descriptors */
1476         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1477             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1478             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1479                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1480                 return -EINVAL;
1481         }
1482
1483         /*
1484          * Free memory prior to re-allocation if needed. This is the case after
1485          * calling nfp_net_stop
1486          */
1487         if (dev->data->rx_queues[queue_idx]) {
1488                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1489                 dev->data->rx_queues[queue_idx] = NULL;
1490         }
1491
1492         /* Allocating rx queue data structure */
1493         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1494                                  RTE_CACHE_LINE_SIZE, socket_id);
1495         if (rxq == NULL)
1496                 return -ENOMEM;
1497
1498         /* Hw queues mapping based on firmware confifguration */
1499         rxq->qidx = queue_idx;
1500         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1501         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1502         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1503         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1504
1505         /*
1506          * Tracking mbuf size for detecting a potential mbuf overflow due to
1507          * RX offset
1508          */
1509         rxq->mem_pool = mp;
1510         rxq->mbuf_size = rxq->mem_pool->elt_size;
1511         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1512         hw->flbufsz = rxq->mbuf_size;
1513
1514         rxq->rx_count = nb_desc;
1515         rxq->port_id = dev->data->port_id;
1516         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1517         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1518                                   : ETHER_CRC_LEN);
1519         rxq->drop_en = rx_conf->rx_drop_en;
1520
1521         /*
1522          * Allocate RX ring hardware descriptors. A memzone large enough to
1523          * handle the maximum ring size is allocated in order to allow for
1524          * resizing in later calls to the queue setup function.
1525          */
1526         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1527                                    sizeof(struct nfp_net_rx_desc) *
1528                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1529                                    socket_id);
1530
1531         if (tz == NULL) {
1532                 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1533                 nfp_net_rx_queue_release(rxq);
1534                 return -ENOMEM;
1535         }
1536
1537         /* Saving physical and virtual addresses for the RX ring */
1538         rxq->dma = (uint64_t)tz->iova;
1539         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1540
1541         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1542         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1543                                          sizeof(*rxq->rxbufs) * nb_desc,
1544                                          RTE_CACHE_LINE_SIZE, socket_id);
1545         if (rxq->rxbufs == NULL) {
1546                 nfp_net_rx_queue_release(rxq);
1547                 return -ENOMEM;
1548         }
1549
1550         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1551                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1552
1553         nfp_net_reset_rx_queue(rxq);
1554
1555         dev->data->rx_queues[queue_idx] = rxq;
1556         rxq->hw = hw;
1557
1558         /*
1559          * Telling the HW about the physical address of the RX ring and number
1560          * of descriptors in log2 format
1561          */
1562         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1563         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1564
1565         return 0;
1566 }
1567
1568 static int
1569 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1570 {
1571         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1572         uint64_t dma_addr;
1573         unsigned i;
1574
1575         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1576                    rxq->rx_count);
1577
1578         for (i = 0; i < rxq->rx_count; i++) {
1579                 struct nfp_net_rx_desc *rxd;
1580                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1581
1582                 if (mbuf == NULL) {
1583                         RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1584                                 (unsigned)rxq->qidx);
1585                         return -ENOMEM;
1586                 }
1587
1588                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1589
1590                 rxd = &rxq->rxds[i];
1591                 rxd->fld.dd = 0;
1592                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1593                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1594                 rxe[i].mbuf = mbuf;
1595                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1596         }
1597
1598         /* Make sure all writes are flushed before telling the hardware */
1599         rte_wmb();
1600
1601         /* Not advertising the whole ring as the firmware gets confused if so */
1602         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1603                    rxq->rx_count - 1);
1604
1605         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1606
1607         return 0;
1608 }
1609
1610 static int
1611 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1612                        uint16_t nb_desc, unsigned int socket_id,
1613                        const struct rte_eth_txconf *tx_conf)
1614 {
1615         const struct rte_memzone *tz;
1616         struct nfp_net_txq *txq;
1617         uint16_t tx_free_thresh;
1618         struct nfp_net_hw *hw;
1619
1620         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1621
1622         PMD_INIT_FUNC_TRACE();
1623
1624         /* Validating number of descriptors */
1625         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1626             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1627             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1628                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1629                 return -EINVAL;
1630         }
1631
1632         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1633                                     tx_conf->tx_free_thresh :
1634                                     DEFAULT_TX_FREE_THRESH);
1635
1636         if (tx_free_thresh > (nb_desc)) {
1637                 RTE_LOG(ERR, PMD,
1638                         "tx_free_thresh must be less than the number of TX "
1639                         "descriptors. (tx_free_thresh=%u port=%d "
1640                         "queue=%d)\n", (unsigned int)tx_free_thresh,
1641                         dev->data->port_id, (int)queue_idx);
1642                 return -(EINVAL);
1643         }
1644
1645         /*
1646          * Free memory prior to re-allocation if needed. This is the case after
1647          * calling nfp_net_stop
1648          */
1649         if (dev->data->tx_queues[queue_idx]) {
1650                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1651                            queue_idx);
1652                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1653                 dev->data->tx_queues[queue_idx] = NULL;
1654         }
1655
1656         /* Allocating tx queue data structure */
1657         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1658                                  RTE_CACHE_LINE_SIZE, socket_id);
1659         if (txq == NULL) {
1660                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1661                 return -ENOMEM;
1662         }
1663
1664         /*
1665          * Allocate TX ring hardware descriptors. A memzone large enough to
1666          * handle the maximum ring size is allocated in order to allow for
1667          * resizing in later calls to the queue setup function.
1668          */
1669         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1670                                    sizeof(struct nfp_net_tx_desc) *
1671                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1672                                    socket_id);
1673         if (tz == NULL) {
1674                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1675                 nfp_net_tx_queue_release(txq);
1676                 return -ENOMEM;
1677         }
1678
1679         txq->tx_count = nb_desc;
1680         txq->tx_free_thresh = tx_free_thresh;
1681         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1682         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1683         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1684
1685         /* queue mapping based on firmware configuration */
1686         txq->qidx = queue_idx;
1687         txq->tx_qcidx = queue_idx * hw->stride_tx;
1688         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1689
1690         txq->port_id = dev->data->port_id;
1691         txq->txq_flags = tx_conf->txq_flags;
1692
1693         /* Saving physical and virtual addresses for the TX ring */
1694         txq->dma = (uint64_t)tz->iova;
1695         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1696
1697         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1698         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1699                                          sizeof(*txq->txbufs) * nb_desc,
1700                                          RTE_CACHE_LINE_SIZE, socket_id);
1701         if (txq->txbufs == NULL) {
1702                 nfp_net_tx_queue_release(txq);
1703                 return -ENOMEM;
1704         }
1705         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1706                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1707
1708         nfp_net_reset_tx_queue(txq);
1709
1710         dev->data->tx_queues[queue_idx] = txq;
1711         txq->hw = hw;
1712
1713         /*
1714          * Telling the HW about the physical address of the TX ring and number
1715          * of descriptors in log2 format
1716          */
1717         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1718         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1719
1720         return 0;
1721 }
1722
1723 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1724 static inline void
1725 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1726                struct rte_mbuf *mb)
1727 {
1728         uint64_t ol_flags;
1729         struct nfp_net_hw *hw = txq->hw;
1730
1731         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1732                 goto clean_txd;
1733
1734         ol_flags = mb->ol_flags;
1735
1736         if (!(ol_flags & PKT_TX_TCP_SEG))
1737                 goto clean_txd;
1738
1739         txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1740         txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1741         txd->flags = PCIE_DESC_TX_LSO;
1742         return;
1743
1744 clean_txd:
1745         txd->flags = 0;
1746         txd->l4_offset = 0;
1747         txd->lso = 0;
1748 }
1749
1750 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1751 static inline void
1752 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1753                  struct rte_mbuf *mb)
1754 {
1755         uint64_t ol_flags;
1756         struct nfp_net_hw *hw = txq->hw;
1757
1758         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1759                 return;
1760
1761         ol_flags = mb->ol_flags;
1762
1763         /* IPv6 does not need checksum */
1764         if (ol_flags & PKT_TX_IP_CKSUM)
1765                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1766
1767         switch (ol_flags & PKT_TX_L4_MASK) {
1768         case PKT_TX_UDP_CKSUM:
1769                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1770                 break;
1771         case PKT_TX_TCP_CKSUM:
1772                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1773                 break;
1774         }
1775
1776         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1777                 txd->flags |= PCIE_DESC_TX_CSUM;
1778 }
1779
1780 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1781 static inline void
1782 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1783                  struct rte_mbuf *mb)
1784 {
1785         struct nfp_net_hw *hw = rxq->hw;
1786
1787         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1788                 return;
1789
1790         /* If IPv4 and IP checksum error, fail */
1791         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1792             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1793                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1794
1795         /* If neither UDP nor TCP return */
1796         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1797             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1798                 return;
1799
1800         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1801             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1802                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1803
1804         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1805             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1806                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1807 }
1808
1809 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1810 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1811
1812 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1813
1814 /*
1815  * nfp_net_set_hash - Set mbuf hash data
1816  *
1817  * The RSS hash and hash-type are pre-pended to the packet data.
1818  * Extract and decode it and set the mbuf fields.
1819  */
1820 static inline void
1821 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1822                  struct rte_mbuf *mbuf)
1823 {
1824         struct nfp_net_hw *hw = rxq->hw;
1825         uint8_t *meta_offset;
1826         uint32_t meta_info;
1827         uint32_t hash = 0;
1828         uint32_t hash_type = 0;
1829
1830         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1831                 return;
1832
1833         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1834                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1835                         return;
1836
1837                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1838                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1839
1840         } else if (NFP_DESC_META_LEN(rxd)) {
1841                 /*
1842                  * new metadata api:
1843                  * <----  32 bit  ----->
1844                  * m    field type word
1845                  * e     data field #2
1846                  * t     data field #1
1847                  * a     data field #0
1848                  * ====================
1849                  *    packet data
1850                  *
1851                  * Field type word contains up to 8 4bit field types
1852                  * A 4bit field type refers to a data field word
1853                  * A data field word can have several 4bit field types
1854                  */
1855                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1856                 meta_offset -= NFP_DESC_META_LEN(rxd);
1857                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1858                 meta_offset += 4;
1859                 /* NFP PMD just supports metadata for hashing */
1860                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1861                 case NFP_NET_META_HASH:
1862                         /* next field type is about the hash type */
1863                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1864                         /* hash value is in the data field */
1865                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1866                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1867                         break;
1868                 default:
1869                         /* Unsupported metadata can be a performance issue */
1870                         return;
1871                 }
1872         } else {
1873                 return;
1874         }
1875
1876         mbuf->hash.rss = hash;
1877         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1878
1879         switch (hash_type) {
1880         case NFP_NET_RSS_IPV4:
1881                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1882                 break;
1883         case NFP_NET_RSS_IPV6:
1884                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1885                 break;
1886         case NFP_NET_RSS_IPV6_EX:
1887                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1888                 break;
1889         default:
1890                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1891         }
1892 }
1893
1894 static inline void
1895 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1896 {
1897         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1898 }
1899
1900 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1901
1902 /*
1903  * RX path design:
1904  *
1905  * There are some decissions to take:
1906  * 1) How to check DD RX descriptors bit
1907  * 2) How and when to allocate new mbufs
1908  *
1909  * Current implementation checks just one single DD bit each loop. As each
1910  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1911  * a single cache line instead. Tests with this change have not shown any
1912  * performance improvement but it requires further investigation. For example,
1913  * depending on which descriptor is next, the number of descriptors could be
1914  * less than 8 for just checking those in the same cache line. This implies
1915  * extra work which could be counterproductive by itself. Indeed, last firmware
1916  * changes are just doing this: writing several descriptors with the DD bit
1917  * for saving PCIe bandwidth and DMA operations from the NFP.
1918  *
1919  * Mbuf allocation is done when a new packet is received. Then the descriptor
1920  * is automatically linked with the new mbuf and the old one is given to the
1921  * user. The main drawback with this design is mbuf allocation is heavier than
1922  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1923  * cache point of view it does not seem allocating the mbuf early on as we are
1924  * doing now have any benefit at all. Again, tests with this change have not
1925  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1926  * so looking at the implications of this type of allocation should be studied
1927  * deeply
1928  */
1929
1930 static uint16_t
1931 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1932 {
1933         struct nfp_net_rxq *rxq;
1934         struct nfp_net_rx_desc *rxds;
1935         struct nfp_net_rx_buff *rxb;
1936         struct nfp_net_hw *hw;
1937         struct rte_mbuf *mb;
1938         struct rte_mbuf *new_mb;
1939         uint16_t nb_hold;
1940         uint64_t dma_addr;
1941         int avail;
1942
1943         rxq = rx_queue;
1944         if (unlikely(rxq == NULL)) {
1945                 /*
1946                  * DPDK just checks the queue is lower than max queues
1947                  * enabled. But the queue needs to be configured
1948                  */
1949                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1950                 return -EINVAL;
1951         }
1952
1953         hw = rxq->hw;
1954         avail = 0;
1955         nb_hold = 0;
1956
1957         while (avail < nb_pkts) {
1958                 rxb = &rxq->rxbufs[rxq->rd_p];
1959                 if (unlikely(rxb == NULL)) {
1960                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1961                         break;
1962                 }
1963
1964                 rxds = &rxq->rxds[rxq->rd_p];
1965                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1966                         break;
1967
1968                 /*
1969                  * Memory barrier to ensure that we won't do other
1970                  * reads before the DD bit.
1971                  */
1972                 rte_rmb();
1973
1974                 /*
1975                  * We got a packet. Let's alloc a new mbuff for refilling the
1976                  * free descriptor ring as soon as possible
1977                  */
1978                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1979                 if (unlikely(new_mb == NULL)) {
1980                         RTE_LOG_DP(DEBUG, PMD,
1981                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
1982                                 rxq->port_id, (unsigned int)rxq->qidx);
1983                         nfp_net_mbuf_alloc_failed(rxq);
1984                         break;
1985                 }
1986
1987                 nb_hold++;
1988
1989                 /*
1990                  * Grab the mbuff and refill the descriptor with the
1991                  * previously allocated mbuff
1992                  */
1993                 mb = rxb->mbuf;
1994                 rxb->mbuf = new_mb;
1995
1996                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1997                            rxds->rxd.data_len, rxq->mbuf_size);
1998
1999                 /* Size of this segment */
2000                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2001                 /* Size of the whole packet. We just support 1 segment */
2002                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2003
2004                 if (unlikely((mb->data_len + hw->rx_offset) >
2005                              rxq->mbuf_size)) {
2006                         /*
2007                          * This should not happen and the user has the
2008                          * responsibility of avoiding it. But we have
2009                          * to give some info about the error
2010                          */
2011                         RTE_LOG_DP(ERR, PMD,
2012                                 "mbuf overflow likely due to the RX offset.\n"
2013                                 "\t\tYour mbuf size should have extra space for"
2014                                 " RX offset=%u bytes.\n"
2015                                 "\t\tCurrently you just have %u bytes available"
2016                                 " but the received packet is %u bytes long",
2017                                 hw->rx_offset,
2018                                 rxq->mbuf_size - hw->rx_offset,
2019                                 mb->data_len);
2020                         return -EINVAL;
2021                 }
2022
2023                 /* Filling the received mbuff with packet info */
2024                 if (hw->rx_offset)
2025                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2026                 else
2027                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2028                                        NFP_DESC_META_LEN(rxds);
2029
2030                 /* No scatter mode supported */
2031                 mb->nb_segs = 1;
2032                 mb->next = NULL;
2033
2034                 mb->port = rxq->port_id;
2035
2036                 /* Checking the RSS flag */
2037                 nfp_net_set_hash(rxq, rxds, mb);
2038
2039                 /* Checking the checksum flag */
2040                 nfp_net_rx_cksum(rxq, rxds, mb);
2041
2042                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2043                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2044                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2045                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2046                 }
2047
2048                 /* Adding the mbuff to the mbuff array passed by the app */
2049                 rx_pkts[avail++] = mb;
2050
2051                 /* Now resetting and updating the descriptor */
2052                 rxds->vals[0] = 0;
2053                 rxds->vals[1] = 0;
2054                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2055                 rxds->fld.dd = 0;
2056                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2057                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2058
2059                 rxq->rd_p++;
2060                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2061                         rxq->rd_p = 0;
2062         }
2063
2064         if (nb_hold == 0)
2065                 return nb_hold;
2066
2067         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received\n",
2068                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2069
2070         nb_hold += rxq->nb_rx_hold;
2071
2072         /*
2073          * FL descriptors needs to be written before incrementing the
2074          * FL queue WR pointer
2075          */
2076         rte_wmb();
2077         if (nb_hold > rxq->rx_free_thresh) {
2078                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2079                            rxq->port_id, (unsigned int)rxq->qidx,
2080                            (unsigned)nb_hold, (unsigned)avail);
2081                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2082                 nb_hold = 0;
2083         }
2084         rxq->nb_rx_hold = nb_hold;
2085
2086         return avail;
2087 }
2088
2089 /*
2090  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2091  * status
2092  * @txq: TX queue to work with
2093  * Returns number of descriptors freed
2094  */
2095 int
2096 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2097 {
2098         uint32_t qcp_rd_p;
2099         int todo;
2100
2101         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2102                    " status\n", txq->qidx);
2103
2104         /* Work out how many packets have been sent */
2105         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2106
2107         if (qcp_rd_p == txq->rd_p) {
2108                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2109                            "packets (%u, %u)\n", txq->qidx,
2110                            qcp_rd_p, txq->rd_p);
2111                 return 0;
2112         }
2113
2114         if (qcp_rd_p > txq->rd_p)
2115                 todo = qcp_rd_p - txq->rd_p;
2116         else
2117                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2118
2119         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2120                    qcp_rd_p, txq->rd_p, txq->rd_p);
2121
2122         if (todo == 0)
2123                 return todo;
2124
2125         txq->rd_p += todo;
2126         if (unlikely(txq->rd_p >= txq->tx_count))
2127                 txq->rd_p -= txq->tx_count;
2128
2129         return todo;
2130 }
2131
2132 /* Leaving always free descriptors for avoiding wrapping confusion */
2133 static inline
2134 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2135 {
2136         if (txq->wr_p >= txq->rd_p)
2137                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2138         else
2139                 return txq->rd_p - txq->wr_p - 8;
2140 }
2141
2142 /*
2143  * nfp_net_txq_full - Check if the TX queue free descriptors
2144  * is below tx_free_threshold
2145  *
2146  * @txq: TX queue to check
2147  *
2148  * This function uses the host copy* of read/write pointers
2149  */
2150 static inline
2151 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2152 {
2153         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2154 }
2155
2156 static uint16_t
2157 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2158 {
2159         struct nfp_net_txq *txq;
2160         struct nfp_net_hw *hw;
2161         struct nfp_net_tx_desc *txds, txd;
2162         struct rte_mbuf *pkt;
2163         uint64_t dma_addr;
2164         int pkt_size, dma_size;
2165         uint16_t free_descs, issued_descs;
2166         struct rte_mbuf **lmbuf;
2167         int i;
2168
2169         txq = tx_queue;
2170         hw = txq->hw;
2171         txds = &txq->txds[txq->wr_p];
2172
2173         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2174                    txq->qidx, txq->wr_p, nb_pkts);
2175
2176         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2177                 nfp_net_tx_free_bufs(txq);
2178
2179         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2180         if (unlikely(free_descs == 0))
2181                 return 0;
2182
2183         pkt = *tx_pkts;
2184
2185         i = 0;
2186         issued_descs = 0;
2187         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2188                    txq->qidx, nb_pkts);
2189         /* Sending packets */
2190         while ((i < nb_pkts) && free_descs) {
2191                 /* Grabbing the mbuf linked to the current descriptor */
2192                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2193                 /* Warming the cache for releasing the mbuf later on */
2194                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2195
2196                 pkt = *(tx_pkts + i);
2197
2198                 if (unlikely((pkt->nb_segs > 1) &&
2199                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2200                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2201                         rte_panic("Multisegment packet unsupported\n");
2202                 }
2203
2204                 /* Checking if we have enough descriptors */
2205                 if (unlikely(pkt->nb_segs > free_descs))
2206                         goto xmit_end;
2207
2208                 /*
2209                  * Checksum and VLAN flags just in the first descriptor for a
2210                  * multisegment packet, but TSO info needs to be in all of them.
2211                  */
2212                 txd.data_len = pkt->pkt_len;
2213                 nfp_net_tx_tso(txq, &txd, pkt);
2214                 nfp_net_tx_cksum(txq, &txd, pkt);
2215
2216                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2217                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2218                         txd.flags |= PCIE_DESC_TX_VLAN;
2219                         txd.vlan = pkt->vlan_tci;
2220                 }
2221
2222                 /*
2223                  * mbuf data_len is the data in one segment and pkt_len data
2224                  * in the whole packet. When the packet is just one segment,
2225                  * then data_len = pkt_len
2226                  */
2227                 pkt_size = pkt->pkt_len;
2228
2229                 while (pkt) {
2230                         /* Copying TSO, VLAN and cksum info */
2231                         *txds = txd;
2232
2233                         /* Releasing mbuf used by this descriptor previously*/
2234                         if (*lmbuf)
2235                                 rte_pktmbuf_free_seg(*lmbuf);
2236
2237                         /*
2238                          * Linking mbuf with descriptor for being released
2239                          * next time descriptor is used
2240                          */
2241                         *lmbuf = pkt;
2242
2243                         dma_size = pkt->data_len;
2244                         dma_addr = rte_mbuf_data_iova(pkt);
2245                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2246                                    "%" PRIx64 "\n", dma_addr);
2247
2248                         /* Filling descriptors fields */
2249                         txds->dma_len = dma_size;
2250                         txds->data_len = txd.data_len;
2251                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2252                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2253                         ASSERT(free_descs > 0);
2254                         free_descs--;
2255
2256                         txq->wr_p++;
2257                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2258                                 txq->wr_p = 0;
2259
2260                         pkt_size -= dma_size;
2261                         if (!pkt_size)
2262                                 /* End of packet */
2263                                 txds->offset_eop |= PCIE_DESC_TX_EOP;
2264                         else
2265                                 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2266
2267                         pkt = pkt->next;
2268                         /* Referencing next free TX descriptor */
2269                         txds = &txq->txds[txq->wr_p];
2270                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2271                         issued_descs++;
2272                 }
2273                 i++;
2274         }
2275
2276 xmit_end:
2277         /* Increment write pointers. Force memory write before we let HW know */
2278         rte_wmb();
2279         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2280
2281         return i;
2282 }
2283
2284 static int
2285 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2286 {
2287         uint32_t new_ctrl, update;
2288         struct nfp_net_hw *hw;
2289         int ret;
2290
2291         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2292         new_ctrl = 0;
2293
2294         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2295             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2296                 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2297                         " ETH_VLAN_EXTEND_OFFLOAD");
2298
2299         /* Enable vlan strip if it is not configured yet */
2300         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2301             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2302                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2303
2304         /* Disable vlan strip just if it is configured */
2305         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2306             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2307                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2308
2309         if (new_ctrl == 0)
2310                 return 0;
2311
2312         update = NFP_NET_CFG_UPDATE_GEN;
2313
2314         ret = nfp_net_reconfig(hw, new_ctrl, update);
2315         if (!ret)
2316                 hw->ctrl = new_ctrl;
2317
2318         return ret;
2319 }
2320
2321 static int
2322 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2323                     struct rte_eth_rss_reta_entry64 *reta_conf,
2324                     uint16_t reta_size)
2325 {
2326         uint32_t reta, mask;
2327         int i, j;
2328         int idx, shift;
2329         struct nfp_net_hw *hw =
2330                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331
2332         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2333                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2334                         "(%d) doesn't match the number hardware can supported "
2335                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2336                 return -EINVAL;
2337         }
2338
2339         /*
2340          * Update Redirection Table. There are 128 8bit-entries which can be
2341          * manage as 32 32bit-entries
2342          */
2343         for (i = 0; i < reta_size; i += 4) {
2344                 /* Handling 4 RSS entries per loop */
2345                 idx = i / RTE_RETA_GROUP_SIZE;
2346                 shift = i % RTE_RETA_GROUP_SIZE;
2347                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2348
2349                 if (!mask)
2350                         continue;
2351
2352                 reta = 0;
2353                 /* If all 4 entries were set, don't need read RETA register */
2354                 if (mask != 0xF)
2355                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2356
2357                 for (j = 0; j < 4; j++) {
2358                         if (!(mask & (0x1 << j)))
2359                                 continue;
2360                         if (mask != 0xF)
2361                                 /* Clearing the entry bits */
2362                                 reta &= ~(0xFF << (8 * j));
2363                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2364                 }
2365                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2366                               reta);
2367         }
2368         return 0;
2369 }
2370
2371 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2372 static int
2373 nfp_net_reta_update(struct rte_eth_dev *dev,
2374                     struct rte_eth_rss_reta_entry64 *reta_conf,
2375                     uint16_t reta_size)
2376 {
2377         struct nfp_net_hw *hw =
2378                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379         uint32_t update;
2380         int ret;
2381
2382         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2383                 return -EINVAL;
2384
2385         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2386         if (ret != 0)
2387                 return ret;
2388
2389         update = NFP_NET_CFG_UPDATE_RSS;
2390
2391         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2392                 return -EIO;
2393
2394         return 0;
2395 }
2396
2397  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2398 static int
2399 nfp_net_reta_query(struct rte_eth_dev *dev,
2400                    struct rte_eth_rss_reta_entry64 *reta_conf,
2401                    uint16_t reta_size)
2402 {
2403         uint8_t i, j, mask;
2404         int idx, shift;
2405         uint32_t reta;
2406         struct nfp_net_hw *hw;
2407
2408         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409
2410         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2411                 return -EINVAL;
2412
2413         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2414                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2415                         "(%d) doesn't match the number hardware can supported "
2416                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2417                 return -EINVAL;
2418         }
2419
2420         /*
2421          * Reading Redirection Table. There are 128 8bit-entries which can be
2422          * manage as 32 32bit-entries
2423          */
2424         for (i = 0; i < reta_size; i += 4) {
2425                 /* Handling 4 RSS entries per loop */
2426                 idx = i / RTE_RETA_GROUP_SIZE;
2427                 shift = i % RTE_RETA_GROUP_SIZE;
2428                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2429
2430                 if (!mask)
2431                         continue;
2432
2433                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2434                                     shift);
2435                 for (j = 0; j < 4; j++) {
2436                         if (!(mask & (0x1 << j)))
2437                                 continue;
2438                         reta_conf->reta[shift + j] =
2439                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2440                 }
2441         }
2442         return 0;
2443 }
2444
2445 static int
2446 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2447                         struct rte_eth_rss_conf *rss_conf)
2448 {
2449         struct nfp_net_hw *hw;
2450         uint64_t rss_hf;
2451         uint32_t cfg_rss_ctrl = 0;
2452         uint8_t key;
2453         int i;
2454
2455         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456
2457         /* Writing the key byte a byte */
2458         for (i = 0; i < rss_conf->rss_key_len; i++) {
2459                 memcpy(&key, &rss_conf->rss_key[i], 1);
2460                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2461         }
2462
2463         rss_hf = rss_conf->rss_hf;
2464
2465         if (rss_hf & ETH_RSS_IPV4)
2466                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2467                                 NFP_NET_CFG_RSS_IPV4_TCP |
2468                                 NFP_NET_CFG_RSS_IPV4_UDP;
2469
2470         if (rss_hf & ETH_RSS_IPV6)
2471                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2472                                 NFP_NET_CFG_RSS_IPV6_TCP |
2473                                 NFP_NET_CFG_RSS_IPV6_UDP;
2474
2475         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2476         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2477
2478         /* configuring where to apply the RSS hash */
2479         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2480
2481         /* Writing the key size */
2482         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2483
2484         return 0;
2485 }
2486
2487 static int
2488 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2489                         struct rte_eth_rss_conf *rss_conf)
2490 {
2491         uint32_t update;
2492         uint64_t rss_hf;
2493         struct nfp_net_hw *hw;
2494
2495         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496
2497         rss_hf = rss_conf->rss_hf;
2498
2499         /* Checking if RSS is enabled */
2500         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2501                 if (rss_hf != 0) { /* Enable RSS? */
2502                         RTE_LOG(ERR, PMD, "RSS unsupported\n");
2503                         return -EINVAL;
2504                 }
2505                 return 0; /* Nothing to do */
2506         }
2507
2508         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2509                 RTE_LOG(ERR, PMD, "hash key too long\n");
2510                 return -EINVAL;
2511         }
2512
2513         nfp_net_rss_hash_write(dev, rss_conf);
2514
2515         update = NFP_NET_CFG_UPDATE_RSS;
2516
2517         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2518                 return -EIO;
2519
2520         return 0;
2521 }
2522
2523 static int
2524 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2525                           struct rte_eth_rss_conf *rss_conf)
2526 {
2527         uint64_t rss_hf;
2528         uint32_t cfg_rss_ctrl;
2529         uint8_t key;
2530         int i;
2531         struct nfp_net_hw *hw;
2532
2533         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534
2535         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2536                 return -EINVAL;
2537
2538         rss_hf = rss_conf->rss_hf;
2539         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2540
2541         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2542                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2543
2544         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2545                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2546
2547         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2548                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2549
2550         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2551                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2552
2553         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2554                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2555
2556         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2557                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2558
2559         /* Reading the key size */
2560         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2561
2562         /* Reading the key byte a byte */
2563         for (i = 0; i < rss_conf->rss_key_len; i++) {
2564                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2565                 memcpy(&rss_conf->rss_key[i], &key, 1);
2566         }
2567
2568         return 0;
2569 }
2570
2571 static int
2572 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2573 {
2574         struct rte_eth_conf *dev_conf;
2575         struct rte_eth_rss_conf rss_conf;
2576         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2577         uint16_t rx_queues = dev->data->nb_rx_queues;
2578         uint16_t queue;
2579         int i, j, ret;
2580
2581         RTE_LOG(INFO, PMD, "setting default RSS conf for %u queues\n",
2582                 rx_queues);
2583
2584         nfp_reta_conf[0].mask = ~0x0;
2585         nfp_reta_conf[1].mask = ~0x0;
2586
2587         queue = 0;
2588         for (i = 0; i < 0x40; i += 8) {
2589                 for (j = i; j < (i + 8); j++) {
2590                         nfp_reta_conf[0].reta[j] = queue;
2591                         nfp_reta_conf[1].reta[j] = queue++;
2592                         queue %= rx_queues;
2593                 }
2594         }
2595         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2596         if (ret != 0)
2597                 return ret;
2598
2599         dev_conf = &dev->data->dev_conf;
2600         if (!dev_conf) {
2601                 RTE_LOG(INFO, PMD, "wrong rss conf");
2602                 return -EINVAL;
2603         }
2604         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2605
2606         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2607
2608         return ret;
2609 }
2610
2611
2612 /* Initialise and register driver with DPDK Application */
2613 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2614         .dev_configure          = nfp_net_configure,
2615         .dev_start              = nfp_net_start,
2616         .dev_stop               = nfp_net_stop,
2617         .dev_close              = nfp_net_close,
2618         .promiscuous_enable     = nfp_net_promisc_enable,
2619         .promiscuous_disable    = nfp_net_promisc_disable,
2620         .link_update            = nfp_net_link_update,
2621         .stats_get              = nfp_net_stats_get,
2622         .stats_reset            = nfp_net_stats_reset,
2623         .dev_infos_get          = nfp_net_infos_get,
2624         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2625         .mtu_set                = nfp_net_dev_mtu_set,
2626         .vlan_offload_set       = nfp_net_vlan_offload_set,
2627         .reta_update            = nfp_net_reta_update,
2628         .reta_query             = nfp_net_reta_query,
2629         .rss_hash_update        = nfp_net_rss_hash_update,
2630         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2631         .rx_queue_setup         = nfp_net_rx_queue_setup,
2632         .rx_queue_release       = nfp_net_rx_queue_release,
2633         .rx_queue_count         = nfp_net_rx_queue_count,
2634         .tx_queue_setup         = nfp_net_tx_queue_setup,
2635         .tx_queue_release       = nfp_net_tx_queue_release,
2636         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2637         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2638 };
2639
2640 /*
2641  * All eth_dev created got its private data, but before nfp_net_init, that
2642  * private data is referencing private data for all the PF ports. This is due
2643  * to how the vNIC bars are mapped based on first port, so all ports need info
2644  * about port 0 private data. Inside nfp_net_init the private data pointer is
2645  * changed to the right address for each port once the bars have been mapped.
2646  *
2647  * This functions helps to find out which port and therefore which offset
2648  * inside the private data array to use.
2649  */
2650 static int
2651 get_pf_port_number(char *name)
2652 {
2653         char *pf_str = name;
2654         int size = 0;
2655
2656         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2657                 pf_str++;
2658
2659         if (size == 30)
2660                 /*
2661                  * This should not happen at all and it would mean major
2662                  * implementation fault.
2663                  */
2664                 rte_panic("nfp_net: problem with pf device name\n");
2665
2666         /* Expecting _portX with X within [0,7] */
2667         pf_str += 5;
2668
2669         return (int)strtol(pf_str, NULL, 10);
2670 }
2671
2672 static int
2673 nfp_net_init(struct rte_eth_dev *eth_dev)
2674 {
2675         struct rte_pci_device *pci_dev;
2676         struct nfp_net_hw *hw, *hwport0;
2677
2678         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2679         uint32_t start_q;
2680         int stride = 4;
2681
2682         nspu_desc_t *nspu_desc = NULL;
2683         uint64_t bar_offset;
2684         int port = 0;
2685
2686         PMD_INIT_FUNC_TRACE();
2687
2688         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2689
2690         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2691             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2692                 port = get_pf_port_number(eth_dev->data->name);
2693                 if (port < 0 || port > 7) {
2694                         RTE_LOG(ERR, PMD, "Port value is wrong\n");
2695                         return -ENODEV;
2696                 }
2697
2698                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2699
2700                 /* This points to port 0 private data */
2701                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2702
2703                 /* This points to the specific port private data */
2704                 hw = &hwport0[port];
2705                 hw->pf_port_idx = port;
2706         } else {
2707                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2708                 hwport0 = 0;
2709         }
2710
2711         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2712         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2713         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2714
2715         /* For secondary processes, the primary has done all the work */
2716         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2717                 return 0;
2718
2719         rte_eth_copy_pci_info(eth_dev, pci_dev);
2720
2721         hw->device_id = pci_dev->id.device_id;
2722         hw->vendor_id = pci_dev->id.vendor_id;
2723         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2724         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2725
2726         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2727                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2728                      pci_dev->addr.domain, pci_dev->addr.bus,
2729                      pci_dev->addr.devid, pci_dev->addr.function);
2730
2731         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2732         if (hw->ctrl_bar == NULL) {
2733                 RTE_LOG(ERR, PMD,
2734                         "hw->ctrl_bar is NULL. BAR0 not configured\n");
2735                 return -ENODEV;
2736         }
2737
2738         if (hw->is_pf && port == 0) {
2739                 nspu_desc = hw->nspu_desc;
2740
2741                 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2742                         /*
2743                          * A firmware should be there after PF probe so this
2744                          * should not happen.
2745                          */
2746                         RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2747                         return -ENODEV;
2748                 }
2749
2750                 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2751                 hw->ctrl_bar += bar_offset;
2752                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2753         }
2754
2755         if (port > 0) {
2756                 if (!hwport0->ctrl_bar)
2757                         return -ENODEV;
2758
2759                 /* address based on port0 offset */
2760                 hw->ctrl_bar = hwport0->ctrl_bar +
2761                                (port * NFP_PF_CSR_SLICE_SIZE);
2762         }
2763
2764         PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2765
2766         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2767         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2768
2769         /* Work out where in the BAR the queues start. */
2770         switch (pci_dev->id.device_id) {
2771         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2772         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2773         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2774                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2775                 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2776                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2777                 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2778                 break;
2779         default:
2780                 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2781                 return -ENODEV;
2782         }
2783
2784         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2785         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2786
2787         if (hw->is_pf && port == 0) {
2788                 /* configure access to tx/rx vNIC BARs */
2789                 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2790                 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2791                                     bar_offset);
2792                 hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2793
2794                 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2795                 hwport0->hw_queues += bar_offset;
2796
2797                 /* Lets seize the chance to read eth table from hw */
2798                 if (nfp_nsp_eth_read_table(nspu_desc, &hw->eth_table))
2799                         return -ENODEV;
2800         }
2801
2802         if (hw->is_pf) {
2803                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2804                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2805                 eth_dev->data->dev_private = hw;
2806         } else {
2807                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2808                              tx_bar_off;
2809                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2810                              rx_bar_off;
2811         }
2812
2813         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2814                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2815
2816         nfp_net_cfg_queue_setup(hw);
2817
2818         /* Get some of the read-only fields from the config BAR */
2819         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2820         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2821         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2822         hw->mtu = ETHER_MTU;
2823
2824         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2825                 hw->rx_offset = NFP_NET_RX_OFFSET;
2826         else
2827                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2828
2829         PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2830                      hw->ver, hw->max_mtu);
2831         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2832                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2833                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2834                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2835                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2836                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2837                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2838                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2839                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2840                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2841                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2842                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "");
2843
2844         hw->ctrl = 0;
2845
2846         hw->stride_rx = stride;
2847         hw->stride_tx = stride;
2848
2849         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2850                      hw->max_rx_queues, hw->max_tx_queues);
2851
2852         /* Initializing spinlock for reconfigs */
2853         rte_spinlock_init(&hw->reconfig_lock);
2854
2855         /* Allocating memory for mac addr */
2856         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2857         if (eth_dev->data->mac_addrs == NULL) {
2858                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2859                 return -ENOMEM;
2860         }
2861
2862         if (hw->is_pf) {
2863                 nfp_net_pf_read_mac(hwport0, port);
2864                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2865         } else {
2866                 nfp_net_vf_read_mac(hw);
2867         }
2868
2869         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2870                 /* Using random mac addresses for VFs */
2871                 eth_random_addr(&hw->mac_addr[0]);
2872                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2873         }
2874
2875         /* Copying mac address to DPDK eth_dev struct */
2876         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2877                         &eth_dev->data->mac_addrs[0]);
2878
2879         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2880                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2881                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2882                      pci_dev->id.device_id,
2883                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2884                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2885
2886         /* Registering LSC interrupt handler */
2887         rte_intr_callback_register(&pci_dev->intr_handle,
2888                                    nfp_net_dev_interrupt_handler,
2889                                    (void *)eth_dev);
2890
2891         /* Telling the firmware about the LSC interrupt entry */
2892         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2893
2894         /* Recording current stats counters values */
2895         nfp_net_stats_reset(eth_dev);
2896
2897         return 0;
2898 }
2899
2900 static int
2901 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2902                   nfpu_desc_t *nfpu_desc, void **priv)
2903 {
2904         struct rte_eth_dev *eth_dev;
2905         struct nfp_net_hw *hw;
2906         char *port_name;
2907         int ret;
2908
2909         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2910         if (!port_name)
2911                 return -ENOMEM;
2912
2913         if (ports > 1)
2914                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2915         else
2916                 sprintf(port_name, "%s", dev->device.name);
2917
2918         eth_dev = rte_eth_dev_allocate(port_name);
2919         if (!eth_dev)
2920                 return -ENOMEM;
2921
2922         if (port == 0) {
2923                 *priv = rte_zmalloc(port_name,
2924                                     sizeof(struct nfp_net_adapter) * ports,
2925                                     RTE_CACHE_LINE_SIZE);
2926                 if (!*priv) {
2927                         rte_eth_dev_release_port(eth_dev);
2928                         return -ENOMEM;
2929                 }
2930         }
2931
2932         eth_dev->data->dev_private = *priv;
2933
2934         /*
2935          * dev_private pointing to port0 dev_private because we need
2936          * to configure vNIC bars based on port0 at nfp_net_init.
2937          * Then dev_private is adjusted per port.
2938          */
2939         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2940         hw->nspu_desc = nfpu_desc->nspu;
2941         hw->nfpu_desc = nfpu_desc;
2942         hw->is_pf = 1;
2943         if (ports > 1)
2944                 hw->pf_multiport_enabled = 1;
2945
2946         eth_dev->device = &dev->device;
2947         rte_eth_copy_pci_info(eth_dev, dev);
2948
2949         ret = nfp_net_init(eth_dev);
2950
2951         if (ret)
2952                 rte_eth_dev_release_port(eth_dev);
2953
2954         rte_free(port_name);
2955
2956         return ret;
2957 }
2958
2959 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2960                             struct rte_pci_device *dev)
2961 {
2962         nfpu_desc_t *nfpu_desc;
2963         nspu_desc_t *nspu_desc;
2964         uint64_t offset_symbol;
2965         uint8_t *bar_offset;
2966         int major, minor;
2967         int total_ports;
2968         void *priv = 0;
2969         int ret = -ENODEV;
2970         int i;
2971
2972         if (!dev)
2973                 return ret;
2974
2975         nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2976         if (!nfpu_desc)
2977                 return -ENOMEM;
2978
2979         if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2980                 RTE_LOG(ERR, PMD,
2981                         "nfpu_open failed\n");
2982                 goto nfpu_error;
2983         }
2984
2985         nspu_desc = nfpu_desc->nspu;
2986
2987
2988         /* Check NSP ABI version */
2989         if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2990                 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2991                 goto error;
2992         }
2993         PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2994
2995         if ((major == 0) && (minor < 20)) {
2996                 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2997                 goto error;
2998         }
2999
3000         ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
3001                                &offset_symbol);
3002         if (ret)
3003                 goto error;
3004
3005         bar_offset = (uint8_t *)dev->mem_resource[0].addr;
3006         bar_offset += offset_symbol;
3007         total_ports = (uint32_t)*bar_offset;
3008         PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
3009
3010         if (total_ports <= 0 || total_ports > 8) {
3011                 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
3012                 ret = -ENODEV;
3013                 goto error;
3014         }
3015
3016         for (i = 0; i < total_ports; i++) {
3017                 ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
3018                 if (ret)
3019                         goto error;
3020         }
3021
3022         return 0;
3023
3024 error:
3025         nfpu_close(nfpu_desc);
3026 nfpu_error:
3027         rte_free(nfpu_desc);
3028
3029         return ret;
3030 }
3031
3032 int nfp_logtype_init;
3033 int nfp_logtype_driver;
3034
3035 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3036         {
3037                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3038                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3039         },
3040         {
3041                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3042                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3043         },
3044         {
3045                 .vendor_id = 0,
3046         },
3047 };
3048
3049 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3050         {
3051                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3052                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3053         },
3054         {
3055                 .vendor_id = 0,
3056         },
3057 };
3058
3059 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3060         struct rte_pci_device *pci_dev)
3061 {
3062         return rte_eth_dev_pci_generic_probe(pci_dev,
3063                 sizeof(struct nfp_net_adapter), nfp_net_init);
3064 }
3065
3066 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3067 {
3068         struct rte_eth_dev *eth_dev;
3069         struct nfp_net_hw *hw, *hwport0;
3070         int port = 0;
3071
3072         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3073         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3074             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3075                 port = get_pf_port_number(eth_dev->data->name);
3076                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3077                 hw = &hwport0[port];
3078         } else {
3079                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3080         }
3081         /* hotplug is not possible with multiport PF */
3082         if (hw->pf_multiport_enabled)
3083                 return -ENOTSUP;
3084         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3085 }
3086
3087 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3088         .id_table = pci_id_nfp_pf_net_map,
3089         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3090         .probe = nfp_pf_pci_probe,
3091         .remove = eth_nfp_pci_remove,
3092 };
3093
3094 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3095         .id_table = pci_id_nfp_vf_net_map,
3096         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3097         .probe = eth_nfp_pci_probe,
3098         .remove = eth_nfp_pci_remove,
3099 };
3100
3101 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3102 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3103 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3104 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3105 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3106 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3107
3108 RTE_INIT(nfp_init_log);
3109 static void
3110 nfp_init_log(void)
3111 {
3112         nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3113         if (nfp_logtype_init >= 0)
3114                 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3115         nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3116         if (nfp_logtype_driver >= 0)
3117                 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3118 }
3119 /*
3120  * Local variables:
3121  * c-file-style: "Linux"
3122  * indent-tabs-mode: t
3123  * End:
3124  */