2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
47 #include <rte_debug.h>
48 #include <rte_ethdev.h>
50 #include <rte_ether.h>
51 #include <rte_malloc.h>
52 #include <rte_memzone.h>
53 #include <rte_mempool.h>
54 #include <rte_version.h>
55 #include <rte_string_fns.h>
56 #include <rte_alarm.h>
57 #include <rte_spinlock.h>
59 #include "nfp_net_pmd.h"
60 #include "nfp_net_logs.h"
61 #include "nfp_net_ctrl.h"
64 static void nfp_net_close(struct rte_eth_dev *dev);
65 static int nfp_net_configure(struct rte_eth_dev *dev);
66 static void nfp_net_dev_interrupt_handler(struct rte_intr_handle *handle,
68 static void nfp_net_dev_interrupt_delayed_handler(void *param);
69 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
70 static void nfp_net_infos_get(struct rte_eth_dev *dev,
71 struct rte_eth_dev_info *dev_info);
72 static int nfp_net_init(struct rte_eth_dev *eth_dev);
73 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
74 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
75 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
76 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
77 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
79 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
81 static void nfp_net_rx_queue_release(void *rxq);
82 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
83 uint16_t nb_desc, unsigned int socket_id,
84 const struct rte_eth_rxconf *rx_conf,
85 struct rte_mempool *mp);
86 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
87 static void nfp_net_tx_queue_release(void *txq);
88 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
89 uint16_t nb_desc, unsigned int socket_id,
90 const struct rte_eth_txconf *tx_conf);
91 static int nfp_net_start(struct rte_eth_dev *dev);
92 static void nfp_net_stats_get(struct rte_eth_dev *dev,
93 struct rte_eth_stats *stats);
94 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
95 static void nfp_net_stop(struct rte_eth_dev *dev);
96 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
100 * The offset of the queue controller queues in the PCIe Target. These
101 * happen to be at the same offset on the NFP6000 and the NFP3200 so
102 * we use a single macro here.
104 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
106 /* Maximum value which can be added to a queue with one transaction */
107 #define NFP_QCP_MAX_ADD 0x7f
109 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
110 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
112 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
114 NFP_QCP_READ_PTR = 0,
119 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
120 * @q: Base address for queue structure
121 * @ptr: Add to the Read or Write pointer
122 * @val: Value to add to the queue pointer
124 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
127 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
131 if (ptr == NFP_QCP_READ_PTR)
132 off = NFP_QCP_QUEUE_ADD_RPTR;
134 off = NFP_QCP_QUEUE_ADD_WPTR;
136 while (val > NFP_QCP_MAX_ADD) {
137 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
138 val -= NFP_QCP_MAX_ADD;
141 nn_writel(rte_cpu_to_le_32(val), q + off);
145 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
146 * @q: Base address for queue structure
147 * @ptr: Read or Write pointer
149 static inline uint32_t
150 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
155 if (ptr == NFP_QCP_READ_PTR)
156 off = NFP_QCP_QUEUE_STS_LO;
158 off = NFP_QCP_QUEUE_STS_HI;
160 val = rte_cpu_to_le_32(nn_readl(q + off));
162 if (ptr == NFP_QCP_READ_PTR)
163 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
165 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
169 * Functions to read/write from/to Config BAR
170 * Performs any endian conversion necessary.
172 static inline uint8_t
173 nn_cfg_readb(struct nfp_net_hw *hw, int off)
175 return nn_readb(hw->ctrl_bar + off);
179 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
181 nn_writeb(val, hw->ctrl_bar + off);
184 static inline uint32_t
185 nn_cfg_readl(struct nfp_net_hw *hw, int off)
187 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
191 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
193 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
196 static inline uint64_t
197 nn_cfg_readq(struct nfp_net_hw *hw, int off)
199 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
203 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
205 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
208 /* Creating memzone for hardware rings. */
209 static const struct rte_memzone *
210 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
211 uint16_t queue_id, uint32_t ring_size, int socket_id)
213 char z_name[RTE_MEMZONE_NAMESIZE];
214 const struct rte_memzone *mz;
216 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
217 dev->driver->pci_drv.driver.name,
218 ring_name, dev->data->port_id, queue_id);
220 mz = rte_memzone_lookup(z_name);
224 return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
229 * Atomically reads link status information from global structure rte_eth_dev.
232 * - Pointer to the structure rte_eth_dev to read from.
233 * - Pointer to the buffer to be saved with the link status.
236 * - On success, zero.
237 * - On failure, negative value.
240 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
241 struct rte_eth_link *link)
243 struct rte_eth_link *dst = link;
244 struct rte_eth_link *src = &dev->data->dev_link;
246 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
247 *(uint64_t *)src) == 0)
254 * Atomically writes the link status information into global
255 * structure rte_eth_dev.
258 * - Pointer to the structure rte_eth_dev to read from.
259 * - Pointer to the buffer to be saved with the link status.
262 * - On success, zero.
263 * - On failure, negative value.
266 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
267 struct rte_eth_link *link)
269 struct rte_eth_link *dst = &dev->data->dev_link;
270 struct rte_eth_link *src = link;
272 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
273 *(uint64_t *)src) == 0)
280 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
284 if (rxq->rxbufs == NULL)
287 for (i = 0; i < rxq->rx_count; i++) {
288 if (rxq->rxbufs[i].mbuf) {
289 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
290 rxq->rxbufs[i].mbuf = NULL;
296 nfp_net_rx_queue_release(void *rx_queue)
298 struct nfp_net_rxq *rxq = rx_queue;
301 nfp_net_rx_queue_release_mbufs(rxq);
302 rte_free(rxq->rxbufs);
308 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
310 nfp_net_rx_queue_release_mbufs(rxq);
317 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
321 if (txq->txbufs == NULL)
324 for (i = 0; i < txq->tx_count; i++) {
325 if (txq->txbufs[i].mbuf) {
326 rte_pktmbuf_free(txq->txbufs[i].mbuf);
327 txq->txbufs[i].mbuf = NULL;
333 nfp_net_tx_queue_release(void *tx_queue)
335 struct nfp_net_txq *txq = tx_queue;
338 nfp_net_tx_queue_release_mbufs(txq);
339 rte_free(txq->txbufs);
345 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
347 nfp_net_tx_queue_release_mbufs(txq);
355 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
359 struct timespec wait;
361 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
364 if (hw->qcp_cfg == NULL)
365 rte_panic("Bad configuration queue pointer\n");
367 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
370 wait.tv_nsec = 1000000;
372 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
374 /* Poll update field, waiting for NFP to ack the config */
375 for (cnt = 0; ; cnt++) {
376 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
379 if (new & NFP_NET_CFG_UPDATE_ERR) {
380 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x\n", new);
383 if (cnt >= NFP_NET_POLL_TIMEOUT) {
384 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
385 " %dms\n", update, cnt);
386 rte_panic("Exiting\n");
388 nanosleep(&wait, 0); /* waiting for a 1ms */
390 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
395 * Reconfigure the NIC
396 * @nn: device to reconfigure
397 * @ctrl: The value for the ctrl field in the BAR config
398 * @update: The value for the update field in the BAR config
400 * Write the update word to the BAR and ping the reconfig queue. Then poll
401 * until the firmware has acknowledged the update by zeroing the update word.
404 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
408 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
411 rte_spinlock_lock(&hw->reconfig_lock);
413 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
414 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
418 err = __nfp_net_reconfig(hw, update);
420 rte_spinlock_unlock(&hw->reconfig_lock);
426 * Reconfig errors imply situations where they can be handled.
427 * Otherwise, rte_panic is called inside __nfp_net_reconfig
429 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x\n",
435 * Configure an Ethernet device. This function must be invoked first
436 * before any other function in the Ethernet API. This function can
437 * also be re-invoked when a device is in the stopped state.
440 nfp_net_configure(struct rte_eth_dev *dev)
442 struct rte_eth_conf *dev_conf;
443 struct rte_eth_rxmode *rxmode;
444 struct rte_eth_txmode *txmode;
445 uint32_t new_ctrl = 0;
447 struct nfp_net_hw *hw;
449 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
452 * A DPDK app sends info about how many queues to use and how
453 * those queues need to be configured. This is used by the
454 * DPDK core and it makes sure no more queues than those
455 * advertised by the driver are requested. This function is
456 * called after that internal process
459 PMD_INIT_LOG(DEBUG, "Configure\n");
461 dev_conf = &dev->data->dev_conf;
462 rxmode = &dev_conf->rxmode;
463 txmode = &dev_conf->txmode;
465 /* Checking TX mode */
466 if (txmode->mq_mode) {
467 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported\n");
471 /* Checking RX mode */
472 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
473 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
474 update = NFP_NET_CFG_UPDATE_RSS;
475 new_ctrl = NFP_NET_CFG_CTRL_RSS;
477 PMD_INIT_LOG(INFO, "RSS not supported\n");
482 if (rxmode->split_hdr_size) {
483 PMD_INIT_LOG(INFO, "rxmode does not support split header\n");
487 if (rxmode->hw_ip_checksum) {
488 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
489 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
491 PMD_INIT_LOG(INFO, "RXCSUM not supported\n");
496 if (rxmode->hw_vlan_filter) {
497 PMD_INIT_LOG(INFO, "VLAN filter not supported\n");
501 if (rxmode->hw_vlan_strip) {
502 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
503 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
505 PMD_INIT_LOG(INFO, "hw vlan strip not supported\n");
510 if (rxmode->hw_vlan_extend) {
511 PMD_INIT_LOG(INFO, "VLAN extended not supported\n");
515 /* Supporting VLAN insertion by default */
516 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
517 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
519 if (rxmode->jumbo_frame)
520 /* this is handled in rte_eth_dev_configure */
522 if (rxmode->hw_strip_crc) {
523 PMD_INIT_LOG(INFO, "strip CRC not supported\n");
527 if (rxmode->enable_scatter) {
528 PMD_INIT_LOG(INFO, "Scatter not supported\n");
535 update |= NFP_NET_CFG_UPDATE_GEN;
537 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
538 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
547 nfp_net_enable_queues(struct rte_eth_dev *dev)
549 struct nfp_net_hw *hw;
550 uint64_t enabled_queues = 0;
553 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
555 /* Enabling the required TX queues in the device */
556 for (i = 0; i < dev->data->nb_tx_queues; i++)
557 enabled_queues |= (1 << i);
559 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
563 /* Enabling the required RX queues in the device */
564 for (i = 0; i < dev->data->nb_rx_queues; i++)
565 enabled_queues |= (1 << i);
567 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
571 nfp_net_disable_queues(struct rte_eth_dev *dev)
573 struct nfp_net_hw *hw;
574 uint32_t new_ctrl, update = 0;
576 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
578 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
579 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
581 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
582 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
583 NFP_NET_CFG_UPDATE_MSIX;
585 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
586 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
588 /* If an error when reconfig we avoid to change hw state */
589 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
596 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
600 for (i = 0; i < dev->data->nb_rx_queues; i++) {
601 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
608 nfp_net_params_setup(struct nfp_net_hw *hw)
610 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
611 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
615 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
617 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
620 static void nfp_net_read_mac(struct nfp_net_hw *hw)
624 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
625 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
627 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
628 memcpy(&hw->mac_addr[4], &tmp, 2);
632 nfp_net_start(struct rte_eth_dev *dev)
634 uint32_t new_ctrl, update = 0;
635 struct nfp_net_hw *hw;
638 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
640 PMD_INIT_LOG(DEBUG, "Start\n");
642 /* Disabling queues just in case... */
643 nfp_net_disable_queues(dev);
645 /* Writing configuration parameters in the device */
646 nfp_net_params_setup(hw);
648 /* Enabling the required queues in the device */
649 nfp_net_enable_queues(dev);
652 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE | NFP_NET_CFG_UPDATE_MSIX;
653 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
655 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
656 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
658 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
659 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
663 * Allocating rte mbuffs for configured rx queues.
664 * This requires queues being enabled before
666 if (nfp_net_rx_freelist_setup(dev) < 0) {
677 * An error returned by this function should mean the app
678 * exiting and then the system releasing all the memory
679 * allocated even memory coming from hugepages.
681 * The device could be enabled at this point with some queues
682 * ready for getting packets. This is true if the call to
683 * nfp_net_rx_freelist_setup() succeeds for some queues but
684 * fails for subsequent queues.
686 * This should make the app exiting but better if we tell the
689 nfp_net_disable_queues(dev);
694 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
696 nfp_net_stop(struct rte_eth_dev *dev)
700 PMD_INIT_LOG(DEBUG, "Stop\n");
702 nfp_net_disable_queues(dev);
705 for (i = 0; i < dev->data->nb_tx_queues; i++) {
706 nfp_net_reset_tx_queue(
707 (struct nfp_net_txq *)dev->data->tx_queues[i]);
710 for (i = 0; i < dev->data->nb_rx_queues; i++) {
711 nfp_net_reset_rx_queue(
712 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
716 /* Reset and stop device. The device can not be restarted. */
718 nfp_net_close(struct rte_eth_dev *dev)
720 struct nfp_net_hw *hw;
721 struct rte_pci_device *pci_dev;
723 PMD_INIT_LOG(DEBUG, "Close\n");
725 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
726 pci_dev = RTE_DEV_TO_PCI(dev->device);
729 * We assume that the DPDK application is stopping all the
730 * threads/queues before calling the device close function.
735 rte_intr_disable(&pci_dev->intr_handle);
736 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
738 /* unregister callback func from eal lib */
739 rte_intr_callback_unregister(&pci_dev->intr_handle,
740 nfp_net_dev_interrupt_handler,
744 * The ixgbe PMD driver disables the pcie master on the
745 * device. The i40e does not...
750 nfp_net_promisc_enable(struct rte_eth_dev *dev)
752 uint32_t new_ctrl, update = 0;
753 struct nfp_net_hw *hw;
755 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
757 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
759 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
760 PMD_INIT_LOG(INFO, "Promiscuous mode not supported\n");
764 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
765 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
769 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
770 update = NFP_NET_CFG_UPDATE_GEN;
773 * DPDK sets promiscuous mode on just after this call assuming
774 * it can not fail ...
776 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
783 nfp_net_promisc_disable(struct rte_eth_dev *dev)
785 uint32_t new_ctrl, update = 0;
786 struct nfp_net_hw *hw;
788 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
790 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
791 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
795 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
796 update = NFP_NET_CFG_UPDATE_GEN;
799 * DPDK sets promiscuous mode off just before this call
800 * assuming it can not fail ...
802 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
809 * return 0 means link status changed, -1 means not changed
811 * Wait to complete is needed as it can take up to 9 seconds to get the Link
815 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
817 struct nfp_net_hw *hw;
818 struct rte_eth_link link, old;
819 uint32_t nn_link_status;
821 static const uint32_t ls_to_ethtool[] = {
822 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
823 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
824 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
825 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
826 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
827 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
828 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
829 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
832 PMD_DRV_LOG(DEBUG, "Link update\n");
834 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
836 memset(&old, 0, sizeof(old));
837 nfp_net_dev_atomic_read_link_status(dev, &old);
839 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
841 memset(&link, 0, sizeof(struct rte_eth_link));
843 if (nn_link_status & NFP_NET_CFG_STS_LINK)
844 link.link_status = ETH_LINK_UP;
846 link.link_duplex = ETH_LINK_FULL_DUPLEX;
848 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
849 NFP_NET_CFG_STS_LINK_RATE_MASK;
851 if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
852 ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
853 (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
854 /* We really do not know the speed wil old firmware */
855 link.link_speed = ETH_SPEED_NUM_NONE;
857 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
858 link.link_speed = ETH_SPEED_NUM_NONE;
860 link.link_speed = ls_to_ethtool[nn_link_status];
863 if (old.link_status != link.link_status) {
864 nfp_net_dev_atomic_write_link_status(dev, &link);
865 if (link.link_status)
866 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
868 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
876 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
879 struct nfp_net_hw *hw;
880 struct rte_eth_stats nfp_dev_stats;
882 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
884 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
886 /* reading per RX ring stats */
887 for (i = 0; i < dev->data->nb_rx_queues; i++) {
888 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
891 nfp_dev_stats.q_ipackets[i] =
892 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
894 nfp_dev_stats.q_ipackets[i] -=
895 hw->eth_stats_base.q_ipackets[i];
897 nfp_dev_stats.q_ibytes[i] =
898 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
900 nfp_dev_stats.q_ibytes[i] -=
901 hw->eth_stats_base.q_ibytes[i];
904 /* reading per TX ring stats */
905 for (i = 0; i < dev->data->nb_tx_queues; i++) {
906 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
909 nfp_dev_stats.q_opackets[i] =
910 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
912 nfp_dev_stats.q_opackets[i] -=
913 hw->eth_stats_base.q_opackets[i];
915 nfp_dev_stats.q_obytes[i] =
916 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
918 nfp_dev_stats.q_obytes[i] -=
919 hw->eth_stats_base.q_obytes[i];
922 nfp_dev_stats.ipackets =
923 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
925 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
927 nfp_dev_stats.ibytes =
928 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
930 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
932 nfp_dev_stats.opackets =
933 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
935 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
937 nfp_dev_stats.obytes =
938 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
940 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
942 /* reading general device stats */
943 nfp_dev_stats.ierrors =
944 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
946 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
948 nfp_dev_stats.oerrors =
949 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
951 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
953 /* RX ring mbuf allocation failures */
954 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
956 nfp_dev_stats.imissed =
957 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
959 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
962 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
966 nfp_net_stats_reset(struct rte_eth_dev *dev)
969 struct nfp_net_hw *hw;
971 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
974 * hw->eth_stats_base records the per counter starting point.
978 /* reading per RX ring stats */
979 for (i = 0; i < dev->data->nb_rx_queues; i++) {
980 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
983 hw->eth_stats_base.q_ipackets[i] =
984 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
986 hw->eth_stats_base.q_ibytes[i] =
987 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
990 /* reading per TX ring stats */
991 for (i = 0; i < dev->data->nb_tx_queues; i++) {
992 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
995 hw->eth_stats_base.q_opackets[i] =
996 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
998 hw->eth_stats_base.q_obytes[i] =
999 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1002 hw->eth_stats_base.ipackets =
1003 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1005 hw->eth_stats_base.ibytes =
1006 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1008 hw->eth_stats_base.opackets =
1009 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1011 hw->eth_stats_base.obytes =
1012 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1014 /* reading general device stats */
1015 hw->eth_stats_base.ierrors =
1016 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1018 hw->eth_stats_base.oerrors =
1019 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1021 /* RX ring mbuf allocation failures */
1022 dev->data->rx_mbuf_alloc_failed = 0;
1024 hw->eth_stats_base.imissed =
1025 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1029 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1031 struct nfp_net_hw *hw;
1033 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1035 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1036 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1037 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1038 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1039 dev_info->max_rx_pktlen = hw->mtu;
1040 /* Next should change when PF support is implemented */
1041 dev_info->max_mac_addrs = 1;
1043 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1044 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1046 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1047 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1048 DEV_RX_OFFLOAD_UDP_CKSUM |
1049 DEV_RX_OFFLOAD_TCP_CKSUM;
1051 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1052 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1054 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1055 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1056 DEV_TX_OFFLOAD_UDP_CKSUM |
1057 DEV_TX_OFFLOAD_TCP_CKSUM;
1059 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1061 .pthresh = DEFAULT_RX_PTHRESH,
1062 .hthresh = DEFAULT_RX_HTHRESH,
1063 .wthresh = DEFAULT_RX_WTHRESH,
1065 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1069 dev_info->default_txconf = (struct rte_eth_txconf) {
1071 .pthresh = DEFAULT_TX_PTHRESH,
1072 .hthresh = DEFAULT_TX_HTHRESH,
1073 .wthresh = DEFAULT_TX_WTHRESH,
1075 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1076 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1077 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1078 ETH_TXQ_FLAGS_NOOFFLOADS,
1081 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1082 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1084 dev_info->speed_capa = ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1087 static const uint32_t *
1088 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1090 static const uint32_t ptypes[] = {
1091 /* refers to nfp_net_set_hash() */
1092 RTE_PTYPE_INNER_L3_IPV4,
1093 RTE_PTYPE_INNER_L3_IPV6,
1094 RTE_PTYPE_INNER_L3_IPV6_EXT,
1095 RTE_PTYPE_INNER_L4_MASK,
1099 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1105 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1107 struct nfp_net_rxq *rxq;
1108 struct nfp_net_rx_desc *rxds;
1112 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1115 PMD_INIT_LOG(ERR, "Bad queue: %u\n", queue_idx);
1119 idx = rxq->rd_p % rxq->rx_count;
1120 rxds = &rxq->rxds[idx];
1125 * Other PMDs are just checking the DD bit in intervals of 4
1126 * descriptors and counting all four if the first has the DD
1127 * bit on. Of course, this is not accurate but can be good for
1128 * perfomance. But ideally that should be done in descriptors
1129 * chunks belonging to the same cache line
1132 while (count < rxq->rx_count) {
1133 rxds = &rxq->rxds[idx];
1134 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1141 if ((idx) == rxq->rx_count)
1149 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1151 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1152 struct rte_eth_link link;
1154 memset(&link, 0, sizeof(link));
1155 nfp_net_dev_atomic_read_link_status(dev, &link);
1156 if (link.link_status)
1157 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1158 (int)(dev->data->port_id), (unsigned)link.link_speed,
1159 link.link_duplex == ETH_LINK_FULL_DUPLEX
1160 ? "full-duplex" : "half-duplex");
1162 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1163 (int)(dev->data->port_id));
1165 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1166 pci_dev->addr.domain, pci_dev->addr.bus,
1167 pci_dev->addr.devid, pci_dev->addr.function);
1170 /* Interrupt configuration and handling */
1173 * nfp_net_irq_unmask - Unmask an interrupt
1175 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1176 * clear the ICR for the entry.
1179 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1181 struct nfp_net_hw *hw;
1182 struct rte_pci_device *pci_dev;
1184 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1185 pci_dev = RTE_DEV_TO_PCI(dev->device);
1187 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1188 /* If MSI-X auto-masking is used, clear the entry */
1190 rte_intr_enable(&pci_dev->intr_handle);
1192 /* Make sure all updates are written before un-masking */
1194 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1195 NFP_NET_CFG_ICR_UNMASKED);
1200 nfp_net_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1204 struct rte_eth_link link;
1205 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1207 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1209 /* get the link status */
1210 memset(&link, 0, sizeof(link));
1211 nfp_net_dev_atomic_read_link_status(dev, &link);
1213 nfp_net_link_update(dev, 0);
1216 if (!link.link_status) {
1217 /* handle it 1 sec later, wait it being stable */
1218 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1219 /* likely to down */
1221 /* handle it 4 sec later, wait it being stable */
1222 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1225 if (rte_eal_alarm_set(timeout * 1000,
1226 nfp_net_dev_interrupt_delayed_handler,
1228 RTE_LOG(ERR, PMD, "Error setting alarm");
1230 nfp_net_irq_unmask(dev);
1235 * Interrupt handler which shall be registered for alarm callback for delayed
1236 * handling specific interrupt to wait for the stable nic state. As the NIC
1237 * interrupt state is not stable for nfp after link is just down, it needs
1238 * to wait 4 seconds to get the stable status.
1240 * @param handle Pointer to interrupt handle.
1241 * @param param The address of parameter (struct rte_eth_dev *)
1246 nfp_net_dev_interrupt_delayed_handler(void *param)
1248 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1250 nfp_net_link_update(dev, 0);
1251 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1253 nfp_net_dev_link_status_print(dev);
1256 nfp_net_irq_unmask(dev);
1260 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1262 struct nfp_net_hw *hw;
1264 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1266 /* check that mtu is within the allowed range */
1267 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1270 /* switch to jumbo mode if needed */
1271 if ((uint32_t)mtu > ETHER_MAX_LEN)
1272 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1274 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1276 /* update max frame size */
1277 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1279 /* writing to configuration space */
1280 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1288 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1289 uint16_t queue_idx, uint16_t nb_desc,
1290 unsigned int socket_id,
1291 const struct rte_eth_rxconf *rx_conf,
1292 struct rte_mempool *mp)
1294 const struct rte_memzone *tz;
1295 struct nfp_net_rxq *rxq;
1296 struct nfp_net_hw *hw;
1298 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1300 PMD_INIT_FUNC_TRACE();
1302 /* Validating number of descriptors */
1303 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1304 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1305 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1306 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1311 * Free memory prior to re-allocation if needed. This is the case after
1312 * calling nfp_net_stop
1314 if (dev->data->rx_queues[queue_idx]) {
1315 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1316 dev->data->rx_queues[queue_idx] = NULL;
1319 /* Allocating rx queue data structure */
1320 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1321 RTE_CACHE_LINE_SIZE, socket_id);
1325 /* Hw queues mapping based on firmware confifguration */
1326 rxq->qidx = queue_idx;
1327 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1328 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1329 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1330 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1333 * Tracking mbuf size for detecting a potential mbuf overflow due to
1337 rxq->mbuf_size = rxq->mem_pool->elt_size;
1338 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1339 hw->flbufsz = rxq->mbuf_size;
1341 rxq->rx_count = nb_desc;
1342 rxq->port_id = dev->data->port_id;
1343 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1344 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1346 rxq->drop_en = rx_conf->rx_drop_en;
1349 * Allocate RX ring hardware descriptors. A memzone large enough to
1350 * handle the maximum ring size is allocated in order to allow for
1351 * resizing in later calls to the queue setup function.
1353 tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1354 sizeof(struct nfp_net_rx_desc) *
1355 NFP_NET_MAX_RX_DESC, socket_id);
1358 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1359 nfp_net_rx_queue_release(rxq);
1363 /* Saving physical and virtual addresses for the RX ring */
1364 rxq->dma = (uint64_t)tz->phys_addr;
1365 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1367 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1368 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1369 sizeof(*rxq->rxbufs) * nb_desc,
1370 RTE_CACHE_LINE_SIZE, socket_id);
1371 if (rxq->rxbufs == NULL) {
1372 nfp_net_rx_queue_release(rxq);
1376 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1377 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1379 nfp_net_reset_rx_queue(rxq);
1381 dev->data->rx_queues[queue_idx] = rxq;
1385 * Telling the HW about the physical address of the RX ring and number
1386 * of descriptors in log2 format
1388 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1389 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1395 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1397 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1401 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1404 for (i = 0; i < rxq->rx_count; i++) {
1405 struct nfp_net_rx_desc *rxd;
1406 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1409 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1410 (unsigned)rxq->qidx);
1414 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1416 rxd = &rxq->rxds[i];
1418 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1419 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1421 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1426 /* Make sure all writes are flushed before telling the hardware */
1429 /* Not advertising the whole ring as the firmware gets confused if so */
1430 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1433 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1439 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1440 uint16_t nb_desc, unsigned int socket_id,
1441 const struct rte_eth_txconf *tx_conf)
1443 const struct rte_memzone *tz;
1444 struct nfp_net_txq *txq;
1445 uint16_t tx_free_thresh;
1446 struct nfp_net_hw *hw;
1448 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1450 PMD_INIT_FUNC_TRACE();
1452 /* Validating number of descriptors */
1453 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1454 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1455 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1456 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1460 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1461 tx_conf->tx_free_thresh :
1462 DEFAULT_TX_FREE_THRESH);
1464 if (tx_free_thresh > (nb_desc)) {
1466 "tx_free_thresh must be less than the number of TX "
1467 "descriptors. (tx_free_thresh=%u port=%d "
1468 "queue=%d)\n", (unsigned int)tx_free_thresh,
1469 (int)dev->data->port_id, (int)queue_idx);
1474 * Free memory prior to re-allocation if needed. This is the case after
1475 * calling nfp_net_stop
1477 if (dev->data->tx_queues[queue_idx]) {
1478 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1480 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1481 dev->data->tx_queues[queue_idx] = NULL;
1484 /* Allocating tx queue data structure */
1485 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1486 RTE_CACHE_LINE_SIZE, socket_id);
1488 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1493 * Allocate TX ring hardware descriptors. A memzone large enough to
1494 * handle the maximum ring size is allocated in order to allow for
1495 * resizing in later calls to the queue setup function.
1497 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1498 sizeof(struct nfp_net_tx_desc) *
1499 NFP_NET_MAX_TX_DESC, socket_id);
1501 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1502 nfp_net_tx_queue_release(txq);
1506 txq->tx_count = nb_desc;
1508 txq->tx_free_thresh = tx_free_thresh;
1509 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1510 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1511 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1513 /* queue mapping based on firmware configuration */
1514 txq->qidx = queue_idx;
1515 txq->tx_qcidx = queue_idx * hw->stride_tx;
1516 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1518 txq->port_id = dev->data->port_id;
1519 txq->txq_flags = tx_conf->txq_flags;
1521 /* Saving physical and virtual addresses for the TX ring */
1522 txq->dma = (uint64_t)tz->phys_addr;
1523 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1525 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1526 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1527 sizeof(*txq->txbufs) * nb_desc,
1528 RTE_CACHE_LINE_SIZE, socket_id);
1529 if (txq->txbufs == NULL) {
1530 nfp_net_tx_queue_release(txq);
1533 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1534 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1536 nfp_net_reset_tx_queue(txq);
1538 dev->data->tx_queues[queue_idx] = txq;
1542 * Telling the HW about the physical address of the TX ring and number
1543 * of descriptors in log2 format
1545 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1546 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1551 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1553 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1554 struct rte_mbuf *mb)
1557 struct nfp_net_hw *hw = txq->hw;
1559 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1562 ol_flags = mb->ol_flags;
1564 /* IPv6 does not need checksum */
1565 if (ol_flags & PKT_TX_IP_CKSUM)
1566 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1568 switch (ol_flags & PKT_TX_L4_MASK) {
1569 case PKT_TX_UDP_CKSUM:
1570 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1572 case PKT_TX_TCP_CKSUM:
1573 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1577 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1578 txd->flags |= PCIE_DESC_TX_CSUM;
1581 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1583 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1584 struct rte_mbuf *mb)
1586 struct nfp_net_hw *hw = rxq->hw;
1588 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1591 /* If IPv4 and IP checksum error, fail */
1592 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1593 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1594 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1596 /* If neither UDP nor TCP return */
1597 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1598 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1601 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1602 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1603 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1605 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1606 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1607 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1610 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1611 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1614 * nfp_net_set_hash - Set mbuf hash data
1616 * The RSS hash and hash-type are pre-pended to the packet data.
1617 * Extract and decode it and set the mbuf fields.
1620 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1621 struct rte_mbuf *mbuf)
1625 struct nfp_net_hw *hw = rxq->hw;
1627 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1630 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1633 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1634 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1636 mbuf->hash.rss = hash;
1637 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1639 switch (hash_type) {
1640 case NFP_NET_RSS_IPV4:
1641 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1643 case NFP_NET_RSS_IPV6:
1644 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1646 case NFP_NET_RSS_IPV6_EX:
1647 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1650 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1655 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1657 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1660 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1665 * There are some decissions to take:
1666 * 1) How to check DD RX descriptors bit
1667 * 2) How and when to allocate new mbufs
1669 * Current implementation checks just one single DD bit each loop. As each
1670 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1671 * a single cache line instead. Tests with this change have not shown any
1672 * performance improvement but it requires further investigation. For example,
1673 * depending on which descriptor is next, the number of descriptors could be
1674 * less than 8 for just checking those in the same cache line. This implies
1675 * extra work which could be counterproductive by itself. Indeed, last firmware
1676 * changes are just doing this: writing several descriptors with the DD bit
1677 * for saving PCIe bandwidth and DMA operations from the NFP.
1679 * Mbuf allocation is done when a new packet is received. Then the descriptor
1680 * is automatically linked with the new mbuf and the old one is given to the
1681 * user. The main drawback with this design is mbuf allocation is heavier than
1682 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1683 * cache point of view it does not seem allocating the mbuf early on as we are
1684 * doing now have any benefit at all. Again, tests with this change have not
1685 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1686 * so looking at the implications of this type of allocation should be studied
1691 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1693 struct nfp_net_rxq *rxq;
1694 struct nfp_net_rx_desc *rxds;
1695 struct nfp_net_rx_buff *rxb;
1696 struct nfp_net_hw *hw;
1697 struct rte_mbuf *mb;
1698 struct rte_mbuf *new_mb;
1705 if (unlikely(rxq == NULL)) {
1707 * DPDK just checks the queue is lower than max queues
1708 * enabled. But the queue needs to be configured
1710 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1718 while (avail < nb_pkts) {
1719 idx = rxq->rd_p % rxq->rx_count;
1721 rxb = &rxq->rxbufs[idx];
1722 if (unlikely(rxb == NULL)) {
1723 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1728 * Memory barrier to ensure that we won't do other
1729 * reads before the DD bit.
1733 rxds = &rxq->rxds[idx];
1734 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1738 * We got a packet. Let's alloc a new mbuff for refilling the
1739 * free descriptor ring as soon as possible
1741 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1742 if (unlikely(new_mb == NULL)) {
1743 RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1744 "queue_id=%u\n", (unsigned)rxq->port_id,
1745 (unsigned)rxq->qidx);
1746 nfp_net_mbuf_alloc_failed(rxq);
1753 * Grab the mbuff and refill the descriptor with the
1754 * previously allocated mbuff
1759 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1760 rxds->rxd.data_len, rxq->mbuf_size);
1762 /* Size of this segment */
1763 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1764 /* Size of the whole packet. We just support 1 segment */
1765 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1767 if (unlikely((mb->data_len + hw->rx_offset) >
1770 * This should not happen and the user has the
1771 * responsibility of avoiding it. But we have
1772 * to give some info about the error
1774 RTE_LOG_DP(ERR, PMD,
1775 "mbuf overflow likely due to the RX offset.\n"
1776 "\t\tYour mbuf size should have extra space for"
1777 " RX offset=%u bytes.\n"
1778 "\t\tCurrently you just have %u bytes available"
1779 " but the received packet is %u bytes long",
1781 rxq->mbuf_size - hw->rx_offset,
1786 /* Filling the received mbuff with packet info */
1788 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1790 mb->data_off = RTE_PKTMBUF_HEADROOM +
1791 NFP_DESC_META_LEN(rxds);
1793 /* No scatter mode supported */
1797 /* Checking the RSS flag */
1798 nfp_net_set_hash(rxq, rxds, mb);
1800 /* Checking the checksum flag */
1801 nfp_net_rx_cksum(rxq, rxds, mb);
1803 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1804 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1805 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1806 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1809 /* Adding the mbuff to the mbuff array passed by the app */
1810 rx_pkts[avail++] = mb;
1812 /* Now resetting and updating the descriptor */
1815 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1817 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1818 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1826 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1827 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1829 nb_hold += rxq->nb_rx_hold;
1832 * FL descriptors needs to be written before incrementing the
1833 * FL queue WR pointer
1836 if (nb_hold > rxq->rx_free_thresh) {
1837 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1838 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1839 (unsigned)nb_hold, (unsigned)avail);
1840 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1843 rxq->nb_rx_hold = nb_hold;
1849 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1851 * @txq: TX queue to work with
1852 * Returns number of descriptors freed
1855 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1860 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1861 " status\n", txq->qidx);
1863 /* Work out how many packets have been sent */
1864 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1866 if (qcp_rd_p == txq->qcp_rd_p) {
1867 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1868 "packets (%u, %u)\n", txq->qidx,
1869 qcp_rd_p, txq->qcp_rd_p);
1873 if (qcp_rd_p > txq->qcp_rd_p)
1874 todo = qcp_rd_p - txq->qcp_rd_p;
1876 todo = qcp_rd_p + txq->tx_count - txq->qcp_rd_p;
1878 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->qcp_rd_p: %u, qcp->rd_p: %u\n",
1879 qcp_rd_p, txq->qcp_rd_p, txq->rd_p);
1884 txq->qcp_rd_p += todo;
1885 txq->qcp_rd_p %= txq->tx_count;
1891 /* Leaving always free descriptors for avoiding wrapping confusion */
1892 #define NFP_FREE_TX_DESC(t) (t->tx_count - (t->wr_p - t->rd_p) - 8)
1895 * nfp_net_txq_full - Check if the TX queue free descriptors
1896 * is below tx_free_threshold
1898 * @txq: TX queue to check
1900 * This function uses the host copy* of read/write pointers
1903 int nfp_net_txq_full(struct nfp_net_txq *txq)
1905 return NFP_FREE_TX_DESC(txq) < txq->tx_free_thresh;
1909 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1911 struct nfp_net_txq *txq;
1912 struct nfp_net_hw *hw;
1913 struct nfp_net_tx_desc *txds;
1914 struct rte_mbuf *pkt;
1916 int pkt_size, dma_size;
1917 uint16_t free_descs, issued_descs;
1918 struct rte_mbuf **lmbuf;
1923 txds = &txq->txds[txq->tail];
1925 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
1926 txq->qidx, txq->tail, nb_pkts);
1928 if ((NFP_FREE_TX_DESC(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
1929 nfp_net_tx_free_bufs(txq);
1931 free_descs = (uint16_t)NFP_FREE_TX_DESC(txq);
1932 if (unlikely(free_descs == 0))
1939 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
1940 txq->qidx, nb_pkts);
1941 /* Sending packets */
1942 while ((i < nb_pkts) && free_descs) {
1943 /* Grabbing the mbuf linked to the current descriptor */
1944 lmbuf = &txq->txbufs[txq->tail].mbuf;
1945 /* Warming the cache for releasing the mbuf later on */
1946 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
1948 pkt = *(tx_pkts + i);
1950 if (unlikely((pkt->nb_segs > 1) &&
1951 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
1952 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set\n");
1953 rte_panic("Multisegment packet unsupported\n");
1956 /* Checking if we have enough descriptors */
1957 if (unlikely(pkt->nb_segs > free_descs))
1961 * Checksum and VLAN flags just in the first descriptor for a
1962 * multisegment packet
1964 nfp_net_tx_cksum(txq, txds, pkt);
1966 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
1967 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
1968 txds->flags |= PCIE_DESC_TX_VLAN;
1969 txds->vlan = pkt->vlan_tci;
1972 if (pkt->ol_flags & PKT_TX_TCP_SEG)
1973 rte_panic("TSO is not supported\n");
1976 * mbuf data_len is the data in one segment and pkt_len data
1977 * in the whole packet. When the packet is just one segment,
1978 * then data_len = pkt_len
1980 pkt_size = pkt->pkt_len;
1982 /* Releasing mbuf which was prefetched above */
1984 rte_pktmbuf_free(*lmbuf);
1986 * Linking mbuf with descriptor for being released
1987 * next time descriptor is used
1992 dma_size = pkt->data_len;
1993 dma_addr = rte_mbuf_data_dma_addr(pkt);
1994 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
1995 "%" PRIx64 "\n", dma_addr);
1997 /* Filling descriptors fields */
1998 txds->dma_len = dma_size;
1999 txds->data_len = pkt->pkt_len;
2000 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2001 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2002 ASSERT(free_descs > 0);
2007 if (unlikely(txq->tail == txq->tx_count)) /* wrapping?*/
2010 pkt_size -= dma_size;
2013 txds->offset_eop |= PCIE_DESC_TX_EOP;
2015 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2018 /* Referencing next free TX descriptor */
2019 txds = &txq->txds[txq->tail];
2026 /* Increment write pointers. Force memory write before we let HW know */
2028 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2034 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2036 uint32_t new_ctrl, update;
2037 struct nfp_net_hw *hw;
2039 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2042 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2043 (mask & ETH_VLAN_FILTER_OFFLOAD))
2044 RTE_LOG(INFO, PMD, "Not support for ETH_VLAN_FILTER_OFFLOAD or"
2045 " ETH_VLAN_FILTER_EXTEND");
2047 /* Enable vlan strip if it is not configured yet */
2048 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2049 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2050 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2052 /* Disable vlan strip just if it is configured */
2053 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2054 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2055 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2060 update = NFP_NET_CFG_UPDATE_GEN;
2062 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2065 hw->ctrl = new_ctrl;
2068 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2070 nfp_net_reta_update(struct rte_eth_dev *dev,
2071 struct rte_eth_rss_reta_entry64 *reta_conf,
2074 uint32_t reta, mask;
2078 struct nfp_net_hw *hw =
2079 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2081 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2084 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2085 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2086 "(%d) doesn't match the number hardware can supported "
2087 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2092 * Update Redirection Table. There are 128 8bit-entries which can be
2093 * manage as 32 32bit-entries
2095 for (i = 0; i < reta_size; i += 4) {
2096 /* Handling 4 RSS entries per loop */
2097 idx = i / RTE_RETA_GROUP_SIZE;
2098 shift = i % RTE_RETA_GROUP_SIZE;
2099 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2105 /* If all 4 entries were set, don't need read RETA register */
2107 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2109 for (j = 0; j < 4; j++) {
2110 if (!(mask & (0x1 << j)))
2113 /* Clearing the entry bits */
2114 reta &= ~(0xFF << (8 * j));
2115 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2117 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2120 update = NFP_NET_CFG_UPDATE_RSS;
2122 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2128 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2130 nfp_net_reta_query(struct rte_eth_dev *dev,
2131 struct rte_eth_rss_reta_entry64 *reta_conf,
2137 struct nfp_net_hw *hw;
2139 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2144 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2145 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2146 "(%d) doesn't match the number hardware can supported "
2147 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2152 * Reading Redirection Table. There are 128 8bit-entries which can be
2153 * manage as 32 32bit-entries
2155 for (i = 0; i < reta_size; i += 4) {
2156 /* Handling 4 RSS entries per loop */
2157 idx = i / RTE_RETA_GROUP_SIZE;
2158 shift = i % RTE_RETA_GROUP_SIZE;
2159 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2164 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2165 for (j = 0; j < 4; j++) {
2166 if (!(mask & (0x1 << j)))
2168 reta_conf->reta[shift + j] =
2169 (uint8_t)((reta >> (8 * j)) & 0xF);
2176 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2177 struct rte_eth_rss_conf *rss_conf)
2180 uint32_t cfg_rss_ctrl = 0;
2184 struct nfp_net_hw *hw;
2186 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188 rss_hf = rss_conf->rss_hf;
2190 /* Checking if RSS is enabled */
2191 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2192 if (rss_hf != 0) { /* Enable RSS? */
2193 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2196 return 0; /* Nothing to do */
2199 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2200 RTE_LOG(ERR, PMD, "hash key too long\n");
2204 if (rss_hf & ETH_RSS_IPV4)
2205 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2206 NFP_NET_CFG_RSS_IPV4_TCP |
2207 NFP_NET_CFG_RSS_IPV4_UDP;
2209 if (rss_hf & ETH_RSS_IPV6)
2210 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2211 NFP_NET_CFG_RSS_IPV6_TCP |
2212 NFP_NET_CFG_RSS_IPV6_UDP;
2214 /* configuring where to apply the RSS hash */
2215 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2217 /* Writing the key byte a byte */
2218 for (i = 0; i < rss_conf->rss_key_len; i++) {
2219 memcpy(&key, &rss_conf->rss_key[i], 1);
2220 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2223 /* Writing the key size */
2224 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2226 update = NFP_NET_CFG_UPDATE_RSS;
2228 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2235 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2236 struct rte_eth_rss_conf *rss_conf)
2239 uint32_t cfg_rss_ctrl;
2242 struct nfp_net_hw *hw;
2244 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2249 rss_hf = rss_conf->rss_hf;
2250 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2252 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2253 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2255 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2256 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2258 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2259 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2261 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2262 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2264 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2265 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2267 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2268 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2270 /* Reading the key size */
2271 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2273 /* Reading the key byte a byte */
2274 for (i = 0; i < rss_conf->rss_key_len; i++) {
2275 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2276 memcpy(&rss_conf->rss_key[i], &key, 1);
2282 /* Initialise and register driver with DPDK Application */
2283 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2284 .dev_configure = nfp_net_configure,
2285 .dev_start = nfp_net_start,
2286 .dev_stop = nfp_net_stop,
2287 .dev_close = nfp_net_close,
2288 .promiscuous_enable = nfp_net_promisc_enable,
2289 .promiscuous_disable = nfp_net_promisc_disable,
2290 .link_update = nfp_net_link_update,
2291 .stats_get = nfp_net_stats_get,
2292 .stats_reset = nfp_net_stats_reset,
2293 .dev_infos_get = nfp_net_infos_get,
2294 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2295 .mtu_set = nfp_net_dev_mtu_set,
2296 .vlan_offload_set = nfp_net_vlan_offload_set,
2297 .reta_update = nfp_net_reta_update,
2298 .reta_query = nfp_net_reta_query,
2299 .rss_hash_update = nfp_net_rss_hash_update,
2300 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2301 .rx_queue_setup = nfp_net_rx_queue_setup,
2302 .rx_queue_release = nfp_net_rx_queue_release,
2303 .rx_queue_count = nfp_net_rx_queue_count,
2304 .tx_queue_setup = nfp_net_tx_queue_setup,
2305 .tx_queue_release = nfp_net_tx_queue_release,
2309 nfp_net_init(struct rte_eth_dev *eth_dev)
2311 struct rte_pci_device *pci_dev;
2312 struct nfp_net_hw *hw;
2314 uint32_t tx_bar_off, rx_bar_off;
2318 PMD_INIT_FUNC_TRACE();
2320 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2322 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2323 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2324 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2326 /* For secondary processes, the primary has done all the work */
2327 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2330 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2331 rte_eth_copy_pci_info(eth_dev, pci_dev);
2332 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
2334 hw->device_id = pci_dev->id.device_id;
2335 hw->vendor_id = pci_dev->id.vendor_id;
2336 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2337 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2339 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u\n",
2340 pci_dev->id.vendor_id, pci_dev->id.device_id,
2341 pci_dev->addr.domain, pci_dev->addr.bus,
2342 pci_dev->addr.devid, pci_dev->addr.function);
2344 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2345 if (hw->ctrl_bar == NULL) {
2347 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2350 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2351 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2353 /* Work out where in the BAR the queues start. */
2354 switch (pci_dev->id.device_id) {
2355 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2356 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2357 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2358 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2359 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2362 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2366 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x\n", tx_bar_off);
2367 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x\n", rx_bar_off);
2369 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2370 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2372 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p\n",
2373 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2375 nfp_net_cfg_queue_setup(hw);
2377 /* Get some of the read-only fields from the config BAR */
2378 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2379 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2380 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2381 hw->mtu = hw->max_mtu;
2383 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2384 hw->rx_offset = NFP_NET_RX_OFFSET;
2386 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2388 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d\n",
2389 hw->ver, hw->max_mtu);
2390 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s\n", hw->cap,
2391 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2392 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2393 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2394 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2395 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2396 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2397 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2398 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2399 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2403 hw->stride_rx = stride;
2404 hw->stride_tx = stride;
2406 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u\n",
2407 hw->max_rx_queues, hw->max_tx_queues);
2409 /* Initializing spinlock for reconfigs */
2410 rte_spinlock_init(&hw->reconfig_lock);
2412 /* Allocating memory for mac addr */
2413 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2414 if (eth_dev->data->mac_addrs == NULL) {
2415 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2419 nfp_net_read_mac(hw);
2421 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr))
2422 /* Using random mac addresses for VFs */
2423 eth_random_addr(&hw->mac_addr[0]);
2425 /* Copying mac address to DPDK eth_dev struct */
2426 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2427 ð_dev->data->mac_addrs[0]);
2429 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2430 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2431 eth_dev->data->port_id, pci_dev->id.vendor_id,
2432 pci_dev->id.device_id,
2433 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2434 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2436 /* Registering LSC interrupt handler */
2437 rte_intr_callback_register(&pci_dev->intr_handle,
2438 nfp_net_dev_interrupt_handler,
2441 /* enable uio intr after callback register */
2442 rte_intr_enable(&pci_dev->intr_handle);
2444 /* Telling the firmware about the LSC interrupt entry */
2445 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2447 /* Recording current stats counters values */
2448 nfp_net_stats_reset(eth_dev);
2453 static struct rte_pci_id pci_id_nfp_net_map[] = {
2455 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2456 PCI_DEVICE_ID_NFP6000_PF_NIC)
2459 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2460 PCI_DEVICE_ID_NFP6000_VF_NIC)
2467 static struct eth_driver rte_nfp_net_pmd = {
2469 .id_table = pci_id_nfp_net_map,
2470 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2471 .probe = rte_eth_dev_pci_probe,
2472 .remove = rte_eth_dev_pci_remove,
2474 .eth_dev_init = nfp_net_init,
2475 .dev_private_size = sizeof(struct nfp_net_adapter),
2478 RTE_PMD_REGISTER_PCI(net_nfp, rte_nfp_net_pmd.pci_drv);
2479 RTE_PMD_REGISTER_PCI_TABLE(net_nfp, pci_id_nfp_net_map);
2480 RTE_PMD_REGISTER_KMOD_DEP(net_nfp, "* igb_uio | uio_pci_generic | vfio");
2484 * c-file-style: "Linux"
2485 * indent-tabs-mode: t