1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
9 * vim:shiftwidth=8:noexpandtab
11 * @file dpdk/pmd/nfp_net.c
13 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
19 #include <rte_debug.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
23 #include <rte_ether.h>
24 #include <rte_malloc.h>
25 #include <rte_memzone.h>
26 #include <rte_mempool.h>
27 #include <rte_version.h>
28 #include <rte_string_fns.h>
29 #include <rte_alarm.h>
30 #include <rte_spinlock.h>
31 #include <rte_service_component.h>
33 #include "nfpcore/nfp_cpp.h"
34 #include "nfpcore/nfp_nffw.h"
35 #include "nfpcore/nfp_hwinfo.h"
36 #include "nfpcore/nfp_mip.h"
37 #include "nfpcore/nfp_rtsym.h"
38 #include "nfpcore/nfp_nsp.h"
40 #include "nfp_net_pmd.h"
41 #include "nfp_net_logs.h"
42 #include "nfp_net_ctrl.h"
44 #include <sys/types.h>
45 #include <sys/socket.h>
49 #include <sys/ioctl.h>
53 static int nfp_net_close(struct rte_eth_dev *dev);
54 static int nfp_net_configure(struct rte_eth_dev *dev);
55 static void nfp_net_dev_interrupt_handler(void *param);
56 static void nfp_net_dev_interrupt_delayed_handler(void *param);
57 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
58 static int nfp_net_infos_get(struct rte_eth_dev *dev,
59 struct rte_eth_dev_info *dev_info);
60 static int nfp_net_init(struct rte_eth_dev *eth_dev);
61 static int nfp_pf_init(struct rte_eth_dev *eth_dev);
62 static int nfp_pci_uninit(struct rte_eth_dev *eth_dev);
63 static int nfp_init_phyports(struct nfp_pf_dev *pf_dev);
64 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
65 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
66 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
67 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
68 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
70 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
72 static void nfp_net_rx_queue_release(void *rxq);
73 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
74 uint16_t nb_desc, unsigned int socket_id,
75 const struct rte_eth_rxconf *rx_conf,
76 struct rte_mempool *mp);
77 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
78 static void nfp_net_tx_queue_release(void *txq);
79 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
80 uint16_t nb_desc, unsigned int socket_id,
81 const struct rte_eth_txconf *tx_conf);
82 static int nfp_net_start(struct rte_eth_dev *dev);
83 static int nfp_net_stats_get(struct rte_eth_dev *dev,
84 struct rte_eth_stats *stats);
85 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
86 static int nfp_net_stop(struct rte_eth_dev *dev);
87 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
90 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
91 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
92 struct rte_eth_rss_conf *rss_conf);
93 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
94 struct rte_eth_rss_reta_entry64 *reta_conf,
96 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
97 struct rte_eth_rss_conf *rss_conf);
98 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
99 struct rte_ether_addr *mac_addr);
100 static int32_t nfp_cpp_bridge_service_func(void *args);
101 static int nfp_fw_setup(struct rte_pci_device *dev,
103 struct nfp_eth_table *nfp_eth_table,
104 struct nfp_hwinfo *hwinfo);
107 /* The offset of the queue controller queues in the PCIe Target */
108 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
110 /* Maximum value which can be added to a queue with one transaction */
111 #define NFP_QCP_MAX_ADD 0x7f
113 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
114 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
116 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
118 NFP_QCP_READ_PTR = 0,
123 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
124 * @q: Base address for queue structure
125 * @ptr: Add to the Read or Write pointer
126 * @val: Value to add to the queue pointer
128 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
131 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
135 if (ptr == NFP_QCP_READ_PTR)
136 off = NFP_QCP_QUEUE_ADD_RPTR;
138 off = NFP_QCP_QUEUE_ADD_WPTR;
140 while (val > NFP_QCP_MAX_ADD) {
141 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
142 val -= NFP_QCP_MAX_ADD;
145 nn_writel(rte_cpu_to_le_32(val), q + off);
149 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
150 * @q: Base address for queue structure
151 * @ptr: Read or Write pointer
153 static inline uint32_t
154 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
159 if (ptr == NFP_QCP_READ_PTR)
160 off = NFP_QCP_QUEUE_STS_LO;
162 off = NFP_QCP_QUEUE_STS_HI;
164 val = rte_cpu_to_le_32(nn_readl(q + off));
166 if (ptr == NFP_QCP_READ_PTR)
167 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
169 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
173 * Functions to read/write from/to Config BAR
174 * Performs any endian conversion necessary.
176 static inline uint8_t
177 nn_cfg_readb(struct nfp_net_hw *hw, int off)
179 return nn_readb(hw->ctrl_bar + off);
183 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
185 nn_writeb(val, hw->ctrl_bar + off);
188 static inline uint32_t
189 nn_cfg_readl(struct nfp_net_hw *hw, int off)
191 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
195 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
197 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
200 static inline uint64_t
201 nn_cfg_readq(struct nfp_net_hw *hw, int off)
203 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
207 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
209 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
213 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
217 if (rxq->rxbufs == NULL)
220 for (i = 0; i < rxq->rx_count; i++) {
221 if (rxq->rxbufs[i].mbuf) {
222 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
223 rxq->rxbufs[i].mbuf = NULL;
229 nfp_net_rx_queue_release(void *rx_queue)
231 struct nfp_net_rxq *rxq = rx_queue;
234 nfp_net_rx_queue_release_mbufs(rxq);
235 rte_free(rxq->rxbufs);
241 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
243 nfp_net_rx_queue_release_mbufs(rxq);
249 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
253 if (txq->txbufs == NULL)
256 for (i = 0; i < txq->tx_count; i++) {
257 if (txq->txbufs[i].mbuf) {
258 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
259 txq->txbufs[i].mbuf = NULL;
265 nfp_net_tx_queue_release(void *tx_queue)
267 struct nfp_net_txq *txq = tx_queue;
270 nfp_net_tx_queue_release_mbufs(txq);
271 rte_free(txq->txbufs);
277 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
279 nfp_net_tx_queue_release_mbufs(txq);
285 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
289 struct timespec wait;
291 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
294 if (hw->qcp_cfg == NULL)
295 rte_panic("Bad configuration queue pointer\n");
297 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
300 wait.tv_nsec = 1000000;
302 PMD_DRV_LOG(DEBUG, "Polling for update ack...");
304 /* Poll update field, waiting for NFP to ack the config */
305 for (cnt = 0; ; cnt++) {
306 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
309 if (new & NFP_NET_CFG_UPDATE_ERR) {
310 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
313 if (cnt >= NFP_NET_POLL_TIMEOUT) {
314 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
315 " %dms", update, cnt);
316 rte_panic("Exiting\n");
318 nanosleep(&wait, 0); /* waiting for a 1ms */
320 PMD_DRV_LOG(DEBUG, "Ack DONE");
325 * Reconfigure the NIC
326 * @nn: device to reconfigure
327 * @ctrl: The value for the ctrl field in the BAR config
328 * @update: The value for the update field in the BAR config
330 * Write the update word to the BAR and ping the reconfig queue. Then poll
331 * until the firmware has acknowledged the update by zeroing the update word.
334 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
338 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
341 rte_spinlock_lock(&hw->reconfig_lock);
343 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
344 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
348 err = __nfp_net_reconfig(hw, update);
350 rte_spinlock_unlock(&hw->reconfig_lock);
356 * Reconfig errors imply situations where they can be handled.
357 * Otherwise, rte_panic is called inside __nfp_net_reconfig
359 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
365 * Configure an Ethernet device. This function must be invoked first
366 * before any other function in the Ethernet API. This function can
367 * also be re-invoked when a device is in the stopped state.
370 nfp_net_configure(struct rte_eth_dev *dev)
372 struct rte_eth_conf *dev_conf;
373 struct rte_eth_rxmode *rxmode;
374 struct rte_eth_txmode *txmode;
375 struct nfp_net_hw *hw;
377 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
380 * A DPDK app sends info about how many queues to use and how
381 * those queues need to be configured. This is used by the
382 * DPDK core and it makes sure no more queues than those
383 * advertised by the driver are requested. This function is
384 * called after that internal process
387 PMD_INIT_LOG(DEBUG, "Configure");
389 dev_conf = &dev->data->dev_conf;
390 rxmode = &dev_conf->rxmode;
391 txmode = &dev_conf->txmode;
393 if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
394 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
396 /* Checking TX mode */
397 if (txmode->mq_mode) {
398 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
402 /* Checking RX mode */
403 if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
404 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
405 PMD_INIT_LOG(INFO, "RSS not supported");
413 nfp_net_enable_queues(struct rte_eth_dev *dev)
415 struct nfp_net_hw *hw;
416 uint64_t enabled_queues = 0;
419 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
421 /* Enabling the required TX queues in the device */
422 for (i = 0; i < dev->data->nb_tx_queues; i++)
423 enabled_queues |= (1 << i);
425 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
429 /* Enabling the required RX queues in the device */
430 for (i = 0; i < dev->data->nb_rx_queues; i++)
431 enabled_queues |= (1 << i);
433 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
437 nfp_net_disable_queues(struct rte_eth_dev *dev)
439 struct nfp_net_hw *hw;
440 uint32_t new_ctrl, update = 0;
442 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
444 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
445 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
447 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
448 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
449 NFP_NET_CFG_UPDATE_MSIX;
451 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
452 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
454 /* If an error when reconfig we avoid to change hw state */
455 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
462 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
466 for (i = 0; i < dev->data->nb_rx_queues; i++) {
467 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
474 nfp_net_params_setup(struct nfp_net_hw *hw)
476 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
477 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
481 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
483 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
486 #define ETH_ADDR_LEN 6
489 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
493 for (i = 0; i < ETH_ADDR_LEN; i++)
498 nfp_net_pf_read_mac(struct nfp_pf_dev *pf_dev, int port)
500 struct nfp_eth_table *nfp_eth_table;
501 struct nfp_net_hw *hw = NULL;
503 /* Grab a pointer to the correct physical port */
504 hw = pf_dev->ports[port];
506 nfp_eth_table = nfp_eth_read_ports(pf_dev->cpp);
508 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
509 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
516 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
520 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
521 memcpy(&hw->mac_addr[0], &tmp, 4);
523 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
524 memcpy(&hw->mac_addr[4], &tmp, 2);
528 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
530 uint32_t mac0 = *(uint32_t *)mac;
533 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
536 mac1 = *(uint16_t *)mac;
537 nn_writew(rte_cpu_to_be_16(mac1),
538 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
542 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
544 struct nfp_net_hw *hw;
545 uint32_t update, ctrl;
547 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
548 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
549 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
550 PMD_INIT_LOG(INFO, "MAC address unable to change when"
555 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
556 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
559 /* Writing new MAC to the specific port BAR address */
560 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
562 /* Signal the NIC about the change */
563 update = NFP_NET_CFG_UPDATE_MACADDR;
565 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
566 (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
567 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
568 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
569 PMD_INIT_LOG(INFO, "MAC address update failed");
576 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
577 struct rte_intr_handle *intr_handle)
579 struct nfp_net_hw *hw;
582 if (!intr_handle->intr_vec) {
583 intr_handle->intr_vec =
584 rte_zmalloc("intr_vec",
585 dev->data->nb_rx_queues * sizeof(int), 0);
586 if (!intr_handle->intr_vec) {
587 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
588 " intr_vec", dev->data->nb_rx_queues);
593 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
595 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
596 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
597 /* UIO just supports one queue and no LSC*/
598 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
599 intr_handle->intr_vec[0] = 0;
601 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
602 for (i = 0; i < dev->data->nb_rx_queues; i++) {
604 * The first msix vector is reserved for non
607 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
608 intr_handle->intr_vec[i] = i + 1;
609 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
610 intr_handle->intr_vec[i]);
614 /* Avoiding TX interrupts */
615 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
620 nfp_check_offloads(struct rte_eth_dev *dev)
622 struct nfp_net_hw *hw;
623 struct rte_eth_conf *dev_conf;
624 struct rte_eth_rxmode *rxmode;
625 struct rte_eth_txmode *txmode;
628 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
630 dev_conf = &dev->data->dev_conf;
631 rxmode = &dev_conf->rxmode;
632 txmode = &dev_conf->txmode;
634 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
635 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
636 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
639 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
640 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
641 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
644 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
645 hw->mtu = rxmode->max_rx_pkt_len;
647 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
648 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
651 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
652 ctrl |= NFP_NET_CFG_CTRL_L2BC;
655 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
656 ctrl |= NFP_NET_CFG_CTRL_L2MC;
658 /* TX checksum offload */
659 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
660 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
661 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
662 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
665 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
666 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
667 ctrl |= NFP_NET_CFG_CTRL_LSO;
669 ctrl |= NFP_NET_CFG_CTRL_LSO2;
673 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
674 ctrl |= NFP_NET_CFG_CTRL_GATHER;
680 nfp_net_start(struct rte_eth_dev *dev)
682 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
683 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
684 uint32_t new_ctrl, update = 0;
685 struct nfp_net_hw *hw;
686 struct nfp_pf_dev *pf_dev;
687 struct rte_eth_conf *dev_conf;
688 struct rte_eth_rxmode *rxmode;
689 uint32_t intr_vector;
692 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
693 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(dev->data->dev_private);
695 PMD_INIT_LOG(DEBUG, "Start");
697 /* Disabling queues just in case... */
698 nfp_net_disable_queues(dev);
700 /* Enabling the required queues in the device */
701 nfp_net_enable_queues(dev);
703 /* check and configure queue intr-vector mapping */
704 if (dev->data->dev_conf.intr_conf.rxq != 0) {
705 if (pf_dev->multiport) {
706 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
707 "with NFP multiport PF");
710 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
712 * Better not to share LSC with RX interrupts.
713 * Unregistering LSC interrupt handler
715 rte_intr_callback_unregister(&pci_dev->intr_handle,
716 nfp_net_dev_interrupt_handler, (void *)dev);
718 if (dev->data->nb_rx_queues > 1) {
719 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
720 "supports 1 queue with UIO");
724 intr_vector = dev->data->nb_rx_queues;
725 if (rte_intr_efd_enable(intr_handle, intr_vector))
728 nfp_configure_rx_interrupt(dev, intr_handle);
729 update = NFP_NET_CFG_UPDATE_MSIX;
732 rte_intr_enable(intr_handle);
734 new_ctrl = nfp_check_offloads(dev);
736 /* Writing configuration parameters in the device */
737 nfp_net_params_setup(hw);
739 dev_conf = &dev->data->dev_conf;
740 rxmode = &dev_conf->rxmode;
742 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
743 nfp_net_rss_config_default(dev);
744 update |= NFP_NET_CFG_UPDATE_RSS;
745 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
749 new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
751 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
753 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
754 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
756 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
757 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
761 * Allocating rte mbufs for configured rx queues.
762 * This requires queues being enabled before
764 if (nfp_net_rx_freelist_setup(dev) < 0) {
769 if (hw->is_phyport) {
770 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
771 /* Configure the physical port up */
772 nfp_eth_set_configured(hw->cpp, hw->idx, 1);
774 nfp_eth_set_configured(dev->process_private,
784 * An error returned by this function should mean the app
785 * exiting and then the system releasing all the memory
786 * allocated even memory coming from hugepages.
788 * The device could be enabled at this point with some queues
789 * ready for getting packets. This is true if the call to
790 * nfp_net_rx_freelist_setup() succeeds for some queues but
791 * fails for subsequent queues.
793 * This should make the app exiting but better if we tell the
796 nfp_net_disable_queues(dev);
801 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
803 nfp_net_stop(struct rte_eth_dev *dev)
806 struct nfp_net_hw *hw;
808 PMD_INIT_LOG(DEBUG, "Stop");
810 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
812 nfp_net_disable_queues(dev);
815 for (i = 0; i < dev->data->nb_tx_queues; i++) {
816 nfp_net_reset_tx_queue(
817 (struct nfp_net_txq *)dev->data->tx_queues[i]);
820 for (i = 0; i < dev->data->nb_rx_queues; i++) {
821 nfp_net_reset_rx_queue(
822 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
825 if (hw->is_phyport) {
826 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
827 /* Configure the physical port down */
828 nfp_eth_set_configured(hw->cpp, hw->idx, 0);
830 nfp_eth_set_configured(dev->process_private,
837 /* Set the link up. */
839 nfp_net_set_link_up(struct rte_eth_dev *dev)
841 struct nfp_net_hw *hw;
843 PMD_DRV_LOG(DEBUG, "Set link up");
845 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
850 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
851 /* Configure the physical port down */
852 return nfp_eth_set_configured(hw->cpp, hw->idx, 1);
854 return nfp_eth_set_configured(dev->process_private,
858 /* Set the link down. */
860 nfp_net_set_link_down(struct rte_eth_dev *dev)
862 struct nfp_net_hw *hw;
864 PMD_DRV_LOG(DEBUG, "Set link down");
866 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
871 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
872 /* Configure the physical port down */
873 return nfp_eth_set_configured(hw->cpp, hw->idx, 0);
875 return nfp_eth_set_configured(dev->process_private,
879 /* Reset and stop device. The device can not be restarted. */
881 nfp_net_close(struct rte_eth_dev *dev)
883 struct nfp_net_hw *hw;
884 struct rte_pci_device *pci_dev;
887 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
890 PMD_INIT_LOG(DEBUG, "Close");
892 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
893 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
896 * We assume that the DPDK application is stopping all the
897 * threads/queues before calling the device close function.
900 nfp_net_disable_queues(dev);
903 for (i = 0; i < dev->data->nb_tx_queues; i++) {
904 nfp_net_reset_tx_queue(
905 (struct nfp_net_txq *)dev->data->tx_queues[i]);
908 for (i = 0; i < dev->data->nb_rx_queues; i++) {
909 nfp_net_reset_rx_queue(
910 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
913 /* Only free PF resources after all physical ports have been closed */
914 if (pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC ||
915 pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC) {
916 struct nfp_pf_dev *pf_dev;
917 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(dev->data->dev_private);
919 /* Mark this port as unused and free device priv resources*/
920 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
921 pf_dev->ports[hw->idx] = NULL;
922 rte_eth_dev_release_port(dev);
924 for (i = 0; i < pf_dev->total_phyports; i++) {
925 /* Check to see if ports are still in use */
926 if (pf_dev->ports[i])
930 /* Now it is safe to free all PF resources */
931 PMD_INIT_LOG(INFO, "Freeing PF resources");
932 nfp_cpp_area_free(pf_dev->ctrl_area);
933 nfp_cpp_area_free(pf_dev->hwqueues_area);
934 free(pf_dev->hwinfo);
935 free(pf_dev->sym_tbl);
936 nfp_cpp_free(pf_dev->cpp);
940 rte_intr_disable(&pci_dev->intr_handle);
942 /* unregister callback func from eal lib */
943 rte_intr_callback_unregister(&pci_dev->intr_handle,
944 nfp_net_dev_interrupt_handler,
948 * The ixgbe PMD driver disables the pcie master on the
949 * device. The i40e does not...
956 nfp_net_promisc_enable(struct rte_eth_dev *dev)
958 uint32_t new_ctrl, update = 0;
959 struct nfp_net_hw *hw;
962 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
964 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
966 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
967 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
971 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
972 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
976 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
977 update = NFP_NET_CFG_UPDATE_GEN;
980 * DPDK sets promiscuous mode on just after this call assuming
981 * it can not fail ...
983 ret = nfp_net_reconfig(hw, new_ctrl, update);
993 nfp_net_promisc_disable(struct rte_eth_dev *dev)
995 uint32_t new_ctrl, update = 0;
996 struct nfp_net_hw *hw;
999 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1001 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
1002 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
1006 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
1007 update = NFP_NET_CFG_UPDATE_GEN;
1010 * DPDK sets promiscuous mode off just before this call
1011 * assuming it can not fail ...
1013 ret = nfp_net_reconfig(hw, new_ctrl, update);
1017 hw->ctrl = new_ctrl;
1023 * return 0 means link status changed, -1 means not changed
1025 * Wait to complete is needed as it can take up to 9 seconds to get the Link
1029 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1031 struct nfp_net_hw *hw;
1032 struct rte_eth_link link;
1033 uint32_t nn_link_status;
1036 static const uint32_t ls_to_ethtool[] = {
1037 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
1038 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
1039 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
1040 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
1041 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
1042 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
1043 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
1044 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
1047 PMD_DRV_LOG(DEBUG, "Link update");
1049 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1051 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1053 memset(&link, 0, sizeof(struct rte_eth_link));
1055 if (nn_link_status & NFP_NET_CFG_STS_LINK)
1056 link.link_status = ETH_LINK_UP;
1058 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1060 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1061 NFP_NET_CFG_STS_LINK_RATE_MASK;
1063 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1064 link.link_speed = ETH_SPEED_NUM_NONE;
1066 link.link_speed = ls_to_ethtool[nn_link_status];
1068 ret = rte_eth_linkstatus_set(dev, &link);
1070 if (link.link_status)
1071 PMD_DRV_LOG(INFO, "NIC Link is Up");
1073 PMD_DRV_LOG(INFO, "NIC Link is Down");
1079 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1082 struct nfp_net_hw *hw;
1083 struct rte_eth_stats nfp_dev_stats;
1085 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1087 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1089 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1091 /* reading per RX ring stats */
1092 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1093 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1096 nfp_dev_stats.q_ipackets[i] =
1097 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1099 nfp_dev_stats.q_ipackets[i] -=
1100 hw->eth_stats_base.q_ipackets[i];
1102 nfp_dev_stats.q_ibytes[i] =
1103 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1105 nfp_dev_stats.q_ibytes[i] -=
1106 hw->eth_stats_base.q_ibytes[i];
1109 /* reading per TX ring stats */
1110 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1111 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1114 nfp_dev_stats.q_opackets[i] =
1115 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1117 nfp_dev_stats.q_opackets[i] -=
1118 hw->eth_stats_base.q_opackets[i];
1120 nfp_dev_stats.q_obytes[i] =
1121 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1123 nfp_dev_stats.q_obytes[i] -=
1124 hw->eth_stats_base.q_obytes[i];
1127 nfp_dev_stats.ipackets =
1128 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1130 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1132 nfp_dev_stats.ibytes =
1133 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1135 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1137 nfp_dev_stats.opackets =
1138 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1140 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1142 nfp_dev_stats.obytes =
1143 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1145 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1147 /* reading general device stats */
1148 nfp_dev_stats.ierrors =
1149 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1151 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1153 nfp_dev_stats.oerrors =
1154 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1156 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1158 /* RX ring mbuf allocation failures */
1159 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1161 nfp_dev_stats.imissed =
1162 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1164 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1167 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1174 nfp_net_stats_reset(struct rte_eth_dev *dev)
1177 struct nfp_net_hw *hw;
1179 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1182 * hw->eth_stats_base records the per counter starting point.
1183 * Lets update it now
1186 /* reading per RX ring stats */
1187 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1188 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1191 hw->eth_stats_base.q_ipackets[i] =
1192 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1194 hw->eth_stats_base.q_ibytes[i] =
1195 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1198 /* reading per TX ring stats */
1199 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1200 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1203 hw->eth_stats_base.q_opackets[i] =
1204 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1206 hw->eth_stats_base.q_obytes[i] =
1207 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1210 hw->eth_stats_base.ipackets =
1211 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1213 hw->eth_stats_base.ibytes =
1214 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1216 hw->eth_stats_base.opackets =
1217 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1219 hw->eth_stats_base.obytes =
1220 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1222 /* reading general device stats */
1223 hw->eth_stats_base.ierrors =
1224 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1226 hw->eth_stats_base.oerrors =
1227 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1229 /* RX ring mbuf allocation failures */
1230 dev->data->rx_mbuf_alloc_failed = 0;
1232 hw->eth_stats_base.imissed =
1233 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1239 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1241 struct nfp_net_hw *hw;
1243 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1246 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1247 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1248 dev_info->max_rx_pktlen = hw->max_mtu;
1249 /* Next should change when PF support is implemented */
1250 dev_info->max_mac_addrs = 1;
1252 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1253 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1255 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1256 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1257 DEV_RX_OFFLOAD_UDP_CKSUM |
1258 DEV_RX_OFFLOAD_TCP_CKSUM;
1260 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME |
1261 DEV_RX_OFFLOAD_RSS_HASH;
1263 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1264 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1266 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1267 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1268 DEV_TX_OFFLOAD_UDP_CKSUM |
1269 DEV_TX_OFFLOAD_TCP_CKSUM;
1271 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1272 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1274 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1275 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1277 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1279 .pthresh = DEFAULT_RX_PTHRESH,
1280 .hthresh = DEFAULT_RX_HTHRESH,
1281 .wthresh = DEFAULT_RX_WTHRESH,
1283 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1287 dev_info->default_txconf = (struct rte_eth_txconf) {
1289 .pthresh = DEFAULT_TX_PTHRESH,
1290 .hthresh = DEFAULT_TX_HTHRESH,
1291 .wthresh = DEFAULT_TX_WTHRESH,
1293 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1294 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1297 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1298 .nb_max = NFP_NET_MAX_RX_DESC,
1299 .nb_min = NFP_NET_MIN_RX_DESC,
1300 .nb_align = NFP_ALIGN_RING_DESC,
1303 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1304 .nb_max = NFP_NET_MAX_TX_DESC,
1305 .nb_min = NFP_NET_MIN_TX_DESC,
1306 .nb_align = NFP_ALIGN_RING_DESC,
1307 .nb_seg_max = NFP_TX_MAX_SEG,
1308 .nb_mtu_seg_max = NFP_TX_MAX_MTU_SEG,
1311 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1312 ETH_RSS_NONFRAG_IPV4_TCP |
1313 ETH_RSS_NONFRAG_IPV4_UDP |
1315 ETH_RSS_NONFRAG_IPV6_TCP |
1316 ETH_RSS_NONFRAG_IPV6_UDP;
1318 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1319 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1321 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1322 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1323 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1328 static const uint32_t *
1329 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1331 static const uint32_t ptypes[] = {
1332 /* refers to nfp_net_set_hash() */
1333 RTE_PTYPE_INNER_L3_IPV4,
1334 RTE_PTYPE_INNER_L3_IPV6,
1335 RTE_PTYPE_INNER_L3_IPV6_EXT,
1336 RTE_PTYPE_INNER_L4_MASK,
1340 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1346 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1348 struct nfp_net_rxq *rxq;
1349 struct nfp_net_rx_desc *rxds;
1353 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1360 * Other PMDs are just checking the DD bit in intervals of 4
1361 * descriptors and counting all four if the first has the DD
1362 * bit on. Of course, this is not accurate but can be good for
1363 * performance. But ideally that should be done in descriptors
1364 * chunks belonging to the same cache line
1367 while (count < rxq->rx_count) {
1368 rxds = &rxq->rxds[idx];
1369 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1376 if ((idx) == rxq->rx_count)
1384 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1386 struct rte_pci_device *pci_dev;
1387 struct nfp_net_hw *hw;
1390 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1391 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1393 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1396 /* Make sure all updates are written before un-masking */
1398 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1399 NFP_NET_CFG_ICR_UNMASKED);
1404 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1406 struct rte_pci_device *pci_dev;
1407 struct nfp_net_hw *hw;
1410 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1411 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1413 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1416 /* Make sure all updates are written before un-masking */
1418 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1423 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1425 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1426 struct rte_eth_link link;
1428 rte_eth_linkstatus_get(dev, &link);
1429 if (link.link_status)
1430 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1431 dev->data->port_id, link.link_speed,
1432 link.link_duplex == ETH_LINK_FULL_DUPLEX
1433 ? "full-duplex" : "half-duplex");
1435 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1436 dev->data->port_id);
1438 PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
1439 pci_dev->addr.domain, pci_dev->addr.bus,
1440 pci_dev->addr.devid, pci_dev->addr.function);
1443 /* Interrupt configuration and handling */
1446 * nfp_net_irq_unmask - Unmask an interrupt
1448 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1449 * clear the ICR for the entry.
1452 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1454 struct nfp_net_hw *hw;
1455 struct rte_pci_device *pci_dev;
1457 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1460 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1461 /* If MSI-X auto-masking is used, clear the entry */
1463 rte_intr_ack(&pci_dev->intr_handle);
1465 /* Make sure all updates are written before un-masking */
1467 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1468 NFP_NET_CFG_ICR_UNMASKED);
1473 nfp_net_dev_interrupt_handler(void *param)
1476 struct rte_eth_link link;
1477 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1479 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1481 rte_eth_linkstatus_get(dev, &link);
1483 nfp_net_link_update(dev, 0);
1486 if (!link.link_status) {
1487 /* handle it 1 sec later, wait it being stable */
1488 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1489 /* likely to down */
1491 /* handle it 4 sec later, wait it being stable */
1492 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1495 if (rte_eal_alarm_set(timeout * 1000,
1496 nfp_net_dev_interrupt_delayed_handler,
1498 PMD_INIT_LOG(ERR, "Error setting alarm");
1500 nfp_net_irq_unmask(dev);
1505 * Interrupt handler which shall be registered for alarm callback for delayed
1506 * handling specific interrupt to wait for the stable nic state. As the NIC
1507 * interrupt state is not stable for nfp after link is just down, it needs
1508 * to wait 4 seconds to get the stable status.
1510 * @param handle Pointer to interrupt handle.
1511 * @param param The address of parameter (struct rte_eth_dev *)
1516 nfp_net_dev_interrupt_delayed_handler(void *param)
1518 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1520 nfp_net_link_update(dev, 0);
1521 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1523 nfp_net_dev_link_status_print(dev);
1526 nfp_net_irq_unmask(dev);
1530 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1532 struct nfp_net_hw *hw;
1534 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1536 /* check that mtu is within the allowed range */
1537 if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1540 /* mtu setting is forbidden if port is started */
1541 if (dev->data->dev_started) {
1542 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1543 dev->data->port_id);
1547 /* switch to jumbo mode if needed */
1548 if ((uint32_t)mtu > RTE_ETHER_MTU)
1549 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1551 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1553 /* update max frame size */
1554 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1556 /* writing to configuration space */
1557 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1565 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1566 uint16_t queue_idx, uint16_t nb_desc,
1567 unsigned int socket_id,
1568 const struct rte_eth_rxconf *rx_conf,
1569 struct rte_mempool *mp)
1571 const struct rte_memzone *tz;
1572 struct nfp_net_rxq *rxq;
1573 struct nfp_net_hw *hw;
1574 uint32_t rx_desc_sz;
1576 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578 PMD_INIT_FUNC_TRACE();
1580 /* Validating number of descriptors */
1581 rx_desc_sz = nb_desc * sizeof(struct nfp_net_rx_desc);
1582 if (rx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1583 nb_desc > NFP_NET_MAX_RX_DESC ||
1584 nb_desc < NFP_NET_MIN_RX_DESC) {
1585 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1590 * Free memory prior to re-allocation if needed. This is the case after
1591 * calling nfp_net_stop
1593 if (dev->data->rx_queues[queue_idx]) {
1594 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1595 dev->data->rx_queues[queue_idx] = NULL;
1598 /* Allocating rx queue data structure */
1599 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1600 RTE_CACHE_LINE_SIZE, socket_id);
1604 /* Hw queues mapping based on firmware configuration */
1605 rxq->qidx = queue_idx;
1606 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1607 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1608 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1609 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1612 * Tracking mbuf size for detecting a potential mbuf overflow due to
1616 rxq->mbuf_size = rxq->mem_pool->elt_size;
1617 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1618 hw->flbufsz = rxq->mbuf_size;
1620 rxq->rx_count = nb_desc;
1621 rxq->port_id = dev->data->port_id;
1622 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1623 rxq->drop_en = rx_conf->rx_drop_en;
1626 * Allocate RX ring hardware descriptors. A memzone large enough to
1627 * handle the maximum ring size is allocated in order to allow for
1628 * resizing in later calls to the queue setup function.
1630 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1631 sizeof(struct nfp_net_rx_desc) *
1632 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1636 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1637 nfp_net_rx_queue_release(rxq);
1641 /* Saving physical and virtual addresses for the RX ring */
1642 rxq->dma = (uint64_t)tz->iova;
1643 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1645 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1646 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1647 sizeof(*rxq->rxbufs) * nb_desc,
1648 RTE_CACHE_LINE_SIZE, socket_id);
1649 if (rxq->rxbufs == NULL) {
1650 nfp_net_rx_queue_release(rxq);
1654 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1655 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1657 nfp_net_reset_rx_queue(rxq);
1659 dev->data->rx_queues[queue_idx] = rxq;
1663 * Telling the HW about the physical address of the RX ring and number
1664 * of descriptors in log2 format
1666 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1667 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1673 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1675 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1679 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1682 for (i = 0; i < rxq->rx_count; i++) {
1683 struct nfp_net_rx_desc *rxd;
1684 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1687 PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1688 (unsigned)rxq->qidx);
1692 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1694 rxd = &rxq->rxds[i];
1696 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1697 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1699 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1702 /* Make sure all writes are flushed before telling the hardware */
1705 /* Not advertising the whole ring as the firmware gets confused if so */
1706 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1709 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1715 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1716 uint16_t nb_desc, unsigned int socket_id,
1717 const struct rte_eth_txconf *tx_conf)
1719 const struct rte_memzone *tz;
1720 struct nfp_net_txq *txq;
1721 uint16_t tx_free_thresh;
1722 struct nfp_net_hw *hw;
1723 uint32_t tx_desc_sz;
1725 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727 PMD_INIT_FUNC_TRACE();
1729 /* Validating number of descriptors */
1730 tx_desc_sz = nb_desc * sizeof(struct nfp_net_tx_desc);
1731 if (tx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1732 nb_desc > NFP_NET_MAX_TX_DESC ||
1733 nb_desc < NFP_NET_MIN_TX_DESC) {
1734 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1738 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1739 tx_conf->tx_free_thresh :
1740 DEFAULT_TX_FREE_THRESH);
1742 if (tx_free_thresh > (nb_desc)) {
1744 "tx_free_thresh must be less than the number of TX "
1745 "descriptors. (tx_free_thresh=%u port=%d "
1746 "queue=%d)", (unsigned int)tx_free_thresh,
1747 dev->data->port_id, (int)queue_idx);
1752 * Free memory prior to re-allocation if needed. This is the case after
1753 * calling nfp_net_stop
1755 if (dev->data->tx_queues[queue_idx]) {
1756 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1758 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1759 dev->data->tx_queues[queue_idx] = NULL;
1762 /* Allocating tx queue data structure */
1763 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1764 RTE_CACHE_LINE_SIZE, socket_id);
1766 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1771 * Allocate TX ring hardware descriptors. A memzone large enough to
1772 * handle the maximum ring size is allocated in order to allow for
1773 * resizing in later calls to the queue setup function.
1775 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1776 sizeof(struct nfp_net_tx_desc) *
1777 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1780 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1781 nfp_net_tx_queue_release(txq);
1785 txq->tx_count = nb_desc;
1786 txq->tx_free_thresh = tx_free_thresh;
1787 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1788 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1789 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1791 /* queue mapping based on firmware configuration */
1792 txq->qidx = queue_idx;
1793 txq->tx_qcidx = queue_idx * hw->stride_tx;
1794 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1796 txq->port_id = dev->data->port_id;
1798 /* Saving physical and virtual addresses for the TX ring */
1799 txq->dma = (uint64_t)tz->iova;
1800 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1802 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1803 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1804 sizeof(*txq->txbufs) * nb_desc,
1805 RTE_CACHE_LINE_SIZE, socket_id);
1806 if (txq->txbufs == NULL) {
1807 nfp_net_tx_queue_release(txq);
1810 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1811 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1813 nfp_net_reset_tx_queue(txq);
1815 dev->data->tx_queues[queue_idx] = txq;
1819 * Telling the HW about the physical address of the TX ring and number
1820 * of descriptors in log2 format
1822 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1823 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1828 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1830 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1831 struct rte_mbuf *mb)
1834 struct nfp_net_hw *hw = txq->hw;
1836 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1839 ol_flags = mb->ol_flags;
1841 if (!(ol_flags & PKT_TX_TCP_SEG))
1844 txd->l3_offset = mb->l2_len;
1845 txd->l4_offset = mb->l2_len + mb->l3_len;
1846 txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1847 txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1848 txd->flags = PCIE_DESC_TX_LSO;
1855 txd->lso_hdrlen = 0;
1859 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1861 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1862 struct rte_mbuf *mb)
1865 struct nfp_net_hw *hw = txq->hw;
1867 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1870 ol_flags = mb->ol_flags;
1872 /* IPv6 does not need checksum */
1873 if (ol_flags & PKT_TX_IP_CKSUM)
1874 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1876 switch (ol_flags & PKT_TX_L4_MASK) {
1877 case PKT_TX_UDP_CKSUM:
1878 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1880 case PKT_TX_TCP_CKSUM:
1881 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1885 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1886 txd->flags |= PCIE_DESC_TX_CSUM;
1889 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1891 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1892 struct rte_mbuf *mb)
1894 struct nfp_net_hw *hw = rxq->hw;
1896 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1899 /* If IPv4 and IP checksum error, fail */
1900 if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1901 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1902 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1904 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1906 /* If neither UDP nor TCP return */
1907 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1908 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1911 if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1912 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1914 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1917 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1918 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1920 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1923 * nfp_net_set_hash - Set mbuf hash data
1925 * The RSS hash and hash-type are pre-pended to the packet data.
1926 * Extract and decode it and set the mbuf fields.
1929 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1930 struct rte_mbuf *mbuf)
1932 struct nfp_net_hw *hw = rxq->hw;
1933 uint8_t *meta_offset;
1936 uint32_t hash_type = 0;
1938 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1941 /* this is true for new firmwares */
1942 if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1943 (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1944 NFP_DESC_META_LEN(rxd))) {
1947 * <---- 32 bit ----->
1952 * ====================
1955 * Field type word contains up to 8 4bit field types
1956 * A 4bit field type refers to a data field word
1957 * A data field word can have several 4bit field types
1959 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1960 meta_offset -= NFP_DESC_META_LEN(rxd);
1961 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1963 /* NFP PMD just supports metadata for hashing */
1964 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1965 case NFP_NET_META_HASH:
1966 /* next field type is about the hash type */
1967 meta_info >>= NFP_NET_META_FIELD_SIZE;
1968 /* hash value is in the data field */
1969 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1970 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1973 /* Unsupported metadata can be a performance issue */
1977 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1980 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1981 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1984 mbuf->hash.rss = hash;
1985 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1987 switch (hash_type) {
1988 case NFP_NET_RSS_IPV4:
1989 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1991 case NFP_NET_RSS_IPV6:
1992 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1994 case NFP_NET_RSS_IPV6_EX:
1995 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1997 case NFP_NET_RSS_IPV4_TCP:
1998 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2000 case NFP_NET_RSS_IPV6_TCP:
2001 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2003 case NFP_NET_RSS_IPV4_UDP:
2004 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2006 case NFP_NET_RSS_IPV6_UDP:
2007 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
2010 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
2015 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
2017 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
2020 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
2025 * There are some decisions to take:
2026 * 1) How to check DD RX descriptors bit
2027 * 2) How and when to allocate new mbufs
2029 * Current implementation checks just one single DD bit each loop. As each
2030 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
2031 * a single cache line instead. Tests with this change have not shown any
2032 * performance improvement but it requires further investigation. For example,
2033 * depending on which descriptor is next, the number of descriptors could be
2034 * less than 8 for just checking those in the same cache line. This implies
2035 * extra work which could be counterproductive by itself. Indeed, last firmware
2036 * changes are just doing this: writing several descriptors with the DD bit
2037 * for saving PCIe bandwidth and DMA operations from the NFP.
2039 * Mbuf allocation is done when a new packet is received. Then the descriptor
2040 * is automatically linked with the new mbuf and the old one is given to the
2041 * user. The main drawback with this design is mbuf allocation is heavier than
2042 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2043 * cache point of view it does not seem allocating the mbuf early on as we are
2044 * doing now have any benefit at all. Again, tests with this change have not
2045 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2046 * so looking at the implications of this type of allocation should be studied
2051 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2053 struct nfp_net_rxq *rxq;
2054 struct nfp_net_rx_desc *rxds;
2055 struct nfp_net_rx_buff *rxb;
2056 struct nfp_net_hw *hw;
2057 struct rte_mbuf *mb;
2058 struct rte_mbuf *new_mb;
2064 if (unlikely(rxq == NULL)) {
2066 * DPDK just checks the queue is lower than max queues
2067 * enabled. But the queue needs to be configured
2069 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2077 while (avail < nb_pkts) {
2078 rxb = &rxq->rxbufs[rxq->rd_p];
2079 if (unlikely(rxb == NULL)) {
2080 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2084 rxds = &rxq->rxds[rxq->rd_p];
2085 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2089 * Memory barrier to ensure that we won't do other
2090 * reads before the DD bit.
2095 * We got a packet. Let's alloc a new mbuf for refilling the
2096 * free descriptor ring as soon as possible
2098 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2099 if (unlikely(new_mb == NULL)) {
2100 RTE_LOG_DP(DEBUG, PMD,
2101 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2102 rxq->port_id, (unsigned int)rxq->qidx);
2103 nfp_net_mbuf_alloc_failed(rxq);
2110 * Grab the mbuf and refill the descriptor with the
2111 * previously allocated mbuf
2116 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2117 rxds->rxd.data_len, rxq->mbuf_size);
2119 /* Size of this segment */
2120 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2121 /* Size of the whole packet. We just support 1 segment */
2122 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2124 if (unlikely((mb->data_len + hw->rx_offset) >
2127 * This should not happen and the user has the
2128 * responsibility of avoiding it. But we have
2129 * to give some info about the error
2131 RTE_LOG_DP(ERR, PMD,
2132 "mbuf overflow likely due to the RX offset.\n"
2133 "\t\tYour mbuf size should have extra space for"
2134 " RX offset=%u bytes.\n"
2135 "\t\tCurrently you just have %u bytes available"
2136 " but the received packet is %u bytes long",
2138 rxq->mbuf_size - hw->rx_offset,
2143 /* Filling the received mbuf with packet info */
2145 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2147 mb->data_off = RTE_PKTMBUF_HEADROOM +
2148 NFP_DESC_META_LEN(rxds);
2150 /* No scatter mode supported */
2154 mb->port = rxq->port_id;
2156 /* Checking the RSS flag */
2157 nfp_net_set_hash(rxq, rxds, mb);
2159 /* Checking the checksum flag */
2160 nfp_net_rx_cksum(rxq, rxds, mb);
2162 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2163 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2164 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2165 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2168 /* Adding the mbuf to the mbuf array passed by the app */
2169 rx_pkts[avail++] = mb;
2171 /* Now resetting and updating the descriptor */
2174 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2176 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2177 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2180 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2187 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received",
2188 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2190 nb_hold += rxq->nb_rx_hold;
2193 * FL descriptors needs to be written before incrementing the
2194 * FL queue WR pointer
2197 if (nb_hold > rxq->rx_free_thresh) {
2198 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2199 rxq->port_id, (unsigned int)rxq->qidx,
2200 (unsigned)nb_hold, (unsigned)avail);
2201 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2204 rxq->nb_rx_hold = nb_hold;
2210 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2212 * @txq: TX queue to work with
2213 * Returns number of descriptors freed
2216 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2221 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2222 " status", txq->qidx);
2224 /* Work out how many packets have been sent */
2225 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2227 if (qcp_rd_p == txq->rd_p) {
2228 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2229 "packets (%u, %u)", txq->qidx,
2230 qcp_rd_p, txq->rd_p);
2234 if (qcp_rd_p > txq->rd_p)
2235 todo = qcp_rd_p - txq->rd_p;
2237 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2239 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2240 qcp_rd_p, txq->rd_p, txq->rd_p);
2246 if (unlikely(txq->rd_p >= txq->tx_count))
2247 txq->rd_p -= txq->tx_count;
2252 /* Leaving always free descriptors for avoiding wrapping confusion */
2254 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2256 if (txq->wr_p >= txq->rd_p)
2257 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2259 return txq->rd_p - txq->wr_p - 8;
2263 * nfp_net_txq_full - Check if the TX queue free descriptors
2264 * is below tx_free_threshold
2266 * @txq: TX queue to check
2268 * This function uses the host copy* of read/write pointers
2271 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2273 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2277 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2279 struct nfp_net_txq *txq;
2280 struct nfp_net_hw *hw;
2281 struct nfp_net_tx_desc *txds, txd;
2282 struct rte_mbuf *pkt;
2284 int pkt_size, dma_size;
2285 uint16_t free_descs, issued_descs;
2286 struct rte_mbuf **lmbuf;
2291 txds = &txq->txds[txq->wr_p];
2293 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2294 txq->qidx, txq->wr_p, nb_pkts);
2296 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2297 nfp_net_tx_free_bufs(txq);
2299 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2300 if (unlikely(free_descs == 0))
2307 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2308 txq->qidx, nb_pkts);
2309 /* Sending packets */
2310 while ((i < nb_pkts) && free_descs) {
2311 /* Grabbing the mbuf linked to the current descriptor */
2312 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2313 /* Warming the cache for releasing the mbuf later on */
2314 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2316 pkt = *(tx_pkts + i);
2318 if (unlikely((pkt->nb_segs > 1) &&
2319 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2320 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2321 rte_panic("Multisegment packet unsupported\n");
2324 /* Checking if we have enough descriptors */
2325 if (unlikely(pkt->nb_segs > free_descs))
2329 * Checksum and VLAN flags just in the first descriptor for a
2330 * multisegment packet, but TSO info needs to be in all of them.
2332 txd.data_len = pkt->pkt_len;
2333 nfp_net_tx_tso(txq, &txd, pkt);
2334 nfp_net_tx_cksum(txq, &txd, pkt);
2336 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2337 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2338 txd.flags |= PCIE_DESC_TX_VLAN;
2339 txd.vlan = pkt->vlan_tci;
2343 * mbuf data_len is the data in one segment and pkt_len data
2344 * in the whole packet. When the packet is just one segment,
2345 * then data_len = pkt_len
2347 pkt_size = pkt->pkt_len;
2350 /* Copying TSO, VLAN and cksum info */
2353 /* Releasing mbuf used by this descriptor previously*/
2355 rte_pktmbuf_free_seg(*lmbuf);
2358 * Linking mbuf with descriptor for being released
2359 * next time descriptor is used
2363 dma_size = pkt->data_len;
2364 dma_addr = rte_mbuf_data_iova(pkt);
2365 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2366 "%" PRIx64 "", dma_addr);
2368 /* Filling descriptors fields */
2369 txds->dma_len = dma_size;
2370 txds->data_len = txd.data_len;
2371 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2372 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2373 ASSERT(free_descs > 0);
2377 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2380 pkt_size -= dma_size;
2383 * Making the EOP, packets with just one segment
2386 if (likely(!pkt_size))
2387 txds->offset_eop = PCIE_DESC_TX_EOP;
2389 txds->offset_eop = 0;
2392 /* Referencing next free TX descriptor */
2393 txds = &txq->txds[txq->wr_p];
2394 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2401 /* Increment write pointers. Force memory write before we let HW know */
2403 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2409 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2411 uint32_t new_ctrl, update;
2412 struct nfp_net_hw *hw;
2415 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2418 /* Enable vlan strip if it is not configured yet */
2419 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2420 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2421 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2423 /* Disable vlan strip just if it is configured */
2424 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2425 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2426 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2431 update = NFP_NET_CFG_UPDATE_GEN;
2433 ret = nfp_net_reconfig(hw, new_ctrl, update);
2435 hw->ctrl = new_ctrl;
2441 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2442 struct rte_eth_rss_reta_entry64 *reta_conf,
2445 uint32_t reta, mask;
2448 struct nfp_net_hw *hw =
2449 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2451 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2452 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2453 "(%d) doesn't match the number hardware can supported "
2454 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2459 * Update Redirection Table. There are 128 8bit-entries which can be
2460 * manage as 32 32bit-entries
2462 for (i = 0; i < reta_size; i += 4) {
2463 /* Handling 4 RSS entries per loop */
2464 idx = i / RTE_RETA_GROUP_SIZE;
2465 shift = i % RTE_RETA_GROUP_SIZE;
2466 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2472 /* If all 4 entries were set, don't need read RETA register */
2474 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2476 for (j = 0; j < 4; j++) {
2477 if (!(mask & (0x1 << j)))
2480 /* Clearing the entry bits */
2481 reta &= ~(0xFF << (8 * j));
2482 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2484 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2490 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2492 nfp_net_reta_update(struct rte_eth_dev *dev,
2493 struct rte_eth_rss_reta_entry64 *reta_conf,
2496 struct nfp_net_hw *hw =
2497 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2501 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2504 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2508 update = NFP_NET_CFG_UPDATE_RSS;
2510 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2516 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2518 nfp_net_reta_query(struct rte_eth_dev *dev,
2519 struct rte_eth_rss_reta_entry64 *reta_conf,
2525 struct nfp_net_hw *hw;
2527 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2529 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2532 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2533 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2534 "(%d) doesn't match the number hardware can supported "
2535 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2540 * Reading Redirection Table. There are 128 8bit-entries which can be
2541 * manage as 32 32bit-entries
2543 for (i = 0; i < reta_size; i += 4) {
2544 /* Handling 4 RSS entries per loop */
2545 idx = i / RTE_RETA_GROUP_SIZE;
2546 shift = i % RTE_RETA_GROUP_SIZE;
2547 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2552 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2554 for (j = 0; j < 4; j++) {
2555 if (!(mask & (0x1 << j)))
2557 reta_conf[idx].reta[shift + j] =
2558 (uint8_t)((reta >> (8 * j)) & 0xF);
2565 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2566 struct rte_eth_rss_conf *rss_conf)
2568 struct nfp_net_hw *hw;
2570 uint32_t cfg_rss_ctrl = 0;
2574 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576 /* Writing the key byte a byte */
2577 for (i = 0; i < rss_conf->rss_key_len; i++) {
2578 memcpy(&key, &rss_conf->rss_key[i], 1);
2579 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2582 rss_hf = rss_conf->rss_hf;
2584 if (rss_hf & ETH_RSS_IPV4)
2585 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2587 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2588 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2590 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2591 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2593 if (rss_hf & ETH_RSS_IPV6)
2594 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2596 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2597 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2599 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2600 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2602 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2603 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2605 /* configuring where to apply the RSS hash */
2606 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2608 /* Writing the key size */
2609 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2615 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2616 struct rte_eth_rss_conf *rss_conf)
2620 struct nfp_net_hw *hw;
2622 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2624 rss_hf = rss_conf->rss_hf;
2626 /* Checking if RSS is enabled */
2627 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2628 if (rss_hf != 0) { /* Enable RSS? */
2629 PMD_DRV_LOG(ERR, "RSS unsupported");
2632 return 0; /* Nothing to do */
2635 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2636 PMD_DRV_LOG(ERR, "hash key too long");
2640 nfp_net_rss_hash_write(dev, rss_conf);
2642 update = NFP_NET_CFG_UPDATE_RSS;
2644 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2651 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2652 struct rte_eth_rss_conf *rss_conf)
2655 uint32_t cfg_rss_ctrl;
2658 struct nfp_net_hw *hw;
2660 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2662 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2665 rss_hf = rss_conf->rss_hf;
2666 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2668 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2669 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2671 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2672 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2674 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2675 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2677 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2678 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2680 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2681 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2683 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2684 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2686 /* Propagate current RSS hash functions to caller */
2687 rss_conf->rss_hf = rss_hf;
2689 /* Reading the key size */
2690 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2692 /* Reading the key byte a byte */
2693 for (i = 0; i < rss_conf->rss_key_len; i++) {
2694 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2695 memcpy(&rss_conf->rss_key[i], &key, 1);
2702 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2704 struct rte_eth_conf *dev_conf;
2705 struct rte_eth_rss_conf rss_conf;
2706 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2707 uint16_t rx_queues = dev->data->nb_rx_queues;
2711 PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2714 nfp_reta_conf[0].mask = ~0x0;
2715 nfp_reta_conf[1].mask = ~0x0;
2718 for (i = 0; i < 0x40; i += 8) {
2719 for (j = i; j < (i + 8); j++) {
2720 nfp_reta_conf[0].reta[j] = queue;
2721 nfp_reta_conf[1].reta[j] = queue++;
2725 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2729 dev_conf = &dev->data->dev_conf;
2731 PMD_DRV_LOG(INFO, "wrong rss conf");
2734 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2736 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2742 /* Initialise and register driver with DPDK Application */
2743 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2744 .dev_configure = nfp_net_configure,
2745 .dev_start = nfp_net_start,
2746 .dev_stop = nfp_net_stop,
2747 .dev_set_link_up = nfp_net_set_link_up,
2748 .dev_set_link_down = nfp_net_set_link_down,
2749 .dev_close = nfp_net_close,
2750 .promiscuous_enable = nfp_net_promisc_enable,
2751 .promiscuous_disable = nfp_net_promisc_disable,
2752 .link_update = nfp_net_link_update,
2753 .stats_get = nfp_net_stats_get,
2754 .stats_reset = nfp_net_stats_reset,
2755 .dev_infos_get = nfp_net_infos_get,
2756 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2757 .mtu_set = nfp_net_dev_mtu_set,
2758 .mac_addr_set = nfp_set_mac_addr,
2759 .vlan_offload_set = nfp_net_vlan_offload_set,
2760 .reta_update = nfp_net_reta_update,
2761 .reta_query = nfp_net_reta_query,
2762 .rss_hash_update = nfp_net_rss_hash_update,
2763 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2764 .rx_queue_setup = nfp_net_rx_queue_setup,
2765 .rx_queue_release = nfp_net_rx_queue_release,
2766 .tx_queue_setup = nfp_net_tx_queue_setup,
2767 .tx_queue_release = nfp_net_tx_queue_release,
2768 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2769 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2774 nfp_net_init(struct rte_eth_dev *eth_dev)
2776 struct rte_pci_device *pci_dev;
2777 struct nfp_pf_dev *pf_dev;
2778 struct nfp_net_hw *hw;
2780 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2786 PMD_INIT_FUNC_TRACE();
2788 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2790 /* Use backpointer here to the PF of this eth_dev */
2791 pf_dev = NFP_NET_DEV_PRIVATE_TO_PF(eth_dev->data->dev_private);
2793 /* NFP can not handle DMA addresses requiring more than 40 bits */
2794 if (rte_mem_check_dma_mask(40)) {
2795 RTE_LOG(ERR, PMD, "device %s can not be used:",
2796 pci_dev->device.name);
2797 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2801 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2802 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2803 port = ((struct nfp_net_hw *)eth_dev->data->dev_private)->idx;
2804 if (port < 0 || port > 7) {
2805 PMD_DRV_LOG(ERR, "Port value is wrong");
2809 /* This points to the specific port private data */
2810 PMD_INIT_LOG(DEBUG, "Working with physical port number %d",
2813 /* Use PF array of physical ports to get pointer to
2814 * this specific port
2816 hw = pf_dev->ports[port];
2819 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2822 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2823 eth_dev->rx_queue_count = nfp_net_rx_queue_count;
2824 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2825 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2827 /* For secondary processes, the primary has done all the work */
2828 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2831 rte_eth_copy_pci_info(eth_dev, pci_dev);
2833 hw->device_id = pci_dev->id.device_id;
2834 hw->vendor_id = pci_dev->id.vendor_id;
2835 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2836 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2838 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2839 pci_dev->id.vendor_id, pci_dev->id.device_id,
2840 pci_dev->addr.domain, pci_dev->addr.bus,
2841 pci_dev->addr.devid, pci_dev->addr.function);
2843 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2844 if (hw->ctrl_bar == NULL) {
2846 "hw->ctrl_bar is NULL. BAR0 not configured");
2850 if (hw->is_phyport) {
2852 hw->ctrl_bar = pf_dev->ctrl_bar;
2854 if (!pf_dev->ctrl_bar)
2856 /* Use port offset in pf ctrl_bar for this
2859 hw->ctrl_bar = pf_dev->ctrl_bar +
2860 (port * NFP_PF_CSR_SLICE_SIZE);
2864 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2866 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2867 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2869 /* Work out where in the BAR the queues start. */
2870 switch (pci_dev->id.device_id) {
2871 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2872 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2873 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2874 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2875 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2876 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2877 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2880 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2882 goto dev_err_ctrl_map;
2885 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2886 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2888 if (hw->is_phyport) {
2889 hw->tx_bar = pf_dev->hw_queues + tx_bar_off;
2890 hw->rx_bar = pf_dev->hw_queues + rx_bar_off;
2891 eth_dev->data->dev_private = hw;
2893 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2895 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2899 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2900 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2902 nfp_net_cfg_queue_setup(hw);
2904 /* Get some of the read-only fields from the config BAR */
2905 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2906 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2907 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2908 hw->mtu = RTE_ETHER_MTU;
2910 /* VLAN insertion is incompatible with LSOv2 */
2911 if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2912 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2914 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2915 hw->rx_offset = NFP_NET_RX_OFFSET;
2917 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2919 PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2920 NFD_CFG_MAJOR_VERSION_of(hw->ver),
2921 NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2923 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2924 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2925 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2926 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2927 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2928 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2929 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2930 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2931 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2932 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2933 hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "",
2934 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2935 hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "",
2936 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "",
2937 hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : "");
2941 hw->stride_rx = stride;
2942 hw->stride_tx = stride;
2944 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2945 hw->max_rx_queues, hw->max_tx_queues);
2947 /* Initializing spinlock for reconfigs */
2948 rte_spinlock_init(&hw->reconfig_lock);
2950 /* Allocating memory for mac addr */
2951 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2952 RTE_ETHER_ADDR_LEN, 0);
2953 if (eth_dev->data->mac_addrs == NULL) {
2954 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2956 goto dev_err_queues_map;
2959 if (hw->is_phyport) {
2960 nfp_net_pf_read_mac(pf_dev, port);
2961 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2963 nfp_net_vf_read_mac(hw);
2966 if (!rte_is_valid_assigned_ether_addr(
2967 (struct rte_ether_addr *)&hw->mac_addr)) {
2968 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2970 /* Using random mac addresses for VFs */
2971 rte_eth_random_addr(&hw->mac_addr[0]);
2972 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2975 /* Copying mac address to DPDK eth_dev struct */
2976 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2977 ð_dev->data->mac_addrs[0]);
2979 if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2980 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2982 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2984 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2985 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2986 eth_dev->data->port_id, pci_dev->id.vendor_id,
2987 pci_dev->id.device_id,
2988 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2989 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2991 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2992 /* Registering LSC interrupt handler */
2993 rte_intr_callback_register(&pci_dev->intr_handle,
2994 nfp_net_dev_interrupt_handler,
2996 /* Telling the firmware about the LSC interrupt entry */
2997 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2998 /* Recording current stats counters values */
2999 nfp_net_stats_reset(eth_dev);
3005 nfp_cpp_area_free(hw->hwqueues_area);
3007 nfp_cpp_area_free(hw->ctrl_area);
3012 #define NFP_CPP_MEMIO_BOUNDARY (1 << 20)
3015 * Serving a write request to NFP from host programs. The request
3016 * sends the write size and the CPP target. The bridge makes use
3017 * of CPP interface handler configured by the PMD setup.
3020 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3022 struct nfp_cpp_area *area;
3023 off_t offset, nfp_offset;
3024 uint32_t cpp_id, pos, len;
3025 uint32_t tmpbuf[16];
3026 size_t count, curlen, totlen = 0;
3029 PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3030 sizeof(off_t), sizeof(size_t));
3032 /* Reading the count param */
3033 err = recv(sockfd, &count, sizeof(off_t), 0);
3034 if (err != sizeof(off_t))
3039 /* Reading the offset param */
3040 err = recv(sockfd, &offset, sizeof(off_t), 0);
3041 if (err != sizeof(off_t))
3044 /* Obtain target's CPP ID and offset in target */
3045 cpp_id = (offset >> 40) << 8;
3046 nfp_offset = offset & ((1ull << 40) - 1);
3048 PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3050 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3051 cpp_id, nfp_offset);
3053 /* Adjust length if not aligned */
3054 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3055 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3056 curlen = NFP_CPP_MEMIO_BOUNDARY -
3057 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3061 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3062 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3063 nfp_offset, curlen);
3065 RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3069 /* mapping the target */
3070 err = nfp_cpp_area_acquire(area);
3072 RTE_LOG(ERR, PMD, "area acquire failed\n");
3073 nfp_cpp_area_free(area);
3077 for (pos = 0; pos < curlen; pos += len) {
3079 if (len > sizeof(tmpbuf))
3080 len = sizeof(tmpbuf);
3082 PMD_CPP_LOG(DEBUG, "%s: Receive %u of %zu\n", __func__,
3084 err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3085 if (err != (int)len) {
3087 "%s: error when receiving, %d of %zu\n",
3088 __func__, err, count);
3089 nfp_cpp_area_release(area);
3090 nfp_cpp_area_free(area);
3093 err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3095 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3096 nfp_cpp_area_release(area);
3097 nfp_cpp_area_free(area);
3104 nfp_cpp_area_release(area);
3105 nfp_cpp_area_free(area);
3108 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3109 NFP_CPP_MEMIO_BOUNDARY : count;
3116 * Serving a read request to NFP from host programs. The request
3117 * sends the read size and the CPP target. The bridge makes use
3118 * of CPP interface handler configured by the PMD setup. The read
3119 * data is sent to the requester using the same socket.
3122 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3124 struct nfp_cpp_area *area;
3125 off_t offset, nfp_offset;
3126 uint32_t cpp_id, pos, len;
3127 uint32_t tmpbuf[16];
3128 size_t count, curlen, totlen = 0;
3131 PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3132 sizeof(off_t), sizeof(size_t));
3134 /* Reading the count param */
3135 err = recv(sockfd, &count, sizeof(off_t), 0);
3136 if (err != sizeof(off_t))
3141 /* Reading the offset param */
3142 err = recv(sockfd, &offset, sizeof(off_t), 0);
3143 if (err != sizeof(off_t))
3146 /* Obtain target's CPP ID and offset in target */
3147 cpp_id = (offset >> 40) << 8;
3148 nfp_offset = offset & ((1ull << 40) - 1);
3150 PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3152 PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3153 cpp_id, nfp_offset);
3155 /* Adjust length if not aligned */
3156 if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3157 (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3158 curlen = NFP_CPP_MEMIO_BOUNDARY -
3159 (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3163 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3164 nfp_offset, curlen);
3166 RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3170 err = nfp_cpp_area_acquire(area);
3172 RTE_LOG(ERR, PMD, "area acquire failed\n");
3173 nfp_cpp_area_free(area);
3177 for (pos = 0; pos < curlen; pos += len) {
3179 if (len > sizeof(tmpbuf))
3180 len = sizeof(tmpbuf);
3182 err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3184 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3185 nfp_cpp_area_release(area);
3186 nfp_cpp_area_free(area);
3189 PMD_CPP_LOG(DEBUG, "%s: sending %u of %zu\n", __func__,
3192 err = send(sockfd, tmpbuf, len, 0);
3193 if (err != (int)len) {
3195 "%s: error when sending: %d of %zu\n",
3196 __func__, err, count);
3197 nfp_cpp_area_release(area);
3198 nfp_cpp_area_free(area);
3205 nfp_cpp_area_release(area);
3206 nfp_cpp_area_free(area);
3209 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3210 NFP_CPP_MEMIO_BOUNDARY : count;
3215 #define NFP_IOCTL 'n'
3216 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3218 * Serving a ioctl command from host NFP tools. This usually goes to
3219 * a kernel driver char driver but it is not available when the PF is
3220 * bound to the PMD. Currently just one ioctl command is served and it
3221 * does not require any CPP access at all.
3224 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3226 uint32_t cmd, ident_size, tmp;
3229 /* Reading now the IOCTL command */
3230 err = recv(sockfd, &cmd, 4, 0);
3232 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3236 /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3237 if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3238 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3242 err = recv(sockfd, &ident_size, 4, 0);
3244 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3248 tmp = nfp_cpp_model(cpp);
3250 PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3252 err = send(sockfd, &tmp, 4, 0);
3254 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3258 tmp = cpp->interface;
3260 PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3262 err = send(sockfd, &tmp, 4, 0);
3264 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3271 #define NFP_BRIDGE_OP_READ 20
3272 #define NFP_BRIDGE_OP_WRITE 30
3273 #define NFP_BRIDGE_OP_IOCTL 40
3276 * This is the code to be executed by a service core. The CPP bridge interface
3277 * is based on a unix socket and requests usually received by a kernel char
3278 * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3279 * can be executed with a wrapper library and LD_LIBRARY being completely
3280 * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3284 nfp_cpp_bridge_service_func(void *args)
3286 struct sockaddr address;
3287 struct nfp_cpp *cpp = args;
3288 int sockfd, datafd, op, ret;
3290 unlink("/tmp/nfp_cpp");
3291 sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3293 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3298 memset(&address, 0, sizeof(struct sockaddr));
3300 address.sa_family = AF_UNIX;
3301 strcpy(address.sa_data, "/tmp/nfp_cpp");
3303 ret = bind(sockfd, (const struct sockaddr *)&address,
3304 sizeof(struct sockaddr));
3306 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3312 ret = listen(sockfd, 20);
3314 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3321 datafd = accept(sockfd, NULL, NULL);
3323 RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3325 RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3331 ret = recv(datafd, &op, 4, 0);
3333 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3338 PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3340 if (op == NFP_BRIDGE_OP_READ)
3341 nfp_cpp_bridge_serve_read(datafd, cpp);
3343 if (op == NFP_BRIDGE_OP_WRITE)
3344 nfp_cpp_bridge_serve_write(datafd, cpp);
3346 if (op == NFP_BRIDGE_OP_IOCTL)
3347 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3359 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
3362 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3364 struct nfp_cpp *cpp = nsp->cpp;
3369 struct stat file_stat;
3372 /* Looking for firmware file in order of priority */
3374 /* First try to find a firmware image specific for this device */
3375 snprintf(serial, sizeof(serial),
3376 "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3377 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3378 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3379 cpp->interface & 0xff);
3381 snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3384 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3385 fw_f = open(fw_name, O_RDONLY);
3389 /* Then try the PCI name */
3390 snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3393 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3394 fw_f = open(fw_name, O_RDONLY);
3398 /* Finally try the card type and media */
3399 snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3400 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3401 fw_f = open(fw_name, O_RDONLY);
3403 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3408 if (fstat(fw_f, &file_stat) < 0) {
3409 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3414 fsize = file_stat.st_size;
3415 PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3416 fw_name, (uint64_t)fsize);
3418 fw_buf = malloc((size_t)fsize);
3420 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3424 memset(fw_buf, 0, fsize);
3426 bytes = read(fw_f, fw_buf, fsize);
3427 if (bytes != fsize) {
3428 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3429 "Just %" PRIu64 " of %" PRIu64 " bytes read",
3430 (uint64_t)bytes, (uint64_t)fsize);
3436 PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3437 nfp_nsp_load_fw(nsp, fw_buf, bytes);
3438 PMD_DRV_LOG(INFO, "Done");
3447 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3448 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3450 struct nfp_nsp *nsp;
3451 const char *nfp_fw_model;
3452 char card_desc[100];
3455 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3458 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3460 PMD_DRV_LOG(ERR, "firmware model NOT found");
3464 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3465 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3466 nfp_eth_table->count);
3470 PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3471 nfp_eth_table->count);
3473 PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3475 snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3476 nfp_fw_model, nfp_eth_table->count,
3477 nfp_eth_table->ports[0].speed / 1000);
3479 nsp = nfp_nsp_open(cpp);
3481 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3485 nfp_nsp_device_soft_reset(nsp);
3486 err = nfp_fw_upload(dev, nsp, card_desc);
3492 static int nfp_init_phyports(struct nfp_pf_dev *pf_dev)
3494 struct nfp_net_hw *hw;
3495 struct rte_eth_dev *eth_dev;
3499 /* Loop through all physical ports on PF */
3500 for (i = 0; i < pf_dev->total_phyports; i++) {
3501 const unsigned int numa_node = rte_socket_id();
3502 char port_name[RTE_ETH_NAME_MAX_LEN];
3504 snprintf(port_name, sizeof(port_name), "%s_port%d",
3505 pf_dev->pci_dev->device.name, i);
3507 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3508 eth_dev = rte_eth_dev_attach_secondary(port_name);
3511 "secondary process attach failed, "
3512 "ethdev doesn't exist");
3517 eth_dev->process_private = pf_dev->cpp;
3521 /* First port has already been initialized */
3523 eth_dev = pf_dev->eth_dev;
3524 goto skip_dev_alloc;
3527 /* Allocate a eth_dev for remaining ports */
3528 eth_dev = rte_eth_dev_allocate(port_name);
3534 /* Allocate memory for remaining ports */
3535 eth_dev->data->dev_private =
3536 rte_zmalloc_socket(port_name, sizeof(struct nfp_net_hw),
3537 RTE_CACHE_LINE_SIZE, numa_node);
3538 if (!eth_dev->data->dev_private) {
3540 rte_eth_dev_release_port(eth_dev);
3545 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3547 /* Add this device to the PF's array of physical ports */
3548 pf_dev->ports[i] = hw;
3550 hw->pf_dev = pf_dev;
3551 hw->cpp = pf_dev->cpp;
3552 hw->eth_dev = eth_dev;
3554 hw->is_phyport = true;
3557 eth_dev->device = &pf_dev->pci_dev->device;
3559 /* ctrl/tx/rx BAR mappings and remaining init happens in
3562 ret = nfp_net_init(eth_dev);
3569 rte_eth_dev_probing_finish(eth_dev);
3571 } /* End loop, all ports on this PF */
3575 for (i = 0; i < pf_dev->total_phyports; i++) {
3576 if (pf_dev->ports[i] && pf_dev->ports[i]->eth_dev) {
3577 struct rte_eth_dev *tmp_dev;
3578 tmp_dev = pf_dev->ports[i]->eth_dev;
3579 rte_eth_dev_release_port(tmp_dev);
3580 pf_dev->ports[i] = NULL;
3587 static int nfp_pf_init(struct rte_eth_dev *eth_dev)
3589 struct rte_pci_device *pci_dev;
3590 struct nfp_net_hw *hw = NULL;
3591 struct nfp_pf_dev *pf_dev = NULL;
3592 struct nfp_cpp *cpp;
3593 struct nfp_hwinfo *hwinfo;
3594 struct nfp_rtsym_table *sym_tbl;
3595 struct nfp_eth_table *nfp_eth_table = NULL;
3596 struct rte_service_spec service;
3597 char name[RTE_ETH_NAME_MAX_LEN];
3602 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3603 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev);
3609 * When device bound to UIO, the device could be used, by mistake,
3610 * by two DPDK apps, and the UIO driver does not avoid it. This
3611 * could lead to a serious problem when configuring the NFP CPP
3612 * interface. Here we avoid this telling to the CPP init code to
3613 * use a lock file if UIO is being used.
3615 if (pci_dev->kdrv == RTE_PCI_KDRV_VFIO)
3616 cpp = nfp_cpp_from_device_name(pci_dev, 0);
3618 cpp = nfp_cpp_from_device_name(pci_dev, 1);
3621 PMD_INIT_LOG(ERR, "A CPP handle can not be obtained");
3626 hwinfo = nfp_hwinfo_read(cpp);
3628 PMD_INIT_LOG(ERR, "Error reading hwinfo table");
3633 nfp_eth_table = nfp_eth_read_ports(cpp);
3634 if (!nfp_eth_table) {
3635 PMD_INIT_LOG(ERR, "Error reading NFP ethernet table");
3637 goto hwinfo_cleanup;
3640 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3641 if (nfp_fw_setup(pci_dev, cpp, nfp_eth_table, hwinfo)) {
3642 PMD_INIT_LOG(ERR, "Error when uploading firmware");
3644 goto eth_table_cleanup;
3648 /* Now the symbol table should be there */
3649 sym_tbl = nfp_rtsym_table_read(cpp);
3651 PMD_INIT_LOG(ERR, "Something is wrong with the firmware"
3654 goto eth_table_cleanup;
3657 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3658 if (total_ports != (int)nfp_eth_table->count) {
3659 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3661 goto sym_tbl_cleanup;
3664 PMD_INIT_LOG(INFO, "Total physical ports: %d", total_ports);
3666 if (total_ports <= 0 || total_ports > 8) {
3667 PMD_INIT_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3669 goto sym_tbl_cleanup;
3671 /* Allocate memory for the PF "device" */
3672 snprintf(name, sizeof(name), "nfp_pf%d", eth_dev->data->port_id);
3673 pf_dev = rte_zmalloc(name, sizeof(*pf_dev), 0);
3676 goto sym_tbl_cleanup;
3679 /* Populate the newly created PF device */
3681 pf_dev->hwinfo = hwinfo;
3682 pf_dev->sym_tbl = sym_tbl;
3683 pf_dev->total_phyports = total_ports;
3685 if (total_ports > 1)
3686 pf_dev->multiport = true;
3688 pf_dev->pci_dev = pci_dev;
3690 /* The first eth_dev is part of the PF struct */
3691 pf_dev->eth_dev = eth_dev;
3693 /* Map the symbol table */
3694 pf_dev->ctrl_bar = nfp_rtsym_map(pf_dev->sym_tbl, "_pf0_net_bar0",
3695 pf_dev->total_phyports * 32768,
3696 &pf_dev->ctrl_area);
3697 if (!pf_dev->ctrl_bar) {
3698 PMD_INIT_LOG(ERR, "nfp_rtsym_map fails for _pf0_net_ctrl_bar");
3703 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", pf_dev->ctrl_bar);
3705 /* configure access to tx/rx vNIC BARs */
3706 pf_dev->hw_queues = nfp_cpp_map_area(pf_dev->cpp, 0, 0,
3708 NFP_QCP_QUEUE_AREA_SZ,
3709 &pf_dev->hwqueues_area);
3710 if (!pf_dev->hw_queues) {
3711 PMD_INIT_LOG(ERR, "nfp_rtsym_map fails for net.qc");
3713 goto ctrl_area_cleanup;
3716 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p", pf_dev->hw_queues);
3718 /* Initialize and prep physical ports now
3719 * This will loop through all physical ports
3721 ret = nfp_init_phyports(pf_dev);
3723 PMD_INIT_LOG(ERR, "Could not create physical ports");
3724 goto hwqueues_cleanup;
3728 * The rte_service needs to be created just once per PMD.
3729 * And the cpp handler needs to be linked to the service.
3730 * Secondary processes will be used for debugging DPDK apps
3731 * when requiring to use the CPP interface for accessing NFP
3732 * components. And the cpp handler for secondary processes is
3733 * available at this point.
3735 memset(&service, 0, sizeof(struct rte_service_spec));
3736 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3737 service.callback = nfp_cpp_bridge_service_func;
3738 service.callback_userdata = (void *)cpp;
3740 if (rte_service_component_register(&service,
3741 &hw->nfp_cpp_service_id))
3742 RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3744 RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3749 nfp_cpp_area_free(pf_dev->hwqueues_area);
3751 nfp_cpp_area_free(pf_dev->ctrl_area);
3757 free(nfp_eth_table);
3764 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3765 struct rte_pci_device *dev)
3767 return rte_eth_dev_pci_generic_probe(dev,
3768 sizeof(struct nfp_net_hw), nfp_pf_init);
3771 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3773 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3774 PCI_DEVICE_ID_NFP4000_PF_NIC)
3777 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3778 PCI_DEVICE_ID_NFP6000_PF_NIC)
3785 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3787 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3788 PCI_DEVICE_ID_NFP6000_VF_NIC)
3795 static int nfp_pci_uninit(struct rte_eth_dev *eth_dev)
3797 struct rte_pci_device *pci_dev;
3800 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3802 if (pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC ||
3803 pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC) {
3804 /* Free up all physical ports under PF */
3805 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3806 rte_eth_dev_close(port_id);
3808 * Ports can be closed and freed but hotplugging is not
3809 * currently supported
3814 /* VF cleanup, just free private port data */
3815 return nfp_net_close(eth_dev);
3818 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3819 struct rte_pci_device *pci_dev)
3821 return rte_eth_dev_pci_generic_probe(pci_dev,
3822 sizeof(struct nfp_net_adapter), nfp_net_init);
3825 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3827 return rte_eth_dev_pci_generic_remove(pci_dev, nfp_pci_uninit);
3830 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3831 .id_table = pci_id_nfp_pf_net_map,
3832 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3833 .probe = nfp_pf_pci_probe,
3834 .remove = eth_nfp_pci_remove,
3837 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3838 .id_table = pci_id_nfp_vf_net_map,
3839 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3840 .probe = eth_nfp_pci_probe,
3841 .remove = eth_nfp_pci_remove,
3844 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3845 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3846 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3847 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3848 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3849 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3850 RTE_LOG_REGISTER(nfp_logtype_init, pmd.net.nfp.init, NOTICE);
3851 RTE_LOG_REGISTER(nfp_logtype_driver, pmd.net.nfp.driver, NOTICE);
3854 * c-file-style: "Linux"
3855 * indent-tabs-mode: t